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   1 /*
   2  *  arch/ppc/kernel/open_pic.c -- OpenPIC Interrupt Handling
   3  *
   4  *  Copyright (C) 1997 Geert Uytterhoeven
   5  *
   6  *  This file is subject to the terms and conditions of the GNU General Public
   7  *  License.  See the file COPYING in the main directory of this archive
   8  *  for more details.
   9  */
  10
  11 #include <linux/config.h>
  12 #include <linux/types.h>
  13 #include <linux/kernel.h>
  14 #include <linux/sched.h>
  15 #include <linux/init.h>
  16 #include <linux/irq.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/sysdev.h>
  19 #include <linux/errno.h>
  20 #include <asm/ptrace.h>
  21 #include <asm/signal.h>
  22 #include <asm/io.h>
  23 #include <asm/irq.h>
  24 #include <asm/sections.h>
  25 #include <asm/open_pic.h>
  26 #include <asm/i8259.h>
  27
  28 #include "open_pic_defs.h"
  29
  30 #if defined(CONFIG_PRPMC800) || defined(CONFIG_85xx)
  31 #define OPENPIC_BIG_ENDIAN
  32 #endif
  33
  34 void __iomem *OpenPIC_Addr;
  35 static volatile struct OpenPIC __iomem *OpenPIC = NULL;
  36
  37 /*
  38  * We define OpenPIC_InitSenses table thusly:
  39  * bit 0x1: sense, 0 for edge and 1 for level.
  40  * bit 0x2: polarity, 0 for negative, 1 for positive.
  41  */
  42 u_int OpenPIC_NumInitSenses __initdata = 0;
  43 u_char *OpenPIC_InitSenses __initdata = NULL;
  44 extern int use_of_interrupt_tree;
  45
  46 static u_int NumProcessors;
  47 static u_int NumSources;
  48 static int open_pic_irq_offset;
  49 static volatile OpenPIC_Source __iomem *ISR[NR_IRQS];
  50 static int openpic_cascade_irq = -1;
  51 static int (*openpic_cascade_fn)(struct pt_regs *);
  52
  53 /* Global Operations */
  54 static void openpic_disable_8259_pass_through(void);
  55 static void openpic_set_spurious(u_int vector);
  56
  57 #ifdef CONFIG_SMP
  58 /* Interprocessor Interrupts */
  59 static void openpic_initipi(u_int ipi, u_int pri, u_int vector);
  60 static irqreturn_t openpic_ipi_action(int cpl, void *dev_id, struct pt_regs *);
  61 #endif
  62
  63 /* Timer Interrupts */
  64 static void openpic_inittimer(u_int timer, u_int pri, u_int vector);
  65 static void openpic_maptimer(u_int timer, cpumask_t cpumask);
  66
  67 /* Interrupt Sources */
  68 static void openpic_enable_irq(u_int irq);
  69 static void openpic_disable_irq(u_int irq);
  70 static void openpic_initirq(u_int irq, u_int pri, u_int vector, int polarity,
  71                             int is_level);
  72 static void openpic_mapirq(u_int irq, cpumask_t cpumask, cpumask_t keepmask);
  73
  74 /*
  75  * These functions are not used but the code is kept here
  76  * for completeness and future reference.
  77  */
  78 #ifdef notused
  79 static void openpic_enable_8259_pass_through(void);
  80 static u_int openpic_get_spurious(void);
  81 static void openpic_set_sense(u_int irq, int sense);
  82 #endif /* notused */
  83
  84 /*
  85  * Description of the openpic for the higher-level irq code
  86  */
  87 static void openpic_end_irq(unsigned int irq_nr);
  88 static void openpic_ack_irq(unsigned int irq_nr);
  89 static void openpic_set_affinity(unsigned int irq_nr, cpumask_t cpumask);
  90
  91 struct hw_interrupt_type open_pic = {
  92         .typename       = " OpenPIC  ",
  93         .enable         = openpic_enable_irq,
  94         .disable        = openpic_disable_irq,
  95         .ack            = openpic_ack_irq,
  96         .end            = openpic_end_irq,
  97         .set_affinity   = openpic_set_affinity,
  98 };
  99
 100 #ifdef CONFIG_SMP
 101 static void openpic_end_ipi(unsigned int irq_nr);
 102 static void openpic_ack_ipi(unsigned int irq_nr);
 103 static void openpic_enable_ipi(unsigned int irq_nr);
 104 static void openpic_disable_ipi(unsigned int irq_nr);
 105
 106 struct hw_interrupt_type open_pic_ipi = {
 107         .typename       = " OpenPIC  ",
 108         .enable         = openpic_enable_ipi,
 109         .disable        = openpic_disable_ipi,
 110         .ack            = openpic_ack_ipi,
 111         .end            = openpic_end_ipi,
 112 };
 113 #endif /* CONFIG_SMP */
 114
 115 /*
 116  *  Accesses to the current processor's openpic registers
 117  */
 118 #ifdef CONFIG_SMP
 119 #define THIS_CPU                Processor[cpu]
 120 #define DECL_THIS_CPU           int cpu = smp_hw_index[smp_processor_id()]
 121 #define CHECK_THIS_CPU          check_arg_cpu(cpu)
 122 #else
 123 #define THIS_CPU                Processor[0]
 124 #define DECL_THIS_CPU
 125 #define CHECK_THIS_CPU
 126 #endif /* CONFIG_SMP */
 127
 128 #if 1
 129 #define check_arg_ipi(ipi) \
 130     if (ipi < 0 || ipi >= OPENPIC_NUM_IPI) \
 131         printk("open_pic.c:%d: invalid ipi %d\n", __LINE__, ipi);
 132 #define check_arg_timer(timer) \
 133     if (timer < 0 || timer >= OPENPIC_NUM_TIMERS) \
 134         printk("open_pic.c:%d: invalid timer %d\n", __LINE__, timer);
 135 #define check_arg_vec(vec) \
 136     if (vec < 0 || vec >= OPENPIC_NUM_VECTORS) \
 137         printk("open_pic.c:%d: invalid vector %d\n", __LINE__, vec);
 138 #define check_arg_pri(pri) \
 139     if (pri < 0 || pri >= OPENPIC_NUM_PRI) \
 140         printk("open_pic.c:%d: invalid priority %d\n", __LINE__, pri);
 141 /*
 142  * Print out a backtrace if it's out of range, since if it's larger than NR_IRQ's
 143  * data has probably been corrupted and we're going to panic or deadlock later
 144  * anyway --Troy
 145  */
 146 #define check_arg_irq(irq) \
 147     if (irq < open_pic_irq_offset || irq >= NumSources+open_pic_irq_offset \
 148         || ISR[irq - open_pic_irq_offset] == 0) { \
 149       printk("open_pic.c:%d: invalid irq %d\n", __LINE__, irq); \
 150       dump_stack(); }
 151 #define check_arg_cpu(cpu) \
 152     if (cpu < 0 || cpu >= NumProcessors){ \
 153         printk("open_pic.c:%d: invalid cpu %d\n", __LINE__, cpu); \
 154         dump_stack(); }
 155 #else
 156 #define check_arg_ipi(ipi)      do {} while (0)
 157 #define check_arg_timer(timer)  do {} while (0)
 158 #define check_arg_vec(vec)      do {} while (0)
 159 #define check_arg_pri(pri)      do {} while (0)
 160 #define check_arg_irq(irq)      do {} while (0)
 161 #define check_arg_cpu(cpu)      do {} while (0)
 162 #endif
 163
 164 u_int openpic_read(volatile u_int __iomem *addr)
 165 {
 166         u_int val;
 167
 168 #ifdef OPENPIC_BIG_ENDIAN
 169         val = in_be32(addr);
 170 #else
 171         val = in_le32(addr);
 172 #endif
 173         return val;
 174 }
 175
 176 static inline void openpic_write(volatile u_int __iomem *addr, u_int val)
 177 {
 178 #ifdef OPENPIC_BIG_ENDIAN
 179         out_be32(addr, val);
 180 #else
 181         out_le32(addr, val);
 182 #endif
 183 }
 184
 185 static inline u_int openpic_readfield(volatile u_int __iomem *addr, u_int mask)
 186 {
 187         u_int val = openpic_read(addr);
 188         return val & mask;
 189 }
 190
 191 inline void openpic_writefield(volatile u_int __iomem *addr, u_int mask,
 192                                u_int field)
 193 {
 194         u_int val = openpic_read(addr);
 195         openpic_write(addr, (val & ~mask) | (field & mask));
 196 }
 197
 198 static inline void openpic_clearfield(volatile u_int __iomem *addr, u_int mask)
 199 {
 200         openpic_writefield(addr, mask, 0);
 201 }
 202
 203 static inline void openpic_setfield(volatile u_int __iomem *addr, u_int mask)
 204 {
 205         openpic_writefield(addr, mask, mask);
 206 }
 207
 208 static void openpic_safe_writefield(volatile u_int __iomem *addr, u_int mask,
 209                                     u_int field)
 210 {
 211         openpic_setfield(addr, OPENPIC_MASK);
 212         while (openpic_read(addr) & OPENPIC_ACTIVITY);
 213         openpic_writefield(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK);
 214 }
 215
 216 #ifdef CONFIG_SMP
 217 /* yes this is right ... bug, feature, you decide! -- tgall */
 218 u_int openpic_read_IPI(volatile u_int __iomem * addr)
 219 {
 220          u_int val = 0;
 221 #if defined(OPENPIC_BIG_ENDIAN) || defined(CONFIG_POWER3)
 222         val = in_be32(addr);
 223 #else
 224         val = in_le32(addr);
 225 #endif
 226         return val;
 227 }
 228
 229 /* because of the power3 be / le above, this is needed */
 230 inline void openpic_writefield_IPI(volatile u_int __iomem * addr, u_int mask, u_int field)
 231 {
 232         u_int  val = openpic_read_IPI(addr);
 233         openpic_write(addr, (val & ~mask) | (field & mask));
 234 }
 235
 236 static inline void openpic_clearfield_IPI(volatile u_int __iomem *addr, u_int mask)
 237 {
 238         openpic_writefield_IPI(addr, mask, 0);
 239 }
 240
 241 static inline void openpic_setfield_IPI(volatile u_int __iomem *addr, u_int mask)
 242 {
 243         openpic_writefield_IPI(addr, mask, mask);
 244 }
 245
 246 static void openpic_safe_writefield_IPI(volatile u_int __iomem *addr, u_int mask, u_int field)
 247 {
 248         openpic_setfield_IPI(addr, OPENPIC_MASK);
 249
 250         /* wait until it's not in use */
 251         /* BenH: Is this code really enough ? I would rather check the result
 252          *       and eventually retry ...
 253          */
 254         while(openpic_read_IPI(addr) & OPENPIC_ACTIVITY);
 255
 256         openpic_writefield_IPI(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK);
 257 }
 258 #endif /* CONFIG_SMP */
 259
 260 #ifdef CONFIG_EPIC_SERIAL_MODE
 261 /* On platforms that may use EPIC serial mode, the default is enabled. */
 262 int epic_serial_mode = 1;
 263
 264 static void __init openpic_eicr_set_clk(u_int clkval)
 265 {
 266         openpic_writefield(&OpenPIC->Global.Global_Configuration1,
 267                         OPENPIC_EICR_S_CLK_MASK, (clkval << 28));
 268 }
 269
 270 static void __init openpic_enable_sie(void)
 271 {
 272         openpic_setfield(&OpenPIC->Global.Global_Configuration1,
 273                         OPENPIC_EICR_SIE);
 274 }
 275 #endif
 276
 277 #if defined(CONFIG_EPIC_SERIAL_MODE)
 278 static void openpic_reset(void)
 279 {
 280         openpic_setfield(&OpenPIC->Global.Global_Configuration0,
 281                          OPENPIC_CONFIG_RESET);
 282         while (openpic_readfield(&OpenPIC->Global.Global_Configuration0,
 283                                  OPENPIC_CONFIG_RESET))
 284                 mb();
 285 }
 286 #endif
 287
 288 void __init openpic_set_sources(int first_irq, int num_irqs, void __iomem *first_ISR)
 289 {
 290         volatile OpenPIC_Source __iomem *src = first_ISR;
 291         int i, last_irq;
 292
 293         last_irq = first_irq + num_irqs;
 294         if (last_irq > NumSources)
 295                 NumSources = last_irq;
 296         if (src == 0)
 297                 src = &((struct OpenPIC __iomem *)OpenPIC_Addr)->Source[first_irq];
 298         for (i = first_irq; i < last_irq; ++i, ++src)
 299                 ISR[i] = src;
 300 }
 301
 302 /*
 303  * The `offset' parameter defines where the interrupts handled by the
 304  * OpenPIC start in the space of interrupt numbers that the kernel knows
 305  * about.  In other words, the OpenPIC's IRQ0 is numbered `offset' in the
 306  * kernel's interrupt numbering scheme.
 307  * We assume there is only one OpenPIC.
 308  */
 309 void __init openpic_init(int offset)
 310 {
 311         u_int t, i;
 312         u_int timerfreq;
 313         const char *version;
 314
 315         if (!OpenPIC_Addr) {
 316                 printk("No OpenPIC found !\n");
 317                 return;
 318         }
 319         OpenPIC = (volatile struct OpenPIC __iomem *)OpenPIC_Addr;
 320
 321 #ifdef CONFIG_EPIC_SERIAL_MODE
 322         /* Have to start from ground zero.
 323         */
 324         openpic_reset();
 325 #endif
 326
 327         if (ppc_md.progress) ppc_md.progress("openpic: enter", 0x122);
 328
 329         t = openpic_read(&OpenPIC->Global.Feature_Reporting0);
 330         switch (t & OPENPIC_FEATURE_VERSION_MASK) {
 331         case 1:
 332                 version = "1.0";
 333                 break;
 334         case 2:
 335                 version = "1.2";
 336                 break;
 337         case 3:
 338                 version = "1.3";
 339                 break;
 340         default:
 341                 version = "?";
 342                 break;
 343         }
 344         NumProcessors = ((t & OPENPIC_FEATURE_LAST_PROCESSOR_MASK) >>
 345                          OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT) + 1;
 346         if (NumSources == 0)
 347                 openpic_set_sources(0,
 348                                     ((t & OPENPIC_FEATURE_LAST_SOURCE_MASK) >>
 349                                      OPENPIC_FEATURE_LAST_SOURCE_SHIFT) + 1,
 350                                     NULL);
 351         printk("OpenPIC Version %s (%d CPUs and %d IRQ sources) at %p\n",
 352                version, NumProcessors, NumSources, OpenPIC);
 353         timerfreq = openpic_read(&OpenPIC->Global.Timer_Frequency);
 354         if (timerfreq)
 355                 printk("OpenPIC timer frequency is %d.%06d MHz\n",
 356                        timerfreq / 1000000, timerfreq % 1000000);
 357
 358         open_pic_irq_offset = offset;
 359
 360         /* Initialize timer interrupts */
 361         if ( ppc_md.progress ) ppc_md.progress("openpic: timer",0x3ba);
 362         for (i = 0; i < OPENPIC_NUM_TIMERS; i++) {
 363                 /* Disabled, Priority 0 */
 364                 openpic_inittimer(i, 0, OPENPIC_VEC_TIMER+i+offset);
 365                 /* No processor */
 366                 openpic_maptimer(i, CPU_MASK_NONE);
 367         }
 368
 369 #ifdef CONFIG_SMP
 370         /* Initialize IPI interrupts */
 371         if ( ppc_md.progress ) ppc_md.progress("openpic: ipi",0x3bb);
 372         for (i = 0; i < OPENPIC_NUM_IPI; i++) {
 373                 /* Disabled, Priority 10..13 */
 374                 openpic_initipi(i, 10+i, OPENPIC_VEC_IPI+i+offset);
 375                 /* IPIs are per-CPU */
 376                 irq_desc[OPENPIC_VEC_IPI+i+offset].status |= IRQ_PER_CPU;
 377                 irq_desc[OPENPIC_VEC_IPI+i+offset].handler = &open_pic_ipi;
 378         }
 379 #endif
 380
 381         /* Initialize external interrupts */
 382         if (ppc_md.progress) ppc_md.progress("openpic: external",0x3bc);
 383
 384         openpic_set_priority(0xf);
 385
 386         /* Init all external sources, including possibly the cascade. */
 387         for (i = 0; i < NumSources; i++) {
 388                 int sense;
 389
 390                 if (ISR[i] == 0)
 391                         continue;
 392
 393                 /* the bootloader may have left it enabled (bad !) */
 394                 openpic_disable_irq(i+offset);
 395
 396                 sense = (i < OpenPIC_NumInitSenses)? OpenPIC_InitSenses[i]: \
 397                                 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE);
 398
 399                 if (sense & IRQ_SENSE_MASK)
 400                         irq_desc[i+offset].status = IRQ_LEVEL;
 401
 402                 /* Enabled, Priority 8 */
 403                 openpic_initirq(i, 8, i+offset, (sense & IRQ_POLARITY_MASK),
 404                                 (sense & IRQ_SENSE_MASK));
 405                 /* Processor 0 */
 406                 openpic_mapirq(i, CPU_MASK_CPU0, CPU_MASK_NONE);
 407         }
 408
 409         /* Init descriptors */
 410         for (i = offset; i < NumSources + offset; i++)
 411                 irq_desc[i].handler = &open_pic;
 412
 413         /* Initialize the spurious interrupt */
 414         if (ppc_md.progress) ppc_md.progress("openpic: spurious",0x3bd);
 415         openpic_set_spurious(OPENPIC_VEC_SPURIOUS);
 416         openpic_disable_8259_pass_through();
 417 #ifdef CONFIG_EPIC_SERIAL_MODE
 418         if (epic_serial_mode) {
 419                 openpic_eicr_set_clk(7);        /* Slowest value until we know better */
 420                 openpic_enable_sie();
 421         }
 422 #endif
 423         openpic_set_priority(0);
 424
 425         if (ppc_md.progress) ppc_md.progress("openpic: exit",0x222);
 426 }
 427
 428 #ifdef notused
 429 static void openpic_enable_8259_pass_through(void)
 430 {
 431         openpic_clearfield(&OpenPIC->Global.Global_Configuration0,
 432                            OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
 433 }
 434 #endif /* notused */
 435
 436 static void openpic_disable_8259_pass_through(void)
 437 {
 438         openpic_setfield(&OpenPIC->Global.Global_Configuration0,
 439                          OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
 440 }
 441
 442 /*
 443  *  Find out the current interrupt
 444  */
 445 u_int openpic_irq(void)
 446 {
 447         u_int vec;
 448         DECL_THIS_CPU;
 449
 450         CHECK_THIS_CPU;
 451         vec = openpic_readfield(&OpenPIC->THIS_CPU.Interrupt_Acknowledge,
 452                                 OPENPIC_VECTOR_MASK);
 453         return vec;
 454 }
 455
 456 void openpic_eoi(void)
 457 {
 458         DECL_THIS_CPU;
 459
 460         CHECK_THIS_CPU;
 461         openpic_write(&OpenPIC->THIS_CPU.EOI, 0);
 462         /* Handle PCI write posting */
 463         (void)openpic_read(&OpenPIC->THIS_CPU.EOI);
 464 }
 465
 466 u_int openpic_get_priority(void)
 467 {
 468         DECL_THIS_CPU;
 469
 470         CHECK_THIS_CPU;
 471         return openpic_readfield(&OpenPIC->THIS_CPU.Current_Task_Priority,
 472                                  OPENPIC_CURRENT_TASK_PRIORITY_MASK);
 473 }
 474
 475 void openpic_set_priority(u_int pri)
 476 {
 477         DECL_THIS_CPU;
 478
 479         CHECK_THIS_CPU;
 480         check_arg_pri(pri);
 481         openpic_writefield(&OpenPIC->THIS_CPU.Current_Task_Priority,
 482                            OPENPIC_CURRENT_TASK_PRIORITY_MASK, pri);
 483 }
 484
 485 /*
 486  *  Get/set the spurious vector
 487  */
 488 #ifdef notused
 489 static u_int openpic_get_spurious(void)
 490 {
 491         return openpic_readfield(&OpenPIC->Global.Spurious_Vector,
 492                                  OPENPIC_VECTOR_MASK);
 493 }
 494 #endif /* notused */
 495
 496 static void openpic_set_spurious(u_int vec)
 497 {
 498         check_arg_vec(vec);
 499         openpic_writefield(&OpenPIC->Global.Spurious_Vector, OPENPIC_VECTOR_MASK,
 500                            vec);
 501 }
 502
 503 #ifdef CONFIG_SMP
 504 /*
 505  * Convert a cpu mask from logical to physical cpu numbers.
 506  */
 507 static inline cpumask_t physmask(cpumask_t cpumask)
 508 {
 509         int i;
 510         cpumask_t mask = CPU_MASK_NONE;
 511
 512         cpus_and(cpumask, cpu_online_map, cpumask);
 513
 514         for (i = 0; i < NR_CPUS; i++)
 515                 if (cpu_isset(i, cpumask))
 516                         cpu_set(smp_hw_index[i], mask);
 517
 518         return mask;
 519 }
 520 #else
 521 #define physmask(cpumask)       (cpumask)
 522 #endif
 523
 524 void openpic_reset_processor_phys(u_int mask)
 525 {
 526         openpic_write(&OpenPIC->Global.Processor_Initialization, mask);
 527 }
 528
 529 #if defined(CONFIG_SMP) || defined(CONFIG_PM)
 530 static DEFINE_SPINLOCK(openpic_setup_lock);
 531 #endif
 532
 533 #ifdef CONFIG_SMP
 534 /*
 535  *  Initialize an interprocessor interrupt (and disable it)
 536  *
 537  *  ipi: OpenPIC interprocessor interrupt number
 538  *  pri: interrupt source priority
 539  *  vec: the vector it will produce
 540  */
 541 static void __init openpic_initipi(u_int ipi, u_int pri, u_int vec)
 542 {
 543         check_arg_ipi(ipi);
 544         check_arg_pri(pri);
 545         check_arg_vec(vec);
 546         openpic_safe_writefield_IPI(&OpenPIC->Global.IPI_Vector_Priority(ipi),
 547                                 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK,
 548                                 (pri << OPENPIC_PRIORITY_SHIFT) | vec);
 549 }
 550
 551 /*
 552  *  Send an IPI to one or more CPUs
 553  *
 554  *  Externally called, however, it takes an IPI number (0...OPENPIC_NUM_IPI)
 555  *  and not a system-wide interrupt number
 556  */
 557 void openpic_cause_IPI(u_int ipi, cpumask_t cpumask)
 558 {
 559         DECL_THIS_CPU;
 560
 561         CHECK_THIS_CPU;
 562         check_arg_ipi(ipi);
 563         openpic_write(&OpenPIC->THIS_CPU.IPI_Dispatch(ipi),
 564                       cpus_addr(physmask(cpumask))[0]);
 565 }
 566
 567 void openpic_request_IPIs(void)
 568 {
 569         int i;
 570
 571         /*
 572          * Make sure this matches what is defined in smp.c for
 573          * smp_message_{pass|recv}() or what shows up in
 574          * /proc/interrupts will be wrong!!! --Troy */
 575
 576         if (OpenPIC == NULL)
 577                 return;
 578
 579         /* IPIs are marked SA_INTERRUPT as they must run with irqs disabled */
 580         request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset,
 581                     openpic_ipi_action, SA_INTERRUPT,
 582                     "IPI0 (call function)", NULL);
 583         request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+1,
 584                     openpic_ipi_action, SA_INTERRUPT,
 585                     "IPI1 (reschedule)", NULL);
 586         request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+2,
 587                     openpic_ipi_action, SA_INTERRUPT,
 588                     "IPI2 (invalidate tlb)", NULL);
 589         request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+3,
 590                     openpic_ipi_action, SA_INTERRUPT,
 591                     "IPI3 (xmon break)", NULL);
 592
 593         for ( i = 0; i < OPENPIC_NUM_IPI ; i++ )
 594                 openpic_enable_ipi(OPENPIC_VEC_IPI+open_pic_irq_offset+i);
 595 }
 596
 597 /*
 598  * Do per-cpu setup for SMP systems.
 599  *
 600  * Get IPI's working and start taking interrupts.
 601  *   -- Cort
 602  */
 603
 604 void __devinit do_openpic_setup_cpu(void)
 605 {
 606 #ifdef CONFIG_IRQ_ALL_CPUS
 607         int i;
 608         cpumask_t msk = CPU_MASK_NONE;
 609 #endif
 610         spin_lock(&openpic_setup_lock);
 611
 612 #ifdef CONFIG_IRQ_ALL_CPUS
 613         cpu_set(smp_hw_index[smp_processor_id()], msk);
 614
 615         /* let the openpic know we want intrs. default affinity
 616          * is 0xffffffff until changed via /proc
 617          * That's how it's done on x86. If we want it differently, then
 618          * we should make sure we also change the default values of irq_affinity
 619          * in irq.c.
 620          */
 621         for (i = 0; i < NumSources; i++)
 622                 openpic_mapirq(i, msk, CPU_MASK_ALL);
 623 #endif /* CONFIG_IRQ_ALL_CPUS */
 624         openpic_set_priority(0);
 625
 626         spin_unlock(&openpic_setup_lock);
 627 }
 628 #endif /* CONFIG_SMP */
 629
 630 /*
 631  *  Initialize a timer interrupt (and disable it)
 632  *
 633  *  timer: OpenPIC timer number
 634  *  pri: interrupt source priority
 635  *  vec: the vector it will produce
 636  */
 637 static void __init openpic_inittimer(u_int timer, u_int pri, u_int vec)
 638 {
 639         check_arg_timer(timer);
 640         check_arg_pri(pri);
 641         check_arg_vec(vec);
 642         openpic_safe_writefield(&OpenPIC->Global.Timer[timer].Vector_Priority,
 643                                 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK,
 644                                 (pri << OPENPIC_PRIORITY_SHIFT) | vec);
 645 }
 646
 647 /*
 648  *  Map a timer interrupt to one or more CPUs
 649  */
 650 static void __init openpic_maptimer(u_int timer, cpumask_t cpumask)
 651 {
 652         cpumask_t phys = physmask(cpumask);
 653         check_arg_timer(timer);
 654         openpic_write(&OpenPIC->Global.Timer[timer].Destination,
 655                       cpus_addr(phys)[0]);
 656 }
 657
 658 /*
 659  * Initalize the interrupt source which will generate an NMI.
 660  * This raises the interrupt's priority from 8 to 9.
 661  *
 662  * irq: The logical IRQ which generates an NMI.
 663  */
 664 void __init
 665 openpic_init_nmi_irq(u_int irq)
 666 {
 667         check_arg_irq(irq);
 668         openpic_safe_writefield(&ISR[irq - open_pic_irq_offset]->Vector_Priority,
 669                                 OPENPIC_PRIORITY_MASK,
 670                                 9 << OPENPIC_PRIORITY_SHIFT);
 671 }
 672
 673 /*
 674  *
 675  * All functions below take an offset'ed irq argument
 676  *
 677  */
 678
 679 /*
 680  * Hookup a cascade to the OpenPIC.
 681  */
 682
 683 static struct irqaction openpic_cascade_irqaction = {
 684         .handler = no_action,
 685         .flags = SA_INTERRUPT,
 686         .mask = CPU_MASK_NONE,
 687 };
 688
 689 void __init
 690 openpic_hookup_cascade(u_int irq, char *name,
 691         int (*cascade_fn)(struct pt_regs *))
 692 {
 693         openpic_cascade_irq = irq;
 694         openpic_cascade_fn = cascade_fn;
 695
 696         if (setup_irq(irq, &openpic_cascade_irqaction))
 697                 printk("Unable to get OpenPIC IRQ %d for cascade\n",
 698                                 irq - open_pic_irq_offset);
 699 }
 700
 701 /*
 702  *  Enable/disable an external interrupt source
 703  *
 704  *  Externally called, irq is an offseted system-wide interrupt number
 705  */
 706 static void openpic_enable_irq(u_int irq)
 707 {
 708         volatile u_int __iomem *vpp;
 709
 710         check_arg_irq(irq);
 711         vpp = &ISR[irq - open_pic_irq_offset]->Vector_Priority;
 712         openpic_clearfield(vpp, OPENPIC_MASK);
 713         /* make sure mask gets to controller before we return to user */
 714         do {
 715                 mb(); /* sync is probably useless here */
 716         } while (openpic_readfield(vpp, OPENPIC_MASK));
 717 }
 718
 719 static void openpic_disable_irq(u_int irq)
 720 {
 721         volatile u_int __iomem *vpp;
 722         u32 vp;
 723
 724         check_arg_irq(irq);
 725         vpp = &ISR[irq - open_pic_irq_offset]->Vector_Priority;
 726         openpic_setfield(vpp, OPENPIC_MASK);
 727         /* make sure mask gets to controller before we return to user */
 728         do {
 729                 mb();  /* sync is probably useless here */
 730                 vp = openpic_readfield(vpp, OPENPIC_MASK | OPENPIC_ACTIVITY);
 731         } while((vp & OPENPIC_ACTIVITY) && !(vp & OPENPIC_MASK));
 732 }
 733
 734 #ifdef CONFIG_SMP
 735 /*
 736  *  Enable/disable an IPI interrupt source
 737  *
 738  *  Externally called, irq is an offseted system-wide interrupt number
 739  */
 740 void openpic_enable_ipi(u_int irq)
 741 {
 742         irq -= (OPENPIC_VEC_IPI+open_pic_irq_offset);
 743         check_arg_ipi(irq);
 744         openpic_clearfield_IPI(&OpenPIC->Global.IPI_Vector_Priority(irq), OPENPIC_MASK);
 745
 746 }
 747
 748 void openpic_disable_ipi(u_int irq)
 749 {
 750         irq -= (OPENPIC_VEC_IPI+open_pic_irq_offset);
 751         check_arg_ipi(irq);
 752         openpic_setfield_IPI(&OpenPIC->Global.IPI_Vector_Priority(irq), OPENPIC_MASK);
 753 }
 754 #endif
 755
 756 /*
 757  *  Initialize an interrupt source (and disable it!)
 758  *
 759  *  irq: OpenPIC interrupt number
 760  *  pri: interrupt source priority
 761  *  vec: the vector it will produce
 762  *  pol: polarity (1 for positive, 0 for negative)
 763  *  sense: 1 for level, 0 for edge
 764  */
 765 static void __init
 766 openpic_initirq(u_int irq, u_int pri, u_int vec, int pol, int sense)
 767 {
 768         openpic_safe_writefield(&ISR[irq]->Vector_Priority,
 769                                 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK |
 770                                 OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK,
 771                                 (pri << OPENPIC_PRIORITY_SHIFT) | vec |
 772                                 (pol ? OPENPIC_POLARITY_POSITIVE :
 773                                         OPENPIC_POLARITY_NEGATIVE) |
 774                                 (sense ? OPENPIC_SENSE_LEVEL : OPENPIC_SENSE_EDGE));
 775 }
 776
 777 /*
 778  *  Map an interrupt source to one or more CPUs
 779  */
 780 static void openpic_mapirq(u_int irq, cpumask_t physmask, cpumask_t keepmask)
 781 {
 782         if (ISR[irq] == 0)
 783                 return;
 784         if (!cpus_empty(keepmask)) {
 785                 cpumask_t irqdest = { .bits[0] = openpic_read(&ISR[irq]->Destination) };
 786                 cpus_and(irqdest, irqdest, keepmask);
 787                 cpus_or(physmask, physmask, irqdest);
 788         }
 789         openpic_write(&ISR[irq]->Destination, cpus_addr(physmask)[0]);
 790 }
 791
 792 #ifdef notused
 793 /*
 794  *  Set the sense for an interrupt source (and disable it!)
 795  *
 796  *  sense: 1 for level, 0 for edge
 797  */
 798 static void openpic_set_sense(u_int irq, int sense)
 799 {
 800         if (ISR[irq] != 0)
 801                 openpic_safe_writefield(&ISR[irq]->Vector_Priority,
 802                                         OPENPIC_SENSE_LEVEL,
 803                                         (sense ? OPENPIC_SENSE_LEVEL : 0));
 804 }
 805 #endif /* notused */
 806
 807 /* No spinlocks, should not be necessary with the OpenPIC
 808  * (1 register = 1 interrupt and we have the desc lock).
 809  */
 810 static void openpic_ack_irq(unsigned int irq_nr)
 811 {
 812 #ifdef __SLOW_VERSION__
 813         openpic_disable_irq(irq_nr);
 814         openpic_eoi();
 815 #else
 816         if ((irq_desc[irq_nr].status & IRQ_LEVEL) == 0)
 817                 openpic_eoi();
 818 #endif
 819 }
 820
 821 static void openpic_end_irq(unsigned int irq_nr)
 822 {
 823 #ifdef __SLOW_VERSION__
 824         if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))
 825             && irq_desc[irq_nr].action)
 826                 openpic_enable_irq(irq_nr);
 827 #else
 828         if ((irq_desc[irq_nr].status & IRQ_LEVEL) != 0)
 829                 openpic_eoi();
 830 #endif
 831 }
 832
 833 static void openpic_set_affinity(unsigned int irq_nr, cpumask_t cpumask)
 834 {
 835         openpic_mapirq(irq_nr - open_pic_irq_offset, physmask(cpumask), CPU_MASK_NONE);
 836 }
 837
 838 #ifdef CONFIG_SMP
 839 static void openpic_ack_ipi(unsigned int irq_nr)
 840 {
 841         openpic_eoi();
 842 }
 843
 844 static void openpic_end_ipi(unsigned int irq_nr)
 845 {
 846 }
 847
 848 static irqreturn_t openpic_ipi_action(int cpl, void *dev_id, struct pt_regs *regs)
 849 {
 850         smp_message_recv(cpl-OPENPIC_VEC_IPI-open_pic_irq_offset, regs);
 851         return IRQ_HANDLED;
 852 }
 853
 854 #endif /* CONFIG_SMP */
 855
 856 int
 857 openpic_get_irq(struct pt_regs *regs)
 858 {
 859         int irq = openpic_irq();
 860
 861         /*
 862          * Check for the cascade interrupt and call the cascaded
 863          * interrupt controller function (usually i8259_irq) if so.
 864          * This should move to irq.c eventually.  -- paulus
 865          */
 866         if (irq == openpic_cascade_irq && openpic_cascade_fn != NULL) {
 867                 int cirq = openpic_cascade_fn(regs);
 868
 869                 /* Allow for the cascade being shared with other devices */
 870                 if (cirq != -1) {
 871                         irq = cirq;
 872                         openpic_eoi();
 873                 }
 874         } else if (irq == OPENPIC_VEC_SPURIOUS)
 875                 irq = -1;
 876         return irq;
 877 }
 878
 879 #ifdef CONFIG_SMP
 880 void
 881 smp_openpic_message_pass(int target, int msg, unsigned long data, int wait)
 882 {
 883         cpumask_t mask = CPU_MASK_ALL;
 884         /* make sure we're sending something that translates to an IPI */
 885         if (msg > 0x3) {
 886                 printk("SMP %d: smp_message_pass: unknown msg %d\n",
 887                        smp_processor_id(), msg);
 888                 return;
 889         }
 890         switch (target) {
 891         case MSG_ALL:
 892                 openpic_cause_IPI(msg, mask);
 893                 break;
 894         case MSG_ALL_BUT_SELF:
 895                 cpu_clear(smp_processor_id(), mask);
 896                 openpic_cause_IPI(msg, mask);
 897                 break;
 898         default:
 899                 openpic_cause_IPI(msg, cpumask_of_cpu(target));
 900                 break;
 901         }
 902 }
 903 #endif /* CONFIG_SMP */
 904
 905 #ifdef CONFIG_PM
 906
 907 /*
 908  * We implement the IRQ controller as a sysdev and put it
 909  * to sleep at powerdown stage (the callback is named suspend,
 910  * but it's old semantics, for the Device Model, it's really
 911  * powerdown). The possible problem is that another sysdev that
 912  * happens to be suspend after this one will have interrupts off,
 913  * that may be an issue... For now, this isn't an issue on pmac
 914  * though...
 915  */
 916
 917 static u32 save_ipi_vp[OPENPIC_NUM_IPI];
 918 static u32 save_irq_src_vp[OPENPIC_MAX_SOURCES];
 919 static u32 save_irq_src_dest[OPENPIC_MAX_SOURCES];
 920 static u32 save_cpu_task_pri[OPENPIC_MAX_PROCESSORS];
 921 static int openpic_suspend_count;
 922
 923 static void openpic_cached_enable_irq(u_int irq)
 924 {
 925         check_arg_irq(irq);
 926         save_irq_src_vp[irq - open_pic_irq_offset] &= ~OPENPIC_MASK;
 927 }
 928
 929 static void openpic_cached_disable_irq(u_int irq)
 930 {
 931         check_arg_irq(irq);
 932         save_irq_src_vp[irq - open_pic_irq_offset] |= OPENPIC_MASK;
 933 }
 934
 935 /* WARNING: Can be called directly by the cpufreq code with NULL parameter,
 936  * we need something better to deal with that... Maybe switch to S1 for
 937  * cpufreq changes
 938  */
 939 int openpic_suspend(struct sys_device *sysdev, u32 state)
 940 {
 941         int     i;
 942         unsigned long flags;
 943
 944         spin_lock_irqsave(&openpic_setup_lock, flags);
 945
 946         if (openpic_suspend_count++ > 0) {
 947                 spin_unlock_irqrestore(&openpic_setup_lock, flags);
 948                 return 0;
 949         }
 950
 951         openpic_set_priority(0xf);
 952
 953         open_pic.enable = openpic_cached_enable_irq;
 954         open_pic.disable = openpic_cached_disable_irq;
 955
 956         for (i=0; i<NumProcessors; i++) {
 957                 save_cpu_task_pri[i] = openpic_read(&OpenPIC->Processor[i].Current_Task_Priority);
 958                 openpic_writefield(&OpenPIC->Processor[i].Current_Task_Priority,
 959                                    OPENPIC_CURRENT_TASK_PRIORITY_MASK, 0xf);
 960         }
 961
 962         for (i=0; i<OPENPIC_NUM_IPI; i++)
 963                 save_ipi_vp[i] = openpic_read(&OpenPIC->Global.IPI_Vector_Priority(i));
 964         for (i=0; i<NumSources; i++) {
 965                 if (ISR[i] == 0)
 966                         continue;
 967                 save_irq_src_vp[i] = openpic_read(&ISR[i]->Vector_Priority) & ~OPENPIC_ACTIVITY;
 968                 save_irq_src_dest[i] = openpic_read(&ISR[i]->Destination);
 969         }
 970
 971         spin_unlock_irqrestore(&openpic_setup_lock, flags);
 972
 973         return 0;
 974 }
 975
 976 /* WARNING: Can be called directly by the cpufreq code with NULL parameter,
 977  * we need something better to deal with that... Maybe switch to S1 for
 978  * cpufreq changes
 979  */
 980 int openpic_resume(struct sys_device *sysdev)
 981 {
 982         int             i;
 983         unsigned long   flags;
 984         u32             vppmask =       OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK |
 985                                         OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK |
 986                                         OPENPIC_MASK;
 987
 988         spin_lock_irqsave(&openpic_setup_lock, flags);
 989
 990         if ((--openpic_suspend_count) > 0) {
 991                 spin_unlock_irqrestore(&openpic_setup_lock, flags);
 992                 return 0;
 993         }
 994
 995         /* OpenPIC sometimes seem to need some time to be fully back up... */
 996         do {
 997                 openpic_set_spurious(OPENPIC_VEC_SPURIOUS);
 998         } while(openpic_readfield(&OpenPIC->Global.Spurious_Vector, OPENPIC_VECTOR_MASK)
 999                         != OPENPIC_VEC_SPURIOUS);
1000
1001         openpic_disable_8259_pass_through();
1002
1003         for (i=0; i<OPENPIC_NUM_IPI; i++)
1004                 openpic_write(&OpenPIC->Global.IPI_Vector_Priority(i),
1005                               save_ipi_vp[i]);
1006         for (i=0; i<NumSources; i++) {
1007                 if (ISR[i] == 0)
1008                         continue;
1009                 openpic_write(&ISR[i]->Destination, save_irq_src_dest[i]);
1010                 openpic_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]);
1011                 /* make sure mask gets to controller before we return to user */
1012                 do {
1013                         openpic_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]);
1014                 } while (openpic_readfield(&ISR[i]->Vector_Priority, vppmask)
1015                          != (save_irq_src_vp[i] & vppmask));
1016         }
1017         for (i=0; i<NumProcessors; i++)
1018                 openpic_write(&OpenPIC->Processor[i].Current_Task_Priority,
1019                               save_cpu_task_pri[i]);
1020
1021         open_pic.enable = openpic_enable_irq;
1022         open_pic.disable = openpic_disable_irq;
1023
1024         openpic_set_priority(0);
1025
1026         spin_unlock_irqrestore(&openpic_setup_lock, flags);
1027
1028         return 0;
1029 }
1030
1031 #endif /* CONFIG_PM */
1032
1033 static struct sysdev_class openpic_sysclass = {
1034         set_kset_name("openpic"),
1035 };
1036
1037 static struct sys_device device_openpic = {
1038         .id             = 0,
1039         .cls            = &openpic_sysclass,
1040 };
1041
1042 static struct sysdev_driver driver_openpic = {
1043 #ifdef CONFIG_PM
1044         .suspend        = &openpic_suspend,
1045         .resume         = &openpic_resume,
1046 #endif /* CONFIG_PM */
1047 };
1048
1049 static int __init init_openpic_sysfs(void)
1050 {
1051         int rc;
1052
1053         if (!OpenPIC_Addr)
1054                 return -ENODEV;
1055         printk(KERN_DEBUG "Registering openpic with sysfs...\n");
1056         rc = sysdev_class_register(&openpic_sysclass);
1057         if (rc) {
1058                 printk(KERN_ERR "Failed registering openpic sys class\n");
1059                 return -ENODEV;
1060         }
1061         rc = sysdev_register(&device_openpic);
1062         if (rc) {
1063                 printk(KERN_ERR "Failed registering openpic sys device\n");
1064                 return -ENODEV;
1065         }
1066         rc = sysdev_driver_register(&openpic_sysclass, &driver_openpic);
1067         if (rc) {
1068                 printk(KERN_ERR "Failed registering openpic sys driver\n");
1069                 return -ENODEV;
1070         }
1071         return 0;
1072 }
1073
1074 subsys_initcall(init_openpic_sysfs);
1075