git.oblomov.eu Git - linux-2.6/blob - drivers/video/aty/atyfb_base.c

   1 /*
   2  *  ATI Frame Buffer Device Driver Core
   3  *
   4  *      Copyright (C) 2004  Alex Kern <alex.kern@gmx.de>
   5  *      Copyright (C) 1997-2001  Geert Uytterhoeven
   6  *      Copyright (C) 1998  Bernd Harries
   7  *      Copyright (C) 1998  Eddie C. Dost  (ecd@skynet.be)
   8  *
   9  *  This driver supports the following ATI graphics chips:
  10  *    - ATI Mach64
  11  *
  12  *  To do: add support for
  13  *    - ATI Rage128 (from aty128fb.c)
  14  *    - ATI Radeon (from radeonfb.c)
  15  *
  16  *  This driver is partly based on the PowerMac console driver:
  17  *
  18  *      Copyright (C) 1996 Paul Mackerras
  19  *
  20  *  and on the PowerMac ATI/mach64 display driver:
  21  *
  22  *      Copyright (C) 1997 Michael AK Tesch
  23  *
  24  *            with work by Jon Howell
  25  *                         Harry AC Eaton
  26  *                         Anthony Tong <atong@uiuc.edu>
  27  *
  28  *  Generic LCD support written by Daniel Mantione, ported from 2.4.20 by Alex Kern
  29  *  Many Thanks to Ville Syrjälä for patches and fixing nasting 16 bit color bug.
  30  *
  31  *  This file is subject to the terms and conditions of the GNU General Public
  32  *  License. See the file COPYING in the main directory of this archive for
  33  *  more details.
  34  *
  35  *  Many thanks to Nitya from ATI devrel for support and patience !
  36  */
  37
  38 /******************************************************************************
  39
  40   TODO:
  41
  42     - cursor support on all cards and all ramdacs.
  43     - cursor parameters controlable via ioctl()s.
  44     - guess PLL and MCLK based on the original PLL register values initialized
  45       by Open Firmware (if they are initialized). BIOS is done
  46
  47     (Anyone with Mac to help with this?)
  48
  49 ******************************************************************************/
  50
  51
  52 #include <linux/module.h>
  53 #include <linux/moduleparam.h>
  54 #include <linux/kernel.h>
  55 #include <linux/errno.h>
  56 #include <linux/string.h>
  57 #include <linux/mm.h>
  58 #include <linux/slab.h>
  59 #include <linux/vmalloc.h>
  60 #include <linux/delay.h>
  61 #include <linux/console.h>
  62 #include <linux/fb.h>
  63 #include <linux/init.h>
  64 #include <linux/pci.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/spinlock.h>
  67 #include <linux/wait.h>
  68 #include <linux/backlight.h>
  69
  70 #include <asm/io.h>
  71 #include <linux/uaccess.h>
  72
  73 #include <video/mach64.h>
  74 #include "atyfb.h"
  75 #include "ati_ids.h"
  76
  77 #ifdef __powerpc__
  78 #include <asm/machdep.h>
  79 #include <asm/prom.h>
  80 #include "../macmodes.h"
  81 #endif
  82 #ifdef __sparc__
  83 #include <asm/fbio.h>
  84 #include <asm/oplib.h>
  85 #include <asm/prom.h>
  86 #endif
  87
  88 #ifdef CONFIG_ADB_PMU
  89 #include <linux/adb.h>
  90 #include <linux/pmu.h>
  91 #endif
  92 #ifdef CONFIG_BOOTX_TEXT
  93 #include <asm/btext.h>
  94 #endif
  95 #ifdef CONFIG_PMAC_BACKLIGHT
  96 #include <asm/backlight.h>
  97 #endif
  98 #ifdef CONFIG_MTRR
  99 #include <asm/mtrr.h>
 100 #endif
 101
 102 /*
 103  * Debug flags.
 104  */
 105 #undef DEBUG
 106 /*#define DEBUG*/
 107
 108 /* Make sure n * PAGE_SIZE is protected at end of Aperture for GUI-regs */
 109 /*  - must be large enough to catch all GUI-Regs   */
 110 /*  - must be aligned to a PAGE boundary           */
 111 #define GUI_RESERVE     (1 * PAGE_SIZE)
 112
 113 /* FIXME: remove the FAIL definition */
 114 #define FAIL(msg) do { \
 115         if (!(var->activate & FB_ACTIVATE_TEST)) \
 116                 printk(KERN_CRIT "atyfb: " msg "\n"); \
 117         return -EINVAL; \
 118 } while (0)
 119 #define FAIL_MAX(msg, x, _max_) do { \
 120         if (x > _max_) { \
 121                 if (!(var->activate & FB_ACTIVATE_TEST)) \
 122                         printk(KERN_CRIT "atyfb: " msg " %x(%x)\n", x, _max_); \
 123                 return -EINVAL; \
 124         } \
 125 } while (0)
 126 #ifdef DEBUG
 127 #define DPRINTK(fmt, args...)   printk(KERN_DEBUG "atyfb: " fmt, ## args)
 128 #else
 129 #define DPRINTK(fmt, args...)
 130 #endif
 131
 132 #define PRINTKI(fmt, args...)   printk(KERN_INFO "atyfb: " fmt, ## args)
 133 #define PRINTKE(fmt, args...)    printk(KERN_ERR "atyfb: " fmt, ## args)
 134
 135 #if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || \
 136 defined (CONFIG_FB_ATY_GENERIC_LCD) || defined(CONFIG_FB_ATY_BACKLIGHT)
 137 static const u32 lt_lcd_regs[] = {
 138         CONFIG_PANEL_LG,
 139         LCD_GEN_CNTL_LG,
 140         DSTN_CONTROL_LG,
 141         HFB_PITCH_ADDR_LG,
 142         HORZ_STRETCHING_LG,
 143         VERT_STRETCHING_LG,
 144         0, /* EXT_VERT_STRETCH */
 145         LT_GIO_LG,
 146         POWER_MANAGEMENT_LG
 147 };
 148
 149 void aty_st_lcd(int index, u32 val, const struct atyfb_par *par)
 150 {
 151         if (M64_HAS(LT_LCD_REGS)) {
 152                 aty_st_le32(lt_lcd_regs[index], val, par);
 153         } else {
 154                 unsigned long temp;
 155
 156                 /* write addr byte */
 157                 temp = aty_ld_le32(LCD_INDEX, par);
 158                 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
 159                 /* write the register value */
 160                 aty_st_le32(LCD_DATA, val, par);
 161         }
 162 }
 163
 164 u32 aty_ld_lcd(int index, const struct atyfb_par *par)
 165 {
 166         if (M64_HAS(LT_LCD_REGS)) {
 167                 return aty_ld_le32(lt_lcd_regs[index], par);
 168         } else {
 169                 unsigned long temp;
 170
 171                 /* write addr byte */
 172                 temp = aty_ld_le32(LCD_INDEX, par);
 173                 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
 174                 /* read the register value */
 175                 return aty_ld_le32(LCD_DATA, par);
 176         }
 177 }
 178 #endif /* defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD) */
 179
 180 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 181 /*
 182  * ATIReduceRatio --
 183  *
 184  * Reduce a fraction by factoring out the largest common divider of the
 185  * fraction's numerator and denominator.
 186  */
 187 static void ATIReduceRatio(int *Numerator, int *Denominator)
 188 {
 189     int Multiplier, Divider, Remainder;
 190
 191     Multiplier = *Numerator;
 192     Divider = *Denominator;
 193
 194     while ((Remainder = Multiplier % Divider))
 195     {
 196         Multiplier = Divider;
 197         Divider = Remainder;
 198     }
 199
 200     *Numerator /= Divider;
 201     *Denominator /= Divider;
 202 }
 203 #endif
 204     /*
 205      *  The Hardware parameters for each card
 206      */
 207
 208 struct pci_mmap_map {
 209         unsigned long voff;
 210         unsigned long poff;
 211         unsigned long size;
 212         unsigned long prot_flag;
 213         unsigned long prot_mask;
 214 };
 215
 216 static struct fb_fix_screeninfo atyfb_fix __devinitdata = {
 217         .id             = "ATY Mach64",
 218         .type           = FB_TYPE_PACKED_PIXELS,
 219         .visual         = FB_VISUAL_PSEUDOCOLOR,
 220         .xpanstep       = 8,
 221         .ypanstep       = 1,
 222 };
 223
 224     /*
 225      *  Frame buffer device API
 226      */
 227
 228 static int atyfb_open(struct fb_info *info, int user);
 229 static int atyfb_release(struct fb_info *info, int user);
 230 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
 231 static int atyfb_set_par(struct fb_info *info);
 232 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 233         u_int transp, struct fb_info *info);
 234 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
 235 static int atyfb_blank(int blank, struct fb_info *info);
 236 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg);
 237 #ifdef __sparc__
 238 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma);
 239 #endif
 240 static int atyfb_sync(struct fb_info *info);
 241
 242     /*
 243      *  Internal routines
 244      */
 245
 246 static int aty_init(struct fb_info *info);
 247 static void aty_resume_chip(struct fb_info *info);
 248 #ifdef CONFIG_ATARI
 249 static int store_video_par(char *videopar, unsigned char m64_num);
 250 #endif
 251
 252 static struct crtc saved_crtc;
 253 static union aty_pll saved_pll;
 254 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc);
 255
 256 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc);
 257 static int aty_var_to_crtc(const struct fb_info *info, const struct fb_var_screeninfo *var, struct crtc *crtc);
 258 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var);
 259 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info);
 260 #ifdef CONFIG_PPC
 261 static int read_aty_sense(const struct atyfb_par *par);
 262 #endif
 263
 264
 265     /*
 266      *  Interface used by the world
 267      */
 268
 269 static struct fb_var_screeninfo default_var = {
 270         /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
 271         640, 480, 640, 480, 0, 0, 8, 0,
 272         {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
 273         0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
 274         0, FB_VMODE_NONINTERLACED
 275 };
 276
 277 static struct fb_videomode defmode = {
 278         /* 640x480 @ 60 Hz, 31.5 kHz hsync */
 279         NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
 280         0, FB_VMODE_NONINTERLACED
 281 };
 282
 283 static struct fb_ops atyfb_ops = {
 284         .owner          = THIS_MODULE,
 285         .fb_open        = atyfb_open,
 286         .fb_release     = atyfb_release,
 287         .fb_check_var   = atyfb_check_var,
 288         .fb_set_par     = atyfb_set_par,
 289         .fb_setcolreg   = atyfb_setcolreg,
 290         .fb_pan_display = atyfb_pan_display,
 291         .fb_blank       = atyfb_blank,
 292         .fb_ioctl       = atyfb_ioctl,
 293         .fb_fillrect    = atyfb_fillrect,
 294         .fb_copyarea    = atyfb_copyarea,
 295         .fb_imageblit   = atyfb_imageblit,
 296 #ifdef __sparc__
 297         .fb_mmap        = atyfb_mmap,
 298 #endif
 299         .fb_sync        = atyfb_sync,
 300 };
 301
 302 static int noaccel;
 303 #ifdef CONFIG_MTRR
 304 static int nomtrr;
 305 #endif
 306 static int vram;
 307 static int pll;
 308 static int mclk;
 309 static int xclk;
 310 static int comp_sync __devinitdata = -1;
 311 static char *mode;
 312
 313 #ifdef CONFIG_PMAC_BACKLIGHT
 314 static int backlight __devinitdata = 1;
 315 #else
 316 static int backlight __devinitdata = 0;
 317 #endif
 318
 319 #ifdef CONFIG_PPC
 320 static int default_vmode __devinitdata = VMODE_CHOOSE;
 321 static int default_cmode __devinitdata = CMODE_CHOOSE;
 322
 323 module_param_named(vmode, default_vmode, int, 0);
 324 MODULE_PARM_DESC(vmode, "int: video mode for mac");
 325 module_param_named(cmode, default_cmode, int, 0);
 326 MODULE_PARM_DESC(cmode, "int: color mode for mac");
 327 #endif
 328
 329 #ifdef CONFIG_ATARI
 330 static unsigned int mach64_count __devinitdata = 0;
 331 static unsigned long phys_vmembase[FB_MAX] __devinitdata = { 0, };
 332 static unsigned long phys_size[FB_MAX] __devinitdata = { 0, };
 333 static unsigned long phys_guiregbase[FB_MAX] __devinitdata = { 0, };
 334 #endif
 335
 336 /* top -> down is an evolution of mach64 chipset, any corrections? */
 337 #define ATI_CHIP_88800GX   (M64F_GX)
 338 #define ATI_CHIP_88800CX   (M64F_GX)
 339
 340 #define ATI_CHIP_264CT     (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
 341 #define ATI_CHIP_264ET     (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
 342
 343 #define ATI_CHIP_264VT     (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_MAGIC_FIFO)
 344 #define ATI_CHIP_264GT     (M64F_GT | M64F_INTEGRATED               | M64F_MAGIC_FIFO | M64F_EXTRA_BRIGHT)
 345
 346 #define ATI_CHIP_264VTB    (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP)
 347 #define ATI_CHIP_264VT3    (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL)
 348 #define ATI_CHIP_264VT4    (M64F_VT | M64F_INTEGRATED               | M64F_GTB_DSP)
 349
 350 /* FIXME what is this chip? */
 351 #define ATI_CHIP_264LT     (M64F_GT | M64F_INTEGRATED               | M64F_GTB_DSP)
 352
 353 /* make sets shorter */
 354 #define ATI_MODERN_SET     (M64F_GT | M64F_INTEGRATED               | M64F_GTB_DSP | M64F_EXTRA_BRIGHT)
 355
 356 #define ATI_CHIP_264GTB    (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
 357 /*#define ATI_CHIP_264GTDVD  ?*/
 358 #define ATI_CHIP_264LTG    (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
 359
 360 #define ATI_CHIP_264GT2C   (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE)
 361 #define ATI_CHIP_264GTPRO  (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
 362 #define ATI_CHIP_264LTPRO  (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
 363
 364 #define ATI_CHIP_264XL     (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4)
 365 #define ATI_CHIP_MOBILITY  (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_MOBIL_BUS)
 366
 367 static struct {
 368         u16 pci_id;
 369         const char *name;
 370         int pll, mclk, xclk, ecp_max;
 371         u32 features;
 372 } aty_chips[] __devinitdata = {
 373 #ifdef CONFIG_FB_ATY_GX
 374         /* Mach64 GX */
 375         { PCI_CHIP_MACH64GX, "ATI888GX00 (Mach64 GX)", 135, 50, 50, 0, ATI_CHIP_88800GX },
 376         { PCI_CHIP_MACH64CX, "ATI888CX00 (Mach64 CX)", 135, 50, 50, 0, ATI_CHIP_88800CX },
 377 #endif /* CONFIG_FB_ATY_GX */
 378
 379 #ifdef CONFIG_FB_ATY_CT
 380         { PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, 0, ATI_CHIP_264CT },
 381         { PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, 0, ATI_CHIP_264ET },
 382
 383         /* FIXME what is this chip? */
 384         { PCI_CHIP_MACH64LT, "ATI264LT (Mach64 LT)", 135, 63, 63, 0, ATI_CHIP_264LT },
 385
 386         { PCI_CHIP_MACH64VT, "ATI264VT (Mach64 VT)", 170, 67, 67, 80, ATI_CHIP_264VT },
 387         { PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, 80, ATI_CHIP_264GT },
 388
 389         { PCI_CHIP_MACH64VU, "ATI264VT3 (Mach64 VU)", 200, 67, 67, 80, ATI_CHIP_264VT3 },
 390         { PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GU)", 200, 67, 67, 100, ATI_CHIP_264GTB },
 391
 392         { PCI_CHIP_MACH64LG, "3D RAGE LT (Mach64 LG)", 230, 63, 63, 100, ATI_CHIP_264LTG | M64F_LT_LCD_REGS | M64F_G3_PB_1024x768 },
 393
 394         { PCI_CHIP_MACH64VV, "ATI264VT4 (Mach64 VV)", 230, 83, 83, 100, ATI_CHIP_264VT4 },
 395
 396         { PCI_CHIP_MACH64GV, "3D RAGE IIC (Mach64 GV, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
 397         { PCI_CHIP_MACH64GW, "3D RAGE IIC (Mach64 GW, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
 398         { PCI_CHIP_MACH64GY, "3D RAGE IIC (Mach64 GY, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
 399         { PCI_CHIP_MACH64GZ, "3D RAGE IIC (Mach64 GZ, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
 400
 401         { PCI_CHIP_MACH64GB, "3D RAGE PRO (Mach64 GB, BGA, AGP)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
 402         { PCI_CHIP_MACH64GD, "3D RAGE PRO (Mach64 GD, BGA, AGP 1x)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
 403         { PCI_CHIP_MACH64GI, "3D RAGE PRO (Mach64 GI, BGA, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO | M64F_MAGIC_VRAM_SIZE },
 404         { PCI_CHIP_MACH64GP, "3D RAGE PRO (Mach64 GP, PQFP, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
 405         { PCI_CHIP_MACH64GQ, "3D RAGE PRO (Mach64 GQ, PQFP, PCI, limited 3D)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
 406
 407         { PCI_CHIP_MACH64LB, "3D RAGE LT PRO (Mach64 LB, AGP)", 236, 75, 100, 135, ATI_CHIP_264LTPRO },
 408         { PCI_CHIP_MACH64LD, "3D RAGE LT PRO (Mach64 LD, AGP)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
 409         { PCI_CHIP_MACH64LI, "3D RAGE LT PRO (Mach64 LI, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1_1 | M64F_G3_PB_1024x768 },
 410         { PCI_CHIP_MACH64LP, "3D RAGE LT PRO (Mach64 LP, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1024x768 },
 411         { PCI_CHIP_MACH64LQ, "3D RAGE LT PRO (Mach64 LQ, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
 412
 413         { PCI_CHIP_MACH64GM, "3D RAGE XL (Mach64 GM, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
 414         { PCI_CHIP_MACH64GN, "3D RAGE XC (Mach64 GN, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
 415         { PCI_CHIP_MACH64GO, "3D RAGE XL (Mach64 GO, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
 416         { PCI_CHIP_MACH64GL, "3D RAGE XC (Mach64 GL, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
 417         { PCI_CHIP_MACH64GR, "3D RAGE XL (Mach64 GR, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL | M64F_SDRAM_MAGIC_PLL },
 418         { PCI_CHIP_MACH64GS, "3D RAGE XC (Mach64 GS, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL },
 419
 420         { PCI_CHIP_MACH64LM, "3D RAGE Mobility P/M (Mach64 LM, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
 421         { PCI_CHIP_MACH64LN, "3D RAGE Mobility L (Mach64 LN, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
 422         { PCI_CHIP_MACH64LR, "3D RAGE Mobility P/M (Mach64 LR, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
 423         { PCI_CHIP_MACH64LS, "3D RAGE Mobility L (Mach64 LS, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
 424 #endif /* CONFIG_FB_ATY_CT */
 425 };
 426
 427 /* can not fail */
 428 static int __devinit correct_chipset(struct atyfb_par *par)
 429 {
 430         u8 rev;
 431         u16 type;
 432         u32 chip_id;
 433         const char *name;
 434         int i;
 435
 436         for (i = ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
 437                 if (par->pci_id == aty_chips[i].pci_id)
 438                         break;
 439
 440         name = aty_chips[i].name;
 441         par->pll_limits.pll_max = aty_chips[i].pll;
 442         par->pll_limits.mclk = aty_chips[i].mclk;
 443         par->pll_limits.xclk = aty_chips[i].xclk;
 444         par->pll_limits.ecp_max = aty_chips[i].ecp_max;
 445         par->features = aty_chips[i].features;
 446
 447         chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
 448         type = chip_id & CFG_CHIP_TYPE;
 449         rev = (chip_id & CFG_CHIP_REV) >> 24;
 450
 451         switch(par->pci_id) {
 452 #ifdef CONFIG_FB_ATY_GX
 453         case PCI_CHIP_MACH64GX:
 454                 if(type != 0x00d7)
 455                         return -ENODEV;
 456                 break;
 457         case PCI_CHIP_MACH64CX:
 458                 if(type != 0x0057)
 459                         return -ENODEV;
 460                 break;
 461 #endif
 462 #ifdef CONFIG_FB_ATY_CT
 463         case PCI_CHIP_MACH64VT:
 464                 switch (rev & 0x07) {
 465                 case 0x00:
 466                         switch (rev & 0xc0) {
 467                         case 0x00:
 468                                 name = "ATI264VT (A3) (Mach64 VT)";
 469                                 par->pll_limits.pll_max = 170;
 470                                 par->pll_limits.mclk = 67;
 471                                 par->pll_limits.xclk = 67;
 472                                 par->pll_limits.ecp_max = 80;
 473                                 par->features = ATI_CHIP_264VT;
 474                                 break;
 475                         case 0x40:
 476                                 name = "ATI264VT2 (A4) (Mach64 VT)";
 477                                 par->pll_limits.pll_max = 200;
 478                                 par->pll_limits.mclk = 67;
 479                                 par->pll_limits.xclk = 67;
 480                                 par->pll_limits.ecp_max = 80;
 481                                 par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
 482                                 break;
 483                         }
 484                         break;
 485                 case 0x01:
 486                         name = "ATI264VT3 (B1) (Mach64 VT)";
 487                         par->pll_limits.pll_max = 200;
 488                         par->pll_limits.mclk = 67;
 489                         par->pll_limits.xclk = 67;
 490                         par->pll_limits.ecp_max = 80;
 491                         par->features = ATI_CHIP_264VTB;
 492                         break;
 493                 case 0x02:
 494                         name = "ATI264VT3 (B2) (Mach64 VT)";
 495                         par->pll_limits.pll_max = 200;
 496                         par->pll_limits.mclk = 67;
 497                         par->pll_limits.xclk = 67;
 498                         par->pll_limits.ecp_max = 80;
 499                         par->features = ATI_CHIP_264VT3;
 500                         break;
 501                 }
 502                 break;
 503         case PCI_CHIP_MACH64GT:
 504                 switch (rev & 0x07) {
 505                 case 0x01:
 506                         name = "3D RAGE II (Mach64 GT)";
 507                         par->pll_limits.pll_max = 170;
 508                         par->pll_limits.mclk = 67;
 509                         par->pll_limits.xclk = 67;
 510                         par->pll_limits.ecp_max = 80;
 511                         par->features = ATI_CHIP_264GTB;
 512                         break;
 513                 case 0x02:
 514                         name = "3D RAGE II+ (Mach64 GT)";
 515                         par->pll_limits.pll_max = 200;
 516                         par->pll_limits.mclk = 67;
 517                         par->pll_limits.xclk = 67;
 518                         par->pll_limits.ecp_max = 100;
 519                         par->features = ATI_CHIP_264GTB;
 520                         break;
 521                 }
 522                 break;
 523 #endif
 524         }
 525
 526         PRINTKI("%s [0x%04x rev 0x%02x]\n", name, type, rev);
 527         return 0;
 528 }
 529
 530 static char ram_dram[] __devinitdata = "DRAM";
 531 static char ram_resv[] __devinitdata = "RESV";
 532 #ifdef CONFIG_FB_ATY_GX
 533 static char ram_vram[] __devinitdata = "VRAM";
 534 #endif /* CONFIG_FB_ATY_GX */
 535 #ifdef CONFIG_FB_ATY_CT
 536 static char ram_edo[] __devinitdata = "EDO";
 537 static char ram_sdram[] __devinitdata = "SDRAM (1:1)";
 538 static char ram_sgram[] __devinitdata = "SGRAM (1:1)";
 539 static char ram_sdram32[] __devinitdata = "SDRAM (2:1) (32-bit)";
 540 static char ram_off[] __devinitdata = "OFF";
 541 #endif /* CONFIG_FB_ATY_CT */
 542
 543
 544 #ifdef CONFIG_FB_ATY_GX
 545 static char *aty_gx_ram[8] __devinitdata = {
 546         ram_dram, ram_vram, ram_vram, ram_dram,
 547         ram_dram, ram_vram, ram_vram, ram_resv
 548 };
 549 #endif /* CONFIG_FB_ATY_GX */
 550
 551 #ifdef CONFIG_FB_ATY_CT
 552 static char *aty_ct_ram[8] __devinitdata = {
 553         ram_off, ram_dram, ram_edo, ram_edo,
 554         ram_sdram, ram_sgram, ram_sdram32, ram_resv
 555 };
 556 #endif /* CONFIG_FB_ATY_CT */
 557
 558 static u32 atyfb_get_pixclock(struct fb_var_screeninfo *var, struct atyfb_par *par)
 559 {
 560         u32 pixclock = var->pixclock;
 561 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 562         u32 lcd_on_off;
 563         par->pll.ct.xres = 0;
 564         if (par->lcd_table != 0) {
 565                 lcd_on_off = aty_ld_lcd(LCD_GEN_CNTL, par);
 566                 if(lcd_on_off & LCD_ON) {
 567                         par->pll.ct.xres = var->xres;
 568                         pixclock = par->lcd_pixclock;
 569                 }
 570         }
 571 #endif
 572         return pixclock;
 573 }
 574
 575 #if defined(CONFIG_PPC)
 576
 577 /*
 578  *  Apple monitor sense
 579  */
 580
 581 static int __devinit read_aty_sense(const struct atyfb_par *par)
 582 {
 583         int sense, i;
 584
 585         aty_st_le32(GP_IO, 0x31003100, par); /* drive outputs high */
 586         __delay(200);
 587         aty_st_le32(GP_IO, 0, par); /* turn off outputs */
 588         __delay(2000);
 589         i = aty_ld_le32(GP_IO, par); /* get primary sense value */
 590         sense = ((i & 0x3000) >> 3) | (i & 0x100);
 591
 592         /* drive each sense line low in turn and collect the other 2 */
 593         aty_st_le32(GP_IO, 0x20000000, par); /* drive A low */
 594         __delay(2000);
 595         i = aty_ld_le32(GP_IO, par);
 596         sense |= ((i & 0x1000) >> 7) | ((i & 0x100) >> 4);
 597         aty_st_le32(GP_IO, 0x20002000, par); /* drive A high again */
 598         __delay(200);
 599
 600         aty_st_le32(GP_IO, 0x10000000, par); /* drive B low */
 601         __delay(2000);
 602         i = aty_ld_le32(GP_IO, par);
 603         sense |= ((i & 0x2000) >> 10) | ((i & 0x100) >> 6);
 604         aty_st_le32(GP_IO, 0x10001000, par); /* drive B high again */
 605         __delay(200);
 606
 607         aty_st_le32(GP_IO, 0x01000000, par); /* drive C low */
 608         __delay(2000);
 609         sense |= (aty_ld_le32(GP_IO, par) & 0x3000) >> 12;
 610         aty_st_le32(GP_IO, 0, par); /* turn off outputs */
 611         return sense;
 612 }
 613
 614 #endif /* defined(CONFIG_PPC) */
 615
 616 /* ------------------------------------------------------------------------- */
 617
 618 /*
 619  *  CRTC programming
 620  */
 621
 622 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc)
 623 {
 624 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 625         if (par->lcd_table != 0) {
 626                 if(!M64_HAS(LT_LCD_REGS)) {
 627                     crtc->lcd_index = aty_ld_le32(LCD_INDEX, par);
 628                     aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
 629                 }
 630                 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par);
 631                 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par);
 632
 633
 634                 /* switch to non shadow registers */
 635                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
 636                     ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
 637
 638                 /* save stretching */
 639                 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
 640                 crtc->vert_stretching = aty_ld_lcd(VERT_STRETCHING, par);
 641                 if (!M64_HAS(LT_LCD_REGS))
 642                         crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par);
 643         }
 644 #endif
 645         crtc->h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
 646         crtc->h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
 647         crtc->v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
 648         crtc->v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
 649         crtc->vline_crnt_vline = aty_ld_le32(CRTC_VLINE_CRNT_VLINE, par);
 650         crtc->off_pitch = aty_ld_le32(CRTC_OFF_PITCH, par);
 651         crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
 652
 653 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 654         if (par->lcd_table != 0) {
 655                 /* switch to shadow registers */
 656                 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
 657                         SHADOW_EN | SHADOW_RW_EN, par);
 658
 659                 crtc->shadow_h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
 660                 crtc->shadow_h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
 661                 crtc->shadow_v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
 662                 crtc->shadow_v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
 663
 664                 aty_st_le32(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
 665         }
 666 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
 667 }
 668
 669 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc)
 670 {
 671 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 672         if (par->lcd_table != 0) {
 673                 /* stop CRTC */
 674                 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~(CRTC_EXT_DISP_EN | CRTC_EN), par);
 675
 676                 /* update non-shadow registers first */
 677                 aty_st_lcd(CONFIG_PANEL, crtc->lcd_config_panel, par);
 678                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
 679                         ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
 680
 681                 /* temporarily disable stretching */
 682                 aty_st_lcd(HORZ_STRETCHING,
 683                         crtc->horz_stretching &
 684                         ~(HORZ_STRETCH_MODE | HORZ_STRETCH_EN), par);
 685                 aty_st_lcd(VERT_STRETCHING,
 686                         crtc->vert_stretching &
 687                         ~(VERT_STRETCH_RATIO1 | VERT_STRETCH_RATIO2 |
 688                         VERT_STRETCH_USE0 | VERT_STRETCH_EN), par);
 689         }
 690 #endif
 691         /* turn off CRT */
 692         aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~CRTC_EN, par);
 693
 694         DPRINTK("setting up CRTC\n");
 695         DPRINTK("set primary CRT to %ix%i %c%c composite %c\n",
 696             ((((crtc->h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->v_tot_disp>>16) & 0x7ff) + 1),
 697             (crtc->h_sync_strt_wid & 0x200000)?'N':'P', (crtc->v_sync_strt_wid & 0x200000)?'N':'P',
 698             (crtc->gen_cntl & CRTC_CSYNC_EN)?'P':'N');
 699
 700         DPRINTK("CRTC_H_TOTAL_DISP: %x\n",crtc->h_tot_disp);
 701         DPRINTK("CRTC_H_SYNC_STRT_WID: %x\n",crtc->h_sync_strt_wid);
 702         DPRINTK("CRTC_V_TOTAL_DISP: %x\n",crtc->v_tot_disp);
 703         DPRINTK("CRTC_V_SYNC_STRT_WID: %x\n",crtc->v_sync_strt_wid);
 704         DPRINTK("CRTC_OFF_PITCH: %x\n", crtc->off_pitch);
 705         DPRINTK("CRTC_VLINE_CRNT_VLINE: %x\n", crtc->vline_crnt_vline);
 706         DPRINTK("CRTC_GEN_CNTL: %x\n",crtc->gen_cntl);
 707
 708         aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, par);
 709         aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, par);
 710         aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, par);
 711         aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, par);
 712         aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, par);
 713         aty_st_le32(CRTC_VLINE_CRNT_VLINE, crtc->vline_crnt_vline, par);
 714
 715         aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, par);
 716 #if 0
 717         FIXME
 718         if (par->accel_flags & FB_ACCELF_TEXT)
 719                 aty_init_engine(par, info);
 720 #endif
 721 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 722         /* after setting the CRTC registers we should set the LCD registers. */
 723         if (par->lcd_table != 0) {
 724                 /* switch to shadow registers */
 725                 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
 726                         (SHADOW_EN | SHADOW_RW_EN), par);
 727
 728                 DPRINTK("set shadow CRT to %ix%i %c%c\n",
 729                     ((((crtc->shadow_h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->shadow_v_tot_disp>>16) & 0x7ff) + 1),
 730                     (crtc->shadow_h_sync_strt_wid & 0x200000)?'N':'P', (crtc->shadow_v_sync_strt_wid & 0x200000)?'N':'P');
 731
 732                 DPRINTK("SHADOW CRTC_H_TOTAL_DISP: %x\n", crtc->shadow_h_tot_disp);
 733                 DPRINTK("SHADOW CRTC_H_SYNC_STRT_WID: %x\n", crtc->shadow_h_sync_strt_wid);
 734                 DPRINTK("SHADOW CRTC_V_TOTAL_DISP: %x\n", crtc->shadow_v_tot_disp);
 735                 DPRINTK("SHADOW CRTC_V_SYNC_STRT_WID: %x\n", crtc->shadow_v_sync_strt_wid);
 736
 737                 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->shadow_h_tot_disp, par);
 738                 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->shadow_h_sync_strt_wid, par);
 739                 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->shadow_v_tot_disp, par);
 740                 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->shadow_v_sync_strt_wid, par);
 741
 742                 /* restore CRTC selection & shadow state and enable stretching */
 743                 DPRINTK("LCD_GEN_CNTL: %x\n", crtc->lcd_gen_cntl);
 744                 DPRINTK("HORZ_STRETCHING: %x\n", crtc->horz_stretching);
 745                 DPRINTK("VERT_STRETCHING: %x\n", crtc->vert_stretching);
 746                 if(!M64_HAS(LT_LCD_REGS))
 747                     DPRINTK("EXT_VERT_STRETCH: %x\n", crtc->ext_vert_stretch);
 748
 749                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
 750                 aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching, par);
 751                 aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching, par);
 752                 if(!M64_HAS(LT_LCD_REGS)) {
 753                     aty_st_lcd(EXT_VERT_STRETCH, crtc->ext_vert_stretch, par);
 754                     aty_ld_le32(LCD_INDEX, par);
 755                     aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
 756                 }
 757         }
 758 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
 759 }
 760
 761 static int aty_var_to_crtc(const struct fb_info *info,
 762         const struct fb_var_screeninfo *var, struct crtc *crtc)
 763 {
 764         struct atyfb_par *par = (struct atyfb_par *) info->par;
 765         u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
 766         u32 sync, vmode, vdisplay;
 767         u32 h_total, h_disp, h_sync_strt, h_sync_end, h_sync_dly, h_sync_wid, h_sync_pol;
 768         u32 v_total, v_disp, v_sync_strt, v_sync_end, v_sync_wid, v_sync_pol, c_sync;
 769         u32 pix_width, dp_pix_width, dp_chain_mask;
 770
 771         /* input */
 772         xres = var->xres;
 773         yres = var->yres;
 774         vxres = var->xres_virtual;
 775         vyres = var->yres_virtual;
 776         xoffset = var->xoffset;
 777         yoffset = var->yoffset;
 778         bpp = var->bits_per_pixel;
 779         if (bpp == 16)
 780                 bpp = (var->green.length == 5) ? 15 : 16;
 781         sync = var->sync;
 782         vmode = var->vmode;
 783
 784         /* convert (and round up) and validate */
 785         if (vxres < xres + xoffset)
 786                 vxres = xres + xoffset;
 787         h_disp = xres;
 788
 789         if (vyres < yres + yoffset)
 790                 vyres = yres + yoffset;
 791         v_disp = yres;
 792
 793         if (bpp <= 8) {
 794                 bpp = 8;
 795                 pix_width = CRTC_PIX_WIDTH_8BPP;
 796                 dp_pix_width =
 797                     HOST_8BPP | SRC_8BPP | DST_8BPP |
 798                     BYTE_ORDER_LSB_TO_MSB;
 799                 dp_chain_mask = DP_CHAIN_8BPP;
 800         } else if (bpp <= 15) {
 801                 bpp = 16;
 802                 pix_width = CRTC_PIX_WIDTH_15BPP;
 803                 dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
 804                     BYTE_ORDER_LSB_TO_MSB;
 805                 dp_chain_mask = DP_CHAIN_15BPP;
 806         } else if (bpp <= 16) {
 807                 bpp = 16;
 808                 pix_width = CRTC_PIX_WIDTH_16BPP;
 809                 dp_pix_width = HOST_16BPP | SRC_16BPP | DST_16BPP |
 810                     BYTE_ORDER_LSB_TO_MSB;
 811                 dp_chain_mask = DP_CHAIN_16BPP;
 812         } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
 813                 bpp = 24;
 814                 pix_width = CRTC_PIX_WIDTH_24BPP;
 815                 dp_pix_width =
 816                     HOST_8BPP | SRC_8BPP | DST_8BPP |
 817                     BYTE_ORDER_LSB_TO_MSB;
 818                 dp_chain_mask = DP_CHAIN_24BPP;
 819         } else if (bpp <= 32) {
 820                 bpp = 32;
 821                 pix_width = CRTC_PIX_WIDTH_32BPP;
 822                 dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
 823                     BYTE_ORDER_LSB_TO_MSB;
 824                 dp_chain_mask = DP_CHAIN_32BPP;
 825         } else
 826                 FAIL("invalid bpp");
 827
 828         if (vxres * vyres * bpp / 8 > info->fix.smem_len)
 829                 FAIL("not enough video RAM");
 830
 831         h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
 832         v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
 833
 834         if((xres > 1600) || (yres > 1200)) {
 835                 FAIL("MACH64 chips are designed for max 1600x1200\n"
 836                 "select anoter resolution.");
 837         }
 838         h_sync_strt = h_disp + var->right_margin;
 839         h_sync_end = h_sync_strt + var->hsync_len;
 840         h_sync_dly  = var->right_margin & 7;
 841         h_total = h_sync_end + h_sync_dly + var->left_margin;
 842
 843         v_sync_strt = v_disp + var->lower_margin;
 844         v_sync_end = v_sync_strt + var->vsync_len;
 845         v_total = v_sync_end + var->upper_margin;
 846
 847 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 848         if (par->lcd_table != 0) {
 849                 if(!M64_HAS(LT_LCD_REGS)) {
 850                     u32 lcd_index = aty_ld_le32(LCD_INDEX, par);
 851                     crtc->lcd_index = lcd_index &
 852                         ~(LCD_INDEX_MASK | LCD_DISPLAY_DIS | LCD_SRC_SEL | CRTC2_DISPLAY_DIS);
 853                     aty_st_le32(LCD_INDEX, lcd_index, par);
 854                 }
 855
 856                 if (!M64_HAS(MOBIL_BUS))
 857                         crtc->lcd_index |= CRTC2_DISPLAY_DIS;
 858
 859                 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par) | 0x4000;
 860                 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par) & ~CRTC_RW_SELECT;
 861
 862                 crtc->lcd_gen_cntl &=
 863                         ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 | TVCLK_PM_EN |
 864                         /*VCLK_DAC_PM_EN | USE_SHADOWED_VEND |*/
 865                         USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
 866                 crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR | LOCK_8DOT;
 867
 868                 if((crtc->lcd_gen_cntl & LCD_ON) &&
 869                         ((xres > par->lcd_width) || (yres > par->lcd_height))) {
 870                         /* We cannot display the mode on the LCD. If the CRT is enabled
 871                            we can turn off the LCD.
 872                            If the CRT is off, it isn't a good idea to switch it on; we don't
 873                            know if one is connected. So it's better to fail then.
 874                          */
 875                         if (crtc->lcd_gen_cntl & CRT_ON) {
 876                                 if (!(var->activate & FB_ACTIVATE_TEST))
 877                                         PRINTKI("Disable LCD panel, because video mode does not fit.\n");
 878                                 crtc->lcd_gen_cntl &= ~LCD_ON;
 879                                 /*aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);*/
 880                         } else {
 881                                 if (!(var->activate & FB_ACTIVATE_TEST))
 882                                         PRINTKE("Video mode exceeds size of LCD panel.\nConnect this computer to a conventional monitor if you really need this mode.\n");
 883                                 return -EINVAL;
 884                         }
 885                 }
 886         }
 887
 888         if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON)) {
 889                 int VScan = 1;
 890                 /* bpp -> bytespp, 1,4 -> 0; 8 -> 2; 15,16 -> 1; 24 -> 6; 32 -> 5
 891                 const u8 DFP_h_sync_dly_LT[] = { 0, 2, 1, 6, 5 };
 892                 const u8 ADD_to_strt_wid_and_dly_LT_DAC[] = { 0, 5, 6, 9, 9, 12, 12 };  */
 893
 894                 vmode &= ~(FB_VMODE_DOUBLE | FB_VMODE_INTERLACED);
 895
 896                 /* This is horror! When we simulate, say 640x480 on an 800x600
 897                    LCD monitor, the CRTC should be programmed 800x600 values for
 898                    the non visible part, but 640x480 for the visible part.
 899                    This code has been tested on a laptop with it's 1400x1050 LCD
 900                    monitor and a conventional monitor both switched on.
 901                    Tested modes: 1280x1024, 1152x864, 1024x768, 800x600,
 902                     works with little glitches also with DOUBLESCAN modes
 903                  */
 904                 if (yres < par->lcd_height) {
 905                         VScan = par->lcd_height / yres;
 906                         if(VScan > 1) {
 907                                 VScan = 2;
 908                                 vmode |= FB_VMODE_DOUBLE;
 909                         }
 910                 }
 911
 912                 h_sync_strt = h_disp + par->lcd_right_margin;
 913                 h_sync_end = h_sync_strt + par->lcd_hsync_len;
 914                 h_sync_dly = /*DFP_h_sync_dly[ ( bpp + 1 ) / 3 ]; */par->lcd_hsync_dly;
 915                 h_total = h_disp + par->lcd_hblank_len;
 916
 917                 v_sync_strt = v_disp + par->lcd_lower_margin / VScan;
 918                 v_sync_end = v_sync_strt + par->lcd_vsync_len / VScan;
 919                 v_total = v_disp + par->lcd_vblank_len / VScan;
 920         }
 921 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
 922
 923         h_disp = (h_disp >> 3) - 1;
 924         h_sync_strt = (h_sync_strt >> 3) - 1;
 925         h_sync_end = (h_sync_end >> 3) - 1;
 926         h_total = (h_total >> 3) - 1;
 927         h_sync_wid = h_sync_end - h_sync_strt;
 928
 929         FAIL_MAX("h_disp too large", h_disp, 0xff);
 930         FAIL_MAX("h_sync_strt too large", h_sync_strt, 0x1ff);
 931         /*FAIL_MAX("h_sync_wid too large", h_sync_wid, 0x1f);*/
 932         if(h_sync_wid > 0x1f)
 933                 h_sync_wid = 0x1f;
 934         FAIL_MAX("h_total too large", h_total, 0x1ff);
 935
 936         if (vmode & FB_VMODE_DOUBLE) {
 937                 v_disp <<= 1;
 938                 v_sync_strt <<= 1;
 939                 v_sync_end <<= 1;
 940                 v_total <<= 1;
 941         }
 942
 943         vdisplay = yres;
 944 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 945         if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON))
 946                 vdisplay  = par->lcd_height;
 947 #endif
 948
 949         v_disp--;
 950         v_sync_strt--;
 951         v_sync_end--;
 952         v_total--;
 953         v_sync_wid = v_sync_end - v_sync_strt;
 954
 955         FAIL_MAX("v_disp too large", v_disp, 0x7ff);
 956         FAIL_MAX("v_sync_stsrt too large", v_sync_strt, 0x7ff);
 957         /*FAIL_MAX("v_sync_wid too large", v_sync_wid, 0x1f);*/
 958         if(v_sync_wid > 0x1f)
 959                 v_sync_wid = 0x1f;
 960         FAIL_MAX("v_total too large", v_total, 0x7ff);
 961
 962         c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
 963
 964         /* output */
 965         crtc->vxres = vxres;
 966         crtc->vyres = vyres;
 967         crtc->xoffset = xoffset;
 968         crtc->yoffset = yoffset;
 969         crtc->bpp = bpp;
 970         crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19);
 971         crtc->vline_crnt_vline = 0;
 972
 973         crtc->h_tot_disp = h_total | (h_disp<<16);
 974         crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) |
 975                 ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) | (h_sync_pol<<21);
 976         crtc->v_tot_disp = v_total | (v_disp<<16);
 977         crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21);
 978
 979         /* crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_PRESERVED_MASK; */
 980         crtc->gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | pix_width | c_sync;
 981         crtc->gen_cntl |= CRTC_VGA_LINEAR;
 982
 983         /* Enable doublescan mode if requested */
 984         if (vmode & FB_VMODE_DOUBLE)
 985                 crtc->gen_cntl |= CRTC_DBL_SCAN_EN;
 986         /* Enable interlaced mode if requested */
 987         if (vmode & FB_VMODE_INTERLACED)
 988                 crtc->gen_cntl |= CRTC_INTERLACE_EN;
 989 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 990         if (par->lcd_table != 0) {
 991                 vdisplay = yres;
 992                 if(vmode & FB_VMODE_DOUBLE)
 993                         vdisplay <<= 1;
 994                 crtc->gen_cntl &= ~(CRTC2_EN | CRTC2_PIX_WIDTH);
 995                 crtc->lcd_gen_cntl &= ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 |
 996                         /*TVCLK_PM_EN | VCLK_DAC_PM_EN |*/
 997                         USE_SHADOWED_VEND | USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
 998                 crtc->lcd_gen_cntl |= (DONT_SHADOW_VPAR/* | LOCK_8DOT*/);
 999
1000                 /* MOBILITY M1 tested, FIXME: LT */
1001                 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
1002                 if (!M64_HAS(LT_LCD_REGS))
1003                         crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par) &
1004                                 ~(AUTO_VERT_RATIO | VERT_STRETCH_MODE | VERT_STRETCH_RATIO3);
1005
1006                 crtc->horz_stretching &=
1007                         ~(HORZ_STRETCH_RATIO | HORZ_STRETCH_LOOP | AUTO_HORZ_RATIO |
1008                         HORZ_STRETCH_MODE | HORZ_STRETCH_EN);
1009                 if (xres < par->lcd_width && crtc->lcd_gen_cntl & LCD_ON) {
1010                         do {
1011                                 /*
1012                                 * The horizontal blender misbehaves when HDisplay is less than a
1013                                 * a certain threshold (440 for a 1024-wide panel).  It doesn't
1014                                 * stretch such modes enough.  Use pixel replication instead of
1015                                 * blending to stretch modes that can be made to exactly fit the
1016                                 * panel width.  The undocumented "NoLCDBlend" option allows the
1017                                 * pixel-replicated mode to be slightly wider or narrower than the
1018                                 * panel width.  It also causes a mode that is exactly half as wide
1019                                 * as the panel to be pixel-replicated, rather than blended.
1020                                 */
1021                                 int HDisplay  = xres & ~7;
1022                                 int nStretch  = par->lcd_width / HDisplay;
1023                                 int Remainder = par->lcd_width % HDisplay;
1024
1025                                 if ((!Remainder && ((nStretch > 2))) ||
1026                                         (((HDisplay * 16) / par->lcd_width) < 7)) {
1027                                         static const char StretchLoops[] = {10, 12, 13, 15, 16};
1028                                         int horz_stretch_loop = -1, BestRemainder;
1029                                         int Numerator = HDisplay, Denominator = par->lcd_width;
1030                                         int Index = 5;
1031                                         ATIReduceRatio(&Numerator, &Denominator);
1032
1033                                         BestRemainder = (Numerator * 16) / Denominator;
1034                                         while (--Index >= 0) {
1035                                                 Remainder = ((Denominator - Numerator) * StretchLoops[Index]) %
1036                                                         Denominator;
1037                                                 if (Remainder < BestRemainder) {
1038                                                         horz_stretch_loop = Index;
1039                                                         if (!(BestRemainder = Remainder))
1040                                                                 break;
1041                                                 }
1042                                         }
1043
1044                                         if ((horz_stretch_loop >= 0) && !BestRemainder) {
1045                                                 int horz_stretch_ratio = 0, Accumulator = 0;
1046                                                 int reuse_previous = 1;
1047
1048                                                 Index = StretchLoops[horz_stretch_loop];
1049
1050                                                 while (--Index >= 0) {
1051                                                         if (Accumulator > 0)
1052                                                                 horz_stretch_ratio |= reuse_previous;
1053                                                         else
1054                                                                 Accumulator += Denominator;
1055                                                         Accumulator -= Numerator;
1056                                                         reuse_previous <<= 1;
1057                                                 }
1058
1059                                                 crtc->horz_stretching |= (HORZ_STRETCH_EN |
1060                                                         ((horz_stretch_loop & HORZ_STRETCH_LOOP) << 16) |
1061                                                         (horz_stretch_ratio & HORZ_STRETCH_RATIO));
1062                                                 break;      /* Out of the do { ... } while (0) */
1063                                         }
1064                                 }
1065
1066                                 crtc->horz_stretching |= (HORZ_STRETCH_MODE | HORZ_STRETCH_EN |
1067                                         (((HDisplay * (HORZ_STRETCH_BLEND + 1)) / par->lcd_width) & HORZ_STRETCH_BLEND));
1068                         } while (0);
1069                 }
1070
1071                 if (vdisplay < par->lcd_height && crtc->lcd_gen_cntl & LCD_ON) {
1072                         crtc->vert_stretching = (VERT_STRETCH_USE0 | VERT_STRETCH_EN |
1073                                 (((vdisplay * (VERT_STRETCH_RATIO0 + 1)) / par->lcd_height) & VERT_STRETCH_RATIO0));
1074
1075                         if (!M64_HAS(LT_LCD_REGS) &&
1076                             xres <= (M64_HAS(MOBIL_BUS)?1024:800))
1077                                 crtc->ext_vert_stretch |= VERT_STRETCH_MODE;
1078                 } else {
1079                         /*
1080                          * Don't use vertical blending if the mode is too wide or not
1081                          * vertically stretched.
1082                          */
1083                         crtc->vert_stretching = 0;
1084                 }
1085                 /* copy to shadow crtc */
1086                 crtc->shadow_h_tot_disp = crtc->h_tot_disp;
1087                 crtc->shadow_h_sync_strt_wid = crtc->h_sync_strt_wid;
1088                 crtc->shadow_v_tot_disp = crtc->v_tot_disp;
1089                 crtc->shadow_v_sync_strt_wid = crtc->v_sync_strt_wid;
1090         }
1091 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1092
1093         if (M64_HAS(MAGIC_FIFO)) {
1094                 /* FIXME: display FIFO low watermark values */
1095                 crtc->gen_cntl |= (aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_FIFO_LWM);
1096         }
1097         crtc->dp_pix_width = dp_pix_width;
1098         crtc->dp_chain_mask = dp_chain_mask;
1099
1100         return 0;
1101 }
1102
1103 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var)
1104 {
1105         u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
1106         u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid,
1107             h_sync_pol;
1108         u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1109         u32 pix_width;
1110         u32 double_scan, interlace;
1111
1112         /* input */
1113         h_total = crtc->h_tot_disp & 0x1ff;
1114         h_disp = (crtc->h_tot_disp >> 16) & 0xff;
1115         h_sync_strt = (crtc->h_sync_strt_wid & 0xff) | ((crtc->h_sync_strt_wid >> 4) & 0x100);
1116         h_sync_dly = (crtc->h_sync_strt_wid >> 8) & 0x7;
1117         h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x1f;
1118         h_sync_pol = (crtc->h_sync_strt_wid >> 21) & 0x1;
1119         v_total = crtc->v_tot_disp & 0x7ff;
1120         v_disp = (crtc->v_tot_disp >> 16) & 0x7ff;
1121         v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1122         v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1123         v_sync_pol = (crtc->v_sync_strt_wid >> 21) & 0x1;
1124         c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1125         pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1126         double_scan = crtc->gen_cntl & CRTC_DBL_SCAN_EN;
1127         interlace = crtc->gen_cntl & CRTC_INTERLACE_EN;
1128
1129         /* convert */
1130         xres = (h_disp + 1) * 8;
1131         yres = v_disp + 1;
1132         left = (h_total - h_sync_strt - h_sync_wid) * 8 - h_sync_dly;
1133         right = (h_sync_strt - h_disp) * 8 + h_sync_dly;
1134         hslen = h_sync_wid * 8;
1135         upper = v_total - v_sync_strt - v_sync_wid;
1136         lower = v_sync_strt - v_disp;
1137         vslen = v_sync_wid;
1138         sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1139             (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1140             (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1141
1142         switch (pix_width) {
1143 #if 0
1144         case CRTC_PIX_WIDTH_4BPP:
1145                 bpp = 4;
1146                 var->red.offset = 0;
1147                 var->red.length = 8;
1148                 var->green.offset = 0;
1149                 var->green.length = 8;
1150                 var->blue.offset = 0;
1151                 var->blue.length = 8;
1152                 var->transp.offset = 0;
1153                 var->transp.length = 0;
1154                 break;
1155 #endif
1156         case CRTC_PIX_WIDTH_8BPP:
1157                 bpp = 8;
1158                 var->red.offset = 0;
1159                 var->red.length = 8;
1160                 var->green.offset = 0;
1161                 var->green.length = 8;
1162                 var->blue.offset = 0;
1163                 var->blue.length = 8;
1164                 var->transp.offset = 0;
1165                 var->transp.length = 0;
1166                 break;
1167         case CRTC_PIX_WIDTH_15BPP:      /* RGB 555 */
1168                 bpp = 16;
1169                 var->red.offset = 10;
1170                 var->red.length = 5;
1171                 var->green.offset = 5;
1172                 var->green.length = 5;
1173                 var->blue.offset = 0;
1174                 var->blue.length = 5;
1175                 var->transp.offset = 0;
1176                 var->transp.length = 0;
1177                 break;
1178         case CRTC_PIX_WIDTH_16BPP:      /* RGB 565 */
1179                 bpp = 16;
1180                 var->red.offset = 11;
1181                 var->red.length = 5;
1182                 var->green.offset = 5;
1183                 var->green.length = 6;
1184                 var->blue.offset = 0;
1185                 var->blue.length = 5;
1186                 var->transp.offset = 0;
1187                 var->transp.length = 0;
1188                 break;
1189         case CRTC_PIX_WIDTH_24BPP:      /* RGB 888 */
1190                 bpp = 24;
1191                 var->red.offset = 16;
1192                 var->red.length = 8;
1193                 var->green.offset = 8;
1194                 var->green.length = 8;
1195                 var->blue.offset = 0;
1196                 var->blue.length = 8;
1197                 var->transp.offset = 0;
1198                 var->transp.length = 0;
1199                 break;
1200         case CRTC_PIX_WIDTH_32BPP:      /* ARGB 8888 */
1201                 bpp = 32;
1202                 var->red.offset = 16;
1203                 var->red.length = 8;
1204                 var->green.offset = 8;
1205                 var->green.length = 8;
1206                 var->blue.offset = 0;
1207                 var->blue.length = 8;
1208                 var->transp.offset = 24;
1209                 var->transp.length = 8;
1210                 break;
1211         default:
1212                 PRINTKE("Invalid pixel width\n");
1213                 return -EINVAL;
1214         }
1215
1216         /* output */
1217         var->xres = xres;
1218         var->yres = yres;
1219         var->xres_virtual = crtc->vxres;
1220         var->yres_virtual = crtc->vyres;
1221         var->bits_per_pixel = bpp;
1222         var->left_margin = left;
1223         var->right_margin = right;
1224         var->upper_margin = upper;
1225         var->lower_margin = lower;
1226         var->hsync_len = hslen;
1227         var->vsync_len = vslen;
1228         var->sync = sync;
1229         var->vmode = FB_VMODE_NONINTERLACED;
1230         /* In double scan mode, the vertical parameters are doubled, so we need to
1231            half them to get the right values.
1232            In interlaced mode the values are already correct, so no correction is
1233            necessary.
1234          */
1235         if (interlace)
1236                 var->vmode = FB_VMODE_INTERLACED;
1237
1238         if (double_scan) {
1239                 var->vmode = FB_VMODE_DOUBLE;
1240                 var->yres>>=1;
1241                 var->upper_margin>>=1;
1242                 var->lower_margin>>=1;
1243                 var->vsync_len>>=1;
1244         }
1245
1246         return 0;
1247 }
1248
1249 /* ------------------------------------------------------------------------- */
1250
1251 static int atyfb_set_par(struct fb_info *info)
1252 {
1253         struct atyfb_par *par = (struct atyfb_par *) info->par;
1254         struct fb_var_screeninfo *var = &info->var;
1255         u32 tmp, pixclock;
1256         int err;
1257 #ifdef DEBUG
1258         struct fb_var_screeninfo debug;
1259         u32 pixclock_in_ps;
1260 #endif
1261         if (par->asleep)
1262                 return 0;
1263
1264         if ((err = aty_var_to_crtc(info, var, &par->crtc)))
1265                 return err;
1266
1267         pixclock = atyfb_get_pixclock(var, par);
1268
1269         if (pixclock == 0) {
1270                 PRINTKE("Invalid pixclock\n");
1271                 return -EINVAL;
1272         } else {
1273                 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &par->pll)))
1274                         return err;
1275         }
1276
1277         par->accel_flags = var->accel_flags; /* hack */
1278
1279         if (var->accel_flags) {
1280                 info->fbops->fb_sync = atyfb_sync;
1281                 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1282         } else {
1283                 info->fbops->fb_sync = NULL;
1284                 info->flags |= FBINFO_HWACCEL_DISABLED;
1285         }
1286
1287         if (par->blitter_may_be_busy)
1288                 wait_for_idle(par);
1289
1290         aty_set_crtc(par, &par->crtc);
1291         par->dac_ops->set_dac(info, &par->pll, var->bits_per_pixel, par->accel_flags);
1292         par->pll_ops->set_pll(info, &par->pll);
1293
1294 #ifdef DEBUG
1295         if(par->pll_ops && par->pll_ops->pll_to_var)
1296                 pixclock_in_ps = par->pll_ops->pll_to_var(info, &(par->pll));
1297         else
1298                 pixclock_in_ps = 0;
1299
1300         if(0 == pixclock_in_ps) {
1301                 PRINTKE("ALERT ops->pll_to_var get 0\n");
1302                 pixclock_in_ps = pixclock;
1303         }
1304
1305         memset(&debug, 0, sizeof(debug));
1306         if(!aty_crtc_to_var(&(par->crtc), &debug)) {
1307                 u32 hSync, vRefresh;
1308                 u32 h_disp, h_sync_strt, h_sync_end, h_total;
1309                 u32 v_disp, v_sync_strt, v_sync_end, v_total;
1310
1311                 h_disp = debug.xres;
1312                 h_sync_strt = h_disp + debug.right_margin;
1313                 h_sync_end = h_sync_strt + debug.hsync_len;
1314                 h_total = h_sync_end + debug.left_margin;
1315                 v_disp = debug.yres;
1316                 v_sync_strt = v_disp + debug.lower_margin;
1317                 v_sync_end = v_sync_strt + debug.vsync_len;
1318                 v_total = v_sync_end + debug.upper_margin;
1319
1320                 hSync = 1000000000 / (pixclock_in_ps * h_total);
1321                 vRefresh = (hSync * 1000) / v_total;
1322                 if (par->crtc.gen_cntl & CRTC_INTERLACE_EN)
1323                 vRefresh *= 2;
1324                 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1325                 vRefresh /= 2;
1326
1327                 DPRINTK("atyfb_set_par\n");
1328                 DPRINTK(" Set Visible Mode to %ix%i-%i\n", var->xres, var->yres, var->bits_per_pixel);
1329                 DPRINTK(" Virtual resolution %ix%i, pixclock_in_ps %i (calculated %i)\n",
1330                         var->xres_virtual, var->yres_virtual, pixclock, pixclock_in_ps);
1331                 DPRINTK(" Dot clock:           %i MHz\n", 1000000 / pixclock_in_ps);
1332                 DPRINTK(" Horizontal sync:     %i kHz\n", hSync);
1333                 DPRINTK(" Vertical refresh:    %i Hz\n", vRefresh);
1334                 DPRINTK(" x  style: %i.%03i %i %i %i %i   %i %i %i %i\n",
1335                         1000000 / pixclock_in_ps, 1000000 % pixclock_in_ps,
1336                         h_disp, h_sync_strt, h_sync_end, h_total,
1337                         v_disp, v_sync_strt, v_sync_end, v_total);
1338                 DPRINTK(" fb style: %i  %i %i %i %i %i %i %i %i\n",
1339                         pixclock_in_ps,
1340                         debug.left_margin, h_disp, debug.right_margin, debug.hsync_len,
1341                         debug.upper_margin, v_disp, debug.lower_margin, debug.vsync_len);
1342         }
1343 #endif /* DEBUG */
1344
1345         if (!M64_HAS(INTEGRATED)) {
1346                 /* Don't forget MEM_CNTL */
1347                 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf0ffffff;
1348                 switch (var->bits_per_pixel) {
1349                 case 8:
1350                         tmp |= 0x02000000;
1351                         break;
1352                 case 16:
1353                         tmp |= 0x03000000;
1354                         break;
1355                 case 32:
1356                         tmp |= 0x06000000;
1357                         break;
1358                 }
1359                 aty_st_le32(MEM_CNTL, tmp, par);
1360         } else {
1361                 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf00fffff;
1362                 if (!M64_HAS(MAGIC_POSTDIV))
1363                         tmp |= par->mem_refresh_rate << 20;
1364                 switch (var->bits_per_pixel) {
1365                 case 8:
1366                 case 24:
1367                         tmp |= 0x00000000;
1368                         break;
1369                 case 16:
1370                         tmp |= 0x04000000;
1371                         break;
1372                 case 32:
1373                         tmp |= 0x08000000;
1374                         break;
1375                 }
1376                 if (M64_HAS(CT_BUS)) {
1377                         aty_st_le32(DAC_CNTL, 0x87010184, par);
1378                         aty_st_le32(BUS_CNTL, 0x680000f9, par);
1379                 } else if (M64_HAS(VT_BUS)) {
1380                         aty_st_le32(DAC_CNTL, 0x87010184, par);
1381                         aty_st_le32(BUS_CNTL, 0x680000f9, par);
1382                 } else if (M64_HAS(MOBIL_BUS)) {
1383                         aty_st_le32(DAC_CNTL, 0x80010102, par);
1384                         aty_st_le32(BUS_CNTL, 0x7b33a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1385                 } else {
1386                         /* GT */
1387                         aty_st_le32(DAC_CNTL, 0x86010102, par);
1388                         aty_st_le32(BUS_CNTL, 0x7b23a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1389                         aty_st_le32(EXT_MEM_CNTL, aty_ld_le32(EXT_MEM_CNTL, par) | 0x5000001, par);
1390                 }
1391                 aty_st_le32(MEM_CNTL, tmp, par);
1392         }
1393         aty_st_8(DAC_MASK, 0xff, par);
1394
1395         info->fix.line_length = var->xres_virtual * var->bits_per_pixel/8;
1396         info->fix.visual = var->bits_per_pixel <= 8 ?
1397                 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1398
1399         /* Initialize the graphics engine */
1400         if (par->accel_flags & FB_ACCELF_TEXT)
1401                 aty_init_engine(par, info);
1402
1403 #ifdef CONFIG_BOOTX_TEXT
1404         btext_update_display(info->fix.smem_start,
1405                 (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8,
1406                 ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1,
1407                 var->bits_per_pixel,
1408                 par->crtc.vxres * var->bits_per_pixel / 8);
1409 #endif /* CONFIG_BOOTX_TEXT */
1410 #if 0
1411         /* switch to accelerator mode */
1412         if (!(par->crtc.gen_cntl & CRTC_EXT_DISP_EN))
1413                 aty_st_le32(CRTC_GEN_CNTL, par->crtc.gen_cntl | CRTC_EXT_DISP_EN, par);
1414 #endif
1415 #ifdef DEBUG
1416 {
1417         /* dump non shadow CRTC, pll, LCD registers */
1418         int i; u32 base;
1419
1420         /* CRTC registers */
1421         base = 0x2000;
1422         printk("debug atyfb: Mach64 non-shadow register values:");
1423         for (i = 0; i < 256; i = i+4) {
1424                 if(i%16 == 0) printk("\ndebug atyfb: 0x%04X: ", base + i);
1425                 printk(" %08X", aty_ld_le32(i, par));
1426         }
1427         printk("\n\n");
1428
1429 #ifdef CONFIG_FB_ATY_CT
1430         /* PLL registers */
1431         base = 0x00;
1432         printk("debug atyfb: Mach64 PLL register values:");
1433         for (i = 0; i < 64; i++) {
1434                 if(i%16 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1435                 if(i%4 == 0)  printk(" ");
1436                 printk("%02X", aty_ld_pll_ct(i, par));
1437         }
1438         printk("\n\n");
1439 #endif  /* CONFIG_FB_ATY_CT */
1440
1441 #ifdef CONFIG_FB_ATY_GENERIC_LCD
1442         if (par->lcd_table != 0) {
1443                 /* LCD registers */
1444                 base = 0x00;
1445                 printk("debug atyfb: LCD register values:");
1446                 if(M64_HAS(LT_LCD_REGS)) {
1447                     for(i = 0; i <= POWER_MANAGEMENT; i++) {
1448                         if(i == EXT_VERT_STRETCH)
1449                             continue;
1450                         printk("\ndebug atyfb: 0x%04X: ", lt_lcd_regs[i]);
1451                         printk(" %08X", aty_ld_lcd(i, par));
1452                     }
1453
1454                 } else {
1455                     for (i = 0; i < 64; i++) {
1456                         if(i%4 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1457                         printk(" %08X", aty_ld_lcd(i, par));
1458                     }
1459                 }
1460                 printk("\n\n");
1461         }
1462 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1463 }
1464 #endif /* DEBUG */
1465         return 0;
1466 }
1467
1468 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1469 {
1470         struct atyfb_par *par = (struct atyfb_par *) info->par;
1471         int err;
1472         struct crtc crtc;
1473         union aty_pll pll;
1474         u32 pixclock;
1475
1476         memcpy(&pll, &(par->pll), sizeof(pll));
1477
1478         if((err = aty_var_to_crtc(info, var, &crtc)))
1479                 return err;
1480
1481         pixclock = atyfb_get_pixclock(var, par);
1482
1483         if (pixclock == 0) {
1484                 if (!(var->activate & FB_ACTIVATE_TEST))
1485                         PRINTKE("Invalid pixclock\n");
1486                 return -EINVAL;
1487         } else {
1488                 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &pll)))
1489                         return err;
1490         }
1491
1492         if (var->accel_flags & FB_ACCELF_TEXT)
1493                 info->var.accel_flags = FB_ACCELF_TEXT;
1494         else
1495                 info->var.accel_flags = 0;
1496
1497         aty_crtc_to_var(&crtc, var);
1498         var->pixclock = par->pll_ops->pll_to_var(info, &pll);
1499         return 0;
1500 }
1501
1502 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info)
1503 {
1504         u32 xoffset = info->var.xoffset;
1505         u32 yoffset = info->var.yoffset;
1506         u32 vxres = par->crtc.vxres;
1507         u32 bpp = info->var.bits_per_pixel;
1508
1509         par->crtc.off_pitch = ((yoffset * vxres + xoffset) * bpp / 64) | (vxres << 19);
1510 }
1511
1512
1513     /*
1514      *  Open/Release the frame buffer device
1515      */
1516
1517 static int atyfb_open(struct fb_info *info, int user)
1518 {
1519         struct atyfb_par *par = (struct atyfb_par *) info->par;
1520
1521         if (user) {
1522                 par->open++;
1523 #ifdef __sparc__
1524                 par->mmaped = 0;
1525 #endif
1526         }
1527         return (0);
1528 }
1529
1530 static irqreturn_t aty_irq(int irq, void *dev_id)
1531 {
1532         struct atyfb_par *par = dev_id;
1533         int handled = 0;
1534         u32 int_cntl;
1535
1536         spin_lock(&par->int_lock);
1537
1538         int_cntl = aty_ld_le32(CRTC_INT_CNTL, par);
1539
1540         if (int_cntl & CRTC_VBLANK_INT) {
1541                 /* clear interrupt */
1542                 aty_st_le32(CRTC_INT_CNTL, (int_cntl & CRTC_INT_EN_MASK) | CRTC_VBLANK_INT_AK, par);
1543                 par->vblank.count++;
1544                 if (par->vblank.pan_display) {
1545                         par->vblank.pan_display = 0;
1546                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1547                 }
1548                 wake_up_interruptible(&par->vblank.wait);
1549                 handled = 1;
1550         }
1551
1552         spin_unlock(&par->int_lock);
1553
1554         return IRQ_RETVAL(handled);
1555 }
1556
1557 static int aty_enable_irq(struct atyfb_par *par, int reenable)
1558 {
1559         u32 int_cntl;
1560
1561         if (!test_and_set_bit(0, &par->irq_flags)) {
1562                 if (request_irq(par->irq, aty_irq, IRQF_SHARED, "atyfb", par)) {
1563                         clear_bit(0, &par->irq_flags);
1564                         return -EINVAL;
1565                 }
1566                 spin_lock_irq(&par->int_lock);
1567                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1568                 /* clear interrupt */
1569                 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_AK, par);
1570                 /* enable interrupt */
1571                 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par);
1572                 spin_unlock_irq(&par->int_lock);
1573         } else if (reenable) {
1574                 spin_lock_irq(&par->int_lock);
1575                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1576                 if (!(int_cntl & CRTC_VBLANK_INT_EN)) {
1577                         printk("atyfb: someone disabled IRQ [%08x]\n", int_cntl);
1578                         /* re-enable interrupt */
1579                         aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par );
1580                 }
1581                 spin_unlock_irq(&par->int_lock);
1582         }
1583
1584         return 0;
1585 }
1586
1587 static int aty_disable_irq(struct atyfb_par *par)
1588 {
1589         u32 int_cntl;
1590
1591         if (test_and_clear_bit(0, &par->irq_flags)) {
1592                 if (par->vblank.pan_display) {
1593                         par->vblank.pan_display = 0;
1594                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1595                 }
1596                 spin_lock_irq(&par->int_lock);
1597                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1598                 /* disable interrupt */
1599                 aty_st_le32(CRTC_INT_CNTL, int_cntl & ~CRTC_VBLANK_INT_EN, par );
1600                 spin_unlock_irq(&par->int_lock);
1601                 free_irq(par->irq, par);
1602         }
1603
1604         return 0;
1605 }
1606
1607 static int atyfb_release(struct fb_info *info, int user)
1608 {
1609         struct atyfb_par *par = (struct atyfb_par *) info->par;
1610         if (user) {
1611                 par->open--;
1612                 mdelay(1);
1613                 wait_for_idle(par);
1614                 if (!par->open) {
1615 #ifdef __sparc__
1616                         int was_mmaped = par->mmaped;
1617
1618                         par->mmaped = 0;
1619
1620                         if (was_mmaped) {
1621                                 struct fb_var_screeninfo var;
1622
1623                                 /* Now reset the default display config, we have no
1624                                  * idea what the program(s) which mmap'd the chip did
1625                                  * to the configuration, nor whether it restored it
1626                                  * correctly.
1627                                  */
1628                                 var = default_var;
1629                                 if (noaccel)
1630                                         var.accel_flags &= ~FB_ACCELF_TEXT;
1631                                 else
1632                                         var.accel_flags |= FB_ACCELF_TEXT;
1633                                 if (var.yres == var.yres_virtual) {
1634                                         u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
1635                                         var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
1636                                         if (var.yres_virtual < var.yres)
1637                                                 var.yres_virtual = var.yres;
1638                                 }
1639                         }
1640 #endif
1641                         aty_disable_irq(par);
1642                 }
1643         }
1644         return (0);
1645 }
1646
1647     /*
1648      *  Pan or Wrap the Display
1649      *
1650      *  This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1651      */
1652
1653 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1654 {
1655         struct atyfb_par *par = (struct atyfb_par *) info->par;
1656         u32 xres, yres, xoffset, yoffset;
1657
1658         xres = (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8;
1659         yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1;
1660         if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1661                 yres >>= 1;
1662         xoffset = (var->xoffset + 7) & ~7;
1663         yoffset = var->yoffset;
1664         if (xoffset + xres > par->crtc.vxres || yoffset + yres > par->crtc.vyres)
1665                 return -EINVAL;
1666         info->var.xoffset = xoffset;
1667         info->var.yoffset = yoffset;
1668         if (par->asleep)
1669                 return 0;
1670
1671         set_off_pitch(par, info);
1672         if ((var->activate & FB_ACTIVATE_VBL) && !aty_enable_irq(par, 0)) {
1673                 par->vblank.pan_display = 1;
1674         } else {
1675                 par->vblank.pan_display = 0;
1676                 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1677         }
1678
1679         return 0;
1680 }
1681
1682 static int aty_waitforvblank(struct atyfb_par *par, u32 crtc)
1683 {
1684         struct aty_interrupt *vbl;
1685         unsigned int count;
1686         int ret;
1687
1688         switch (crtc) {
1689         case 0:
1690                 vbl = &par->vblank;
1691                 break;
1692         default:
1693                 return -ENODEV;
1694         }
1695
1696         ret = aty_enable_irq(par, 0);
1697         if (ret)
1698                 return ret;
1699
1700         count = vbl->count;
1701         ret = wait_event_interruptible_timeout(vbl->wait, count != vbl->count, HZ/10);
1702         if (ret < 0) {
1703                 return ret;
1704         }
1705         if (ret == 0) {
1706                 aty_enable_irq(par, 1);
1707                 return -ETIMEDOUT;
1708         }
1709
1710         return 0;
1711 }
1712
1713
1714 #ifdef DEBUG
1715 #define ATYIO_CLKR              0x41545900      /* ATY\00 */
1716 #define ATYIO_CLKW              0x41545901      /* ATY\01 */
1717
1718 struct atyclk {
1719         u32 ref_clk_per;
1720         u8 pll_ref_div;
1721         u8 mclk_fb_div;
1722         u8 mclk_post_div;       /* 1,2,3,4,8 */
1723         u8 mclk_fb_mult;        /* 2 or 4 */
1724         u8 xclk_post_div;       /* 1,2,3,4,8 */
1725         u8 vclk_fb_div;
1726         u8 vclk_post_div;       /* 1,2,3,4,6,8,12 */
1727         u32 dsp_xclks_per_row;  /* 0-16383 */
1728         u32 dsp_loop_latency;   /* 0-15 */
1729         u32 dsp_precision;      /* 0-7 */
1730         u32 dsp_on;             /* 0-2047 */
1731         u32 dsp_off;            /* 0-2047 */
1732 };
1733
1734 #define ATYIO_FEATR             0x41545902      /* ATY\02 */
1735 #define ATYIO_FEATW             0x41545903      /* ATY\03 */
1736 #endif
1737
1738 #ifndef FBIO_WAITFORVSYNC
1739 #define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
1740 #endif
1741
1742 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
1743 {
1744         struct atyfb_par *par = (struct atyfb_par *) info->par;
1745 #ifdef __sparc__
1746         struct fbtype fbtyp;
1747 #endif
1748
1749         switch (cmd) {
1750 #ifdef __sparc__
1751         case FBIOGTYPE:
1752                 fbtyp.fb_type = FBTYPE_PCI_GENERIC;
1753                 fbtyp.fb_width = par->crtc.vxres;
1754                 fbtyp.fb_height = par->crtc.vyres;
1755                 fbtyp.fb_depth = info->var.bits_per_pixel;
1756                 fbtyp.fb_cmsize = info->cmap.len;
1757                 fbtyp.fb_size = info->fix.smem_len;
1758                 if (copy_to_user((struct fbtype __user *) arg, &fbtyp, sizeof(fbtyp)))
1759                         return -EFAULT;
1760                 break;
1761 #endif /* __sparc__ */
1762
1763         case FBIO_WAITFORVSYNC:
1764                 {
1765                         u32 crtc;
1766
1767                         if (get_user(crtc, (__u32 __user *) arg))
1768                                 return -EFAULT;
1769
1770                         return aty_waitforvblank(par, crtc);
1771                 }
1772                 break;
1773
1774 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
1775         case ATYIO_CLKR:
1776                 if (M64_HAS(INTEGRATED)) {
1777                         struct atyclk clk;
1778                         union aty_pll *pll = &(par->pll);
1779                         u32 dsp_config = pll->ct.dsp_config;
1780                         u32 dsp_on_off = pll->ct.dsp_on_off;
1781                         clk.ref_clk_per = par->ref_clk_per;
1782                         clk.pll_ref_div = pll->ct.pll_ref_div;
1783                         clk.mclk_fb_div = pll->ct.mclk_fb_div;
1784                         clk.mclk_post_div = pll->ct.mclk_post_div_real;
1785                         clk.mclk_fb_mult = pll->ct.mclk_fb_mult;
1786                         clk.xclk_post_div = pll->ct.xclk_post_div_real;
1787                         clk.vclk_fb_div = pll->ct.vclk_fb_div;
1788                         clk.vclk_post_div = pll->ct.vclk_post_div_real;
1789                         clk.dsp_xclks_per_row = dsp_config & 0x3fff;
1790                         clk.dsp_loop_latency = (dsp_config >> 16) & 0xf;
1791                         clk.dsp_precision = (dsp_config >> 20) & 7;
1792                         clk.dsp_off = dsp_on_off & 0x7ff;
1793                         clk.dsp_on = (dsp_on_off >> 16) & 0x7ff;
1794                         if (copy_to_user((struct atyclk __user *) arg, &clk,
1795                                          sizeof(clk)))
1796                                 return -EFAULT;
1797                 } else
1798                         return -EINVAL;
1799                 break;
1800         case ATYIO_CLKW:
1801                 if (M64_HAS(INTEGRATED)) {
1802                         struct atyclk clk;
1803                         union aty_pll *pll = &(par->pll);
1804                         if (copy_from_user(&clk, (struct atyclk __user *) arg, sizeof(clk)))
1805                                 return -EFAULT;
1806                         par->ref_clk_per = clk.ref_clk_per;
1807                         pll->ct.pll_ref_div = clk.pll_ref_div;
1808                         pll->ct.mclk_fb_div = clk.mclk_fb_div;
1809                         pll->ct.mclk_post_div_real = clk.mclk_post_div;
1810                         pll->ct.mclk_fb_mult = clk.mclk_fb_mult;
1811                         pll->ct.xclk_post_div_real = clk.xclk_post_div;
1812                         pll->ct.vclk_fb_div = clk.vclk_fb_div;
1813                         pll->ct.vclk_post_div_real = clk.vclk_post_div;
1814                         pll->ct.dsp_config = (clk.dsp_xclks_per_row & 0x3fff) |
1815                                 ((clk.dsp_loop_latency & 0xf)<<16)| ((clk.dsp_precision & 7)<<20);
1816                         pll->ct.dsp_on_off = (clk.dsp_off & 0x7ff) | ((clk.dsp_on & 0x7ff)<<16);
1817                         /*aty_calc_pll_ct(info, &pll->ct);*/
1818                         aty_set_pll_ct(info, pll);
1819                 } else
1820                         return -EINVAL;
1821                 break;
1822         case ATYIO_FEATR:
1823                 if (get_user(par->features, (u32 __user *) arg))
1824                         return -EFAULT;
1825                 break;
1826         case ATYIO_FEATW:
1827                 if (put_user(par->features, (u32 __user *) arg))
1828                         return -EFAULT;
1829                 break;
1830 #endif /* DEBUG && CONFIG_FB_ATY_CT */
1831         default:
1832                 return -EINVAL;
1833         }
1834         return 0;
1835 }
1836
1837 static int atyfb_sync(struct fb_info *info)
1838 {
1839         struct atyfb_par *par = (struct atyfb_par *) info->par;
1840
1841         if (par->blitter_may_be_busy)
1842                 wait_for_idle(par);
1843         return 0;
1844 }
1845
1846 #ifdef __sparc__
1847 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
1848 {
1849         struct atyfb_par *par = (struct atyfb_par *) info->par;
1850         unsigned int size, page, map_size = 0;
1851         unsigned long map_offset = 0;
1852         unsigned long off;
1853         int i;
1854
1855         if (!par->mmap_map)
1856                 return -ENXIO;
1857
1858         if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1859                 return -EINVAL;
1860
1861         off = vma->vm_pgoff << PAGE_SHIFT;
1862         size = vma->vm_end - vma->vm_start;
1863
1864         /* To stop the swapper from even considering these pages. */
1865         vma->vm_flags |= (VM_IO | VM_RESERVED);
1866
1867         if (((vma->vm_pgoff == 0) && (size == info->fix.smem_len)) ||
1868             ((off == info->fix.smem_len) && (size == PAGE_SIZE)))
1869                 off += 0x8000000000000000UL;
1870
1871         vma->vm_pgoff = off >> PAGE_SHIFT;      /* propagate off changes */
1872
1873         /* Each page, see which map applies */
1874         for (page = 0; page < size;) {
1875                 map_size = 0;
1876                 for (i = 0; par->mmap_map[i].size; i++) {
1877                         unsigned long start = par->mmap_map[i].voff;
1878                         unsigned long end = start + par->mmap_map[i].size;
1879                         unsigned long offset = off + page;
1880
1881                         if (start > offset)
1882                                 continue;
1883                         if (offset >= end)
1884                                 continue;
1885
1886                         map_size = par->mmap_map[i].size - (offset - start);
1887                         map_offset =
1888                             par->mmap_map[i].poff + (offset - start);
1889                         break;
1890                 }
1891                 if (!map_size) {
1892                         page += PAGE_SIZE;
1893                         continue;
1894                 }
1895                 if (page + map_size > size)
1896                         map_size = size - page;
1897
1898                 pgprot_val(vma->vm_page_prot) &=
1899                     ~(par->mmap_map[i].prot_mask);
1900                 pgprot_val(vma->vm_page_prot) |= par->mmap_map[i].prot_flag;
1901
1902                 if (remap_pfn_range(vma, vma->vm_start + page,
1903                         map_offset >> PAGE_SHIFT, map_size, vma->vm_page_prot))
1904                         return -EAGAIN;
1905
1906                 page += map_size;
1907         }
1908
1909         if (!map_size)
1910                 return -EINVAL;
1911
1912         if (!par->mmaped)
1913                 par->mmaped = 1;
1914         return 0;
1915 }
1916 #endif /* __sparc__ */
1917
1918
1919
1920 #if defined(CONFIG_PM) && defined(CONFIG_PCI)
1921
1922 #ifdef CONFIG_PPC_PMAC
1923 /* Power management routines. Those are used for PowerBook sleep.
1924  */
1925 static int aty_power_mgmt(int sleep, struct atyfb_par *par)
1926 {
1927         u32 pm;
1928         int timeout;
1929
1930         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1931         pm = (pm & ~PWR_MGT_MODE_MASK) | PWR_MGT_MODE_REG;
1932         aty_st_lcd(POWER_MANAGEMENT, pm, par);
1933         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1934
1935         timeout = 2000;
1936         if (sleep) {
1937                 /* Sleep */
1938                 pm &= ~PWR_MGT_ON;
1939                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1940                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1941                 udelay(10);
1942                 pm &= ~(PWR_BLON | AUTO_PWR_UP);
1943                 pm |= SUSPEND_NOW;
1944                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1945                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1946                 udelay(10);
1947                 pm |= PWR_MGT_ON;
1948                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1949                 do {
1950                         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1951                         mdelay(1);
1952                         if ((--timeout) == 0)
1953                                 break;
1954                 } while ((pm & PWR_MGT_STATUS_MASK) != PWR_MGT_STATUS_SUSPEND);
1955         } else {
1956                 /* Wakeup */
1957                 pm &= ~PWR_MGT_ON;
1958                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1959                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1960                 udelay(10);
1961                 pm &= ~SUSPEND_NOW;
1962                 pm |= (PWR_BLON | AUTO_PWR_UP);
1963                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1964                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1965                 udelay(10);
1966                 pm |= PWR_MGT_ON;
1967                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1968                 do {
1969                         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1970                         mdelay(1);
1971                         if ((--timeout) == 0)
1972                                 break;
1973                 } while ((pm & PWR_MGT_STATUS_MASK) != 0);
1974         }
1975         mdelay(500);
1976
1977         return timeout ? 0 : -EIO;
1978 }
1979 #endif
1980
1981 static int atyfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1982 {
1983         struct fb_info *info = pci_get_drvdata(pdev);
1984         struct atyfb_par *par = (struct atyfb_par *) info->par;
1985
1986         if (state.event == pdev->dev.power.power_state.event)
1987                 return 0;
1988
1989         acquire_console_sem();
1990
1991         fb_set_suspend(info, 1);
1992
1993         /* Idle & reset engine */
1994         wait_for_idle(par);
1995         aty_reset_engine(par);
1996
1997         /* Blank display and LCD */
1998         atyfb_blank(FB_BLANK_POWERDOWN, info);
1999
2000         par->asleep = 1;
2001         par->lock_blank = 1;
2002
2003 #ifdef CONFIG_PPC_PMAC
2004         /* Set chip to "suspend" mode */
2005         if (aty_power_mgmt(1, par)) {
2006                 par->asleep = 0;
2007                 par->lock_blank = 0;
2008                 atyfb_blank(FB_BLANK_UNBLANK, info);
2009                 fb_set_suspend(info, 0);
2010                 release_console_sem();
2011                 return -EIO;
2012         }
2013 #else
2014         pci_set_power_state(pdev, pci_choose_state(pdev, state));
2015 #endif
2016
2017         release_console_sem();
2018
2019         pdev->dev.power.power_state = state;
2020
2021         return 0;
2022 }
2023
2024 static int atyfb_pci_resume(struct pci_dev *pdev)
2025 {
2026         struct fb_info *info = pci_get_drvdata(pdev);
2027         struct atyfb_par *par = (struct atyfb_par *) info->par;
2028
2029         if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2030                 return 0;
2031
2032         acquire_console_sem();
2033
2034 #ifdef CONFIG_PPC_PMAC
2035         if (pdev->dev.power.power_state.event == 2)
2036                 aty_power_mgmt(0, par);
2037 #else
2038         pci_set_power_state(pdev, PCI_D0);
2039 #endif
2040
2041         aty_resume_chip(info);
2042
2043         par->asleep = 0;
2044
2045         /* Restore display */
2046         atyfb_set_par(info);
2047
2048         /* Refresh */
2049         fb_set_suspend(info, 0);
2050
2051         /* Unblank */
2052         par->lock_blank = 0;
2053         atyfb_blank(FB_BLANK_UNBLANK, info);
2054
2055         release_console_sem();
2056
2057         pdev->dev.power.power_state = PMSG_ON;
2058
2059         return 0;
2060 }
2061
2062 #endif /*  defined(CONFIG_PM) && defined(CONFIG_PCI) */
2063
2064 /* Backlight */
2065 #ifdef CONFIG_FB_ATY_BACKLIGHT
2066 #define MAX_LEVEL 0xFF
2067
2068 static int aty_bl_get_level_brightness(struct atyfb_par *par, int level)
2069 {
2070         struct fb_info *info = pci_get_drvdata(par->pdev);
2071         int atylevel;
2072
2073         /* Get and convert the value */
2074         /* No locking of bl_curve since we read a single value */
2075         atylevel = info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL;
2076
2077         if (atylevel < 0)
2078                 atylevel = 0;
2079         else if (atylevel > MAX_LEVEL)
2080                 atylevel = MAX_LEVEL;
2081
2082         return atylevel;
2083 }
2084
2085 static int aty_bl_update_status(struct backlight_device *bd)
2086 {
2087         struct atyfb_par *par = bl_get_data(bd);
2088         unsigned int reg = aty_ld_lcd(LCD_MISC_CNTL, par);
2089         int level;
2090
2091         if (bd->props.power != FB_BLANK_UNBLANK ||
2092             bd->props.fb_blank != FB_BLANK_UNBLANK)
2093                 level = 0;
2094         else
2095                 level = bd->props.brightness;
2096
2097         reg |= (BLMOD_EN | BIASMOD_EN);
2098         if (level > 0) {
2099                 reg &= ~BIAS_MOD_LEVEL_MASK;
2100                 reg |= (aty_bl_get_level_brightness(par, level) << BIAS_MOD_LEVEL_SHIFT);
2101         } else {
2102                 reg &= ~BIAS_MOD_LEVEL_MASK;
2103                 reg |= (aty_bl_get_level_brightness(par, 0) << BIAS_MOD_LEVEL_SHIFT);
2104         }
2105         aty_st_lcd(LCD_MISC_CNTL, reg, par);
2106
2107         return 0;
2108 }
2109
2110 static int aty_bl_get_brightness(struct backlight_device *bd)
2111 {
2112         return bd->props.brightness;
2113 }
2114
2115 static struct backlight_ops aty_bl_data = {
2116         .get_brightness = aty_bl_get_brightness,
2117         .update_status  = aty_bl_update_status,
2118 };
2119
2120 static void aty_bl_init(struct atyfb_par *par)
2121 {
2122         struct fb_info *info = pci_get_drvdata(par->pdev);
2123         struct backlight_device *bd;
2124         char name[12];
2125
2126 #ifdef CONFIG_PMAC_BACKLIGHT
2127         if (!pmac_has_backlight_type("ati"))
2128                 return;
2129 #endif
2130
2131         snprintf(name, sizeof(name), "atybl%d", info->node);
2132
2133         bd = backlight_device_register(name, info->dev, par, &aty_bl_data);
2134         if (IS_ERR(bd)) {
2135                 info->bl_dev = NULL;
2136                 printk(KERN_WARNING "aty: Backlight registration failed\n");
2137                 goto error;
2138         }
2139
2140         info->bl_dev = bd;
2141         fb_bl_default_curve(info, 0,
2142                 0x3F * FB_BACKLIGHT_MAX / MAX_LEVEL,
2143                 0xFF * FB_BACKLIGHT_MAX / MAX_LEVEL);
2144
2145         bd->props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
2146         bd->props.brightness = bd->props.max_brightness;
2147         bd->props.power = FB_BLANK_UNBLANK;
2148         backlight_update_status(bd);
2149
2150         printk("aty: Backlight initialized (%s)\n", name);
2151
2152         return;
2153
2154 error:
2155         return;
2156 }
2157
2158 static void aty_bl_exit(struct backlight_device *bd)
2159 {
2160         backlight_device_unregister(bd);
2161         printk("aty: Backlight unloaded\n");
2162 }
2163
2164 #endif /* CONFIG_FB_ATY_BACKLIGHT */
2165
2166 static void __devinit aty_calc_mem_refresh(struct atyfb_par *par, int xclk)
2167 {
2168         const int ragepro_tbl[] = {
2169                 44, 50, 55, 66, 75, 80, 100
2170         };
2171         const int ragexl_tbl[] = {
2172                 50, 66, 75, 83, 90, 95, 100, 105,
2173                 110, 115, 120, 125, 133, 143, 166
2174         };
2175         const int *refresh_tbl;
2176         int i, size;
2177
2178         if (IS_XL(par->pci_id) || IS_MOBILITY(par->pci_id)) {
2179                 refresh_tbl = ragexl_tbl;
2180                 size = ARRAY_SIZE(ragexl_tbl);
2181         } else {
2182                 refresh_tbl = ragepro_tbl;
2183                 size = ARRAY_SIZE(ragepro_tbl);
2184         }
2185
2186         for (i=0; i < size; i++) {
2187                 if (xclk < refresh_tbl[i])
2188                 break;
2189         }
2190         par->mem_refresh_rate = i;
2191 }
2192
2193     /*
2194      *  Initialisation
2195      */
2196
2197 static struct fb_info *fb_list = NULL;
2198
2199 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2200 static int __devinit atyfb_get_timings_from_lcd(struct atyfb_par *par,
2201                                                 struct fb_var_screeninfo *var)
2202 {
2203         int ret = -EINVAL;
2204
2205         if (par->lcd_table != 0 && (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2206                 *var = default_var;
2207                 var->xres = var->xres_virtual = par->lcd_hdisp;
2208                 var->right_margin = par->lcd_right_margin;
2209                 var->left_margin = par->lcd_hblank_len -
2210                         (par->lcd_right_margin + par->lcd_hsync_dly +
2211                          par->lcd_hsync_len);
2212                 var->hsync_len = par->lcd_hsync_len + par->lcd_hsync_dly;
2213                 var->yres = var->yres_virtual = par->lcd_vdisp;
2214                 var->lower_margin = par->lcd_lower_margin;
2215                 var->upper_margin = par->lcd_vblank_len -
2216                         (par->lcd_lower_margin + par->lcd_vsync_len);
2217                 var->vsync_len = par->lcd_vsync_len;
2218                 var->pixclock = par->lcd_pixclock;
2219                 ret = 0;
2220         }
2221
2222         return ret;
2223 }
2224 #endif /* defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD) */
2225
2226 static int __devinit aty_init(struct fb_info *info)
2227 {
2228         struct atyfb_par *par = (struct atyfb_par *) info->par;
2229         const char *ramname = NULL, *xtal;
2230         int gtb_memsize, has_var = 0;
2231         struct fb_var_screeninfo var;
2232
2233         init_waitqueue_head(&par->vblank.wait);
2234         spin_lock_init(&par->int_lock);
2235
2236 #ifdef CONFIG_FB_ATY_GX
2237         if (!M64_HAS(INTEGRATED)) {
2238                 u32 stat0;
2239                 u8 dac_type, dac_subtype, clk_type;
2240                 stat0 = aty_ld_le32(CONFIG_STAT0, par);
2241                 par->bus_type = (stat0 >> 0) & 0x07;
2242                 par->ram_type = (stat0 >> 3) & 0x07;
2243                 ramname = aty_gx_ram[par->ram_type];
2244                 /* FIXME: clockchip/RAMDAC probing? */
2245                 dac_type = (aty_ld_le32(DAC_CNTL, par) >> 16) & 0x07;
2246 #ifdef CONFIG_ATARI
2247                 clk_type = CLK_ATI18818_1;
2248                 dac_type = (stat0 >> 9) & 0x07;
2249                 if (dac_type == 0x07)
2250                         dac_subtype = DAC_ATT20C408;
2251                 else
2252                         dac_subtype = (aty_ld_8(SCRATCH_REG1 + 1, par) & 0xF0) | dac_type;
2253 #else
2254                 dac_type = DAC_IBMRGB514;
2255                 dac_subtype = DAC_IBMRGB514;
2256                 clk_type = CLK_IBMRGB514;
2257 #endif
2258                 switch (dac_subtype) {
2259                 case DAC_IBMRGB514:
2260                         par->dac_ops = &aty_dac_ibm514;
2261                         break;
2262 #ifdef CONFIG_ATARI
2263                 case DAC_ATI68860_B:
2264                 case DAC_ATI68860_C:
2265                         par->dac_ops = &aty_dac_ati68860b;
2266                         break;
2267                 case DAC_ATT20C408:
2268                 case DAC_ATT21C498:
2269                         par->dac_ops = &aty_dac_att21c498;
2270                         break;
2271 #endif
2272                 default:
2273                         PRINTKI("aty_init: DAC type not implemented yet!\n");
2274                         par->dac_ops = &aty_dac_unsupported;
2275                         break;
2276                 }
2277                 switch (clk_type) {
2278 #ifdef CONFIG_ATARI
2279                 case CLK_ATI18818_1:
2280                         par->pll_ops = &aty_pll_ati18818_1;
2281                         break;
2282 #else
2283                 case CLK_IBMRGB514:
2284                         par->pll_ops = &aty_pll_ibm514;
2285                         break;
2286 #endif
2287 #if 0 /* dead code */
2288                 case CLK_STG1703:
2289                         par->pll_ops = &aty_pll_stg1703;
2290                         break;
2291                 case CLK_CH8398:
2292                         par->pll_ops = &aty_pll_ch8398;
2293                         break;
2294                 case CLK_ATT20C408:
2295                         par->pll_ops = &aty_pll_att20c408;
2296                         break;
2297 #endif
2298                 default:
2299                         PRINTKI("aty_init: CLK type not implemented yet!");
2300                         par->pll_ops = &aty_pll_unsupported;
2301                         break;
2302                 }
2303         }
2304 #endif /* CONFIG_FB_ATY_GX */
2305 #ifdef CONFIG_FB_ATY_CT
2306         if (M64_HAS(INTEGRATED)) {
2307                 par->dac_ops = &aty_dac_ct;
2308                 par->pll_ops = &aty_pll_ct;
2309                 par->bus_type = PCI;
2310                 par->ram_type = (aty_ld_le32(CONFIG_STAT0, par) & 0x07);
2311                 ramname = aty_ct_ram[par->ram_type];
2312                 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
2313                 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
2314                         par->pll_limits.mclk = 63;
2315                 /* Mobility + 32bit memory interface need halved XCLK. */
2316                 if (M64_HAS(MOBIL_BUS) && par->ram_type == SDRAM32)
2317                         par->pll_limits.xclk = (par->pll_limits.xclk + 1) >> 1;
2318         }
2319 #endif
2320 #ifdef CONFIG_PPC_PMAC
2321         /* The Apple iBook1 uses non-standard memory frequencies. We detect it
2322          * and set the frequency manually. */
2323         if (machine_is_compatible("PowerBook2,1")) {
2324                 par->pll_limits.mclk = 70;
2325                 par->pll_limits.xclk = 53;
2326         }
2327 #endif
2328
2329         /* Allow command line to override clocks. */
2330         if (pll)
2331                 par->pll_limits.pll_max = pll;
2332         if (mclk)
2333                 par->pll_limits.mclk = mclk;
2334         if (xclk)
2335                 par->pll_limits.xclk = xclk;
2336
2337         aty_calc_mem_refresh(par, par->pll_limits.xclk);
2338         par->pll_per = 1000000/par->pll_limits.pll_max;
2339         par->mclk_per = 1000000/par->pll_limits.mclk;
2340         par->xclk_per = 1000000/par->pll_limits.xclk;
2341
2342         par->ref_clk_per = 1000000000000ULL / 14318180;
2343         xtal = "14.31818";
2344
2345 #ifdef CONFIG_FB_ATY_CT
2346         if (M64_HAS(GTB_DSP)) {
2347                 u8 pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
2348
2349                 if (pll_ref_div) {
2350                         int diff1, diff2;
2351                         diff1 = 510 * 14 / pll_ref_div - par->pll_limits.pll_max;
2352                         diff2 = 510 * 29 / pll_ref_div - par->pll_limits.pll_max;
2353                         if (diff1 < 0)
2354                                 diff1 = -diff1;
2355                         if (diff2 < 0)
2356                                 diff2 = -diff2;
2357                         if (diff2 < diff1) {
2358                                 par->ref_clk_per = 1000000000000ULL / 29498928;
2359                                 xtal = "29.498928";
2360                         }
2361                 }
2362         }
2363 #endif /* CONFIG_FB_ATY_CT */
2364
2365         /* save previous video mode */
2366         aty_get_crtc(par, &saved_crtc);
2367         if(par->pll_ops->get_pll)
2368                 par->pll_ops->get_pll(info, &saved_pll);
2369
2370         par->mem_cntl = aty_ld_le32(MEM_CNTL, par);
2371         gtb_memsize = M64_HAS(GTB_DSP);
2372         if (gtb_memsize)
2373                 switch (par->mem_cntl & 0xF) {  /* 0xF used instead of MEM_SIZE_ALIAS */
2374                 case MEM_SIZE_512K:
2375                         info->fix.smem_len = 0x80000;
2376                         break;
2377                 case MEM_SIZE_1M:
2378                         info->fix.smem_len = 0x100000;
2379                         break;
2380                 case MEM_SIZE_2M_GTB:
2381                         info->fix.smem_len = 0x200000;
2382                         break;
2383                 case MEM_SIZE_4M_GTB:
2384                         info->fix.smem_len = 0x400000;
2385                         break;
2386                 case MEM_SIZE_6M_GTB:
2387                         info->fix.smem_len = 0x600000;
2388                         break;
2389                 case MEM_SIZE_8M_GTB:
2390                         info->fix.smem_len = 0x800000;
2391                         break;
2392                 default:
2393                         info->fix.smem_len = 0x80000;
2394         } else
2395                 switch (par->mem_cntl & MEM_SIZE_ALIAS) {
2396                 case MEM_SIZE_512K:
2397                         info->fix.smem_len = 0x80000;
2398                         break;
2399                 case MEM_SIZE_1M:
2400                         info->fix.smem_len = 0x100000;
2401                         break;
2402                 case MEM_SIZE_2M:
2403                         info->fix.smem_len = 0x200000;
2404                         break;
2405                 case MEM_SIZE_4M:
2406                         info->fix.smem_len = 0x400000;
2407                         break;
2408                 case MEM_SIZE_6M:
2409                         info->fix.smem_len = 0x600000;
2410                         break;
2411                 case MEM_SIZE_8M:
2412                         info->fix.smem_len = 0x800000;
2413                         break;
2414                 default:
2415                         info->fix.smem_len = 0x80000;
2416                 }
2417
2418         if (M64_HAS(MAGIC_VRAM_SIZE)) {
2419                 if (aty_ld_le32(CONFIG_STAT1, par) & 0x40000000)
2420                         info->fix.smem_len += 0x400000;
2421         }
2422
2423         if (vram) {
2424                 info->fix.smem_len = vram * 1024;
2425                 par->mem_cntl &= ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
2426                 if (info->fix.smem_len <= 0x80000)
2427                         par->mem_cntl |= MEM_SIZE_512K;
2428                 else if (info->fix.smem_len <= 0x100000)
2429                         par->mem_cntl |= MEM_SIZE_1M;
2430                 else if (info->fix.smem_len <= 0x200000)
2431                         par->mem_cntl |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
2432                 else if (info->fix.smem_len <= 0x400000)
2433                         par->mem_cntl |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
2434                 else if (info->fix.smem_len <= 0x600000)
2435                         par->mem_cntl |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
2436                 else
2437                         par->mem_cntl |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
2438                 aty_st_le32(MEM_CNTL, par->mem_cntl, par);
2439         }
2440
2441         /*
2442          *  Reg Block 0 (CT-compatible block) is at mmio_start
2443          *  Reg Block 1 (multimedia extensions) is at mmio_start - 0x400
2444          */
2445         if (M64_HAS(GX)) {
2446                 info->fix.mmio_len = 0x400;
2447                 info->fix.accel = FB_ACCEL_ATI_MACH64GX;
2448         } else if (M64_HAS(CT)) {
2449                 info->fix.mmio_len = 0x400;
2450                 info->fix.accel = FB_ACCEL_ATI_MACH64CT;
2451         } else if (M64_HAS(VT)) {
2452                 info->fix.mmio_start -= 0x400;
2453                 info->fix.mmio_len = 0x800;
2454                 info->fix.accel = FB_ACCEL_ATI_MACH64VT;
2455         } else {/* GT */
2456                 info->fix.mmio_start -= 0x400;
2457                 info->fix.mmio_len = 0x800;
2458                 info->fix.accel = FB_ACCEL_ATI_MACH64GT;
2459         }
2460
2461         PRINTKI("%d%c %s, %s MHz XTAL, %d MHz PLL, %d Mhz MCLK, %d MHz XCLK\n",
2462                info->fix.smem_len == 0x80000 ? 512 : (info->fix.smem_len >> 20),
2463                info->fix.smem_len == 0x80000 ? 'K' : 'M', ramname, xtal, par->pll_limits.pll_max,
2464                par->pll_limits.mclk, par->pll_limits.xclk);
2465
2466 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
2467         if (M64_HAS(INTEGRATED)) {
2468                 int i;
2469                 printk("debug atyfb: BUS_CNTL DAC_CNTL MEM_CNTL EXT_MEM_CNTL CRTC_GEN_CNTL "
2470                        "DSP_CONFIG DSP_ON_OFF CLOCK_CNTL\n"
2471                        "debug atyfb: %08x %08x %08x %08x     %08x      %08x   %08x   %08x\n"
2472                        "debug atyfb: PLL",
2473                         aty_ld_le32(BUS_CNTL, par), aty_ld_le32(DAC_CNTL, par),
2474                         aty_ld_le32(MEM_CNTL, par), aty_ld_le32(EXT_MEM_CNTL, par),
2475                         aty_ld_le32(CRTC_GEN_CNTL, par), aty_ld_le32(DSP_CONFIG, par),
2476                         aty_ld_le32(DSP_ON_OFF, par), aty_ld_le32(CLOCK_CNTL, par));
2477                 for (i = 0; i < 40; i++)
2478                         printk(" %02x", aty_ld_pll_ct(i, par));
2479                 printk("\n");
2480         }
2481 #endif
2482         if(par->pll_ops->init_pll)
2483                 par->pll_ops->init_pll(info, &par->pll);
2484         if (par->pll_ops->resume_pll)
2485                 par->pll_ops->resume_pll(info, &par->pll);
2486
2487         /*
2488          *  Last page of 8 MB (4 MB on ISA) aperture is MMIO,
2489          *  unless the auxiliary register aperture is used.
2490          */
2491
2492         if (!par->aux_start &&
2493                 (info->fix.smem_len == 0x800000 || (par->bus_type == ISA && info->fix.smem_len == 0x400000)))
2494                 info->fix.smem_len -= GUI_RESERVE;
2495
2496         /*
2497          *  Disable register access through the linear aperture
2498          *  if the auxiliary aperture is used so we can access
2499          *  the full 8 MB of video RAM on 8 MB boards.
2500          */
2501         if (par->aux_start)
2502                 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2503
2504 #ifdef CONFIG_MTRR
2505         par->mtrr_aper = -1;
2506         par->mtrr_reg = -1;
2507         if (!nomtrr) {
2508                 /* Cover the whole resource. */
2509                  par->mtrr_aper = mtrr_add(par->res_start, par->res_size, MTRR_TYPE_WRCOMB, 1);
2510                  if (par->mtrr_aper >= 0 && !par->aux_start) {
2511                         /* Make a hole for mmio. */
2512                         par->mtrr_reg = mtrr_add(par->res_start + 0x800000 - GUI_RESERVE,
2513                                 GUI_RESERVE, MTRR_TYPE_UNCACHABLE, 1);
2514                         if (par->mtrr_reg < 0) {
2515                                 mtrr_del(par->mtrr_aper, 0, 0);
2516                                 par->mtrr_aper = -1;
2517                         }
2518                  }
2519         }
2520 #endif
2521
2522         info->fbops = &atyfb_ops;
2523         info->pseudo_palette = par->pseudo_palette;
2524         info->flags = FBINFO_DEFAULT           |
2525                       FBINFO_HWACCEL_IMAGEBLIT |
2526                       FBINFO_HWACCEL_FILLRECT  |
2527                       FBINFO_HWACCEL_COPYAREA  |
2528                       FBINFO_HWACCEL_YPAN;
2529
2530 #ifdef CONFIG_PMAC_BACKLIGHT
2531         if (M64_HAS(G3_PB_1_1) && machine_is_compatible("PowerBook1,1")) {
2532                 /* these bits let the 101 powerbook wake up from sleep -- paulus */
2533                 aty_st_lcd(POWER_MANAGEMENT, aty_ld_lcd(POWER_MANAGEMENT, par)
2534                            | (USE_F32KHZ | TRISTATE_MEM_EN), par);
2535         } else
2536 #endif
2537         if (M64_HAS(MOBIL_BUS) && backlight) {
2538 #ifdef CONFIG_FB_ATY_BACKLIGHT
2539                 aty_bl_init (par);
2540 #endif
2541         }
2542
2543         memset(&var, 0, sizeof(var));
2544 #ifdef CONFIG_PPC
2545         if (machine_is(powermac)) {
2546                 /*
2547                  *  FIXME: The NVRAM stuff should be put in a Mac-specific file, as it
2548                  *         applies to all Mac video cards
2549                  */
2550                 if (mode) {
2551                         if (mac_find_mode(&var, info, mode, 8))
2552                                 has_var = 1;
2553                 } else {
2554                         if (default_vmode == VMODE_CHOOSE) {
2555                                 int sense;
2556                                 if (M64_HAS(G3_PB_1024x768))
2557                                         /* G3 PowerBook with 1024x768 LCD */
2558                                         default_vmode = VMODE_1024_768_60;
2559                                 else if (machine_is_compatible("iMac"))
2560                                         default_vmode = VMODE_1024_768_75;
2561                                 else if (machine_is_compatible
2562                                          ("PowerBook2,1"))
2563                                         /* iBook with 800x600 LCD */
2564                                         default_vmode = VMODE_800_600_60;
2565                                 else
2566                                         default_vmode = VMODE_640_480_67;
2567                                 sense = read_aty_sense(par);
2568                                 PRINTKI("monitor sense=%x, mode %d\n",
2569                                         sense,  mac_map_monitor_sense(sense));
2570                         }
2571                         if (default_vmode <= 0 || default_vmode > VMODE_MAX)
2572                                 default_vmode = VMODE_640_480_60;
2573                         if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
2574                                 default_cmode = CMODE_8;
2575                         if (!mac_vmode_to_var(default_vmode, default_cmode,
2576                                                &var))
2577                                 has_var = 1;
2578                 }
2579         }
2580
2581 #endif /* !CONFIG_PPC */
2582
2583 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2584         if (!atyfb_get_timings_from_lcd(par, &var))
2585                 has_var = 1;
2586 #endif
2587
2588         if (mode && fb_find_mode(&var, info, mode, NULL, 0, &defmode, 8))
2589                 has_var = 1;
2590
2591         if (!has_var)
2592                 var = default_var;
2593
2594         if (noaccel)
2595                 var.accel_flags &= ~FB_ACCELF_TEXT;
2596         else
2597                 var.accel_flags |= FB_ACCELF_TEXT;
2598
2599         if (comp_sync != -1) {
2600                 if (!comp_sync)
2601                         var.sync &= ~FB_SYNC_COMP_HIGH_ACT;
2602                 else
2603                         var.sync |= FB_SYNC_COMP_HIGH_ACT;
2604         }
2605
2606         if (var.yres == var.yres_virtual) {
2607                 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
2608                 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
2609                 if (var.yres_virtual < var.yres)
2610                         var.yres_virtual = var.yres;
2611         }
2612
2613         if (atyfb_check_var(&var, info)) {
2614                 PRINTKE("can't set default video mode\n");
2615                 goto aty_init_exit;
2616         }
2617
2618 #ifdef CONFIG_FB_ATY_CT
2619         if (!noaccel && M64_HAS(INTEGRATED))
2620                 aty_init_cursor(info);
2621 #endif /* CONFIG_FB_ATY_CT */
2622         info->var = var;
2623
2624         if (fb_alloc_cmap(&info->cmap, 256, 0) < 0)
2625                 goto aty_init_exit;
2626
2627         if (register_framebuffer(info) < 0) {
2628                 fb_dealloc_cmap(&info->cmap);
2629                 goto aty_init_exit;
2630         }
2631
2632         fb_list = info;
2633
2634         PRINTKI("fb%d: %s frame buffer device on %s\n",
2635                 info->node, info->fix.id, par->bus_type == ISA ? "ISA" : "PCI");
2636         return 0;
2637
2638 aty_init_exit:
2639         /* restore video mode */
2640         aty_set_crtc(par, &saved_crtc);
2641         par->pll_ops->set_pll(info, &saved_pll);
2642
2643 #ifdef CONFIG_MTRR
2644         if (par->mtrr_reg >= 0) {
2645             mtrr_del(par->mtrr_reg, 0, 0);
2646             par->mtrr_reg = -1;
2647         }
2648         if (par->mtrr_aper >= 0) {
2649             mtrr_del(par->mtrr_aper, 0, 0);
2650             par->mtrr_aper = -1;
2651         }
2652 #endif
2653         return -1;
2654 }
2655
2656 static void aty_resume_chip(struct fb_info *info)
2657 {
2658         struct atyfb_par *par = info->par;
2659
2660         aty_st_le32(MEM_CNTL, par->mem_cntl, par);
2661
2662         if (par->pll_ops->resume_pll)
2663                 par->pll_ops->resume_pll(info, &par->pll);
2664
2665         if (par->aux_start)
2666                 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2667 }
2668
2669 #ifdef CONFIG_ATARI
2670 static int __devinit store_video_par(char *video_str, unsigned char m64_num)
2671 {
2672         char *p;
2673         unsigned long vmembase, size, guiregbase;
2674
2675         PRINTKI("store_video_par() '%s' \n", video_str);
2676
2677         if (!(p = strsep(&video_str, ";")) || !*p)
2678                 goto mach64_invalid;
2679         vmembase = simple_strtoul(p, NULL, 0);
2680         if (!(p = strsep(&video_str, ";")) || !*p)
2681                 goto mach64_invalid;
2682         size = simple_strtoul(p, NULL, 0);
2683         if (!(p = strsep(&video_str, ";")) || !*p)
2684                 goto mach64_invalid;
2685         guiregbase = simple_strtoul(p, NULL, 0);
2686
2687         phys_vmembase[m64_num] = vmembase;
2688         phys_size[m64_num] = size;
2689         phys_guiregbase[m64_num] = guiregbase;
2690         PRINTKI("stored them all: $%08lX $%08lX $%08lX \n", vmembase, size,
2691                guiregbase);
2692         return 0;
2693
2694       mach64_invalid:
2695         phys_vmembase[m64_num] = 0;
2696         return -1;
2697 }
2698 #endif /* CONFIG_ATARI */
2699
2700     /*
2701      *  Blank the display.
2702      */
2703
2704 static int atyfb_blank(int blank, struct fb_info *info)
2705 {
2706         struct atyfb_par *par = (struct atyfb_par *) info->par;
2707         u32 gen_cntl;
2708
2709         if (par->lock_blank || par->asleep)
2710                 return 0;
2711
2712 #ifdef CONFIG_FB_ATY_BACKLIGHT
2713 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2714         if (par->lcd_table && blank > FB_BLANK_NORMAL &&
2715             (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2716                 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2717                 pm &= ~PWR_BLON;
2718                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2719         }
2720 #endif
2721
2722         gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
2723         gen_cntl &= ~0x400004c;
2724         switch (blank) {
2725                 case FB_BLANK_UNBLANK:
2726                         break;
2727                 case FB_BLANK_NORMAL:
2728                         gen_cntl |= 0x4000040;
2729                         break;
2730                 case FB_BLANK_VSYNC_SUSPEND:
2731                         gen_cntl |= 0x4000048;
2732                         break;
2733                 case FB_BLANK_HSYNC_SUSPEND:
2734                         gen_cntl |= 0x4000044;
2735                         break;
2736                 case FB_BLANK_POWERDOWN:
2737                         gen_cntl |= 0x400004c;
2738                         break;
2739         }
2740         aty_st_le32(CRTC_GEN_CNTL, gen_cntl, par);
2741
2742 #ifdef CONFIG_FB_ATY_BACKLIGHT
2743 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2744         if (par->lcd_table && blank <= FB_BLANK_NORMAL &&
2745             (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2746                 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2747                 pm |= PWR_BLON;
2748                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2749         }
2750 #endif
2751
2752         return 0;
2753 }
2754
2755 static void aty_st_pal(u_int regno, u_int red, u_int green, u_int blue,
2756                        const struct atyfb_par *par)
2757 {
2758         aty_st_8(DAC_W_INDEX, regno, par);
2759         aty_st_8(DAC_DATA, red, par);
2760         aty_st_8(DAC_DATA, green, par);
2761         aty_st_8(DAC_DATA, blue, par);
2762 }
2763
2764     /*
2765      *  Set a single color register. The values supplied are already
2766      *  rounded down to the hardware's capabilities (according to the
2767      *  entries in the var structure). Return != 0 for invalid regno.
2768      *  !! 4 & 8 =  PSEUDO, > 8 = DIRECTCOLOR
2769      */
2770
2771 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2772         u_int transp, struct fb_info *info)
2773 {
2774         struct atyfb_par *par = (struct atyfb_par *) info->par;
2775         int i, depth;
2776         u32 *pal = info->pseudo_palette;
2777
2778         depth = info->var.bits_per_pixel;
2779         if (depth == 16)
2780                 depth = (info->var.green.length == 5) ? 15 : 16;
2781
2782         if (par->asleep)
2783                 return 0;
2784
2785         if (regno > 255 ||
2786             (depth == 16 && regno > 63) ||
2787             (depth == 15 && regno > 31))
2788                 return 1;
2789
2790         red >>= 8;
2791         green >>= 8;
2792         blue >>= 8;
2793
2794         par->palette[regno].red = red;
2795         par->palette[regno].green = green;
2796         par->palette[regno].blue = blue;
2797
2798         if (regno < 16) {
2799                 switch (depth) {
2800                 case 15:
2801                         pal[regno] = (regno << 10) | (regno << 5) | regno;
2802                         break;
2803                 case 16:
2804                         pal[regno] = (regno << 11) | (regno << 5) | regno;
2805                         break;
2806                 case 24:
2807                         pal[regno] = (regno << 16) | (regno << 8) | regno;
2808                         break;
2809                 case 32:
2810                         i = (regno << 8) | regno;
2811                         pal[regno] = (i << 16) | i;
2812                         break;
2813                 }
2814         }
2815
2816         i = aty_ld_8(DAC_CNTL, par) & 0xfc;
2817         if (M64_HAS(EXTRA_BRIGHT))
2818                 i |= 0x2; /* DAC_CNTL | 0x2 turns off the extra brightness for gt */
2819         aty_st_8(DAC_CNTL, i, par);
2820         aty_st_8(DAC_MASK, 0xff, par);
2821
2822         if (M64_HAS(INTEGRATED)) {
2823                 if (depth == 16) {
2824                         if (regno < 32)
2825                                 aty_st_pal(regno << 3, red,
2826                                            par->palette[regno<<1].green,
2827                                            blue, par);
2828                         red = par->palette[regno>>1].red;
2829                         blue = par->palette[regno>>1].blue;
2830                         regno <<= 2;
2831                 } else if (depth == 15) {
2832                         regno <<= 3;
2833                         for(i = 0; i < 8; i++) {
2834                             aty_st_pal(regno + i, red, green, blue, par);
2835                         }
2836                 }
2837         }
2838         aty_st_pal(regno, red, green, blue, par);
2839
2840         return 0;
2841 }
2842
2843 #ifdef CONFIG_PCI
2844
2845 #ifdef __sparc__
2846
2847 static int __devinit atyfb_setup_sparc(struct pci_dev *pdev,
2848                         struct fb_info *info, unsigned long addr)
2849 {
2850         struct atyfb_par *par = info->par;
2851         struct device_node *dp;
2852         char prop[128];
2853         int node, len, i, j, ret;
2854         u32 mem, chip_id;
2855
2856         /*
2857          * Map memory-mapped registers.
2858          */
2859         par->ati_regbase = (void *)addr + 0x7ffc00UL;
2860         info->fix.mmio_start = addr + 0x7ffc00UL;
2861
2862         /*
2863          * Map in big-endian aperture.
2864          */
2865         info->screen_base = (char *) (addr + 0x800000UL);
2866         info->fix.smem_start = addr + 0x800000UL;
2867
2868         /*
2869          * Figure mmap addresses from PCI config space.
2870          * Split Framebuffer in big- and little-endian halfs.
2871          */
2872         for (i = 0; i < 6 && pdev->resource[i].start; i++)
2873                 /* nothing */ ;
2874         j = i + 4;
2875
2876         par->mmap_map = kcalloc(j, sizeof(*par->mmap_map), GFP_ATOMIC);
2877         if (!par->mmap_map) {
2878                 PRINTKE("atyfb_setup_sparc() can't alloc mmap_map\n");
2879                 return -ENOMEM;
2880         }
2881
2882         for (i = 0, j = 2; i < 6 && pdev->resource[i].start; i++) {
2883                 struct resource *rp = &pdev->resource[i];
2884                 int io, breg = PCI_BASE_ADDRESS_0 + (i << 2);
2885                 unsigned long base;
2886                 u32 size, pbase;
2887
2888                 base = rp->start;
2889
2890                 io = (rp->flags & IORESOURCE_IO);
2891
2892                 size = rp->end - base + 1;
2893
2894                 pci_read_config_dword(pdev, breg, &pbase);
2895
2896                 if (io)
2897                         size &= ~1;
2898
2899                 /*
2900                  * Map the framebuffer a second time, this time without
2901                  * the braindead _PAGE_IE setting. This is used by the
2902                  * fixed Xserver, but we need to maintain the old mapping
2903                  * to stay compatible with older ones...
2904                  */
2905                 if (base == addr) {
2906                         par->mmap_map[j].voff = (pbase + 0x10000000) & PAGE_MASK;
2907                         par->mmap_map[j].poff = base & PAGE_MASK;
2908                         par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2909                         par->mmap_map[j].prot_mask = _PAGE_CACHE;
2910                         par->mmap_map[j].prot_flag = _PAGE_E;
2911                         j++;
2912                 }
2913
2914                 /*
2915                  * Here comes the old framebuffer mapping with _PAGE_IE
2916                  * set for the big endian half of the framebuffer...
2917                  */
2918                 if (base == addr) {
2919                         par->mmap_map[j].voff = (pbase + 0x800000) & PAGE_MASK;
2920                         par->mmap_map[j].poff = (base + 0x800000) & PAGE_MASK;
2921                         par->mmap_map[j].size = 0x800000;
2922                         par->mmap_map[j].prot_mask = _PAGE_CACHE;
2923                         par->mmap_map[j].prot_flag = _PAGE_E | _PAGE_IE;
2924                         size -= 0x800000;
2925                         j++;
2926                 }
2927
2928                 par->mmap_map[j].voff = pbase & PAGE_MASK;
2929                 par->mmap_map[j].poff = base & PAGE_MASK;
2930                 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2931                 par->mmap_map[j].prot_mask = _PAGE_CACHE;
2932                 par->mmap_map[j].prot_flag = _PAGE_E;
2933                 j++;
2934         }
2935
2936         if((ret = correct_chipset(par)))
2937                 return ret;
2938
2939         if (IS_XL(pdev->device)) {
2940                 /*
2941                  * Fix PROMs idea of MEM_CNTL settings...
2942                  */
2943                 mem = aty_ld_le32(MEM_CNTL, par);
2944                 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
2945                 if (((chip_id & CFG_CHIP_TYPE) == VT_CHIP_ID) && !((chip_id >> 24) & 1)) {
2946                         switch (mem & 0x0f) {
2947                         case 3:
2948                                 mem = (mem & ~(0x0f)) | 2;
2949                                 break;
2950                         case 7:
2951                                 mem = (mem & ~(0x0f)) | 3;
2952                                 break;
2953                         case 9:
2954                                 mem = (mem & ~(0x0f)) | 4;
2955                                 break;
2956                         case 11:
2957                                 mem = (mem & ~(0x0f)) | 5;
2958                                 break;
2959                         default:
2960                                 break;
2961                         }
2962                         if ((aty_ld_le32(CONFIG_STAT0, par) & 7) >= SDRAM)
2963                                 mem &= ~(0x00700000);
2964                 }
2965                 mem &= ~(0xcf80e000);   /* Turn off all undocumented bits. */
2966                 aty_st_le32(MEM_CNTL, mem, par);
2967         }
2968
2969         /*
2970          * If this is the console device, we will set default video
2971          * settings to what the PROM left us with.
2972          */
2973         node = prom_getchild(prom_root_node);
2974         node = prom_searchsiblings(node, "aliases");
2975         if (node) {
2976                 len = prom_getproperty(node, "screen", prop, sizeof(prop));
2977                 if (len > 0) {
2978                         prop[len] = '\0';
2979                         node = prom_finddevice(prop);
2980                 } else
2981                         node = 0;
2982         }
2983
2984         dp = pci_device_to_OF_node(pdev);
2985         if (node == dp->node) {
2986                 struct fb_var_screeninfo *var = &default_var;
2987                 unsigned int N, P, Q, M, T, R;
2988                 u32 v_total, h_total;
2989                 struct crtc crtc;
2990                 u8 pll_regs[16];
2991                 u8 clock_cntl;
2992
2993                 crtc.vxres = prom_getintdefault(node, "width", 1024);
2994                 crtc.vyres = prom_getintdefault(node, "height", 768);
2995                 var->bits_per_pixel = prom_getintdefault(node, "depth", 8);
2996                 var->xoffset = var->yoffset = 0;
2997                 crtc.h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
2998                 crtc.h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
2999                 crtc.v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
3000                 crtc.v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
3001                 crtc.gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
3002                 aty_crtc_to_var(&crtc, var);
3003
3004                 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin;
3005                 v_total = var->yres + var->lower_margin + var->vsync_len + var->upper_margin;
3006
3007                 /*
3008                  * Read the PLL to figure actual Refresh Rate.
3009                  */
3010                 clock_cntl = aty_ld_8(CLOCK_CNTL, par);
3011                 /* DPRINTK("CLOCK_CNTL %02x\n", clock_cntl); */
3012                 for (i = 0; i < 16; i++)
3013                         pll_regs[i] = aty_ld_pll_ct(i, par);
3014
3015                 /*
3016                  * PLL Reference Divider M:
3017                  */
3018                 M = pll_regs[2];
3019
3020                 /*
3021                  * PLL Feedback Divider N (Dependant on CLOCK_CNTL):
3022                  */
3023                 N = pll_regs[7 + (clock_cntl & 3)];
3024
3025                 /*
3026                  * PLL Post Divider P (Dependant on CLOCK_CNTL):
3027                  */
3028                 P = 1 << (pll_regs[6] >> ((clock_cntl & 3) << 1));
3029
3030                 /*
3031                  * PLL Divider Q:
3032                  */
3033                 Q = N / P;
3034
3035                 /*
3036                  * Target Frequency:
3037                  *
3038                  *      T * M
3039                  * Q = -------
3040                  *      2 * R
3041                  *
3042                  * where R is XTALIN (= 14318 or 29498 kHz).
3043                  */
3044                 if (IS_XL(pdev->device))
3045                         R = 29498;
3046                 else
3047                         R = 14318;
3048
3049                 T = 2 * Q * R / M;
3050
3051                 default_var.pixclock = 1000000000 / T;
3052         }
3053
3054         return 0;
3055 }
3056
3057 #else /* __sparc__ */
3058
3059 #ifdef __i386__
3060 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3061 static void __devinit aty_init_lcd(struct atyfb_par *par, u32 bios_base)
3062 {
3063         u32 driv_inf_tab, sig;
3064         u16 lcd_ofs;
3065
3066         /* To support an LCD panel, we should know it's dimensions and
3067          *  it's desired pixel clock.
3068          * There are two ways to do it:
3069          *  - Check the startup video mode and calculate the panel
3070          *    size from it. This is unreliable.
3071          *  - Read it from the driver information table in the video BIOS.
3072         */
3073         /* Address of driver information table is at offset 0x78. */
3074         driv_inf_tab = bios_base + *((u16 *)(bios_base+0x78));
3075
3076         /* Check for the driver information table signature. */
3077         sig = (*(u32 *)driv_inf_tab);
3078         if ((sig == 0x54504c24) || /* Rage LT pro */
3079                 (sig == 0x544d5224) || /* Rage mobility */
3080                 (sig == 0x54435824) || /* Rage XC */
3081                 (sig == 0x544c5824)) { /* Rage XL */
3082                 PRINTKI("BIOS contains driver information table.\n");
3083                 lcd_ofs = (*(u16 *)(driv_inf_tab + 10));
3084                 par->lcd_table = 0;
3085                 if (lcd_ofs != 0) {
3086                         par->lcd_table = bios_base + lcd_ofs;
3087                 }
3088         }
3089
3090         if (par->lcd_table != 0) {
3091                 char model[24];
3092                 char strbuf[16];
3093                 char refresh_rates_buf[100];
3094                 int id, tech, f, i, m, default_refresh_rate;
3095                 char *txtcolour;
3096                 char *txtmonitor;
3097                 char *txtdual;
3098                 char *txtformat;
3099                 u16 width, height, panel_type, refresh_rates;
3100                 u16 *lcdmodeptr;
3101                 u32 format;
3102                 u8 lcd_refresh_rates[16] = {50,56,60,67,70,72,75,76,85,90,100,120,140,150,160,200};
3103                 /* The most important information is the panel size at
3104                  * offset 25 and 27, but there's some other nice information
3105                  * which we print to the screen.
3106                  */
3107                 id = *(u8 *)par->lcd_table;
3108                 strncpy(model,(char *)par->lcd_table+1,24);
3109                 model[23]=0;
3110
3111                 width = par->lcd_width = *(u16 *)(par->lcd_table+25);
3112                 height = par->lcd_height = *(u16 *)(par->lcd_table+27);
3113                 panel_type = *(u16 *)(par->lcd_table+29);
3114                 if (panel_type & 1)
3115                         txtcolour = "colour";
3116                 else
3117                         txtcolour = "monochrome";
3118                 if (panel_type & 2)
3119                         txtdual = "dual (split) ";
3120                 else
3121                         txtdual = "";
3122                 tech = (panel_type>>2) & 63;
3123                 switch (tech) {
3124                 case 0:
3125                         txtmonitor = "passive matrix";
3126                         break;
3127                 case 1:
3128                         txtmonitor = "active matrix";
3129                         break;
3130                 case 2:
3131                         txtmonitor = "active addressed STN";
3132                         break;
3133                 case 3:
3134                         txtmonitor = "EL";
3135                         break;
3136                 case 4:
3137                         txtmonitor = "plasma";
3138                         break;
3139                 default:
3140                         txtmonitor = "unknown";
3141                 }
3142                 format = *(u32 *)(par->lcd_table+57);
3143                 if (tech == 0 || tech == 2) {
3144                         switch (format & 7) {
3145                         case 0:
3146                                 txtformat = "12 bit interface";
3147                                 break;
3148                         case 1:
3149                                 txtformat = "16 bit interface";
3150                                 break;
3151                         case 2:
3152                                 txtformat = "24 bit interface";
3153                                 break;
3154                         default:
3155                                 txtformat = "unkown format";
3156                         }
3157                 } else {
3158                         switch (format & 7) {
3159                         case 0:
3160                                 txtformat = "8 colours";
3161                                 break;
3162                         case 1:
3163                                 txtformat = "512 colours";
3164                                 break;
3165                         case 2:
3166                                 txtformat = "4096 colours";
3167                                 break;
3168                         case 4:
3169                                 txtformat = "262144 colours (LT mode)";
3170                                 break;
3171                         case 5:
3172                                 txtformat = "16777216 colours";
3173                                 break;
3174                         case 6:
3175                                 txtformat = "262144 colours (FDPI-2 mode)";
3176                                 break;
3177                         default:
3178                                 txtformat = "unkown format";
3179                         }
3180                 }
3181                 PRINTKI("%s%s %s monitor detected: %s\n",
3182                         txtdual ,txtcolour, txtmonitor, model);
3183                 PRINTKI("       id=%d, %dx%d pixels, %s\n",
3184                         id, width, height, txtformat);
3185                 refresh_rates_buf[0] = 0;
3186                 refresh_rates = *(u16 *)(par->lcd_table+62);
3187                 m = 1;
3188                 f = 0;
3189                 for (i=0;i<16;i++) {
3190                         if (refresh_rates & m) {
3191                                 if (f == 0) {
3192                                         sprintf(strbuf, "%d", lcd_refresh_rates[i]);
3193                                         f++;
3194                                 } else {
3195                                         sprintf(strbuf, ",%d", lcd_refresh_rates[i]);
3196                                 }
3197                                 strcat(refresh_rates_buf,strbuf);
3198                         }
3199                         m = m << 1;
3200                 }
3201                 default_refresh_rate = (*(u8 *)(par->lcd_table+61) & 0xf0) >> 4;
3202                 PRINTKI("       supports refresh rates [%s], default %d Hz\n",
3203                         refresh_rates_buf, lcd_refresh_rates[default_refresh_rate]);
3204                 par->lcd_refreshrate = lcd_refresh_rates[default_refresh_rate];
3205                 /* We now need to determine the crtc parameters for the
3206                  * LCD monitor. This is tricky, because they are not stored
3207                  * individually in the BIOS. Instead, the BIOS contains a
3208                  * table of display modes that work for this monitor.
3209                  *
3210                  * The idea is that we search for a mode of the same dimensions
3211                  * as the dimensions of the LCD monitor. Say our LCD monitor
3212                  * is 800x600 pixels, we search for a 800x600 monitor.
3213                  * The CRTC parameters we find here are the ones that we need
3214                  * to use to simulate other resolutions on the LCD screen.
3215                  */
3216                 lcdmodeptr = (u16 *)(par->lcd_table + 64);
3217                 while (*lcdmodeptr != 0) {
3218                         u32 modeptr;
3219                         u16 mwidth, mheight, lcd_hsync_start, lcd_vsync_start;
3220                         modeptr = bios_base + *lcdmodeptr;
3221
3222                         mwidth = *((u16 *)(modeptr+0));
3223                         mheight = *((u16 *)(modeptr+2));
3224
3225                         if (mwidth == width && mheight == height) {
3226                                 par->lcd_pixclock = 100000000 / *((u16 *)(modeptr+9));
3227                                 par->lcd_htotal = *((u16 *)(modeptr+17)) & 511;
3228                                 par->lcd_hdisp = *((u16 *)(modeptr+19)) & 511;
3229                                 lcd_hsync_start = *((u16 *)(modeptr+21)) & 511;
3230                                 par->lcd_hsync_dly = (*((u16 *)(modeptr+21)) >> 9) & 7;
3231                                 par->lcd_hsync_len = *((u8 *)(modeptr+23)) & 63;
3232
3233                                 par->lcd_vtotal = *((u16 *)(modeptr+24)) & 2047;
3234                                 par->lcd_vdisp = *((u16 *)(modeptr+26)) & 2047;
3235                                 lcd_vsync_start = *((u16 *)(modeptr+28)) & 2047;
3236                                 par->lcd_vsync_len = (*((u16 *)(modeptr+28)) >> 11) & 31;
3237
3238                                 par->lcd_htotal = (par->lcd_htotal + 1) * 8;
3239                                 par->lcd_hdisp = (par->lcd_hdisp + 1) * 8;
3240                                 lcd_hsync_start = (lcd_hsync_start + 1) * 8;
3241                                 par->lcd_hsync_len = par->lcd_hsync_len * 8;
3242
3243                                 par->lcd_vtotal++;
3244                                 par->lcd_vdisp++;
3245                                 lcd_vsync_start++;
3246
3247                                 par->lcd_right_margin = lcd_hsync_start - par->lcd_hdisp;
3248                                 par->lcd_lower_margin = lcd_vsync_start - par->lcd_vdisp;
3249                                 par->lcd_hblank_len = par->lcd_htotal - par->lcd_hdisp;
3250                                 par->lcd_vblank_len = par->lcd_vtotal - par->lcd_vdisp;
3251                                 break;
3252                         }
3253
3254                         lcdmodeptr++;
3255                 }
3256                 if (*lcdmodeptr == 0) {
3257                         PRINTKE("LCD monitor CRTC parameters not found!!!\n");
3258                         /* To do: Switch to CRT if possible. */
3259                 } else {
3260                         PRINTKI("       LCD CRTC parameters: %d.%d  %d %d %d %d  %d %d %d %d\n",
3261                                 1000000 / par->lcd_pixclock, 1000000 % par->lcd_pixclock,
3262                                 par->lcd_hdisp,
3263                                 par->lcd_hdisp + par->lcd_right_margin,
3264                                 par->lcd_hdisp + par->lcd_right_margin
3265                                         + par->lcd_hsync_dly + par->lcd_hsync_len,
3266                                 par->lcd_htotal,
3267                                 par->lcd_vdisp,
3268                                 par->lcd_vdisp + par->lcd_lower_margin,
3269                                 par->lcd_vdisp + par->lcd_lower_margin + par->lcd_vsync_len,
3270                                 par->lcd_vtotal);
3271                         PRINTKI("                          : %d %d %d %d %d %d %d %d %d\n",
3272                                 par->lcd_pixclock,
3273                                 par->lcd_hblank_len - (par->lcd_right_margin +
3274                                         par->lcd_hsync_dly + par->lcd_hsync_len),
3275                                 par->lcd_hdisp,
3276                                 par->lcd_right_margin,
3277                                 par->lcd_hsync_len,
3278                                 par->lcd_vblank_len - (par->lcd_lower_margin + par->lcd_vsync_len),
3279                                 par->lcd_vdisp,
3280                                 par->lcd_lower_margin,
3281                                 par->lcd_vsync_len);
3282                 }
3283         }
3284 }
3285 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
3286
3287 static int __devinit init_from_bios(struct atyfb_par *par)
3288 {
3289         u32 bios_base, rom_addr;
3290         int ret;
3291
3292         rom_addr = 0xc0000 + ((aty_ld_le32(SCRATCH_REG1, par) & 0x7f) << 11);
3293         bios_base = (unsigned long)ioremap(rom_addr, 0x10000);
3294
3295         /* The BIOS starts with 0xaa55. */
3296         if (*((u16 *)bios_base) == 0xaa55) {
3297
3298                 u8 *bios_ptr;
3299                 u16 rom_table_offset, freq_table_offset;
3300                 PLL_BLOCK_MACH64 pll_block;
3301
3302                 PRINTKI("Mach64 BIOS is located at %x, mapped at %x.\n", rom_addr, bios_base);
3303
3304                 /* check for frequncy table */
3305                 bios_ptr = (u8*)bios_base;
3306                 rom_table_offset = (u16)(bios_ptr[0x48] | (bios_ptr[0x49] << 8));
3307                 freq_table_offset = bios_ptr[rom_table_offset + 16] | (bios_ptr[rom_table_offset + 17] << 8);
3308                 memcpy(&pll_block, bios_ptr + freq_table_offset, sizeof(PLL_BLOCK_MACH64));
3309
3310                 PRINTKI("BIOS frequency table:\n");
3311                 PRINTKI("PCLK_min_freq %d, PCLK_max_freq %d, ref_freq %d, ref_divider %d\n",
3312                         pll_block.PCLK_min_freq, pll_block.PCLK_max_freq,
3313                         pll_block.ref_freq, pll_block.ref_divider);
3314                 PRINTKI("MCLK_pwd %d, MCLK_max_freq %d, XCLK_max_freq %d, SCLK_freq %d\n",
3315                         pll_block.MCLK_pwd, pll_block.MCLK_max_freq,
3316                         pll_block.XCLK_max_freq, pll_block.SCLK_freq);
3317
3318                 par->pll_limits.pll_min = pll_block.PCLK_min_freq/100;
3319                 par->pll_limits.pll_max = pll_block.PCLK_max_freq/100;
3320                 par->pll_limits.ref_clk = pll_block.ref_freq/100;
3321                 par->pll_limits.ref_div = pll_block.ref_divider;
3322                 par->pll_limits.sclk = pll_block.SCLK_freq/100;
3323                 par->pll_limits.mclk = pll_block.MCLK_max_freq/100;
3324                 par->pll_limits.mclk_pm = pll_block.MCLK_pwd/100;
3325                 par->pll_limits.xclk = pll_block.XCLK_max_freq/100;
3326 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3327                 aty_init_lcd(par, bios_base);
3328 #endif
3329                 ret = 0;
3330         } else {
3331                 PRINTKE("no BIOS frequency table found, use parameters\n");
3332                 ret = -ENXIO;
3333         }
3334         iounmap((void* __iomem )bios_base);
3335
3336         return ret;
3337 }
3338 #endif /* __i386__ */
3339
3340 static int __devinit atyfb_setup_generic(struct pci_dev *pdev, struct fb_info *info, unsigned long addr)
3341 {
3342         struct atyfb_par *par = info->par;
3343         u16 tmp;
3344         unsigned long raddr;
3345         struct resource *rrp;
3346         int ret = 0;
3347
3348         raddr = addr + 0x7ff000UL;
3349         rrp = &pdev->resource[2];
3350         if ((rrp->flags & IORESOURCE_MEM) && request_mem_region(rrp->start, rrp->end - rrp->start + 1, "atyfb")) {
3351                 par->aux_start = rrp->start;
3352                 par->aux_size = rrp->end - rrp->start + 1;
3353                 raddr = rrp->start;
3354                 PRINTKI("using auxiliary register aperture\n");
3355         }
3356
3357         info->fix.mmio_start = raddr;
3358         par->ati_regbase = ioremap(info->fix.mmio_start, 0x1000);
3359         if (par->ati_regbase == NULL)
3360                 return -ENOMEM;
3361
3362         info->fix.mmio_start += par->aux_start ? 0x400 : 0xc00;
3363         par->ati_regbase += par->aux_start ? 0x400 : 0xc00;
3364
3365         /*
3366          * Enable memory-space accesses using config-space
3367          * command register.
3368          */
3369         pci_read_config_word(pdev, PCI_COMMAND, &tmp);
3370         if (!(tmp & PCI_COMMAND_MEMORY)) {
3371                 tmp |= PCI_COMMAND_MEMORY;
3372                 pci_write_config_word(pdev, PCI_COMMAND, tmp);
3373         }
3374 #ifdef __BIG_ENDIAN
3375         /* Use the big-endian aperture */
3376         addr += 0x800000;
3377 #endif
3378
3379         /* Map in frame buffer */
3380         info->fix.smem_start = addr;
3381         info->screen_base = ioremap(addr, 0x800000);
3382         if (info->screen_base == NULL) {
3383                 ret = -ENOMEM;
3384                 goto atyfb_setup_generic_fail;
3385         }
3386
3387         if((ret = correct_chipset(par)))
3388                 goto atyfb_setup_generic_fail;
3389 #ifdef __i386__
3390         if((ret = init_from_bios(par)))
3391                 goto atyfb_setup_generic_fail;
3392 #endif
3393         if (!(aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_EXT_DISP_EN))
3394                 par->clk_wr_offset = (inb(R_GENMO) & 0x0CU) >> 2;
3395         else
3396                 par->clk_wr_offset = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
3397
3398         /* according to ATI, we should use clock 3 for acelerated mode */
3399         par->clk_wr_offset = 3;
3400
3401         return 0;
3402
3403 atyfb_setup_generic_fail:
3404         iounmap(par->ati_regbase);
3405         par->ati_regbase = NULL;
3406         if (info->screen_base) {
3407                 iounmap(info->screen_base);
3408                 info->screen_base = NULL;
3409         }
3410         return ret;
3411 }
3412
3413 #endif /* !__sparc__ */
3414
3415 static int __devinit atyfb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3416 {
3417         unsigned long addr, res_start, res_size;
3418         struct fb_info *info;
3419         struct resource *rp;
3420         struct atyfb_par *par;
3421         int i, rc = -ENOMEM;
3422
3423         for (i = ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
3424                 if (pdev->device == aty_chips[i].pci_id)
3425                         break;
3426
3427         if (i < 0)
3428                 return -ENODEV;
3429
3430         /* Enable device in PCI config */
3431         if (pci_enable_device(pdev)) {
3432                 PRINTKE("Cannot enable PCI device\n");
3433                 return -ENXIO;
3434         }
3435
3436         /* Find which resource to use */
3437         rp = &pdev->resource[0];
3438         if (rp->flags & IORESOURCE_IO)
3439                 rp = &pdev->resource[1];
3440         addr = rp->start;
3441         if (!addr)
3442                 return -ENXIO;
3443
3444         /* Reserve space */
3445         res_start = rp->start;
3446         res_size = rp->end - rp->start + 1;
3447         if (!request_mem_region (res_start, res_size, "atyfb"))
3448                 return -EBUSY;
3449
3450         /* Allocate framebuffer */
3451         info = framebuffer_alloc(sizeof(struct atyfb_par), &pdev->dev);
3452         if (!info) {
3453                 PRINTKE("atyfb_pci_probe() can't alloc fb_info\n");
3454                 return -ENOMEM;
3455         }
3456         par = info->par;
3457         info->fix = atyfb_fix;
3458         info->device = &pdev->dev;
3459         par->pci_id = aty_chips[i].pci_id;
3460         par->res_start = res_start;
3461         par->res_size = res_size;
3462         par->irq = pdev->irq;
3463         par->pdev = pdev;
3464
3465         /* Setup "info" structure */
3466 #ifdef __sparc__
3467         rc = atyfb_setup_sparc(pdev, info, addr);
3468 #else
3469         rc = atyfb_setup_generic(pdev, info, addr);
3470 #endif
3471         if (rc)
3472                 goto err_release_mem;
3473
3474         pci_set_drvdata(pdev, info);
3475
3476         /* Init chip & register framebuffer */
3477         if (aty_init(info))
3478                 goto err_release_io;
3479
3480 #ifdef __sparc__
3481         /*
3482          * Add /dev/fb mmap values.
3483          */
3484         par->mmap_map[0].voff = 0x8000000000000000UL;
3485         par->mmap_map[0].poff = (unsigned long) info->screen_base & PAGE_MASK;
3486         par->mmap_map[0].size = info->fix.smem_len;
3487         par->mmap_map[0].prot_mask = _PAGE_CACHE;
3488         par->mmap_map[0].prot_flag = _PAGE_E;
3489         par->mmap_map[1].voff = par->mmap_map[0].voff + info->fix.smem_len;
3490         par->mmap_map[1].poff = (long)par->ati_regbase & PAGE_MASK;
3491         par->mmap_map[1].size = PAGE_SIZE;
3492         par->mmap_map[1].prot_mask = _PAGE_CACHE;
3493         par->mmap_map[1].prot_flag = _PAGE_E;
3494 #endif /* __sparc__ */
3495
3496         return 0;
3497
3498 err_release_io:
3499 #ifdef __sparc__
3500         kfree(par->mmap_map);
3501 #else
3502         if (par->ati_regbase)
3503                 iounmap(par->ati_regbase);
3504         if (info->screen_base)
3505                 iounmap(info->screen_base);
3506 #endif
3507 err_release_mem:
3508         if (par->aux_start)
3509                 release_mem_region(par->aux_start, par->aux_size);
3510
3511         release_mem_region(par->res_start, par->res_size);
3512         framebuffer_release(info);
3513
3514         return rc;
3515 }
3516
3517 #endif /* CONFIG_PCI */
3518
3519 #ifdef CONFIG_ATARI
3520
3521 static int __init atyfb_atari_probe(void)
3522 {
3523         struct atyfb_par *par;
3524         struct fb_info *info;
3525         int m64_num;
3526         u32 clock_r;
3527         int num_found = 0;
3528
3529         for (m64_num = 0; m64_num < mach64_count; m64_num++) {
3530                 if (!phys_vmembase[m64_num] || !phys_size[m64_num] ||
3531                     !phys_guiregbase[m64_num]) {
3532                     PRINTKI("phys_*[%d] parameters not set => returning early. \n", m64_num);
3533                         continue;
3534                 }
3535
3536                 info = framebuffer_alloc(sizeof(struct atyfb_par), NULL);
3537                 if (!info) {
3538                         PRINTKE("atyfb_atari_probe() can't alloc fb_info\n");
3539                         return -ENOMEM;
3540                 }
3541                 par = info->par;
3542
3543                 info->fix = atyfb_fix;
3544
3545                 par->irq = (unsigned int) -1; /* something invalid */
3546
3547                 /*
3548                  *  Map the video memory (physical address given) to somewhere in the
3549                  *  kernel address space.
3550                  */
3551                 info->screen_base = ioremap(phys_vmembase[m64_num], phys_size[m64_num]);
3552                 info->fix.smem_start = (unsigned long)info->screen_base; /* Fake! */
3553                 par->ati_regbase = ioremap(phys_guiregbase[m64_num], 0x10000) +
3554                                                 0xFC00ul;
3555                 info->fix.mmio_start = (unsigned long)par->ati_regbase; /* Fake! */
3556
3557                 aty_st_le32(CLOCK_CNTL, 0x12345678, par);
3558                 clock_r = aty_ld_le32(CLOCK_CNTL, par);
3559
3560                 switch (clock_r & 0x003F) {
3561                 case 0x12:
3562                         par->clk_wr_offset = 3; /*  */
3563                         break;
3564                 case 0x34:
3565                         par->clk_wr_offset = 2; /* Medusa ST-IO ISA Adapter etc. */
3566                         break;
3567                 case 0x16:
3568                         par->clk_wr_offset = 1; /*  */
3569                         break;
3570                 case 0x38:
3571                         par->clk_wr_offset = 0; /* Panther 1 ISA Adapter (Gerald) */
3572                         break;
3573                 }
3574
3575                 /* Fake pci_id for correct_chipset() */
3576                 switch (aty_ld_le32(CONFIG_CHIP_ID, par) & CFG_CHIP_TYPE) {
3577                 case 0x00d7:
3578                         par->pci_id = PCI_CHIP_MACH64GX;
3579                         break;
3580                 case 0x0057:
3581                         par->pci_id = PCI_CHIP_MACH64CX;
3582                         break;
3583                 default:
3584                         break;
3585                 }
3586
3587                 if (correct_chipset(par) || aty_init(info)) {
3588                         iounmap(info->screen_base);
3589                         iounmap(par->ati_regbase);
3590                         framebuffer_release(info);
3591                 } else {
3592                         num_found++;
3593                 }
3594         }
3595
3596         return num_found ? 0 : -ENXIO;
3597 }
3598
3599 #endif /* CONFIG_ATARI */
3600
3601 #ifdef CONFIG_PCI
3602
3603 static void __devexit atyfb_remove(struct fb_info *info)
3604 {
3605         struct atyfb_par *par = (struct atyfb_par *) info->par;
3606
3607         /* restore video mode */
3608         aty_set_crtc(par, &saved_crtc);
3609         par->pll_ops->set_pll(info, &saved_pll);
3610
3611         unregister_framebuffer(info);
3612
3613 #ifdef CONFIG_FB_ATY_BACKLIGHT
3614         if (M64_HAS(MOBIL_BUS))
3615                 aty_bl_exit(info->bl_dev);
3616 #endif
3617
3618 #ifdef CONFIG_MTRR
3619         if (par->mtrr_reg >= 0) {
3620             mtrr_del(par->mtrr_reg, 0, 0);
3621             par->mtrr_reg = -1;
3622         }
3623         if (par->mtrr_aper >= 0) {
3624             mtrr_del(par->mtrr_aper, 0, 0);
3625             par->mtrr_aper = -1;
3626         }
3627 #endif
3628 #ifndef __sparc__
3629         if (par->ati_regbase)
3630                 iounmap(par->ati_regbase);
3631         if (info->screen_base)
3632                 iounmap(info->screen_base);
3633 #ifdef __BIG_ENDIAN
3634         if (info->sprite.addr)
3635                 iounmap(info->sprite.addr);
3636 #endif
3637 #endif
3638 #ifdef __sparc__
3639         kfree(par->mmap_map);
3640 #endif
3641         if (par->aux_start)
3642                 release_mem_region(par->aux_start, par->aux_size);
3643
3644         if (par->res_start)
3645                 release_mem_region(par->res_start, par->res_size);
3646
3647         framebuffer_release(info);
3648 }
3649
3650
3651 static void __devexit atyfb_pci_remove(struct pci_dev *pdev)
3652 {
3653         struct fb_info *info = pci_get_drvdata(pdev);
3654
3655         atyfb_remove(info);
3656 }
3657
3658 /*
3659  * This driver uses its own matching table. That will be more difficult
3660  * to fix, so for now, we just match against any ATI ID and let the
3661  * probe() function find out what's up. That also mean we don't have
3662  * a module ID table though.
3663  */
3664 static struct pci_device_id atyfb_pci_tbl[] = {
3665         { PCI_VENDOR_ID_ATI, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
3666           PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0 },
3667         { 0, }
3668 };
3669
3670 static struct pci_driver atyfb_driver = {
3671         .name           = "atyfb",
3672         .id_table       = atyfb_pci_tbl,
3673         .probe          = atyfb_pci_probe,
3674         .remove         = __devexit_p(atyfb_pci_remove),
3675 #ifdef CONFIG_PM
3676         .suspend        = atyfb_pci_suspend,
3677         .resume         = atyfb_pci_resume,
3678 #endif /* CONFIG_PM */
3679 };
3680
3681 #endif /* CONFIG_PCI */
3682
3683 #ifndef MODULE
3684 static int __init atyfb_setup(char *options)
3685 {
3686         char *this_opt;
3687
3688         if (!options || !*options)
3689                 return 0;
3690
3691         while ((this_opt = strsep(&options, ",")) != NULL) {
3692                 if (!strncmp(this_opt, "noaccel", 7)) {
3693                         noaccel = 1;
3694 #ifdef CONFIG_MTRR
3695                 } else if (!strncmp(this_opt, "nomtrr", 6)) {
3696                         nomtrr = 1;
3697 #endif
3698                 } else if (!strncmp(this_opt, "vram:", 5))
3699                         vram = simple_strtoul(this_opt + 5, NULL, 0);
3700                 else if (!strncmp(this_opt, "pll:", 4))
3701                         pll = simple_strtoul(this_opt + 4, NULL, 0);
3702                 else if (!strncmp(this_opt, "mclk:", 5))
3703                         mclk = simple_strtoul(this_opt + 5, NULL, 0);
3704                 else if (!strncmp(this_opt, "xclk:", 5))
3705                         xclk = simple_strtoul(this_opt+5, NULL, 0);
3706                 else if (!strncmp(this_opt, "comp_sync:", 10))
3707                         comp_sync = simple_strtoul(this_opt+10, NULL, 0);
3708                 else if (!strncmp(this_opt, "backlight:", 10))
3709                         backlight = simple_strtoul(this_opt+10, NULL, 0);
3710 #ifdef CONFIG_PPC
3711                 else if (!strncmp(this_opt, "vmode:", 6)) {
3712                         unsigned int vmode =
3713                             simple_strtoul(this_opt + 6, NULL, 0);
3714                         if (vmode > 0 && vmode <= VMODE_MAX)
3715                                 default_vmode = vmode;
3716                 } else if (!strncmp(this_opt, "cmode:", 6)) {
3717                         unsigned int cmode =
3718                             simple_strtoul(this_opt + 6, NULL, 0);
3719                         switch (cmode) {
3720                         case 0:
3721                         case 8:
3722                                 default_cmode = CMODE_8;
3723                                 break;
3724                         case 15:
3725                         case 16:
3726                                 default_cmode = CMODE_16;
3727                                 break;
3728                         case 24:
3729                         case 32:
3730                                 default_cmode = CMODE_32;
3731                                 break;
3732                         }
3733                 }
3734 #endif
3735 #ifdef CONFIG_ATARI
3736                 /*
3737                  * Why do we need this silly Mach64 argument?
3738                  * We are already here because of mach64= so its redundant.
3739                  */
3740                 else if (MACH_IS_ATARI
3741                          && (!strncmp(this_opt, "Mach64:", 7))) {
3742                         static unsigned char m64_num;
3743                         static char mach64_str[80];
3744                         strlcpy(mach64_str, this_opt + 7, sizeof(mach64_str));
3745                         if (!store_video_par(mach64_str, m64_num)) {
3746                                 m64_num++;
3747                                 mach64_count = m64_num;
3748                         }
3749                 }
3750 #endif
3751                 else
3752                         mode = this_opt;
3753         }
3754         return 0;
3755 }
3756 #endif  /*  MODULE  */
3757
3758 static int __init atyfb_init(void)
3759 {
3760     int err1 = 1, err2 = 1;
3761 #ifndef MODULE
3762     char *option = NULL;
3763
3764     if (fb_get_options("atyfb", &option))
3765         return -ENODEV;
3766     atyfb_setup(option);
3767 #endif
3768
3769 #ifdef CONFIG_PCI
3770     err1 = pci_register_driver(&atyfb_driver);
3771 #endif
3772 #ifdef CONFIG_ATARI
3773     err2 = atyfb_atari_probe();
3774 #endif
3775
3776     return (err1 && err2) ? -ENODEV : 0;
3777 }
3778
3779 static void __exit atyfb_exit(void)
3780 {
3781 #ifdef CONFIG_PCI
3782         pci_unregister_driver(&atyfb_driver);
3783 #endif
3784 }
3785
3786 module_init(atyfb_init);
3787 module_exit(atyfb_exit);
3788
3789 MODULE_DESCRIPTION("FBDev driver for ATI Mach64 cards");
3790 MODULE_LICENSE("GPL");
3791 module_param(noaccel, bool, 0);
3792 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
3793 module_param(vram, int, 0);
3794 MODULE_PARM_DESC(vram, "int: override size of video ram");
3795 module_param(pll, int, 0);
3796 MODULE_PARM_DESC(pll, "int: override video clock");
3797 module_param(mclk, int, 0);
3798 MODULE_PARM_DESC(mclk, "int: override memory clock");
3799 module_param(xclk, int, 0);
3800 MODULE_PARM_DESC(xclk, "int: override accelerated engine clock");
3801 module_param(comp_sync, int, 0);
3802 MODULE_PARM_DESC(comp_sync,
3803                  "Set composite sync signal to low (0) or high (1)");
3804 module_param(mode, charp, 0);
3805 MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
3806 #ifdef CONFIG_MTRR
3807 module_param(nomtrr, bool, 0);
3808 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
3809 #endif