Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-2.6] / drivers / net / wireless / b43legacy / phy.c
1 /*
2
3   Broadcom B43legacy wireless driver
4
5   Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
6                      Stefano Brivio <stefano.brivio@polimi.it>
7                      Michael Buesch <mbuesch@freenet.de>
8                      Danny van Dyk <kugelfang@gentoo.org>
9      Andreas Jaggi <andreas.jaggi@waterwave.ch>
10   Copyright (c) 2007 Larry Finger <Larry.Finger@lwfinger.net>
11
12   Some parts of the code in this file are derived from the ipw2200
13   driver  Copyright(c) 2003 - 2004 Intel Corporation.
14
15   This program is free software; you can redistribute it and/or modify
16   it under the terms of the GNU General Public License as published by
17   the Free Software Foundation; either version 2 of the License, or
18   (at your option) any later version.
19
20   This program is distributed in the hope that it will be useful,
21   but WITHOUT ANY WARRANTY; without even the implied warranty of
22   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23   GNU General Public License for more details.
24
25   You should have received a copy of the GNU General Public License
26   along with this program; see the file COPYING.  If not, write to
27   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
28   Boston, MA 02110-1301, USA.
29
30 */
31
32 #include <linux/delay.h>
33 #include <linux/pci.h>
34 #include <linux/types.h>
35
36 #include "b43legacy.h"
37 #include "phy.h"
38 #include "main.h"
39 #include "radio.h"
40 #include "ilt.h"
41
42
43 static const s8 b43legacy_tssi2dbm_b_table[] = {
44         0x4D, 0x4C, 0x4B, 0x4A,
45         0x4A, 0x49, 0x48, 0x47,
46         0x47, 0x46, 0x45, 0x45,
47         0x44, 0x43, 0x42, 0x42,
48         0x41, 0x40, 0x3F, 0x3E,
49         0x3D, 0x3C, 0x3B, 0x3A,
50         0x39, 0x38, 0x37, 0x36,
51         0x35, 0x34, 0x32, 0x31,
52         0x30, 0x2F, 0x2D, 0x2C,
53         0x2B, 0x29, 0x28, 0x26,
54         0x25, 0x23, 0x21, 0x1F,
55         0x1D, 0x1A, 0x17, 0x14,
56         0x10, 0x0C, 0x06, 0x00,
57           -7,   -7,   -7,   -7,
58           -7,   -7,   -7,   -7,
59           -7,   -7,   -7,   -7,
60 };
61
62 static const s8 b43legacy_tssi2dbm_g_table[] = {
63          77,  77,  77,  76,
64          76,  76,  75,  75,
65          74,  74,  73,  73,
66          73,  72,  72,  71,
67          71,  70,  70,  69,
68          68,  68,  67,  67,
69          66,  65,  65,  64,
70          63,  63,  62,  61,
71          60,  59,  58,  57,
72          56,  55,  54,  53,
73          52,  50,  49,  47,
74          45,  43,  40,  37,
75          33,  28,  22,  14,
76           5,  -7, -20, -20,
77         -20, -20, -20, -20,
78         -20, -20, -20, -20,
79 };
80
81 static void b43legacy_phy_initg(struct b43legacy_wldev *dev);
82
83
84 static inline
85 void b43legacy_voluntary_preempt(void)
86 {
87         B43legacy_BUG_ON(!(!in_atomic() && !in_irq() &&
88                           !in_interrupt() && !irqs_disabled()));
89 #ifndef CONFIG_PREEMPT
90         cond_resched();
91 #endif /* CONFIG_PREEMPT */
92 }
93
94 /* Lock the PHY registers against concurrent access from the microcode.
95  * This lock is nonrecursive. */
96 void b43legacy_phy_lock(struct b43legacy_wldev *dev)
97 {
98 #if B43legacy_DEBUG
99         B43legacy_WARN_ON(dev->phy.phy_locked);
100         dev->phy.phy_locked = 1;
101 #endif
102
103         if (dev->dev->id.revision < 3) {
104                 b43legacy_mac_suspend(dev);
105         } else {
106                 if (!b43legacy_is_mode(dev->wl, NL80211_IFTYPE_AP))
107                         b43legacy_power_saving_ctl_bits(dev, -1, 1);
108         }
109 }
110
111 void b43legacy_phy_unlock(struct b43legacy_wldev *dev)
112 {
113 #if B43legacy_DEBUG
114         B43legacy_WARN_ON(!dev->phy.phy_locked);
115         dev->phy.phy_locked = 0;
116 #endif
117
118         if (dev->dev->id.revision < 3) {
119                 b43legacy_mac_enable(dev);
120         } else {
121                 if (!b43legacy_is_mode(dev->wl, NL80211_IFTYPE_AP))
122                         b43legacy_power_saving_ctl_bits(dev, -1, -1);
123         }
124 }
125
126 u16 b43legacy_phy_read(struct b43legacy_wldev *dev, u16 offset)
127 {
128         b43legacy_write16(dev, B43legacy_MMIO_PHY_CONTROL, offset);
129         return b43legacy_read16(dev, B43legacy_MMIO_PHY_DATA);
130 }
131
132 void b43legacy_phy_write(struct b43legacy_wldev *dev, u16 offset, u16 val)
133 {
134         b43legacy_write16(dev, B43legacy_MMIO_PHY_CONTROL, offset);
135         mmiowb();
136         b43legacy_write16(dev, B43legacy_MMIO_PHY_DATA, val);
137 }
138
139 void b43legacy_phy_calibrate(struct b43legacy_wldev *dev)
140 {
141         struct b43legacy_phy *phy = &dev->phy;
142
143         b43legacy_read32(dev, B43legacy_MMIO_MACCTL); /* Dummy read. */
144         if (phy->calibrated)
145                 return;
146         if (phy->type == B43legacy_PHYTYPE_G && phy->rev == 1) {
147                 b43legacy_wireless_core_reset(dev, 0);
148                 b43legacy_phy_initg(dev);
149                 b43legacy_wireless_core_reset(dev, B43legacy_TMSLOW_GMODE);
150         }
151         phy->calibrated = 1;
152 }
153
154 /* intialize B PHY power control
155  * as described in http://bcm-specs.sipsolutions.net/InitPowerControl
156  */
157 static void b43legacy_phy_init_pctl(struct b43legacy_wldev *dev)
158 {
159         struct b43legacy_phy *phy = &dev->phy;
160         u16 saved_batt = 0;
161         u16 saved_ratt = 0;
162         u16 saved_txctl1 = 0;
163         int must_reset_txpower = 0;
164
165         B43legacy_BUG_ON(!(phy->type == B43legacy_PHYTYPE_B ||
166                           phy->type == B43legacy_PHYTYPE_G));
167         if (is_bcm_board_vendor(dev) &&
168             (dev->dev->bus->boardinfo.type == 0x0416))
169                 return;
170
171         b43legacy_phy_write(dev, 0x0028, 0x8018);
172         b43legacy_write16(dev, 0x03E6, b43legacy_read16(dev, 0x03E6) & 0xFFDF);
173
174         if (phy->type == B43legacy_PHYTYPE_G) {
175                 if (!phy->gmode)
176                         return;
177                 b43legacy_phy_write(dev, 0x047A, 0xC111);
178         }
179         if (phy->savedpctlreg != 0xFFFF)
180                 return;
181 #ifdef CONFIG_B43LEGACY_DEBUG
182         if (phy->manual_txpower_control)
183                 return;
184 #endif
185
186         if (phy->type == B43legacy_PHYTYPE_B &&
187             phy->rev >= 2 &&
188             phy->radio_ver == 0x2050)
189                 b43legacy_radio_write16(dev, 0x0076,
190                                         b43legacy_radio_read16(dev, 0x0076)
191                                         | 0x0084);
192         else {
193                 saved_batt = phy->bbatt;
194                 saved_ratt = phy->rfatt;
195                 saved_txctl1 = phy->txctl1;
196                 if ((phy->radio_rev >= 6) && (phy->radio_rev <= 8)
197                     && /*FIXME: incomplete specs for 5 < revision < 9 */ 0)
198                         b43legacy_radio_set_txpower_bg(dev, 0xB, 0x1F, 0);
199                 else
200                         b43legacy_radio_set_txpower_bg(dev, 0xB, 9, 0);
201                 must_reset_txpower = 1;
202         }
203         b43legacy_dummy_transmission(dev);
204
205         phy->savedpctlreg = b43legacy_phy_read(dev, B43legacy_PHY_G_PCTL);
206
207         if (must_reset_txpower)
208                 b43legacy_radio_set_txpower_bg(dev, saved_batt, saved_ratt,
209                                                saved_txctl1);
210         else
211                 b43legacy_radio_write16(dev, 0x0076, b43legacy_radio_read16(dev,
212                                         0x0076) & 0xFF7B);
213         b43legacy_radio_clear_tssi(dev);
214 }
215
216 static void b43legacy_phy_agcsetup(struct b43legacy_wldev *dev)
217 {
218         struct b43legacy_phy *phy = &dev->phy;
219         u16 offset = 0x0000;
220
221         if (phy->rev == 1)
222                 offset = 0x4C00;
223
224         b43legacy_ilt_write(dev, offset, 0x00FE);
225         b43legacy_ilt_write(dev, offset + 1, 0x000D);
226         b43legacy_ilt_write(dev, offset + 2, 0x0013);
227         b43legacy_ilt_write(dev, offset + 3, 0x0019);
228
229         if (phy->rev == 1) {
230                 b43legacy_ilt_write(dev, 0x1800, 0x2710);
231                 b43legacy_ilt_write(dev, 0x1801, 0x9B83);
232                 b43legacy_ilt_write(dev, 0x1802, 0x9B83);
233                 b43legacy_ilt_write(dev, 0x1803, 0x0F8D);
234                 b43legacy_phy_write(dev, 0x0455, 0x0004);
235         }
236
237         b43legacy_phy_write(dev, 0x04A5, (b43legacy_phy_read(dev, 0x04A5)
238                                           & 0x00FF) | 0x5700);
239         b43legacy_phy_write(dev, 0x041A, (b43legacy_phy_read(dev, 0x041A)
240                                           & 0xFF80) | 0x000F);
241         b43legacy_phy_write(dev, 0x041A, (b43legacy_phy_read(dev, 0x041A)
242                                           & 0xC07F) | 0x2B80);
243         b43legacy_phy_write(dev, 0x048C, (b43legacy_phy_read(dev, 0x048C)
244                                           & 0xF0FF) | 0x0300);
245
246         b43legacy_radio_write16(dev, 0x007A,
247                                 b43legacy_radio_read16(dev, 0x007A)
248                                 | 0x0008);
249
250         b43legacy_phy_write(dev, 0x04A0, (b43legacy_phy_read(dev, 0x04A0)
251                             & 0xFFF0) | 0x0008);
252         b43legacy_phy_write(dev, 0x04A1, (b43legacy_phy_read(dev, 0x04A1)
253                             & 0xF0FF) | 0x0600);
254         b43legacy_phy_write(dev, 0x04A2, (b43legacy_phy_read(dev, 0x04A2)
255                             & 0xF0FF) | 0x0700);
256         b43legacy_phy_write(dev, 0x04A0, (b43legacy_phy_read(dev, 0x04A0)
257                             & 0xF0FF) | 0x0100);
258
259         if (phy->rev == 1)
260                 b43legacy_phy_write(dev, 0x04A2,
261                                     (b43legacy_phy_read(dev, 0x04A2)
262                                     & 0xFFF0) | 0x0007);
263
264         b43legacy_phy_write(dev, 0x0488, (b43legacy_phy_read(dev, 0x0488)
265                             & 0xFF00) | 0x001C);
266         b43legacy_phy_write(dev, 0x0488, (b43legacy_phy_read(dev, 0x0488)
267                             & 0xC0FF) | 0x0200);
268         b43legacy_phy_write(dev, 0x0496, (b43legacy_phy_read(dev, 0x0496)
269                             & 0xFF00) | 0x001C);
270         b43legacy_phy_write(dev, 0x0489, (b43legacy_phy_read(dev, 0x0489)
271                             & 0xFF00) | 0x0020);
272         b43legacy_phy_write(dev, 0x0489, (b43legacy_phy_read(dev, 0x0489)
273                             & 0xC0FF) | 0x0200);
274         b43legacy_phy_write(dev, 0x0482, (b43legacy_phy_read(dev, 0x0482)
275                             & 0xFF00) | 0x002E);
276         b43legacy_phy_write(dev, 0x0496, (b43legacy_phy_read(dev, 0x0496)
277                             & 0x00FF) | 0x1A00);
278         b43legacy_phy_write(dev, 0x0481, (b43legacy_phy_read(dev, 0x0481)
279                             & 0xFF00) | 0x0028);
280         b43legacy_phy_write(dev, 0x0481, (b43legacy_phy_read(dev, 0x0481)
281                             & 0x00FF) | 0x2C00);
282
283         if (phy->rev == 1) {
284                 b43legacy_phy_write(dev, 0x0430, 0x092B);
285                 b43legacy_phy_write(dev, 0x041B,
286                                     (b43legacy_phy_read(dev, 0x041B)
287                                     & 0xFFE1) | 0x0002);
288         } else {
289                 b43legacy_phy_write(dev, 0x041B,
290                                     b43legacy_phy_read(dev, 0x041B) & 0xFFE1);
291                 b43legacy_phy_write(dev, 0x041F, 0x287A);
292                 b43legacy_phy_write(dev, 0x0420,
293                                     (b43legacy_phy_read(dev, 0x0420)
294                                     & 0xFFF0) | 0x0004);
295         }
296
297         if (phy->rev > 2) {
298                 b43legacy_phy_write(dev, 0x0422, 0x287A);
299                 b43legacy_phy_write(dev, 0x0420,
300                                     (b43legacy_phy_read(dev, 0x0420)
301                                     & 0x0FFF) | 0x3000);
302         }
303
304         b43legacy_phy_write(dev, 0x04A8, (b43legacy_phy_read(dev, 0x04A8)
305                             & 0x8080) | 0x7874);
306         b43legacy_phy_write(dev, 0x048E, 0x1C00);
307
308         if (phy->rev == 1) {
309                 b43legacy_phy_write(dev, 0x04AB,
310                                     (b43legacy_phy_read(dev, 0x04AB)
311                                     & 0xF0FF) | 0x0600);
312                 b43legacy_phy_write(dev, 0x048B, 0x005E);
313                 b43legacy_phy_write(dev, 0x048C,
314                                     (b43legacy_phy_read(dev, 0x048C) & 0xFF00)
315                                     | 0x001E);
316                 b43legacy_phy_write(dev, 0x048D, 0x0002);
317         }
318
319         b43legacy_ilt_write(dev, offset + 0x0800, 0);
320         b43legacy_ilt_write(dev, offset + 0x0801, 7);
321         b43legacy_ilt_write(dev, offset + 0x0802, 16);
322         b43legacy_ilt_write(dev, offset + 0x0803, 28);
323
324         if (phy->rev >= 6) {
325                 b43legacy_phy_write(dev, 0x0426,
326                                     (b43legacy_phy_read(dev, 0x0426) & 0xFFFC));
327                 b43legacy_phy_write(dev, 0x0426,
328                                     (b43legacy_phy_read(dev, 0x0426) & 0xEFFF));
329         }
330 }
331
332 static void b43legacy_phy_setupg(struct b43legacy_wldev *dev)
333 {
334         struct b43legacy_phy *phy = &dev->phy;
335         u16 i;
336
337         B43legacy_BUG_ON(phy->type != B43legacy_PHYTYPE_G);
338         if (phy->rev == 1) {
339                 b43legacy_phy_write(dev, 0x0406, 0x4F19);
340                 b43legacy_phy_write(dev, B43legacy_PHY_G_CRS,
341                                     (b43legacy_phy_read(dev,
342                                     B43legacy_PHY_G_CRS) & 0xFC3F) | 0x0340);
343                 b43legacy_phy_write(dev, 0x042C, 0x005A);
344                 b43legacy_phy_write(dev, 0x0427, 0x001A);
345
346                 for (i = 0; i < B43legacy_ILT_FINEFREQG_SIZE; i++)
347                         b43legacy_ilt_write(dev, 0x5800 + i,
348                                             b43legacy_ilt_finefreqg[i]);
349                 for (i = 0; i < B43legacy_ILT_NOISEG1_SIZE; i++)
350                         b43legacy_ilt_write(dev, 0x1800 + i,
351                                             b43legacy_ilt_noiseg1[i]);
352                 for (i = 0; i < B43legacy_ILT_ROTOR_SIZE; i++)
353                         b43legacy_ilt_write32(dev, 0x2000 + i,
354                                               b43legacy_ilt_rotor[i]);
355         } else {
356                 /* nrssi values are signed 6-bit values. Why 0x7654 here? */
357                 b43legacy_nrssi_hw_write(dev, 0xBA98, (s16)0x7654);
358
359                 if (phy->rev == 2) {
360                         b43legacy_phy_write(dev, 0x04C0, 0x1861);
361                         b43legacy_phy_write(dev, 0x04C1, 0x0271);
362                 } else if (phy->rev > 2) {
363                         b43legacy_phy_write(dev, 0x04C0, 0x0098);
364                         b43legacy_phy_write(dev, 0x04C1, 0x0070);
365                         b43legacy_phy_write(dev, 0x04C9, 0x0080);
366                 }
367                 b43legacy_phy_write(dev, 0x042B, b43legacy_phy_read(dev,
368                                     0x042B) | 0x800);
369
370                 for (i = 0; i < 64; i++)
371                         b43legacy_ilt_write(dev, 0x4000 + i, i);
372                 for (i = 0; i < B43legacy_ILT_NOISEG2_SIZE; i++)
373                         b43legacy_ilt_write(dev, 0x1800 + i,
374                                             b43legacy_ilt_noiseg2[i]);
375         }
376
377         if (phy->rev <= 2)
378                 for (i = 0; i < B43legacy_ILT_NOISESCALEG_SIZE; i++)
379                         b43legacy_ilt_write(dev, 0x1400 + i,
380                                             b43legacy_ilt_noisescaleg1[i]);
381         else if ((phy->rev >= 7) && (b43legacy_phy_read(dev, 0x0449) & 0x0200))
382                 for (i = 0; i < B43legacy_ILT_NOISESCALEG_SIZE; i++)
383                         b43legacy_ilt_write(dev, 0x1400 + i,
384                                             b43legacy_ilt_noisescaleg3[i]);
385         else
386                 for (i = 0; i < B43legacy_ILT_NOISESCALEG_SIZE; i++)
387                         b43legacy_ilt_write(dev, 0x1400 + i,
388                                             b43legacy_ilt_noisescaleg2[i]);
389
390         if (phy->rev == 2)
391                 for (i = 0; i < B43legacy_ILT_SIGMASQR_SIZE; i++)
392                         b43legacy_ilt_write(dev, 0x5000 + i,
393                                             b43legacy_ilt_sigmasqr1[i]);
394         else if ((phy->rev > 2) && (phy->rev <= 8))
395                 for (i = 0; i < B43legacy_ILT_SIGMASQR_SIZE; i++)
396                         b43legacy_ilt_write(dev, 0x5000 + i,
397                                             b43legacy_ilt_sigmasqr2[i]);
398
399         if (phy->rev == 1) {
400                 for (i = 0; i < B43legacy_ILT_RETARD_SIZE; i++)
401                         b43legacy_ilt_write32(dev, 0x2400 + i,
402                                               b43legacy_ilt_retard[i]);
403                 for (i = 4; i < 20; i++)
404                         b43legacy_ilt_write(dev, 0x5400 + i, 0x0020);
405                 b43legacy_phy_agcsetup(dev);
406
407                 if (is_bcm_board_vendor(dev) &&
408                     (dev->dev->bus->boardinfo.type == 0x0416) &&
409                     (dev->dev->bus->boardinfo.rev == 0x0017))
410                         return;
411
412                 b43legacy_ilt_write(dev, 0x5001, 0x0002);
413                 b43legacy_ilt_write(dev, 0x5002, 0x0001);
414         } else {
415                 for (i = 0; i <= 0x20; i++)
416                         b43legacy_ilt_write(dev, 0x1000 + i, 0x0820);
417                 b43legacy_phy_agcsetup(dev);
418                 b43legacy_phy_read(dev, 0x0400); /* dummy read */
419                 b43legacy_phy_write(dev, 0x0403, 0x1000);
420                 b43legacy_ilt_write(dev, 0x3C02, 0x000F);
421                 b43legacy_ilt_write(dev, 0x3C03, 0x0014);
422
423                 if (is_bcm_board_vendor(dev) &&
424                     (dev->dev->bus->boardinfo.type == 0x0416) &&
425                     (dev->dev->bus->boardinfo.rev == 0x0017))
426                         return;
427
428                 b43legacy_ilt_write(dev, 0x0401, 0x0002);
429                 b43legacy_ilt_write(dev, 0x0402, 0x0001);
430         }
431 }
432
433 /* Initialize the APHY portion of a GPHY. */
434 static void b43legacy_phy_inita(struct b43legacy_wldev *dev)
435 {
436
437         might_sleep();
438
439         b43legacy_phy_setupg(dev);
440         if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_PACTRL)
441                 b43legacy_phy_write(dev, 0x046E, 0x03CF);
442 }
443
444 static void b43legacy_phy_initb2(struct b43legacy_wldev *dev)
445 {
446         struct b43legacy_phy *phy = &dev->phy;
447         u16 offset;
448         int val;
449
450         b43legacy_write16(dev, 0x03EC, 0x3F22);
451         b43legacy_phy_write(dev, 0x0020, 0x301C);
452         b43legacy_phy_write(dev, 0x0026, 0x0000);
453         b43legacy_phy_write(dev, 0x0030, 0x00C6);
454         b43legacy_phy_write(dev, 0x0088, 0x3E00);
455         val = 0x3C3D;
456         for (offset = 0x0089; offset < 0x00A7; offset++) {
457                 b43legacy_phy_write(dev, offset, val);
458                 val -= 0x0202;
459         }
460         b43legacy_phy_write(dev, 0x03E4, 0x3000);
461         b43legacy_radio_selectchannel(dev, phy->channel, 0);
462         if (phy->radio_ver != 0x2050) {
463                 b43legacy_radio_write16(dev, 0x0075, 0x0080);
464                 b43legacy_radio_write16(dev, 0x0079, 0x0081);
465         }
466         b43legacy_radio_write16(dev, 0x0050, 0x0020);
467         b43legacy_radio_write16(dev, 0x0050, 0x0023);
468         if (phy->radio_ver == 0x2050) {
469                 b43legacy_radio_write16(dev, 0x0050, 0x0020);
470                 b43legacy_radio_write16(dev, 0x005A, 0x0070);
471                 b43legacy_radio_write16(dev, 0x005B, 0x007B);
472                 b43legacy_radio_write16(dev, 0x005C, 0x00B0);
473                 b43legacy_radio_write16(dev, 0x007A, 0x000F);
474                 b43legacy_phy_write(dev, 0x0038, 0x0677);
475                 b43legacy_radio_init2050(dev);
476         }
477         b43legacy_phy_write(dev, 0x0014, 0x0080);
478         b43legacy_phy_write(dev, 0x0032, 0x00CA);
479         b43legacy_phy_write(dev, 0x0032, 0x00CC);
480         b43legacy_phy_write(dev, 0x0035, 0x07C2);
481         b43legacy_phy_lo_b_measure(dev);
482         b43legacy_phy_write(dev, 0x0026, 0xCC00);
483         if (phy->radio_ver != 0x2050)
484                 b43legacy_phy_write(dev, 0x0026, 0xCE00);
485         b43legacy_write16(dev, B43legacy_MMIO_CHANNEL_EXT, 0x1000);
486         b43legacy_phy_write(dev, 0x002A, 0x88A3);
487         if (phy->radio_ver != 0x2050)
488                 b43legacy_phy_write(dev, 0x002A, 0x88C2);
489         b43legacy_radio_set_txpower_bg(dev, 0xFFFF, 0xFFFF, 0xFFFF);
490         b43legacy_phy_init_pctl(dev);
491 }
492
493 static void b43legacy_phy_initb4(struct b43legacy_wldev *dev)
494 {
495         struct b43legacy_phy *phy = &dev->phy;
496         u16 offset;
497         u16 val;
498
499         b43legacy_write16(dev, 0x03EC, 0x3F22);
500         b43legacy_phy_write(dev, 0x0020, 0x301C);
501         b43legacy_phy_write(dev, 0x0026, 0x0000);
502         b43legacy_phy_write(dev, 0x0030, 0x00C6);
503         b43legacy_phy_write(dev, 0x0088, 0x3E00);
504         val = 0x3C3D;
505         for (offset = 0x0089; offset < 0x00A7; offset++) {
506                 b43legacy_phy_write(dev, offset, val);
507                 val -= 0x0202;
508         }
509         b43legacy_phy_write(dev, 0x03E4, 0x3000);
510         b43legacy_radio_selectchannel(dev, phy->channel, 0);
511         if (phy->radio_ver != 0x2050) {
512                 b43legacy_radio_write16(dev, 0x0075, 0x0080);
513                 b43legacy_radio_write16(dev, 0x0079, 0x0081);
514         }
515         b43legacy_radio_write16(dev, 0x0050, 0x0020);
516         b43legacy_radio_write16(dev, 0x0050, 0x0023);
517         if (phy->radio_ver == 0x2050) {
518                 b43legacy_radio_write16(dev, 0x0050, 0x0020);
519                 b43legacy_radio_write16(dev, 0x005A, 0x0070);
520                 b43legacy_radio_write16(dev, 0x005B, 0x007B);
521                 b43legacy_radio_write16(dev, 0x005C, 0x00B0);
522                 b43legacy_radio_write16(dev, 0x007A, 0x000F);
523                 b43legacy_phy_write(dev, 0x0038, 0x0677);
524                 b43legacy_radio_init2050(dev);
525         }
526         b43legacy_phy_write(dev, 0x0014, 0x0080);
527         b43legacy_phy_write(dev, 0x0032, 0x00CA);
528         if (phy->radio_ver == 0x2050)
529                 b43legacy_phy_write(dev, 0x0032, 0x00E0);
530         b43legacy_phy_write(dev, 0x0035, 0x07C2);
531
532         b43legacy_phy_lo_b_measure(dev);
533
534         b43legacy_phy_write(dev, 0x0026, 0xCC00);
535         if (phy->radio_ver == 0x2050)
536                 b43legacy_phy_write(dev, 0x0026, 0xCE00);
537         b43legacy_write16(dev, B43legacy_MMIO_CHANNEL_EXT, 0x1100);
538         b43legacy_phy_write(dev, 0x002A, 0x88A3);
539         if (phy->radio_ver == 0x2050)
540                 b43legacy_phy_write(dev, 0x002A, 0x88C2);
541         b43legacy_radio_set_txpower_bg(dev, 0xFFFF, 0xFFFF, 0xFFFF);
542         if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_RSSI) {
543                 b43legacy_calc_nrssi_slope(dev);
544                 b43legacy_calc_nrssi_threshold(dev);
545         }
546         b43legacy_phy_init_pctl(dev);
547 }
548
549 static void b43legacy_phy_initb5(struct b43legacy_wldev *dev)
550 {
551         struct b43legacy_phy *phy = &dev->phy;
552         u16 offset;
553         u16 value;
554         u8 old_channel;
555
556         if (phy->analog == 1)
557                 b43legacy_radio_write16(dev, 0x007A,
558                                         b43legacy_radio_read16(dev, 0x007A)
559                                         | 0x0050);
560         if (!is_bcm_board_vendor(dev) &&
561             (dev->dev->bus->boardinfo.type != 0x0416)) {
562                 value = 0x2120;
563                 for (offset = 0x00A8 ; offset < 0x00C7; offset++) {
564                         b43legacy_phy_write(dev, offset, value);
565                         value += 0x0202;
566                 }
567         }
568         b43legacy_phy_write(dev, 0x0035,
569                             (b43legacy_phy_read(dev, 0x0035) & 0xF0FF)
570                             | 0x0700);
571         if (phy->radio_ver == 0x2050)
572                 b43legacy_phy_write(dev, 0x0038, 0x0667);
573
574         if (phy->gmode) {
575                 if (phy->radio_ver == 0x2050) {
576                         b43legacy_radio_write16(dev, 0x007A,
577                                         b43legacy_radio_read16(dev, 0x007A)
578                                         | 0x0020);
579                         b43legacy_radio_write16(dev, 0x0051,
580                                         b43legacy_radio_read16(dev, 0x0051)
581                                         | 0x0004);
582                 }
583                 b43legacy_write16(dev, B43legacy_MMIO_PHY_RADIO, 0x0000);
584
585                 b43legacy_phy_write(dev, 0x0802, b43legacy_phy_read(dev, 0x0802)
586                                     | 0x0100);
587                 b43legacy_phy_write(dev, 0x042B, b43legacy_phy_read(dev, 0x042B)
588                                     | 0x2000);
589
590                 b43legacy_phy_write(dev, 0x001C, 0x186A);
591
592                 b43legacy_phy_write(dev, 0x0013, (b43legacy_phy_read(dev,
593                                     0x0013) & 0x00FF) | 0x1900);
594                 b43legacy_phy_write(dev, 0x0035, (b43legacy_phy_read(dev,
595                                     0x0035) & 0xFFC0) | 0x0064);
596                 b43legacy_phy_write(dev, 0x005D, (b43legacy_phy_read(dev,
597                                     0x005D) & 0xFF80) | 0x000A);
598                 b43legacy_phy_write(dev, 0x5B, 0x0000);
599                 b43legacy_phy_write(dev, 0x5C, 0x0000);
600         }
601
602         if (dev->bad_frames_preempt)
603                 b43legacy_phy_write(dev, B43legacy_PHY_RADIO_BITFIELD,
604                                     b43legacy_phy_read(dev,
605                                     B43legacy_PHY_RADIO_BITFIELD) | (1 << 12));
606
607         if (phy->analog == 1) {
608                 b43legacy_phy_write(dev, 0x0026, 0xCE00);
609                 b43legacy_phy_write(dev, 0x0021, 0x3763);
610                 b43legacy_phy_write(dev, 0x0022, 0x1BC3);
611                 b43legacy_phy_write(dev, 0x0023, 0x06F9);
612                 b43legacy_phy_write(dev, 0x0024, 0x037E);
613         } else
614                 b43legacy_phy_write(dev, 0x0026, 0xCC00);
615         b43legacy_phy_write(dev, 0x0030, 0x00C6);
616         b43legacy_write16(dev, 0x03EC, 0x3F22);
617
618         if (phy->analog == 1)
619                 b43legacy_phy_write(dev, 0x0020, 0x3E1C);
620         else
621                 b43legacy_phy_write(dev, 0x0020, 0x301C);
622
623         if (phy->analog == 0)
624                 b43legacy_write16(dev, 0x03E4, 0x3000);
625
626         old_channel = (phy->channel == 0xFF) ? 1 : phy->channel;
627         /* Force to channel 7, even if not supported. */
628         b43legacy_radio_selectchannel(dev, 7, 0);
629
630         if (phy->radio_ver != 0x2050) {
631                 b43legacy_radio_write16(dev, 0x0075, 0x0080);
632                 b43legacy_radio_write16(dev, 0x0079, 0x0081);
633         }
634
635         b43legacy_radio_write16(dev, 0x0050, 0x0020);
636         b43legacy_radio_write16(dev, 0x0050, 0x0023);
637
638         if (phy->radio_ver == 0x2050) {
639                 b43legacy_radio_write16(dev, 0x0050, 0x0020);
640                 b43legacy_radio_write16(dev, 0x005A, 0x0070);
641         }
642
643         b43legacy_radio_write16(dev, 0x005B, 0x007B);
644         b43legacy_radio_write16(dev, 0x005C, 0x00B0);
645
646         b43legacy_radio_write16(dev, 0x007A, b43legacy_radio_read16(dev,
647                                 0x007A) | 0x0007);
648
649         b43legacy_radio_selectchannel(dev, old_channel, 0);
650
651         b43legacy_phy_write(dev, 0x0014, 0x0080);
652         b43legacy_phy_write(dev, 0x0032, 0x00CA);
653         b43legacy_phy_write(dev, 0x002A, 0x88A3);
654
655         b43legacy_radio_set_txpower_bg(dev, 0xFFFF, 0xFFFF, 0xFFFF);
656
657         if (phy->radio_ver == 0x2050)
658                 b43legacy_radio_write16(dev, 0x005D, 0x000D);
659
660         b43legacy_write16(dev, 0x03E4, (b43legacy_read16(dev, 0x03E4) &
661                           0xFFC0) | 0x0004);
662 }
663
664 static void b43legacy_phy_initb6(struct b43legacy_wldev *dev)
665 {
666         struct b43legacy_phy *phy = &dev->phy;
667         u16 offset;
668         u16 val;
669         u8 old_channel;
670
671         b43legacy_phy_write(dev, 0x003E, 0x817A);
672         b43legacy_radio_write16(dev, 0x007A,
673                                 (b43legacy_radio_read16(dev, 0x007A) | 0x0058));
674         if (phy->radio_rev == 4 ||
675              phy->radio_rev == 5) {
676                 b43legacy_radio_write16(dev, 0x0051, 0x0037);
677                 b43legacy_radio_write16(dev, 0x0052, 0x0070);
678                 b43legacy_radio_write16(dev, 0x0053, 0x00B3);
679                 b43legacy_radio_write16(dev, 0x0054, 0x009B);
680                 b43legacy_radio_write16(dev, 0x005A, 0x0088);
681                 b43legacy_radio_write16(dev, 0x005B, 0x0088);
682                 b43legacy_radio_write16(dev, 0x005D, 0x0088);
683                 b43legacy_radio_write16(dev, 0x005E, 0x0088);
684                 b43legacy_radio_write16(dev, 0x007D, 0x0088);
685                 b43legacy_shm_write32(dev, B43legacy_SHM_SHARED,
686                                       B43legacy_UCODEFLAGS_OFFSET,
687                                       (b43legacy_shm_read32(dev,
688                                       B43legacy_SHM_SHARED,
689                                       B43legacy_UCODEFLAGS_OFFSET)
690                                       | 0x00000200));
691         }
692         if (phy->radio_rev == 8) {
693                 b43legacy_radio_write16(dev, 0x0051, 0x0000);
694                 b43legacy_radio_write16(dev, 0x0052, 0x0040);
695                 b43legacy_radio_write16(dev, 0x0053, 0x00B7);
696                 b43legacy_radio_write16(dev, 0x0054, 0x0098);
697                 b43legacy_radio_write16(dev, 0x005A, 0x0088);
698                 b43legacy_radio_write16(dev, 0x005B, 0x006B);
699                 b43legacy_radio_write16(dev, 0x005C, 0x000F);
700                 if (dev->dev->bus->sprom.boardflags_lo & 0x8000) {
701                         b43legacy_radio_write16(dev, 0x005D, 0x00FA);
702                         b43legacy_radio_write16(dev, 0x005E, 0x00D8);
703                 } else {
704                         b43legacy_radio_write16(dev, 0x005D, 0x00F5);
705                         b43legacy_radio_write16(dev, 0x005E, 0x00B8);
706                 }
707                 b43legacy_radio_write16(dev, 0x0073, 0x0003);
708                 b43legacy_radio_write16(dev, 0x007D, 0x00A8);
709                 b43legacy_radio_write16(dev, 0x007C, 0x0001);
710                 b43legacy_radio_write16(dev, 0x007E, 0x0008);
711         }
712         val = 0x1E1F;
713         for (offset = 0x0088; offset < 0x0098; offset++) {
714                 b43legacy_phy_write(dev, offset, val);
715                 val -= 0x0202;
716         }
717         val = 0x3E3F;
718         for (offset = 0x0098; offset < 0x00A8; offset++) {
719                 b43legacy_phy_write(dev, offset, val);
720                 val -= 0x0202;
721         }
722         val = 0x2120;
723         for (offset = 0x00A8; offset < 0x00C8; offset++) {
724                 b43legacy_phy_write(dev, offset, (val & 0x3F3F));
725                 val += 0x0202;
726         }
727         if (phy->type == B43legacy_PHYTYPE_G) {
728                 b43legacy_radio_write16(dev, 0x007A,
729                                         b43legacy_radio_read16(dev, 0x007A) |
730                                         0x0020);
731                 b43legacy_radio_write16(dev, 0x0051,
732                                         b43legacy_radio_read16(dev, 0x0051) |
733                                         0x0004);
734                 b43legacy_phy_write(dev, 0x0802,
735                                     b43legacy_phy_read(dev, 0x0802) | 0x0100);
736                 b43legacy_phy_write(dev, 0x042B,
737                                     b43legacy_phy_read(dev, 0x042B) | 0x2000);
738                 b43legacy_phy_write(dev, 0x5B, 0x0000);
739                 b43legacy_phy_write(dev, 0x5C, 0x0000);
740         }
741
742         old_channel = phy->channel;
743         if (old_channel >= 8)
744                 b43legacy_radio_selectchannel(dev, 1, 0);
745         else
746                 b43legacy_radio_selectchannel(dev, 13, 0);
747
748         b43legacy_radio_write16(dev, 0x0050, 0x0020);
749         b43legacy_radio_write16(dev, 0x0050, 0x0023);
750         udelay(40);
751         if (phy->radio_rev < 6 || phy->radio_rev == 8) {
752                 b43legacy_radio_write16(dev, 0x007C,
753                                         (b43legacy_radio_read16(dev, 0x007C)
754                                         | 0x0002));
755                 b43legacy_radio_write16(dev, 0x0050, 0x0020);
756         }
757         if (phy->radio_rev <= 2) {
758                 b43legacy_radio_write16(dev, 0x0050, 0x0020);
759                 b43legacy_radio_write16(dev, 0x005A, 0x0070);
760                 b43legacy_radio_write16(dev, 0x005B, 0x007B);
761                 b43legacy_radio_write16(dev, 0x005C, 0x00B0);
762         }
763         b43legacy_radio_write16(dev, 0x007A,
764                                 (b43legacy_radio_read16(dev,
765                                 0x007A) & 0x00F8) | 0x0007);
766
767         b43legacy_radio_selectchannel(dev, old_channel, 0);
768
769         b43legacy_phy_write(dev, 0x0014, 0x0200);
770         if (phy->radio_rev >= 6)
771                 b43legacy_phy_write(dev, 0x002A, 0x88C2);
772         else
773                 b43legacy_phy_write(dev, 0x002A, 0x8AC0);
774         b43legacy_phy_write(dev, 0x0038, 0x0668);
775         b43legacy_radio_set_txpower_bg(dev, 0xFFFF, 0xFFFF, 0xFFFF);
776         if (phy->radio_rev == 4 || phy->radio_rev == 5)
777                 b43legacy_phy_write(dev, 0x005D, (b43legacy_phy_read(dev,
778                                     0x005D) & 0xFF80) | 0x0003);
779         if (phy->radio_rev <= 2)
780                 b43legacy_radio_write16(dev, 0x005D, 0x000D);
781
782         if (phy->analog == 4) {
783                 b43legacy_write16(dev, 0x03E4, 0x0009);
784                 b43legacy_phy_write(dev, 0x61, b43legacy_phy_read(dev, 0x61)
785                                     & 0xFFF);
786         } else
787                 b43legacy_phy_write(dev, 0x0002, (b43legacy_phy_read(dev,
788                                     0x0002) & 0xFFC0) | 0x0004);
789         if (phy->type == B43legacy_PHYTYPE_G)
790                 b43legacy_write16(dev, 0x03E6, 0x0);
791         if (phy->type == B43legacy_PHYTYPE_B) {
792                 b43legacy_write16(dev, 0x03E6, 0x8140);
793                 b43legacy_phy_write(dev, 0x0016, 0x0410);
794                 b43legacy_phy_write(dev, 0x0017, 0x0820);
795                 b43legacy_phy_write(dev, 0x0062, 0x0007);
796                 b43legacy_radio_init2050(dev);
797                 b43legacy_phy_lo_g_measure(dev);
798                 if (dev->dev->bus->sprom.boardflags_lo &
799                     B43legacy_BFL_RSSI) {
800                         b43legacy_calc_nrssi_slope(dev);
801                         b43legacy_calc_nrssi_threshold(dev);
802                 }
803                 b43legacy_phy_init_pctl(dev);
804         }
805 }
806
807 static void b43legacy_calc_loopback_gain(struct b43legacy_wldev *dev)
808 {
809         struct b43legacy_phy *phy = &dev->phy;
810         u16 backup_phy[15] = {0};
811         u16 backup_radio[3];
812         u16 backup_bband;
813         u16 i;
814         u16 loop1_cnt;
815         u16 loop1_done;
816         u16 loop1_omitted;
817         u16 loop2_done;
818
819         backup_phy[0] = b43legacy_phy_read(dev, 0x0429);
820         backup_phy[1] = b43legacy_phy_read(dev, 0x0001);
821         backup_phy[2] = b43legacy_phy_read(dev, 0x0811);
822         backup_phy[3] = b43legacy_phy_read(dev, 0x0812);
823         if (phy->rev != 1) {
824                 backup_phy[4] = b43legacy_phy_read(dev, 0x0814);
825                 backup_phy[5] = b43legacy_phy_read(dev, 0x0815);
826         }
827         backup_phy[6] = b43legacy_phy_read(dev, 0x005A);
828         backup_phy[7] = b43legacy_phy_read(dev, 0x0059);
829         backup_phy[8] = b43legacy_phy_read(dev, 0x0058);
830         backup_phy[9] = b43legacy_phy_read(dev, 0x000A);
831         backup_phy[10] = b43legacy_phy_read(dev, 0x0003);
832         backup_phy[11] = b43legacy_phy_read(dev, 0x080F);
833         backup_phy[12] = b43legacy_phy_read(dev, 0x0810);
834         backup_phy[13] = b43legacy_phy_read(dev, 0x002B);
835         backup_phy[14] = b43legacy_phy_read(dev, 0x0015);
836         b43legacy_phy_read(dev, 0x002D); /* dummy read */
837         backup_bband = phy->bbatt;
838         backup_radio[0] = b43legacy_radio_read16(dev, 0x0052);
839         backup_radio[1] = b43legacy_radio_read16(dev, 0x0043);
840         backup_radio[2] = b43legacy_radio_read16(dev, 0x007A);
841
842         b43legacy_phy_write(dev, 0x0429,
843                             b43legacy_phy_read(dev, 0x0429) & 0x3FFF);
844         b43legacy_phy_write(dev, 0x0001,
845                             b43legacy_phy_read(dev, 0x0001) & 0x8000);
846         b43legacy_phy_write(dev, 0x0811,
847                             b43legacy_phy_read(dev, 0x0811) | 0x0002);
848         b43legacy_phy_write(dev, 0x0812,
849                             b43legacy_phy_read(dev, 0x0812) & 0xFFFD);
850         b43legacy_phy_write(dev, 0x0811,
851                             b43legacy_phy_read(dev, 0x0811) | 0x0001);
852         b43legacy_phy_write(dev, 0x0812,
853                             b43legacy_phy_read(dev, 0x0812) & 0xFFFE);
854         if (phy->rev != 1) {
855                 b43legacy_phy_write(dev, 0x0814,
856                                     b43legacy_phy_read(dev, 0x0814) | 0x0001);
857                 b43legacy_phy_write(dev, 0x0815,
858                                     b43legacy_phy_read(dev, 0x0815) & 0xFFFE);
859                 b43legacy_phy_write(dev, 0x0814,
860                                     b43legacy_phy_read(dev, 0x0814) | 0x0002);
861                 b43legacy_phy_write(dev, 0x0815,
862                                     b43legacy_phy_read(dev, 0x0815) & 0xFFFD);
863         }
864         b43legacy_phy_write(dev, 0x0811, b43legacy_phy_read(dev, 0x0811) |
865                             0x000C);
866         b43legacy_phy_write(dev, 0x0812, b43legacy_phy_read(dev, 0x0812) |
867                             0x000C);
868
869         b43legacy_phy_write(dev, 0x0811, (b43legacy_phy_read(dev, 0x0811)
870                             & 0xFFCF) | 0x0030);
871         b43legacy_phy_write(dev, 0x0812, (b43legacy_phy_read(dev, 0x0812)
872                             & 0xFFCF) | 0x0010);
873
874         b43legacy_phy_write(dev, 0x005A, 0x0780);
875         b43legacy_phy_write(dev, 0x0059, 0xC810);
876         b43legacy_phy_write(dev, 0x0058, 0x000D);
877         if (phy->analog == 0)
878                 b43legacy_phy_write(dev, 0x0003, 0x0122);
879         else
880                 b43legacy_phy_write(dev, 0x000A,
881                                     b43legacy_phy_read(dev, 0x000A)
882                                     | 0x2000);
883         if (phy->rev != 1) {
884                 b43legacy_phy_write(dev, 0x0814,
885                                     b43legacy_phy_read(dev, 0x0814) | 0x0004);
886                 b43legacy_phy_write(dev, 0x0815,
887                                     b43legacy_phy_read(dev, 0x0815) & 0xFFFB);
888         }
889         b43legacy_phy_write(dev, 0x0003,
890                             (b43legacy_phy_read(dev, 0x0003)
891                              & 0xFF9F) | 0x0040);
892         if (phy->radio_ver == 0x2050 && phy->radio_rev == 2) {
893                 b43legacy_radio_write16(dev, 0x0052, 0x0000);
894                 b43legacy_radio_write16(dev, 0x0043,
895                                         (b43legacy_radio_read16(dev, 0x0043)
896                                          & 0xFFF0) | 0x0009);
897                 loop1_cnt = 9;
898         } else if (phy->radio_rev == 8) {
899                 b43legacy_radio_write16(dev, 0x0043, 0x000F);
900                 loop1_cnt = 15;
901         } else
902                 loop1_cnt = 0;
903
904         b43legacy_phy_set_baseband_attenuation(dev, 11);
905
906         if (phy->rev >= 3)
907                 b43legacy_phy_write(dev, 0x080F, 0xC020);
908         else
909                 b43legacy_phy_write(dev, 0x080F, 0x8020);
910         b43legacy_phy_write(dev, 0x0810, 0x0000);
911
912         b43legacy_phy_write(dev, 0x002B,
913                             (b43legacy_phy_read(dev, 0x002B)
914                              & 0xFFC0) | 0x0001);
915         b43legacy_phy_write(dev, 0x002B,
916                             (b43legacy_phy_read(dev, 0x002B)
917                              & 0xC0FF) | 0x0800);
918         b43legacy_phy_write(dev, 0x0811,
919                             b43legacy_phy_read(dev, 0x0811) | 0x0100);
920         b43legacy_phy_write(dev, 0x0812,
921                             b43legacy_phy_read(dev, 0x0812) & 0xCFFF);
922         if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_EXTLNA) {
923                 if (phy->rev >= 7) {
924                         b43legacy_phy_write(dev, 0x0811,
925                                             b43legacy_phy_read(dev, 0x0811)
926                                             | 0x0800);
927                         b43legacy_phy_write(dev, 0x0812,
928                                             b43legacy_phy_read(dev, 0x0812)
929                                             | 0x8000);
930                 }
931         }
932         b43legacy_radio_write16(dev, 0x007A,
933                                 b43legacy_radio_read16(dev, 0x007A)
934                                 & 0x00F7);
935
936         for (i = 0; i < loop1_cnt; i++) {
937                 b43legacy_radio_write16(dev, 0x0043, loop1_cnt);
938                 b43legacy_phy_write(dev, 0x0812,
939                                     (b43legacy_phy_read(dev, 0x0812)
940                                      & 0xF0FF) | (i << 8));
941                 b43legacy_phy_write(dev, 0x0015,
942                                     (b43legacy_phy_read(dev, 0x0015)
943                                      & 0x0FFF) | 0xA000);
944                 b43legacy_phy_write(dev, 0x0015,
945                                     (b43legacy_phy_read(dev, 0x0015)
946                                      & 0x0FFF) | 0xF000);
947                 udelay(20);
948                 if (b43legacy_phy_read(dev, 0x002D) >= 0x0DFC)
949                         break;
950         }
951         loop1_done = i;
952         loop1_omitted = loop1_cnt - loop1_done;
953
954         loop2_done = 0;
955         if (loop1_done >= 8) {
956                 b43legacy_phy_write(dev, 0x0812,
957                                     b43legacy_phy_read(dev, 0x0812)
958                                     | 0x0030);
959                 for (i = loop1_done - 8; i < 16; i++) {
960                         b43legacy_phy_write(dev, 0x0812,
961                                             (b43legacy_phy_read(dev, 0x0812)
962                                              & 0xF0FF) | (i << 8));
963                         b43legacy_phy_write(dev, 0x0015,
964                                             (b43legacy_phy_read(dev, 0x0015)
965                                              & 0x0FFF) | 0xA000);
966                         b43legacy_phy_write(dev, 0x0015,
967                                             (b43legacy_phy_read(dev, 0x0015)
968                                              & 0x0FFF) | 0xF000);
969                         udelay(20);
970                         if (b43legacy_phy_read(dev, 0x002D) >= 0x0DFC)
971                                 break;
972                 }
973         }
974
975         if (phy->rev != 1) {
976                 b43legacy_phy_write(dev, 0x0814, backup_phy[4]);
977                 b43legacy_phy_write(dev, 0x0815, backup_phy[5]);
978         }
979         b43legacy_phy_write(dev, 0x005A, backup_phy[6]);
980         b43legacy_phy_write(dev, 0x0059, backup_phy[7]);
981         b43legacy_phy_write(dev, 0x0058, backup_phy[8]);
982         b43legacy_phy_write(dev, 0x000A, backup_phy[9]);
983         b43legacy_phy_write(dev, 0x0003, backup_phy[10]);
984         b43legacy_phy_write(dev, 0x080F, backup_phy[11]);
985         b43legacy_phy_write(dev, 0x0810, backup_phy[12]);
986         b43legacy_phy_write(dev, 0x002B, backup_phy[13]);
987         b43legacy_phy_write(dev, 0x0015, backup_phy[14]);
988
989         b43legacy_phy_set_baseband_attenuation(dev, backup_bband);
990
991         b43legacy_radio_write16(dev, 0x0052, backup_radio[0]);
992         b43legacy_radio_write16(dev, 0x0043, backup_radio[1]);
993         b43legacy_radio_write16(dev, 0x007A, backup_radio[2]);
994
995         b43legacy_phy_write(dev, 0x0811, backup_phy[2] | 0x0003);
996         udelay(10);
997         b43legacy_phy_write(dev, 0x0811, backup_phy[2]);
998         b43legacy_phy_write(dev, 0x0812, backup_phy[3]);
999         b43legacy_phy_write(dev, 0x0429, backup_phy[0]);
1000         b43legacy_phy_write(dev, 0x0001, backup_phy[1]);
1001
1002         phy->loopback_gain[0] = ((loop1_done * 6) - (loop1_omitted * 4)) - 11;
1003         phy->loopback_gain[1] = (24 - (3 * loop2_done)) * 2;
1004 }
1005
1006 static void b43legacy_phy_initg(struct b43legacy_wldev *dev)
1007 {
1008         struct b43legacy_phy *phy = &dev->phy;
1009         u16 tmp;
1010
1011         if (phy->rev == 1)
1012                 b43legacy_phy_initb5(dev);
1013         else
1014                 b43legacy_phy_initb6(dev);
1015         if (phy->rev >= 2 && phy->gmode)
1016                 b43legacy_phy_inita(dev);
1017
1018         if (phy->rev >= 2) {
1019                 b43legacy_phy_write(dev, 0x0814, 0x0000);
1020                 b43legacy_phy_write(dev, 0x0815, 0x0000);
1021         }
1022         if (phy->rev == 2) {
1023                 b43legacy_phy_write(dev, 0x0811, 0x0000);
1024                 b43legacy_phy_write(dev, 0x0015, 0x00C0);
1025         }
1026         if (phy->rev > 5) {
1027                 b43legacy_phy_write(dev, 0x0811, 0x0400);
1028                 b43legacy_phy_write(dev, 0x0015, 0x00C0);
1029         }
1030         if (phy->gmode) {
1031                 tmp = b43legacy_phy_read(dev, 0x0400) & 0xFF;
1032                 if (tmp == 3) {
1033                         b43legacy_phy_write(dev, 0x04C2, 0x1816);
1034                         b43legacy_phy_write(dev, 0x04C3, 0x8606);
1035                 }
1036                 if (tmp == 4 || tmp == 5) {
1037                         b43legacy_phy_write(dev, 0x04C2, 0x1816);
1038                         b43legacy_phy_write(dev, 0x04C3, 0x8006);
1039                         b43legacy_phy_write(dev, 0x04CC,
1040                                             (b43legacy_phy_read(dev,
1041                                              0x04CC) & 0x00FF) |
1042                                              0x1F00);
1043                 }
1044                 if (phy->rev >= 2)
1045                         b43legacy_phy_write(dev, 0x047E, 0x0078);
1046         }
1047         if (phy->radio_rev == 8) {
1048                 b43legacy_phy_write(dev, 0x0801, b43legacy_phy_read(dev, 0x0801)
1049                                     | 0x0080);
1050                 b43legacy_phy_write(dev, 0x043E, b43legacy_phy_read(dev, 0x043E)
1051                                     | 0x0004);
1052         }
1053         if (phy->rev >= 2 && phy->gmode)
1054                 b43legacy_calc_loopback_gain(dev);
1055         if (phy->radio_rev != 8) {
1056                 if (phy->initval == 0xFFFF)
1057                         phy->initval = b43legacy_radio_init2050(dev);
1058                 else
1059                         b43legacy_radio_write16(dev, 0x0078, phy->initval);
1060         }
1061         if (phy->txctl2 == 0xFFFF)
1062                 b43legacy_phy_lo_g_measure(dev);
1063         else {
1064                 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8)
1065                         b43legacy_radio_write16(dev, 0x0052,
1066                                                 (phy->txctl1 << 4) |
1067                                                 phy->txctl2);
1068                 else
1069                         b43legacy_radio_write16(dev, 0x0052,
1070                                                 (b43legacy_radio_read16(dev,
1071                                                  0x0052) & 0xFFF0) |
1072                                                  phy->txctl1);
1073                 if (phy->rev >= 6)
1074                         b43legacy_phy_write(dev, 0x0036,
1075                                             (b43legacy_phy_read(dev, 0x0036)
1076                                              & 0x0FFF) | (phy->txctl2 << 12));
1077                 if (dev->dev->bus->sprom.boardflags_lo &
1078                     B43legacy_BFL_PACTRL)
1079                         b43legacy_phy_write(dev, 0x002E, 0x8075);
1080                 else
1081                         b43legacy_phy_write(dev, 0x002E, 0x807F);
1082                 if (phy->rev < 2)
1083                         b43legacy_phy_write(dev, 0x002F, 0x0101);
1084                 else
1085                         b43legacy_phy_write(dev, 0x002F, 0x0202);
1086         }
1087         if (phy->gmode) {
1088                 b43legacy_phy_lo_adjust(dev, 0);
1089                 b43legacy_phy_write(dev, 0x080F, 0x8078);
1090         }
1091
1092         if (!(dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_RSSI)) {
1093                 /* The specs state to update the NRSSI LT with
1094                  * the value 0x7FFFFFFF here. I think that is some weird
1095                  * compiler optimization in the original driver.
1096                  * Essentially, what we do here is resetting all NRSSI LT
1097                  * entries to -32 (see the clamp_val() in nrssi_hw_update())
1098                  */
1099                 b43legacy_nrssi_hw_update(dev, 0xFFFF);
1100                 b43legacy_calc_nrssi_threshold(dev);
1101         } else if (phy->gmode || phy->rev >= 2) {
1102                 if (phy->nrssi[0] == -1000) {
1103                         B43legacy_WARN_ON(phy->nrssi[1] != -1000);
1104                         b43legacy_calc_nrssi_slope(dev);
1105                 } else {
1106                         B43legacy_WARN_ON(phy->nrssi[1] == -1000);
1107                         b43legacy_calc_nrssi_threshold(dev);
1108                 }
1109         }
1110         if (phy->radio_rev == 8)
1111                 b43legacy_phy_write(dev, 0x0805, 0x3230);
1112         b43legacy_phy_init_pctl(dev);
1113         if (dev->dev->bus->chip_id == 0x4306
1114             && dev->dev->bus->chip_package == 2) {
1115                 b43legacy_phy_write(dev, 0x0429,
1116                                     b43legacy_phy_read(dev, 0x0429) & 0xBFFF);
1117                 b43legacy_phy_write(dev, 0x04C3,
1118                                     b43legacy_phy_read(dev, 0x04C3) & 0x7FFF);
1119         }
1120 }
1121
1122 static u16 b43legacy_phy_lo_b_r15_loop(struct b43legacy_wldev *dev)
1123 {
1124         int i;
1125         u16 ret = 0;
1126         unsigned long flags;
1127
1128         local_irq_save(flags);
1129         for (i = 0; i < 10; i++) {
1130                 b43legacy_phy_write(dev, 0x0015, 0xAFA0);
1131                 udelay(1);
1132                 b43legacy_phy_write(dev, 0x0015, 0xEFA0);
1133                 udelay(10);
1134                 b43legacy_phy_write(dev, 0x0015, 0xFFA0);
1135                 udelay(40);
1136                 ret += b43legacy_phy_read(dev, 0x002C);
1137         }
1138         local_irq_restore(flags);
1139         b43legacy_voluntary_preempt();
1140
1141         return ret;
1142 }
1143
1144 void b43legacy_phy_lo_b_measure(struct b43legacy_wldev *dev)
1145 {
1146         struct b43legacy_phy *phy = &dev->phy;
1147         u16 regstack[12] = { 0 };
1148         u16 mls;
1149         u16 fval;
1150         int i;
1151         int j;
1152
1153         regstack[0] = b43legacy_phy_read(dev, 0x0015);
1154         regstack[1] = b43legacy_radio_read16(dev, 0x0052) & 0xFFF0;
1155
1156         if (phy->radio_ver == 0x2053) {
1157                 regstack[2] = b43legacy_phy_read(dev, 0x000A);
1158                 regstack[3] = b43legacy_phy_read(dev, 0x002A);
1159                 regstack[4] = b43legacy_phy_read(dev, 0x0035);
1160                 regstack[5] = b43legacy_phy_read(dev, 0x0003);
1161                 regstack[6] = b43legacy_phy_read(dev, 0x0001);
1162                 regstack[7] = b43legacy_phy_read(dev, 0x0030);
1163
1164                 regstack[8] = b43legacy_radio_read16(dev, 0x0043);
1165                 regstack[9] = b43legacy_radio_read16(dev, 0x007A);
1166                 regstack[10] = b43legacy_read16(dev, 0x03EC);
1167                 regstack[11] = b43legacy_radio_read16(dev, 0x0052) & 0x00F0;
1168
1169                 b43legacy_phy_write(dev, 0x0030, 0x00FF);
1170                 b43legacy_write16(dev, 0x03EC, 0x3F3F);
1171                 b43legacy_phy_write(dev, 0x0035, regstack[4] & 0xFF7F);
1172                 b43legacy_radio_write16(dev, 0x007A, regstack[9] & 0xFFF0);
1173         }
1174         b43legacy_phy_write(dev, 0x0015, 0xB000);
1175         b43legacy_phy_write(dev, 0x002B, 0x0004);
1176
1177         if (phy->radio_ver == 0x2053) {
1178                 b43legacy_phy_write(dev, 0x002B, 0x0203);
1179                 b43legacy_phy_write(dev, 0x002A, 0x08A3);
1180         }
1181
1182         phy->minlowsig[0] = 0xFFFF;
1183
1184         for (i = 0; i < 4; i++) {
1185                 b43legacy_radio_write16(dev, 0x0052, regstack[1] | i);
1186                 b43legacy_phy_lo_b_r15_loop(dev);
1187         }
1188         for (i = 0; i < 10; i++) {
1189                 b43legacy_radio_write16(dev, 0x0052, regstack[1] | i);
1190                 mls = b43legacy_phy_lo_b_r15_loop(dev) / 10;
1191                 if (mls < phy->minlowsig[0]) {
1192                         phy->minlowsig[0] = mls;
1193                         phy->minlowsigpos[0] = i;
1194                 }
1195         }
1196         b43legacy_radio_write16(dev, 0x0052, regstack[1]
1197                                 | phy->minlowsigpos[0]);
1198
1199         phy->minlowsig[1] = 0xFFFF;
1200
1201         for (i = -4; i < 5; i += 2) {
1202                 for (j = -4; j < 5; j += 2) {
1203                         if (j < 0)
1204                                 fval = (0x0100 * i) + j + 0x0100;
1205                         else
1206                                 fval = (0x0100 * i) + j;
1207                         b43legacy_phy_write(dev, 0x002F, fval);
1208                         mls = b43legacy_phy_lo_b_r15_loop(dev) / 10;
1209                         if (mls < phy->minlowsig[1]) {
1210                                 phy->minlowsig[1] = mls;
1211                                 phy->minlowsigpos[1] = fval;
1212                         }
1213                 }
1214         }
1215         phy->minlowsigpos[1] += 0x0101;
1216
1217         b43legacy_phy_write(dev, 0x002F, phy->minlowsigpos[1]);
1218         if (phy->radio_ver == 0x2053) {
1219                 b43legacy_phy_write(dev, 0x000A, regstack[2]);
1220                 b43legacy_phy_write(dev, 0x002A, regstack[3]);
1221                 b43legacy_phy_write(dev, 0x0035, regstack[4]);
1222                 b43legacy_phy_write(dev, 0x0003, regstack[5]);
1223                 b43legacy_phy_write(dev, 0x0001, regstack[6]);
1224                 b43legacy_phy_write(dev, 0x0030, regstack[7]);
1225
1226                 b43legacy_radio_write16(dev, 0x0043, regstack[8]);
1227                 b43legacy_radio_write16(dev, 0x007A, regstack[9]);
1228
1229                 b43legacy_radio_write16(dev, 0x0052,
1230                                         (b43legacy_radio_read16(dev, 0x0052)
1231                                         & 0x000F) | regstack[11]);
1232
1233                 b43legacy_write16(dev, 0x03EC, regstack[10]);
1234         }
1235         b43legacy_phy_write(dev, 0x0015, regstack[0]);
1236 }
1237
1238 static inline
1239 u16 b43legacy_phy_lo_g_deviation_subval(struct b43legacy_wldev *dev,
1240                                         u16 control)
1241 {
1242         struct b43legacy_phy *phy = &dev->phy;
1243         u16 ret;
1244         unsigned long flags;
1245
1246         local_irq_save(flags);
1247         if (phy->gmode) {
1248                 b43legacy_phy_write(dev, 0x15, 0xE300);
1249                 control <<= 8;
1250                 b43legacy_phy_write(dev, 0x0812, control | 0x00B0);
1251                 udelay(5);
1252                 b43legacy_phy_write(dev, 0x0812, control | 0x00B2);
1253                 udelay(2);
1254                 b43legacy_phy_write(dev, 0x0812, control | 0x00B3);
1255                 udelay(4);
1256                 b43legacy_phy_write(dev, 0x0015, 0xF300);
1257                 udelay(8);
1258         } else {
1259                 b43legacy_phy_write(dev, 0x0015, control | 0xEFA0);
1260                 udelay(2);
1261                 b43legacy_phy_write(dev, 0x0015, control | 0xEFE0);
1262                 udelay(4);
1263                 b43legacy_phy_write(dev, 0x0015, control | 0xFFE0);
1264                 udelay(8);
1265         }
1266         ret = b43legacy_phy_read(dev, 0x002D);
1267         local_irq_restore(flags);
1268         b43legacy_voluntary_preempt();
1269
1270         return ret;
1271 }
1272
1273 static u32 b43legacy_phy_lo_g_singledeviation(struct b43legacy_wldev *dev,
1274                                               u16 control)
1275 {
1276         int i;
1277         u32 ret = 0;
1278
1279         for (i = 0; i < 8; i++)
1280                 ret += b43legacy_phy_lo_g_deviation_subval(dev, control);
1281
1282         return ret;
1283 }
1284
1285 /* Write the LocalOscillator CONTROL */
1286 static inline
1287 void b43legacy_lo_write(struct b43legacy_wldev *dev,
1288                         struct b43legacy_lopair *pair)
1289 {
1290         u16 value;
1291
1292         value = (u8)(pair->low);
1293         value |= ((u8)(pair->high)) << 8;
1294
1295 #ifdef CONFIG_B43LEGACY_DEBUG
1296         /* Sanity check. */
1297         if (pair->low < -8 || pair->low > 8 ||
1298             pair->high < -8 || pair->high > 8) {
1299                 b43legacydbg(dev->wl,
1300                        "WARNING: Writing invalid LOpair "
1301                        "(low: %d, high: %d)\n",
1302                        pair->low, pair->high);
1303                 dump_stack();
1304         }
1305 #endif
1306
1307         b43legacy_phy_write(dev, B43legacy_PHY_G_LO_CONTROL, value);
1308 }
1309
1310 static inline
1311 struct b43legacy_lopair *b43legacy_find_lopair(struct b43legacy_wldev *dev,
1312                                                u16 bbatt,
1313                                                u16 rfatt,
1314                                                u16 tx)
1315 {
1316         static const u8 dict[10] = { 11, 10, 11, 12, 13, 12, 13, 12, 13, 12 };
1317         struct b43legacy_phy *phy = &dev->phy;
1318
1319         if (bbatt > 6)
1320                 bbatt = 6;
1321         B43legacy_WARN_ON(rfatt >= 10);
1322
1323         if (tx == 3)
1324                 return b43legacy_get_lopair(phy, rfatt, bbatt);
1325         return b43legacy_get_lopair(phy, dict[rfatt], bbatt);
1326 }
1327
1328 static inline
1329 struct b43legacy_lopair *b43legacy_current_lopair(struct b43legacy_wldev *dev)
1330 {
1331         struct b43legacy_phy *phy = &dev->phy;
1332
1333         return b43legacy_find_lopair(dev, phy->bbatt,
1334                                      phy->rfatt, phy->txctl1);
1335 }
1336
1337 /* Adjust B/G LO */
1338 void b43legacy_phy_lo_adjust(struct b43legacy_wldev *dev, int fixed)
1339 {
1340         struct b43legacy_lopair *pair;
1341
1342         if (fixed) {
1343                 /* Use fixed values. Only for initialization. */
1344                 pair = b43legacy_find_lopair(dev, 2, 3, 0);
1345         } else
1346                 pair = b43legacy_current_lopair(dev);
1347         b43legacy_lo_write(dev, pair);
1348 }
1349
1350 static void b43legacy_phy_lo_g_measure_txctl2(struct b43legacy_wldev *dev)
1351 {
1352         struct b43legacy_phy *phy = &dev->phy;
1353         u16 txctl2 = 0;
1354         u16 i;
1355         u32 smallest;
1356         u32 tmp;
1357
1358         b43legacy_radio_write16(dev, 0x0052, 0x0000);
1359         udelay(10);
1360         smallest = b43legacy_phy_lo_g_singledeviation(dev, 0);
1361         for (i = 0; i < 16; i++) {
1362                 b43legacy_radio_write16(dev, 0x0052, i);
1363                 udelay(10);
1364                 tmp = b43legacy_phy_lo_g_singledeviation(dev, 0);
1365                 if (tmp < smallest) {
1366                         smallest = tmp;
1367                         txctl2 = i;
1368                 }
1369         }
1370         phy->txctl2 = txctl2;
1371 }
1372
1373 static
1374 void b43legacy_phy_lo_g_state(struct b43legacy_wldev *dev,
1375                               const struct b43legacy_lopair *in_pair,
1376                               struct b43legacy_lopair *out_pair,
1377                               u16 r27)
1378 {
1379         static const struct b43legacy_lopair transitions[8] = {
1380                 { .high =  1,  .low =  1, },
1381                 { .high =  1,  .low =  0, },
1382                 { .high =  1,  .low = -1, },
1383                 { .high =  0,  .low = -1, },
1384                 { .high = -1,  .low = -1, },
1385                 { .high = -1,  .low =  0, },
1386                 { .high = -1,  .low =  1, },
1387                 { .high =  0,  .low =  1, },
1388         };
1389         struct b43legacy_lopair lowest_transition = {
1390                 .high = in_pair->high,
1391                 .low = in_pair->low,
1392         };
1393         struct b43legacy_lopair tmp_pair;
1394         struct b43legacy_lopair transition;
1395         int i = 12;
1396         int state = 0;
1397         int found_lower;
1398         int j;
1399         int begin;
1400         int end;
1401         u32 lowest_deviation;
1402         u32 tmp;
1403
1404         /* Note that in_pair and out_pair can point to the same pair.
1405          * Be careful. */
1406
1407         b43legacy_lo_write(dev, &lowest_transition);
1408         lowest_deviation = b43legacy_phy_lo_g_singledeviation(dev, r27);
1409         do {
1410                 found_lower = 0;
1411                 B43legacy_WARN_ON(!(state >= 0 && state <= 8));
1412                 if (state == 0) {
1413                         begin = 1;
1414                         end = 8;
1415                 } else if (state % 2 == 0) {
1416                         begin = state - 1;
1417                         end = state + 1;
1418                 } else {
1419                         begin = state - 2;
1420                         end = state + 2;
1421                 }
1422                 if (begin < 1)
1423                         begin += 8;
1424                 if (end > 8)
1425                         end -= 8;
1426
1427                 j = begin;
1428                 tmp_pair.high = lowest_transition.high;
1429                 tmp_pair.low = lowest_transition.low;
1430                 while (1) {
1431                         B43legacy_WARN_ON(!(j >= 1 && j <= 8));
1432                         transition.high = tmp_pair.high +
1433                                           transitions[j - 1].high;
1434                         transition.low = tmp_pair.low + transitions[j - 1].low;
1435                         if ((abs(transition.low) < 9)
1436                              && (abs(transition.high) < 9)) {
1437                                 b43legacy_lo_write(dev, &transition);
1438                                 tmp = b43legacy_phy_lo_g_singledeviation(dev,
1439                                                                        r27);
1440                                 if (tmp < lowest_deviation) {
1441                                         lowest_deviation = tmp;
1442                                         state = j;
1443                                         found_lower = 1;
1444
1445                                         lowest_transition.high =
1446                                                                 transition.high;
1447                                         lowest_transition.low = transition.low;
1448                                 }
1449                         }
1450                         if (j == end)
1451                                 break;
1452                         if (j == 8)
1453                                 j = 1;
1454                         else
1455                                 j++;
1456                 }
1457         } while (i-- && found_lower);
1458
1459         out_pair->high = lowest_transition.high;
1460         out_pair->low = lowest_transition.low;
1461 }
1462
1463 /* Set the baseband attenuation value on chip. */
1464 void b43legacy_phy_set_baseband_attenuation(struct b43legacy_wldev *dev,
1465                                             u16 bbatt)
1466 {
1467         struct b43legacy_phy *phy = &dev->phy;
1468         u16 value;
1469
1470         if (phy->analog == 0) {
1471                 value = (b43legacy_read16(dev, 0x03E6) & 0xFFF0);
1472                 value |= (bbatt & 0x000F);
1473                 b43legacy_write16(dev, 0x03E6, value);
1474                 return;
1475         }
1476
1477         if (phy->analog > 1) {
1478                 value = b43legacy_phy_read(dev, 0x0060) & 0xFFC3;
1479                 value |= (bbatt << 2) & 0x003C;
1480         } else {
1481                 value = b43legacy_phy_read(dev, 0x0060) & 0xFF87;
1482                 value |= (bbatt << 3) & 0x0078;
1483         }
1484         b43legacy_phy_write(dev, 0x0060, value);
1485 }
1486
1487 /* http://bcm-specs.sipsolutions.net/LocalOscillator/Measure */
1488 void b43legacy_phy_lo_g_measure(struct b43legacy_wldev *dev)
1489 {
1490         static const u8 pairorder[10] = { 3, 1, 5, 7, 9, 2, 0, 4, 6, 8 };
1491         const int is_initializing = (b43legacy_status(dev)
1492                                      < B43legacy_STAT_STARTED);
1493         struct b43legacy_phy *phy = &dev->phy;
1494         u16 h;
1495         u16 i;
1496         u16 oldi = 0;
1497         u16 j;
1498         struct b43legacy_lopair control;
1499         struct b43legacy_lopair *tmp_control;
1500         u16 tmp;
1501         u16 regstack[16] = { 0 };
1502         u8 oldchannel;
1503
1504         /* XXX: What are these? */
1505         u8 r27 = 0;
1506         u16 r31;
1507
1508         oldchannel = phy->channel;
1509         /* Setup */
1510         if (phy->gmode) {
1511                 regstack[0] = b43legacy_phy_read(dev, B43legacy_PHY_G_CRS);
1512                 regstack[1] = b43legacy_phy_read(dev, 0x0802);
1513                 b43legacy_phy_write(dev, B43legacy_PHY_G_CRS, regstack[0]
1514                                     & 0x7FFF);
1515                 b43legacy_phy_write(dev, 0x0802, regstack[1] & 0xFFFC);
1516         }
1517         regstack[3] = b43legacy_read16(dev, 0x03E2);
1518         b43legacy_write16(dev, 0x03E2, regstack[3] | 0x8000);
1519         regstack[4] = b43legacy_read16(dev, B43legacy_MMIO_CHANNEL_EXT);
1520         regstack[5] = b43legacy_phy_read(dev, 0x15);
1521         regstack[6] = b43legacy_phy_read(dev, 0x2A);
1522         regstack[7] = b43legacy_phy_read(dev, 0x35);
1523         regstack[8] = b43legacy_phy_read(dev, 0x60);
1524         regstack[9] = b43legacy_radio_read16(dev, 0x43);
1525         regstack[10] = b43legacy_radio_read16(dev, 0x7A);
1526         regstack[11] = b43legacy_radio_read16(dev, 0x52);
1527         if (phy->gmode) {
1528                 regstack[12] = b43legacy_phy_read(dev, 0x0811);
1529                 regstack[13] = b43legacy_phy_read(dev, 0x0812);
1530                 regstack[14] = b43legacy_phy_read(dev, 0x0814);
1531                 regstack[15] = b43legacy_phy_read(dev, 0x0815);
1532         }
1533         b43legacy_radio_selectchannel(dev, 6, 0);
1534         if (phy->gmode) {
1535                 b43legacy_phy_write(dev, B43legacy_PHY_G_CRS, regstack[0]
1536                                     & 0x7FFF);
1537                 b43legacy_phy_write(dev, 0x0802, regstack[1] & 0xFFFC);
1538                 b43legacy_dummy_transmission(dev);
1539         }
1540         b43legacy_radio_write16(dev, 0x0043, 0x0006);
1541
1542         b43legacy_phy_set_baseband_attenuation(dev, 2);
1543
1544         b43legacy_write16(dev, B43legacy_MMIO_CHANNEL_EXT, 0x0000);
1545         b43legacy_phy_write(dev, 0x002E, 0x007F);
1546         b43legacy_phy_write(dev, 0x080F, 0x0078);
1547         b43legacy_phy_write(dev, 0x0035, regstack[7] & ~(1 << 7));
1548         b43legacy_radio_write16(dev, 0x007A, regstack[10] & 0xFFF0);
1549         b43legacy_phy_write(dev, 0x002B, 0x0203);
1550         b43legacy_phy_write(dev, 0x002A, 0x08A3);
1551         if (phy->gmode) {
1552                 b43legacy_phy_write(dev, 0x0814, regstack[14] | 0x0003);
1553                 b43legacy_phy_write(dev, 0x0815, regstack[15] & 0xFFFC);
1554                 b43legacy_phy_write(dev, 0x0811, 0x01B3);
1555                 b43legacy_phy_write(dev, 0x0812, 0x00B2);
1556         }
1557         if (is_initializing)
1558                 b43legacy_phy_lo_g_measure_txctl2(dev);
1559         b43legacy_phy_write(dev, 0x080F, 0x8078);
1560
1561         /* Measure */
1562         control.low = 0;
1563         control.high = 0;
1564         for (h = 0; h < 10; h++) {
1565                 /* Loop over each possible RadioAttenuation (0-9) */
1566                 i = pairorder[h];
1567                 if (is_initializing) {
1568                         if (i == 3) {
1569                                 control.low = 0;
1570                                 control.high = 0;
1571                         } else if (((i % 2 == 1) && (oldi % 2 == 1)) ||
1572                                   ((i % 2 == 0) && (oldi % 2 == 0))) {
1573                                 tmp_control = b43legacy_get_lopair(phy, oldi,
1574                                                                    0);
1575                                 memcpy(&control, tmp_control, sizeof(control));
1576                         } else {
1577                                 tmp_control = b43legacy_get_lopair(phy, 3, 0);
1578                                 memcpy(&control, tmp_control, sizeof(control));
1579                         }
1580                 }
1581                 /* Loop over each possible BasebandAttenuation/2 */
1582                 for (j = 0; j < 4; j++) {
1583                         if (is_initializing) {
1584                                 tmp = i * 2 + j;
1585                                 r27 = 0;
1586                                 r31 = 0;
1587                                 if (tmp > 14) {
1588                                         r31 = 1;
1589                                         if (tmp > 17)
1590                                                 r27 = 1;
1591                                         if (tmp > 19)
1592                                                 r27 = 2;
1593                                 }
1594                         } else {
1595                                 tmp_control = b43legacy_get_lopair(phy, i,
1596                                                                    j * 2);
1597                                 if (!tmp_control->used)
1598                                         continue;
1599                                 memcpy(&control, tmp_control, sizeof(control));
1600                                 r27 = 3;
1601                                 r31 = 0;
1602                         }
1603                         b43legacy_radio_write16(dev, 0x43, i);
1604                         b43legacy_radio_write16(dev, 0x52, phy->txctl2);
1605                         udelay(10);
1606                         b43legacy_voluntary_preempt();
1607
1608                         b43legacy_phy_set_baseband_attenuation(dev, j * 2);
1609
1610                         tmp = (regstack[10] & 0xFFF0);
1611                         if (r31)
1612                                 tmp |= 0x0008;
1613                         b43legacy_radio_write16(dev, 0x007A, tmp);
1614
1615                         tmp_control = b43legacy_get_lopair(phy, i, j * 2);
1616                         b43legacy_phy_lo_g_state(dev, &control, tmp_control,
1617                                                  r27);
1618                 }
1619                 oldi = i;
1620         }
1621         /* Loop over each possible RadioAttenuation (10-13) */
1622         for (i = 10; i < 14; i++) {
1623                 /* Loop over each possible BasebandAttenuation/2 */
1624                 for (j = 0; j < 4; j++) {
1625                         if (is_initializing) {
1626                                 tmp_control = b43legacy_get_lopair(phy, i - 9,
1627                                                                  j * 2);
1628                                 memcpy(&control, tmp_control, sizeof(control));
1629                                 /* FIXME: The next line is wrong, as the
1630                                  * following if statement can never trigger. */
1631                                 tmp = (i - 9) * 2 + j - 5;
1632                                 r27 = 0;
1633                                 r31 = 0;
1634                                 if (tmp > 14) {
1635                                         r31 = 1;
1636                                         if (tmp > 17)
1637                                                 r27 = 1;
1638                                         if (tmp > 19)
1639                                                 r27 = 2;
1640                                 }
1641                         } else {
1642                                 tmp_control = b43legacy_get_lopair(phy, i - 9,
1643                                                                    j * 2);
1644                                 if (!tmp_control->used)
1645                                         continue;
1646                                 memcpy(&control, tmp_control, sizeof(control));
1647                                 r27 = 3;
1648                                 r31 = 0;
1649                         }
1650                         b43legacy_radio_write16(dev, 0x43, i - 9);
1651                         /* FIXME: shouldn't txctl1 be zero in the next line
1652                          * and 3 in the loop above? */
1653                         b43legacy_radio_write16(dev, 0x52,
1654                                               phy->txctl2
1655                                               | (3/*txctl1*/ << 4));
1656                         udelay(10);
1657                         b43legacy_voluntary_preempt();
1658
1659                         b43legacy_phy_set_baseband_attenuation(dev, j * 2);
1660
1661                         tmp = (regstack[10] & 0xFFF0);
1662                         if (r31)
1663                                 tmp |= 0x0008;
1664                         b43legacy_radio_write16(dev, 0x7A, tmp);
1665
1666                         tmp_control = b43legacy_get_lopair(phy, i, j * 2);
1667                         b43legacy_phy_lo_g_state(dev, &control, tmp_control,
1668                                                  r27);
1669                 }
1670         }
1671
1672         /* Restoration */
1673         if (phy->gmode) {
1674                 b43legacy_phy_write(dev, 0x0015, 0xE300);
1675                 b43legacy_phy_write(dev, 0x0812, (r27 << 8) | 0xA0);
1676                 udelay(5);
1677                 b43legacy_phy_write(dev, 0x0812, (r27 << 8) | 0xA2);
1678                 udelay(2);
1679                 b43legacy_phy_write(dev, 0x0812, (r27 << 8) | 0xA3);
1680                 b43legacy_voluntary_preempt();
1681         } else
1682                 b43legacy_phy_write(dev, 0x0015, r27 | 0xEFA0);
1683         b43legacy_phy_lo_adjust(dev, is_initializing);
1684         b43legacy_phy_write(dev, 0x002E, 0x807F);
1685         if (phy->gmode)
1686                 b43legacy_phy_write(dev, 0x002F, 0x0202);
1687         else
1688                 b43legacy_phy_write(dev, 0x002F, 0x0101);
1689         b43legacy_write16(dev, B43legacy_MMIO_CHANNEL_EXT, regstack[4]);
1690         b43legacy_phy_write(dev, 0x0015, regstack[5]);
1691         b43legacy_phy_write(dev, 0x002A, regstack[6]);
1692         b43legacy_phy_write(dev, 0x0035, regstack[7]);
1693         b43legacy_phy_write(dev, 0x0060, regstack[8]);
1694         b43legacy_radio_write16(dev, 0x0043, regstack[9]);
1695         b43legacy_radio_write16(dev, 0x007A, regstack[10]);
1696         regstack[11] &= 0x00F0;
1697         regstack[11] |= (b43legacy_radio_read16(dev, 0x52) & 0x000F);
1698         b43legacy_radio_write16(dev, 0x52, regstack[11]);
1699         b43legacy_write16(dev, 0x03E2, regstack[3]);
1700         if (phy->gmode) {
1701                 b43legacy_phy_write(dev, 0x0811, regstack[12]);
1702                 b43legacy_phy_write(dev, 0x0812, regstack[13]);
1703                 b43legacy_phy_write(dev, 0x0814, regstack[14]);
1704                 b43legacy_phy_write(dev, 0x0815, regstack[15]);
1705                 b43legacy_phy_write(dev, B43legacy_PHY_G_CRS, regstack[0]);
1706                 b43legacy_phy_write(dev, 0x0802, regstack[1]);
1707         }
1708         b43legacy_radio_selectchannel(dev, oldchannel, 1);
1709
1710 #ifdef CONFIG_B43LEGACY_DEBUG
1711         {
1712                 /* Sanity check for all lopairs. */
1713                 for (i = 0; i < B43legacy_LO_COUNT; i++) {
1714                         tmp_control = phy->_lo_pairs + i;
1715                         if (tmp_control->low < -8 || tmp_control->low > 8 ||
1716                             tmp_control->high < -8 || tmp_control->high > 8)
1717                                 b43legacywarn(dev->wl,
1718                                        "WARNING: Invalid LOpair (low: %d, high:"
1719                                        " %d, index: %d)\n",
1720                                        tmp_control->low, tmp_control->high, i);
1721                 }
1722         }
1723 #endif /* CONFIG_B43LEGACY_DEBUG */
1724 }
1725
1726 static
1727 void b43legacy_phy_lo_mark_current_used(struct b43legacy_wldev *dev)
1728 {
1729         struct b43legacy_lopair *pair;
1730
1731         pair = b43legacy_current_lopair(dev);
1732         pair->used = 1;
1733 }
1734
1735 void b43legacy_phy_lo_mark_all_unused(struct b43legacy_wldev *dev)
1736 {
1737         struct b43legacy_phy *phy = &dev->phy;
1738         struct b43legacy_lopair *pair;
1739         int i;
1740
1741         for (i = 0; i < B43legacy_LO_COUNT; i++) {
1742                 pair = phy->_lo_pairs + i;
1743                 pair->used = 0;
1744         }
1745 }
1746
1747 /* http://bcm-specs.sipsolutions.net/EstimatePowerOut
1748  * This function converts a TSSI value to dBm in Q5.2
1749  */
1750 static s8 b43legacy_phy_estimate_power_out(struct b43legacy_wldev *dev, s8 tssi)
1751 {
1752         struct b43legacy_phy *phy = &dev->phy;
1753         s8 dbm = 0;
1754         s32 tmp;
1755
1756         tmp = phy->idle_tssi;
1757         tmp += tssi;
1758         tmp -= phy->savedpctlreg;
1759
1760         switch (phy->type) {
1761         case B43legacy_PHYTYPE_B:
1762         case B43legacy_PHYTYPE_G:
1763                 tmp = clamp_val(tmp, 0x00, 0x3F);
1764                 dbm = phy->tssi2dbm[tmp];
1765                 break;
1766         default:
1767                 B43legacy_BUG_ON(1);
1768         }
1769
1770         return dbm;
1771 }
1772
1773 /* http://bcm-specs.sipsolutions.net/RecalculateTransmissionPower */
1774 void b43legacy_phy_xmitpower(struct b43legacy_wldev *dev)
1775 {
1776         struct b43legacy_phy *phy = &dev->phy;
1777         u16 tmp;
1778         u16 txpower;
1779         s8 v0;
1780         s8 v1;
1781         s8 v2;
1782         s8 v3;
1783         s8 average;
1784         int max_pwr;
1785         s16 desired_pwr;
1786         s16 estimated_pwr;
1787         s16 pwr_adjust;
1788         s16 radio_att_delta;
1789         s16 baseband_att_delta;
1790         s16 radio_attenuation;
1791         s16 baseband_attenuation;
1792
1793         if (phy->savedpctlreg == 0xFFFF)
1794                 return;
1795         if ((dev->dev->bus->boardinfo.type == 0x0416) &&
1796             is_bcm_board_vendor(dev))
1797                 return;
1798 #ifdef CONFIG_B43LEGACY_DEBUG
1799         if (phy->manual_txpower_control)
1800                 return;
1801 #endif
1802
1803         B43legacy_BUG_ON(!(phy->type == B43legacy_PHYTYPE_B ||
1804                          phy->type == B43legacy_PHYTYPE_G));
1805         tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x0058);
1806         v0 = (s8)(tmp & 0x00FF);
1807         v1 = (s8)((tmp & 0xFF00) >> 8);
1808         tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x005A);
1809         v2 = (s8)(tmp & 0x00FF);
1810         v3 = (s8)((tmp & 0xFF00) >> 8);
1811         tmp = 0;
1812
1813         if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F || v3 == 0x7F) {
1814                 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1815                                          0x0070);
1816                 v0 = (s8)(tmp & 0x00FF);
1817                 v1 = (s8)((tmp & 0xFF00) >> 8);
1818                 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1819                                          0x0072);
1820                 v2 = (s8)(tmp & 0x00FF);
1821                 v3 = (s8)((tmp & 0xFF00) >> 8);
1822                 if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F || v3 == 0x7F)
1823                         return;
1824                 v0 = (v0 + 0x20) & 0x3F;
1825                 v1 = (v1 + 0x20) & 0x3F;
1826                 v2 = (v2 + 0x20) & 0x3F;
1827                 v3 = (v3 + 0x20) & 0x3F;
1828                 tmp = 1;
1829         }
1830         b43legacy_radio_clear_tssi(dev);
1831
1832         average = (v0 + v1 + v2 + v3 + 2) / 4;
1833
1834         if (tmp && (b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x005E)
1835             & 0x8))
1836                 average -= 13;
1837
1838         estimated_pwr = b43legacy_phy_estimate_power_out(dev, average);
1839
1840         max_pwr = dev->dev->bus->sprom.maxpwr_bg;
1841
1842         if ((dev->dev->bus->sprom.boardflags_lo
1843              & B43legacy_BFL_PACTRL) &&
1844             (phy->type == B43legacy_PHYTYPE_G))
1845                 max_pwr -= 0x3;
1846         if (unlikely(max_pwr <= 0)) {
1847                 b43legacywarn(dev->wl, "Invalid max-TX-power value in SPROM."
1848                         "\n");
1849                 max_pwr = 74; /* fake it */
1850                 dev->dev->bus->sprom.maxpwr_bg = max_pwr;
1851         }
1852
1853         /* Use regulatory information to get the maximum power.
1854          * In the absence of such data from mac80211, we will use 20 dBm, which
1855          * is the value for the EU, US, Canada, and most of the world.
1856          * The regulatory maximum is reduced by the antenna gain (from sprom)
1857          * and 1.5 dBm (a safety factor??). The result is in Q5.2 format
1858          * which accounts for the factor of 4 */
1859 #define REG_MAX_PWR 20
1860         max_pwr = min(REG_MAX_PWR * 4
1861                       - dev->dev->bus->sprom.antenna_gain.ghz24.a0
1862                       - 0x6, max_pwr);
1863
1864         /* find the desired power in Q5.2 - power_level is in dBm
1865          * and limit it - max_pwr is already in Q5.2 */
1866         desired_pwr = clamp_val(phy->power_level << 2, 0, max_pwr);
1867         if (b43legacy_debug(dev, B43legacy_DBG_XMITPOWER))
1868                 b43legacydbg(dev->wl, "Current TX power output: " Q52_FMT
1869                        " dBm, Desired TX power output: " Q52_FMT
1870                        " dBm\n", Q52_ARG(estimated_pwr),
1871                        Q52_ARG(desired_pwr));
1872         /* Check if we need to adjust the current power. The factor of 2 is
1873          * for damping */
1874         pwr_adjust = (desired_pwr - estimated_pwr) / 2;
1875         /* RF attenuation delta
1876          * The minus sign is because lower attenuation => more power */
1877         radio_att_delta = -(pwr_adjust + 7) >> 3;
1878         /* Baseband attenuation delta */
1879         baseband_att_delta = -(pwr_adjust >> 1) - (4 * radio_att_delta);
1880         /* Do we need to adjust anything? */
1881         if ((radio_att_delta == 0) && (baseband_att_delta == 0)) {
1882                 b43legacy_phy_lo_mark_current_used(dev);
1883                 return;
1884         }
1885
1886         /* Calculate the new attenuation values. */
1887         baseband_attenuation = phy->bbatt;
1888         baseband_attenuation += baseband_att_delta;
1889         radio_attenuation = phy->rfatt;
1890         radio_attenuation += radio_att_delta;
1891
1892         /* Get baseband and radio attenuation values into permitted ranges.
1893          * baseband 0-11, radio 0-9.
1894          * Radio attenuation affects power level 4 times as much as baseband.
1895          */
1896         if (radio_attenuation < 0) {
1897                 baseband_attenuation -= (4 * -radio_attenuation);
1898                 radio_attenuation = 0;
1899         } else if (radio_attenuation > 9) {
1900                 baseband_attenuation += (4 * (radio_attenuation - 9));
1901                 radio_attenuation = 9;
1902         } else {
1903                 while (baseband_attenuation < 0 && radio_attenuation > 0) {
1904                         baseband_attenuation += 4;
1905                         radio_attenuation--;
1906                 }
1907                 while (baseband_attenuation > 11 && radio_attenuation < 9) {
1908                         baseband_attenuation -= 4;
1909                         radio_attenuation++;
1910                 }
1911         }
1912         baseband_attenuation = clamp_val(baseband_attenuation, 0, 11);
1913
1914         txpower = phy->txctl1;
1915         if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 2)) {
1916                 if (radio_attenuation <= 1) {
1917                         if (txpower == 0) {
1918                                 txpower = 3;
1919                                 radio_attenuation += 2;
1920                                 baseband_attenuation += 2;
1921                         } else if (dev->dev->bus->sprom.boardflags_lo
1922                                    & B43legacy_BFL_PACTRL) {
1923                                 baseband_attenuation += 4 *
1924                                                      (radio_attenuation - 2);
1925                                 radio_attenuation = 2;
1926                         }
1927                 } else if (radio_attenuation > 4 && txpower != 0) {
1928                         txpower = 0;
1929                         if (baseband_attenuation < 3) {
1930                                 radio_attenuation -= 3;
1931                                 baseband_attenuation += 2;
1932                         } else {
1933                                 radio_attenuation -= 2;
1934                                 baseband_attenuation -= 2;
1935                         }
1936                 }
1937         }
1938         /* Save the control values */
1939         phy->txctl1 = txpower;
1940         baseband_attenuation = clamp_val(baseband_attenuation, 0, 11);
1941         radio_attenuation = clamp_val(radio_attenuation, 0, 9);
1942         phy->rfatt = radio_attenuation;
1943         phy->bbatt = baseband_attenuation;
1944
1945         /* Adjust the hardware */
1946         b43legacy_phy_lock(dev);
1947         b43legacy_radio_lock(dev);
1948         b43legacy_radio_set_txpower_bg(dev, baseband_attenuation,
1949                                        radio_attenuation, txpower);
1950         b43legacy_phy_lo_mark_current_used(dev);
1951         b43legacy_radio_unlock(dev);
1952         b43legacy_phy_unlock(dev);
1953 }
1954
1955 static inline
1956 s32 b43legacy_tssi2dbm_ad(s32 num, s32 den)
1957 {
1958         if (num < 0)
1959                 return num/den;
1960         else
1961                 return (num+den/2)/den;
1962 }
1963
1964 static inline
1965 s8 b43legacy_tssi2dbm_entry(s8 entry [], u8 index, s16 pab0, s16 pab1, s16 pab2)
1966 {
1967         s32 m1;
1968         s32 m2;
1969         s32 f = 256;
1970         s32 q;
1971         s32 delta;
1972         s8 i = 0;
1973
1974         m1 = b43legacy_tssi2dbm_ad(16 * pab0 + index * pab1, 32);
1975         m2 = max(b43legacy_tssi2dbm_ad(32768 + index * pab2, 256), 1);
1976         do {
1977                 if (i > 15)
1978                         return -EINVAL;
1979                 q = b43legacy_tssi2dbm_ad(f * 4096 -
1980                                           b43legacy_tssi2dbm_ad(m2 * f, 16) *
1981                                           f, 2048);
1982                 delta = abs(q - f);
1983                 f = q;
1984                 i++;
1985         } while (delta >= 2);
1986         entry[index] = clamp_val(b43legacy_tssi2dbm_ad(m1 * f, 8192),
1987                                    -127, 128);
1988         return 0;
1989 }
1990
1991 /* http://bcm-specs.sipsolutions.net/TSSI_to_DBM_Table */
1992 int b43legacy_phy_init_tssi2dbm_table(struct b43legacy_wldev *dev)
1993 {
1994         struct b43legacy_phy *phy = &dev->phy;
1995         s16 pab0;
1996         s16 pab1;
1997         s16 pab2;
1998         u8 idx;
1999         s8 *dyn_tssi2dbm;
2000
2001         B43legacy_WARN_ON(!(phy->type == B43legacy_PHYTYPE_B ||
2002                           phy->type == B43legacy_PHYTYPE_G));
2003         pab0 = (s16)(dev->dev->bus->sprom.pa0b0);
2004         pab1 = (s16)(dev->dev->bus->sprom.pa0b1);
2005         pab2 = (s16)(dev->dev->bus->sprom.pa0b2);
2006
2007         if ((dev->dev->bus->chip_id == 0x4301) && (phy->radio_ver != 0x2050)) {
2008                 phy->idle_tssi = 0x34;
2009                 phy->tssi2dbm = b43legacy_tssi2dbm_b_table;
2010                 return 0;
2011         }
2012
2013         if (pab0 != 0 && pab1 != 0 && pab2 != 0 &&
2014             pab0 != -1 && pab1 != -1 && pab2 != -1) {
2015                 /* The pabX values are set in SPROM. Use them. */
2016                 if ((s8)dev->dev->bus->sprom.itssi_bg != 0 &&
2017                     (s8)dev->dev->bus->sprom.itssi_bg != -1)
2018                         phy->idle_tssi = (s8)(dev->dev->bus->sprom.
2019                                           itssi_bg);
2020                 else
2021                         phy->idle_tssi = 62;
2022                 dyn_tssi2dbm = kmalloc(64, GFP_KERNEL);
2023                 if (dyn_tssi2dbm == NULL) {
2024                         b43legacyerr(dev->wl, "Could not allocate memory "
2025                                "for tssi2dbm table\n");
2026                         return -ENOMEM;
2027                 }
2028                 for (idx = 0; idx < 64; idx++)
2029                         if (b43legacy_tssi2dbm_entry(dyn_tssi2dbm, idx, pab0,
2030                                                      pab1, pab2)) {
2031                                 phy->tssi2dbm = NULL;
2032                                 b43legacyerr(dev->wl, "Could not generate "
2033                                        "tssi2dBm table\n");
2034                                 kfree(dyn_tssi2dbm);
2035                                 return -ENODEV;
2036                         }
2037                 phy->tssi2dbm = dyn_tssi2dbm;
2038                 phy->dyn_tssi_tbl = 1;
2039         } else {
2040                 /* pabX values not set in SPROM. */
2041                 switch (phy->type) {
2042                 case B43legacy_PHYTYPE_B:
2043                         phy->idle_tssi = 0x34;
2044                         phy->tssi2dbm = b43legacy_tssi2dbm_b_table;
2045                         break;
2046                 case B43legacy_PHYTYPE_G:
2047                         phy->idle_tssi = 0x34;
2048                         phy->tssi2dbm = b43legacy_tssi2dbm_g_table;
2049                         break;
2050                 }
2051         }
2052
2053         return 0;
2054 }
2055
2056 int b43legacy_phy_init(struct b43legacy_wldev *dev)
2057 {
2058         struct b43legacy_phy *phy = &dev->phy;
2059         int err = -ENODEV;
2060
2061         switch (phy->type) {
2062         case B43legacy_PHYTYPE_B:
2063                 switch (phy->rev) {
2064                 case 2:
2065                         b43legacy_phy_initb2(dev);
2066                         err = 0;
2067                         break;
2068                 case 4:
2069                         b43legacy_phy_initb4(dev);
2070                         err = 0;
2071                         break;
2072                 case 5:
2073                         b43legacy_phy_initb5(dev);
2074                         err = 0;
2075                         break;
2076                 case 6:
2077                         b43legacy_phy_initb6(dev);
2078                         err = 0;
2079                         break;
2080                 }
2081                 break;
2082         case B43legacy_PHYTYPE_G:
2083                 b43legacy_phy_initg(dev);
2084                 err = 0;
2085                 break;
2086         }
2087         if (err)
2088                 b43legacyerr(dev->wl, "Unknown PHYTYPE found\n");
2089
2090         return err;
2091 }
2092
2093 void b43legacy_phy_set_antenna_diversity(struct b43legacy_wldev *dev)
2094 {
2095         struct b43legacy_phy *phy = &dev->phy;
2096         u16 antennadiv;
2097         u16 offset;
2098         u16 value;
2099         u32 ucodeflags;
2100
2101         antennadiv = phy->antenna_diversity;
2102
2103         if (antennadiv == 0xFFFF)
2104                 antennadiv = 3;
2105         B43legacy_WARN_ON(antennadiv > 3);
2106
2107         ucodeflags = b43legacy_shm_read32(dev, B43legacy_SHM_SHARED,
2108                                           B43legacy_UCODEFLAGS_OFFSET);
2109         b43legacy_shm_write32(dev, B43legacy_SHM_SHARED,
2110                               B43legacy_UCODEFLAGS_OFFSET,
2111                               ucodeflags & ~B43legacy_UCODEFLAG_AUTODIV);
2112
2113         switch (phy->type) {
2114         case B43legacy_PHYTYPE_G:
2115                 offset = 0x0400;
2116
2117                 if (antennadiv == 2)
2118                         value = (3/*automatic*/ << 7);
2119                 else
2120                         value = (antennadiv << 7);
2121                 b43legacy_phy_write(dev, offset + 1,
2122                                     (b43legacy_phy_read(dev, offset + 1)
2123                                     & 0x7E7F) | value);
2124
2125                 if (antennadiv >= 2) {
2126                         if (antennadiv == 2)
2127                                 value = (antennadiv << 7);
2128                         else
2129                                 value = (0/*force0*/ << 7);
2130                         b43legacy_phy_write(dev, offset + 0x2B,
2131                                             (b43legacy_phy_read(dev,
2132                                             offset + 0x2B)
2133                                             & 0xFEFF) | value);
2134                 }
2135
2136                 if (phy->type == B43legacy_PHYTYPE_G) {
2137                         if (antennadiv >= 2)
2138                                 b43legacy_phy_write(dev, 0x048C,
2139                                                     b43legacy_phy_read(dev,
2140                                                     0x048C) | 0x2000);
2141                         else
2142                                 b43legacy_phy_write(dev, 0x048C,
2143                                                     b43legacy_phy_read(dev,
2144                                                     0x048C) & ~0x2000);
2145                         if (phy->rev >= 2) {
2146                                 b43legacy_phy_write(dev, 0x0461,
2147                                                     b43legacy_phy_read(dev,
2148                                                     0x0461) | 0x0010);
2149                                 b43legacy_phy_write(dev, 0x04AD,
2150                                                     (b43legacy_phy_read(dev,
2151                                                     0x04AD)
2152                                                     & 0x00FF) | 0x0015);
2153                                 if (phy->rev == 2)
2154                                         b43legacy_phy_write(dev, 0x0427,
2155                                                             0x0008);
2156                                 else
2157                                         b43legacy_phy_write(dev, 0x0427,
2158                                                 (b43legacy_phy_read(dev, 0x0427)
2159                                                  & 0x00FF) | 0x0008);
2160                         } else if (phy->rev >= 6)
2161                                 b43legacy_phy_write(dev, 0x049B, 0x00DC);
2162                 } else {
2163                         if (phy->rev < 3)
2164                                 b43legacy_phy_write(dev, 0x002B,
2165                                                     (b43legacy_phy_read(dev,
2166                                                     0x002B) & 0x00FF)
2167                                                     | 0x0024);
2168                         else {
2169                                 b43legacy_phy_write(dev, 0x0061,
2170                                                     b43legacy_phy_read(dev,
2171                                                     0x0061) | 0x0010);
2172                                 if (phy->rev == 3) {
2173                                         b43legacy_phy_write(dev, 0x0093,
2174                                                             0x001D);
2175                                         b43legacy_phy_write(dev, 0x0027,
2176                                                             0x0008);
2177                                 } else {
2178                                         b43legacy_phy_write(dev, 0x0093,
2179                                                             0x003A);
2180                                         b43legacy_phy_write(dev, 0x0027,
2181                                                 (b43legacy_phy_read(dev, 0x0027)
2182                                                  & 0x00FF) | 0x0008);
2183                                 }
2184                         }
2185                 }
2186                 break;
2187         case B43legacy_PHYTYPE_B:
2188                 if (dev->dev->id.revision == 2)
2189                         value = (3/*automatic*/ << 7);
2190                 else
2191                         value = (antennadiv << 7);
2192                 b43legacy_phy_write(dev, 0x03E2,
2193                                     (b43legacy_phy_read(dev, 0x03E2)
2194                                     & 0xFE7F) | value);
2195                 break;
2196         default:
2197                 B43legacy_WARN_ON(1);
2198         }
2199
2200         if (antennadiv >= 2) {
2201                 ucodeflags = b43legacy_shm_read32(dev, B43legacy_SHM_SHARED,
2202                                                   B43legacy_UCODEFLAGS_OFFSET);
2203                 b43legacy_shm_write32(dev, B43legacy_SHM_SHARED,
2204                                       B43legacy_UCODEFLAGS_OFFSET,
2205                                       ucodeflags | B43legacy_UCODEFLAG_AUTODIV);
2206         }
2207
2208         phy->antenna_diversity = antennadiv;
2209 }
2210
2211 /* Set the PowerSavingControlBits.
2212  * Bitvalues:
2213  *   0  => unset the bit
2214  *   1  => set the bit
2215  *   -1 => calculate the bit
2216  */
2217 void b43legacy_power_saving_ctl_bits(struct b43legacy_wldev *dev,
2218                                      int bit25, int bit26)
2219 {
2220         int i;
2221         u32 status;
2222
2223 /* FIXME: Force 25 to off and 26 to on for now: */
2224 bit25 = 0;
2225 bit26 = 1;
2226
2227         if (bit25 == -1) {
2228                 /* TODO: If powersave is not off and FIXME is not set and we
2229                  *      are not in adhoc and thus is not an AP and we arei
2230                  *      associated, set bit 25 */
2231         }
2232         if (bit26 == -1) {
2233                 /* TODO: If the device is awake or this is an AP, or we are
2234                  *      scanning, or FIXME, or we are associated, or FIXME,
2235                  *      or the latest PS-Poll packet sent was successful,
2236                  *      set bit26  */
2237         }
2238         status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2239         if (bit25)
2240                 status |= B43legacy_MACCTL_HWPS;
2241         else
2242                 status &= ~B43legacy_MACCTL_HWPS;
2243         if (bit26)
2244                 status |= B43legacy_MACCTL_AWAKE;
2245         else
2246                 status &= ~B43legacy_MACCTL_AWAKE;
2247         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
2248         if (bit26 && dev->dev->id.revision >= 5) {
2249                 for (i = 0; i < 100; i++) {
2250                         if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED,
2251                                                  0x0040) != 4)
2252                                 break;
2253                         udelay(10);
2254                 }
2255         }
2256 }