Merge branch 'for-linus' of master.kernel.org:/pub/scm/linux/kernel/git/roland/infiniband
[linux-2.6] / arch / ppc / syslib / open_pic2.c
1 /*
2  *  arch/ppc/kernel/open_pic.c -- OpenPIC Interrupt Handling
3  *
4  *  Copyright (C) 1997 Geert Uytterhoeven
5  *
6  *  This file is subject to the terms and conditions of the GNU General Public
7  *  License.  See the file COPYING in the main directory of this archive
8  *  for more details.
9  *
10  *  This is a duplicate of open_pic.c that deals with U3s MPIC on
11  *  G5 PowerMacs. It's the same file except it's using big endian
12  *  register accesses
13  */
14
15 #include <linux/config.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
18 #include <linux/sched.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/sysdev.h>
22 #include <linux/errno.h>
23 #include <asm/ptrace.h>
24 #include <asm/signal.h>
25 #include <asm/io.h>
26 #include <asm/irq.h>
27 #include <asm/sections.h>
28 #include <asm/open_pic.h>
29 #include <asm/i8259.h>
30
31 #include "open_pic_defs.h"
32
33 void *OpenPIC2_Addr;
34 static volatile struct OpenPIC *OpenPIC2 = NULL;
35 /*
36  * We define OpenPIC_InitSenses table thusly:
37  * bit 0x1: sense, 0 for edge and 1 for level.
38  * bit 0x2: polarity, 0 for negative, 1 for positive.
39  */
40 extern  u_int OpenPIC_NumInitSenses;
41 extern u_char *OpenPIC_InitSenses;
42 extern int use_of_interrupt_tree;
43
44 static u_int NumProcessors;
45 static u_int NumSources;
46 static int open_pic2_irq_offset;
47 static volatile OpenPIC_Source *ISR[NR_IRQS];
48
49 /* Global Operations */
50 static void openpic2_disable_8259_pass_through(void);
51 static void openpic2_set_priority(u_int pri);
52 static void openpic2_set_spurious(u_int vector);
53
54 /* Timer Interrupts */
55 static void openpic2_inittimer(u_int timer, u_int pri, u_int vector);
56 static void openpic2_maptimer(u_int timer, u_int cpumask);
57
58 /* Interrupt Sources */
59 static void openpic2_enable_irq(u_int irq);
60 static void openpic2_disable_irq(u_int irq);
61 static void openpic2_initirq(u_int irq, u_int pri, u_int vector, int polarity,
62                             int is_level);
63 static void openpic2_mapirq(u_int irq, u_int cpumask, u_int keepmask);
64
65 /*
66  * These functions are not used but the code is kept here
67  * for completeness and future reference.
68  */
69 static void openpic2_reset(void);
70 #ifdef notused
71 static void openpic2_enable_8259_pass_through(void);
72 static u_int openpic2_get_priority(void);
73 static u_int openpic2_get_spurious(void);
74 static void openpic2_set_sense(u_int irq, int sense);
75 #endif /* notused */
76
77 /*
78  * Description of the openpic for the higher-level irq code
79  */
80 static void openpic2_end_irq(unsigned int irq_nr);
81 static void openpic2_ack_irq(unsigned int irq_nr);
82
83 struct hw_interrupt_type open_pic2 = {
84         .typename = " OpenPIC2 ",
85         .enable = openpic2_enable_irq,
86         .disable = openpic2_disable_irq,
87         .ack = openpic2_ack_irq,
88         .end = openpic2_end_irq,
89 };
90
91 /*
92  *  Accesses to the current processor's openpic registers
93  *  On cascaded controller, this is only CPU 0
94  */
95 #define THIS_CPU                Processor[0]
96 #define DECL_THIS_CPU
97 #define CHECK_THIS_CPU
98
99 #if 1
100 #define check_arg_ipi(ipi) \
101     if (ipi < 0 || ipi >= OPENPIC_NUM_IPI) \
102         printk("open_pic.c:%d: illegal ipi %d\n", __LINE__, ipi);
103 #define check_arg_timer(timer) \
104     if (timer < 0 || timer >= OPENPIC_NUM_TIMERS) \
105         printk("open_pic.c:%d: illegal timer %d\n", __LINE__, timer);
106 #define check_arg_vec(vec) \
107     if (vec < 0 || vec >= OPENPIC_NUM_VECTORS) \
108         printk("open_pic.c:%d: illegal vector %d\n", __LINE__, vec);
109 #define check_arg_pri(pri) \
110     if (pri < 0 || pri >= OPENPIC_NUM_PRI) \
111         printk("open_pic.c:%d: illegal priority %d\n", __LINE__, pri);
112 /*
113  * Print out a backtrace if it's out of range, since if it's larger than NR_IRQ's
114  * data has probably been corrupted and we're going to panic or deadlock later
115  * anyway --Troy
116  */
117 extern unsigned long* _get_SP(void);
118 #define check_arg_irq(irq) \
119     if (irq < open_pic2_irq_offset || irq >= NumSources+open_pic2_irq_offset \
120         || ISR[irq - open_pic2_irq_offset] == 0) { \
121       printk("open_pic.c:%d: illegal irq %d\n", __LINE__, irq); \
122       /*print_backtrace(_get_SP());*/ }
123 #define check_arg_cpu(cpu) \
124     if (cpu < 0 || cpu >= NumProcessors){ \
125         printk("open_pic2.c:%d: illegal cpu %d\n", __LINE__, cpu); \
126         /*print_backtrace(_get_SP());*/ }
127 #else
128 #define check_arg_ipi(ipi)      do {} while (0)
129 #define check_arg_timer(timer)  do {} while (0)
130 #define check_arg_vec(vec)      do {} while (0)
131 #define check_arg_pri(pri)      do {} while (0)
132 #define check_arg_irq(irq)      do {} while (0)
133 #define check_arg_cpu(cpu)      do {} while (0)
134 #endif
135
136 static u_int openpic2_read(volatile u_int *addr)
137 {
138         u_int val;
139
140         val = in_be32(addr);
141         return val;
142 }
143
144 static inline void openpic2_write(volatile u_int *addr, u_int val)
145 {
146         out_be32(addr, val);
147 }
148
149 static inline u_int openpic2_readfield(volatile u_int *addr, u_int mask)
150 {
151         u_int val = openpic2_read(addr);
152         return val & mask;
153 }
154
155 inline void openpic2_writefield(volatile u_int *addr, u_int mask,
156                                u_int field)
157 {
158         u_int val = openpic2_read(addr);
159         openpic2_write(addr, (val & ~mask) | (field & mask));
160 }
161
162 static inline void openpic2_clearfield(volatile u_int *addr, u_int mask)
163 {
164         openpic2_writefield(addr, mask, 0);
165 }
166
167 static inline void openpic2_setfield(volatile u_int *addr, u_int mask)
168 {
169         openpic2_writefield(addr, mask, mask);
170 }
171
172 static void openpic2_safe_writefield(volatile u_int *addr, u_int mask,
173                                     u_int field)
174 {
175         openpic2_setfield(addr, OPENPIC_MASK);
176         while (openpic2_read(addr) & OPENPIC_ACTIVITY);
177         openpic2_writefield(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK);
178 }
179
180 static void openpic2_reset(void)
181 {
182         openpic2_setfield(&OpenPIC2->Global.Global_Configuration0,
183                          OPENPIC_CONFIG_RESET);
184         while (openpic2_readfield(&OpenPIC2->Global.Global_Configuration0,
185                                  OPENPIC_CONFIG_RESET))
186                 mb();
187 }
188
189 void __init openpic2_set_sources(int first_irq, int num_irqs, void *first_ISR)
190 {
191         volatile OpenPIC_Source *src = first_ISR;
192         int i, last_irq;
193
194         last_irq = first_irq + num_irqs;
195         if (last_irq > NumSources)
196                 NumSources = last_irq;
197         if (src == 0)
198                 src = &((struct OpenPIC *)OpenPIC2_Addr)->Source[first_irq];
199         for (i = first_irq; i < last_irq; ++i, ++src)
200                 ISR[i] = src;
201 }
202
203 /*
204  * The `offset' parameter defines where the interrupts handled by the
205  * OpenPIC start in the space of interrupt numbers that the kernel knows
206  * about.  In other words, the OpenPIC's IRQ0 is numbered `offset' in the
207  * kernel's interrupt numbering scheme.
208  * We assume there is only one OpenPIC.
209  */
210 void __init openpic2_init(int offset)
211 {
212         u_int t, i;
213         u_int timerfreq;
214         const char *version;
215
216         if (!OpenPIC2_Addr) {
217                 printk("No OpenPIC2 found !\n");
218                 return;
219         }
220         OpenPIC2 = (volatile struct OpenPIC *)OpenPIC2_Addr;
221
222         if (ppc_md.progress) ppc_md.progress("openpic: enter", 0x122);
223
224         t = openpic2_read(&OpenPIC2->Global.Feature_Reporting0);
225         switch (t & OPENPIC_FEATURE_VERSION_MASK) {
226         case 1:
227                 version = "1.0";
228                 break;
229         case 2:
230                 version = "1.2";
231                 break;
232         case 3:
233                 version = "1.3";
234                 break;
235         default:
236                 version = "?";
237                 break;
238         }
239         NumProcessors = ((t & OPENPIC_FEATURE_LAST_PROCESSOR_MASK) >>
240                          OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT) + 1;
241         if (NumSources == 0)
242                 openpic2_set_sources(0,
243                                     ((t & OPENPIC_FEATURE_LAST_SOURCE_MASK) >>
244                                      OPENPIC_FEATURE_LAST_SOURCE_SHIFT) + 1,
245                                     NULL);
246         printk("OpenPIC (2) Version %s (%d CPUs and %d IRQ sources) at %p\n",
247                version, NumProcessors, NumSources, OpenPIC2);
248         timerfreq = openpic2_read(&OpenPIC2->Global.Timer_Frequency);
249         if (timerfreq)
250                 printk("OpenPIC timer frequency is %d.%06d MHz\n",
251                        timerfreq / 1000000, timerfreq % 1000000);
252
253         open_pic2_irq_offset = offset;
254
255         /* Initialize timer interrupts */
256         if ( ppc_md.progress ) ppc_md.progress("openpic2: timer",0x3ba);
257         for (i = 0; i < OPENPIC_NUM_TIMERS; i++) {
258                 /* Disabled, Priority 0 */
259                 openpic2_inittimer(i, 0, OPENPIC2_VEC_TIMER+i+offset);
260                 /* No processor */
261                 openpic2_maptimer(i, 0);
262         }
263
264         /* Initialize external interrupts */
265         if (ppc_md.progress) ppc_md.progress("openpic2: external",0x3bc);
266
267         openpic2_set_priority(0xf);
268
269         /* Init all external sources, including possibly the cascade. */
270         for (i = 0; i < NumSources; i++) {
271                 int sense;
272
273                 if (ISR[i] == 0)
274                         continue;
275
276                 /* the bootloader may have left it enabled (bad !) */
277                 openpic2_disable_irq(i+offset);
278
279                 sense = (i < OpenPIC_NumInitSenses)? OpenPIC_InitSenses[i]: \
280                                 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE);
281
282                 if (sense & IRQ_SENSE_MASK)
283                         irq_desc[i+offset].status = IRQ_LEVEL;
284
285                 /* Enabled, Priority 8 */
286                 openpic2_initirq(i, 8, i+offset, (sense & IRQ_POLARITY_MASK),
287                                 (sense & IRQ_SENSE_MASK));
288                 /* Processor 0 */
289                 openpic2_mapirq(i, 1<<0, 0);
290         }
291
292         /* Init descriptors */
293         for (i = offset; i < NumSources + offset; i++)
294                 irq_desc[i].handler = &open_pic2;
295
296         /* Initialize the spurious interrupt */
297         if (ppc_md.progress) ppc_md.progress("openpic2: spurious",0x3bd);
298         openpic2_set_spurious(OPENPIC2_VEC_SPURIOUS+offset);
299
300         openpic2_disable_8259_pass_through();
301         openpic2_set_priority(0);
302
303         if (ppc_md.progress) ppc_md.progress("openpic2: exit",0x222);
304 }
305
306 #ifdef notused
307 static void openpic2_enable_8259_pass_through(void)
308 {
309         openpic2_clearfield(&OpenPIC2->Global.Global_Configuration0,
310                            OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
311 }
312 #endif /* notused */
313
314 /* This can't be __init, it is used in openpic_sleep_restore_intrs */
315 static void openpic2_disable_8259_pass_through(void)
316 {
317         openpic2_setfield(&OpenPIC2->Global.Global_Configuration0,
318                          OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
319 }
320
321 /*
322  *  Find out the current interrupt
323  */
324 u_int openpic2_irq(void)
325 {
326         u_int vec;
327         DECL_THIS_CPU;
328
329         CHECK_THIS_CPU;
330         vec = openpic2_readfield(&OpenPIC2->THIS_CPU.Interrupt_Acknowledge,
331                                 OPENPIC_VECTOR_MASK);
332         return vec;
333 }
334
335 void openpic2_eoi(void)
336 {
337         DECL_THIS_CPU;
338
339         CHECK_THIS_CPU;
340         openpic2_write(&OpenPIC2->THIS_CPU.EOI, 0);
341         /* Handle PCI write posting */
342         (void)openpic2_read(&OpenPIC2->THIS_CPU.EOI);
343 }
344
345 #ifdef notused
346 static u_int openpic2_get_priority(void)
347 {
348         DECL_THIS_CPU;
349
350         CHECK_THIS_CPU;
351         return openpic2_readfield(&OpenPIC2->THIS_CPU.Current_Task_Priority,
352                                  OPENPIC_CURRENT_TASK_PRIORITY_MASK);
353 }
354 #endif /* notused */
355
356 static void __init openpic2_set_priority(u_int pri)
357 {
358         DECL_THIS_CPU;
359
360         CHECK_THIS_CPU;
361         check_arg_pri(pri);
362         openpic2_writefield(&OpenPIC2->THIS_CPU.Current_Task_Priority,
363                            OPENPIC_CURRENT_TASK_PRIORITY_MASK, pri);
364 }
365
366 /*
367  *  Get/set the spurious vector
368  */
369 #ifdef notused
370 static u_int openpic2_get_spurious(void)
371 {
372         return openpic2_readfield(&OpenPIC2->Global.Spurious_Vector,
373                                  OPENPIC_VECTOR_MASK);
374 }
375 #endif /* notused */
376
377 /* This can't be __init, it is used in openpic_sleep_restore_intrs */
378 static void openpic2_set_spurious(u_int vec)
379 {
380         check_arg_vec(vec);
381         openpic2_writefield(&OpenPIC2->Global.Spurious_Vector, OPENPIC_VECTOR_MASK,
382                            vec);
383 }
384
385 static DEFINE_SPINLOCK(openpic2_setup_lock);
386
387 /*
388  *  Initialize a timer interrupt (and disable it)
389  *
390  *  timer: OpenPIC timer number
391  *  pri: interrupt source priority
392  *  vec: the vector it will produce
393  */
394 static void __init openpic2_inittimer(u_int timer, u_int pri, u_int vec)
395 {
396         check_arg_timer(timer);
397         check_arg_pri(pri);
398         check_arg_vec(vec);
399         openpic2_safe_writefield(&OpenPIC2->Global.Timer[timer].Vector_Priority,
400                                 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK,
401                                 (pri << OPENPIC_PRIORITY_SHIFT) | vec);
402 }
403
404 /*
405  *  Map a timer interrupt to one or more CPUs
406  */
407 static void __init openpic2_maptimer(u_int timer, u_int cpumask)
408 {
409         check_arg_timer(timer);
410         openpic2_write(&OpenPIC2->Global.Timer[timer].Destination,
411                       cpumask);
412 }
413
414 /*
415  * Initalize the interrupt source which will generate an NMI.
416  * This raises the interrupt's priority from 8 to 9.
417  *
418  * irq: The logical IRQ which generates an NMI.
419  */
420 void __init
421 openpic2_init_nmi_irq(u_int irq)
422 {
423         check_arg_irq(irq);
424         openpic2_safe_writefield(&ISR[irq - open_pic2_irq_offset]->Vector_Priority,
425                                 OPENPIC_PRIORITY_MASK,
426                                 9 << OPENPIC_PRIORITY_SHIFT);
427 }
428
429 /*
430  *
431  * All functions below take an offset'ed irq argument
432  *
433  */
434
435
436 /*
437  *  Enable/disable an external interrupt source
438  *
439  *  Externally called, irq is an offseted system-wide interrupt number
440  */
441 static void openpic2_enable_irq(u_int irq)
442 {
443         volatile u_int *vpp;
444
445         check_arg_irq(irq);
446         vpp = &ISR[irq - open_pic2_irq_offset]->Vector_Priority;
447         openpic2_clearfield(vpp, OPENPIC_MASK);
448         /* make sure mask gets to controller before we return to user */
449         do {
450                 mb(); /* sync is probably useless here */
451         } while (openpic2_readfield(vpp, OPENPIC_MASK));
452 }
453
454 static void openpic2_disable_irq(u_int irq)
455 {
456         volatile u_int *vpp;
457         u32 vp;
458
459         check_arg_irq(irq);
460         vpp = &ISR[irq - open_pic2_irq_offset]->Vector_Priority;
461         openpic2_setfield(vpp, OPENPIC_MASK);
462         /* make sure mask gets to controller before we return to user */
463         do {
464                 mb();  /* sync is probably useless here */
465                 vp = openpic2_readfield(vpp, OPENPIC_MASK | OPENPIC_ACTIVITY);
466         } while((vp & OPENPIC_ACTIVITY) && !(vp & OPENPIC_MASK));
467 }
468
469
470 /*
471  *  Initialize an interrupt source (and disable it!)
472  *
473  *  irq: OpenPIC interrupt number
474  *  pri: interrupt source priority
475  *  vec: the vector it will produce
476  *  pol: polarity (1 for positive, 0 for negative)
477  *  sense: 1 for level, 0 for edge
478  */
479 static void __init
480 openpic2_initirq(u_int irq, u_int pri, u_int vec, int pol, int sense)
481 {
482         openpic2_safe_writefield(&ISR[irq]->Vector_Priority,
483                                 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK |
484                                 OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK,
485                                 (pri << OPENPIC_PRIORITY_SHIFT) | vec |
486                                 (pol ? OPENPIC_POLARITY_POSITIVE :
487                                         OPENPIC_POLARITY_NEGATIVE) |
488                                 (sense ? OPENPIC_SENSE_LEVEL : OPENPIC_SENSE_EDGE));
489 }
490
491 /*
492  *  Map an interrupt source to one or more CPUs
493  */
494 static void openpic2_mapirq(u_int irq, u_int physmask, u_int keepmask)
495 {
496         if (ISR[irq] == 0)
497                 return;
498         if (keepmask != 0)
499                 physmask |= openpic2_read(&ISR[irq]->Destination) & keepmask;
500         openpic2_write(&ISR[irq]->Destination, physmask);
501 }
502
503 #ifdef notused
504 /*
505  *  Set the sense for an interrupt source (and disable it!)
506  *
507  *  sense: 1 for level, 0 for edge
508  */
509 static void openpic2_set_sense(u_int irq, int sense)
510 {
511         if (ISR[irq] != 0)
512                 openpic2_safe_writefield(&ISR[irq]->Vector_Priority,
513                                         OPENPIC_SENSE_LEVEL,
514                                         (sense ? OPENPIC_SENSE_LEVEL : 0));
515 }
516 #endif /* notused */
517
518 /* No spinlocks, should not be necessary with the OpenPIC
519  * (1 register = 1 interrupt and we have the desc lock).
520  */
521 static void openpic2_ack_irq(unsigned int irq_nr)
522 {
523         openpic2_disable_irq(irq_nr);
524         openpic2_eoi();
525 }
526
527 static void openpic2_end_irq(unsigned int irq_nr)
528 {
529         if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
530                 openpic2_enable_irq(irq_nr);
531 }
532
533 int
534 openpic2_get_irq(struct pt_regs *regs)
535 {
536         int irq = openpic2_irq();
537
538         if (irq == (OPENPIC2_VEC_SPURIOUS + open_pic2_irq_offset))
539                 irq = -1;
540         return irq;
541 }
542
543 #ifdef CONFIG_PM
544
545 /*
546  * We implement the IRQ controller as a sysdev and put it
547  * to sleep at powerdown stage (the callback is named suspend,
548  * but it's old semantics, for the Device Model, it's really
549  * powerdown). The possible problem is that another sysdev that
550  * happens to be suspend after this one will have interrupts off,
551  * that may be an issue... For now, this isn't an issue on pmac
552  * though...
553  */
554
555 static u32 save_ipi_vp[OPENPIC_NUM_IPI];
556 static u32 save_irq_src_vp[OPENPIC_MAX_SOURCES];
557 static u32 save_irq_src_dest[OPENPIC_MAX_SOURCES];
558 static u32 save_cpu_task_pri[OPENPIC_MAX_PROCESSORS];
559 static int openpic_suspend_count;
560
561 static void openpic2_cached_enable_irq(u_int irq)
562 {
563         check_arg_irq(irq);
564         save_irq_src_vp[irq - open_pic2_irq_offset] &= ~OPENPIC_MASK;
565 }
566
567 static void openpic2_cached_disable_irq(u_int irq)
568 {
569         check_arg_irq(irq);
570         save_irq_src_vp[irq - open_pic2_irq_offset] |= OPENPIC_MASK;
571 }
572
573 /* WARNING: Can be called directly by the cpufreq code with NULL parameter,
574  * we need something better to deal with that... Maybe switch to S1 for
575  * cpufreq changes
576  */
577 int openpic2_suspend(struct sys_device *sysdev, pm_message_t state)
578 {
579         int     i;
580         unsigned long flags;
581
582         spin_lock_irqsave(&openpic2_setup_lock, flags);
583
584         if (openpic_suspend_count++ > 0) {
585                 spin_unlock_irqrestore(&openpic2_setup_lock, flags);
586                 return 0;
587         }
588
589         open_pic2.enable = openpic2_cached_enable_irq;
590         open_pic2.disable = openpic2_cached_disable_irq;
591
592         for (i=0; i<NumProcessors; i++) {
593                 save_cpu_task_pri[i] = openpic2_read(&OpenPIC2->Processor[i].Current_Task_Priority);
594                 openpic2_writefield(&OpenPIC2->Processor[i].Current_Task_Priority,
595                                    OPENPIC_CURRENT_TASK_PRIORITY_MASK, 0xf);
596         }
597
598         for (i=0; i<OPENPIC_NUM_IPI; i++)
599                 save_ipi_vp[i] = openpic2_read(&OpenPIC2->Global.IPI_Vector_Priority(i));
600         for (i=0; i<NumSources; i++) {
601                 if (ISR[i] == 0)
602                         continue;
603                 save_irq_src_vp[i] = openpic2_read(&ISR[i]->Vector_Priority) & ~OPENPIC_ACTIVITY;
604                 save_irq_src_dest[i] = openpic2_read(&ISR[i]->Destination);
605         }
606
607         spin_unlock_irqrestore(&openpic2_setup_lock, flags);
608
609         return 0;
610 }
611
612 /* WARNING: Can be called directly by the cpufreq code with NULL parameter,
613  * we need something better to deal with that... Maybe switch to S1 for
614  * cpufreq changes
615  */
616 int openpic2_resume(struct sys_device *sysdev)
617 {
618         int             i;
619         unsigned long   flags;
620         u32             vppmask =       OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK |
621                                         OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK |
622                                         OPENPIC_MASK;
623
624         spin_lock_irqsave(&openpic2_setup_lock, flags);
625
626         if ((--openpic_suspend_count) > 0) {
627                 spin_unlock_irqrestore(&openpic2_setup_lock, flags);
628                 return 0;
629         }
630
631         openpic2_reset();
632
633         /* OpenPIC sometimes seem to need some time to be fully back up... */
634         do {
635                 openpic2_set_spurious(OPENPIC2_VEC_SPURIOUS+open_pic2_irq_offset);
636         } while(openpic2_readfield(&OpenPIC2->Global.Spurious_Vector, OPENPIC_VECTOR_MASK)
637                         != (OPENPIC2_VEC_SPURIOUS + open_pic2_irq_offset));
638         
639         openpic2_disable_8259_pass_through();
640
641         for (i=0; i<OPENPIC_NUM_IPI; i++)
642                 openpic2_write(&OpenPIC2->Global.IPI_Vector_Priority(i),
643                               save_ipi_vp[i]);
644         for (i=0; i<NumSources; i++) {
645                 if (ISR[i] == 0)
646                         continue;
647                 openpic2_write(&ISR[i]->Destination, save_irq_src_dest[i]);
648                 openpic2_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]);
649                 /* make sure mask gets to controller before we return to user */
650                 do {
651                         openpic2_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]);
652                 } while (openpic2_readfield(&ISR[i]->Vector_Priority, vppmask)
653                          != (save_irq_src_vp[i] & vppmask));
654         }
655         for (i=0; i<NumProcessors; i++)
656                 openpic2_write(&OpenPIC2->Processor[i].Current_Task_Priority,
657                               save_cpu_task_pri[i]);
658
659         open_pic2.enable = openpic2_enable_irq;
660         open_pic2.disable = openpic2_disable_irq;
661
662         spin_unlock_irqrestore(&openpic2_setup_lock, flags);
663
664         return 0;
665 }
666
667 #endif /* CONFIG_PM */
668
669 /* HACK ALERT */
670 static struct sysdev_class openpic2_sysclass = {
671         set_kset_name("openpic2"),
672 };
673
674 static struct sys_device device_openpic2 = {
675         .id             = 0,
676         .cls            = &openpic2_sysclass,
677 };
678
679 static struct sysdev_driver driver_openpic2 = {
680 #ifdef CONFIG_PM
681         .suspend        = &openpic2_suspend,
682         .resume         = &openpic2_resume,
683 #endif /* CONFIG_PM */
684 };
685
686 static int __init init_openpic2_sysfs(void)
687 {
688         int rc;
689
690         if (!OpenPIC2_Addr)
691                 return -ENODEV;
692         printk(KERN_DEBUG "Registering openpic2 with sysfs...\n");
693         rc = sysdev_class_register(&openpic2_sysclass);
694         if (rc) {
695                 printk(KERN_ERR "Failed registering openpic sys class\n");
696                 return -ENODEV;
697         }
698         rc = sysdev_register(&device_openpic2);
699         if (rc) {
700                 printk(KERN_ERR "Failed registering openpic sys device\n");
701                 return -ENODEV;
702         }
703         rc = sysdev_driver_register(&openpic2_sysclass, &driver_openpic2);
704         if (rc) {
705                 printk(KERN_ERR "Failed registering openpic sys driver\n");
706                 return -ENODEV;
707         }
708         return 0;
709 }
710
711 subsys_initcall(init_openpic2_sysfs);
712