ACPI: enable MWAIT for C1 idle
[linux-2.6] / drivers / mtd / nand / s3c2410.c
1 /* linux/drivers/mtd/nand/s3c2410.c
2  *
3  * Copyright (c) 2004,2005 Simtec Electronics
4  *      http://www.simtec.co.uk/products/SWLINUX/
5  *      Ben Dooks <ben@simtec.co.uk>
6  *
7  * Samsung S3C2410/S3C240 NAND driver
8  *
9  * Changelog:
10  *      21-Sep-2004  BJD  Initial version
11  *      23-Sep-2004  BJD  Multiple device support
12  *      28-Sep-2004  BJD  Fixed ECC placement for Hardware mode
13  *      12-Oct-2004  BJD  Fixed errors in use of platform data
14  *      18-Feb-2005  BJD  Fix sparse errors
15  *      14-Mar-2005  BJD  Applied tglx's code reduction patch
16  *      02-May-2005  BJD  Fixed s3c2440 support
17  *      02-May-2005  BJD  Reduced hwcontrol decode
18  *      20-Jun-2005  BJD  Updated s3c2440 support, fixed timing bug
19  *      08-Jul-2005  BJD  Fix OOPS when no platform data supplied
20  *      20-Oct-2005  BJD  Fix timing calculation bug
21  *      14-Jan-2006  BJD  Allow clock to be stopped when idle
22  *
23  * $Id: s3c2410.c,v 1.23 2006/04/01 18:06:29 bjd Exp $
24  *
25  * This program is free software; you can redistribute it and/or modify
26  * it under the terms of the GNU General Public License as published by
27  * the Free Software Foundation; either version 2 of the License, or
28  * (at your option) any later version.
29  *
30  * This program is distributed in the hope that it will be useful,
31  * but WITHOUT ANY WARRANTY; without even the implied warranty of
32  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
33  * GNU General Public License for more details.
34  *
35  * You should have received a copy of the GNU General Public License
36  * along with this program; if not, write to the Free Software
37  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
38 */
39
40 #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG
41 #define DEBUG
42 #endif
43
44 #include <linux/module.h>
45 #include <linux/types.h>
46 #include <linux/init.h>
47 #include <linux/kernel.h>
48 #include <linux/string.h>
49 #include <linux/ioport.h>
50 #include <linux/platform_device.h>
51 #include <linux/delay.h>
52 #include <linux/err.h>
53 #include <linux/slab.h>
54 #include <linux/clk.h>
55
56 #include <linux/mtd/mtd.h>
57 #include <linux/mtd/nand.h>
58 #include <linux/mtd/nand_ecc.h>
59 #include <linux/mtd/partitions.h>
60
61 #include <asm/io.h>
62
63 #include <asm/plat-s3c/regs-nand.h>
64 #include <asm/plat-s3c/nand.h>
65
66 #ifdef CONFIG_MTD_NAND_S3C2410_HWECC
67 static int hardware_ecc = 1;
68 #else
69 static int hardware_ecc = 0;
70 #endif
71
72 #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP
73 static int clock_stop = 1;
74 #else
75 static const int clock_stop = 0;
76 #endif
77
78
79 /* new oob placement block for use with hardware ecc generation
80  */
81
82 static struct nand_ecclayout nand_hw_eccoob = {
83         .eccbytes = 3,
84         .eccpos = {0, 1, 2},
85         .oobfree = {{8, 8}}
86 };
87
88 /* controller and mtd information */
89
90 struct s3c2410_nand_info;
91
92 struct s3c2410_nand_mtd {
93         struct mtd_info                 mtd;
94         struct nand_chip                chip;
95         struct s3c2410_nand_set         *set;
96         struct s3c2410_nand_info        *info;
97         int                             scan_res;
98 };
99
100 enum s3c_cpu_type {
101         TYPE_S3C2410,
102         TYPE_S3C2412,
103         TYPE_S3C2440,
104 };
105
106 /* overview of the s3c2410 nand state */
107
108 struct s3c2410_nand_info {
109         /* mtd info */
110         struct nand_hw_control          controller;
111         struct s3c2410_nand_mtd         *mtds;
112         struct s3c2410_platform_nand    *platform;
113
114         /* device info */
115         struct device                   *device;
116         struct resource                 *area;
117         struct clk                      *clk;
118         void __iomem                    *regs;
119         void __iomem                    *sel_reg;
120         int                             sel_bit;
121         int                             mtd_count;
122
123         enum s3c_cpu_type               cpu_type;
124 };
125
126 /* conversion functions */
127
128 static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd)
129 {
130         return container_of(mtd, struct s3c2410_nand_mtd, mtd);
131 }
132
133 static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd)
134 {
135         return s3c2410_nand_mtd_toours(mtd)->info;
136 }
137
138 static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev)
139 {
140         return platform_get_drvdata(dev);
141 }
142
143 static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev)
144 {
145         return dev->dev.platform_data;
146 }
147
148 static inline int allow_clk_stop(struct s3c2410_nand_info *info)
149 {
150         return clock_stop;
151 }
152
153 /* timing calculations */
154
155 #define NS_IN_KHZ 1000000
156
157 static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max)
158 {
159         int result;
160
161         result = (wanted * clk) / NS_IN_KHZ;
162         result++;
163
164         pr_debug("result %d from %ld, %d\n", result, clk, wanted);
165
166         if (result > max) {
167                 printk("%d ns is too big for current clock rate %ld\n", wanted, clk);
168                 return -1;
169         }
170
171         if (result < 1)
172                 result = 1;
173
174         return result;
175 }
176
177 #define to_ns(ticks,clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk))
178
179 /* controller setup */
180
181 static int s3c2410_nand_inithw(struct s3c2410_nand_info *info,
182                                struct platform_device *pdev)
183 {
184         struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
185         unsigned long clkrate = clk_get_rate(info->clk);
186         int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4;
187         int tacls, twrph0, twrph1;
188         unsigned long cfg = 0;
189
190         /* calculate the timing information for the controller */
191
192         clkrate /= 1000;        /* turn clock into kHz for ease of use */
193
194         if (plat != NULL) {
195                 tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max);
196                 twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8);
197                 twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8);
198         } else {
199                 /* default timings */
200                 tacls = tacls_max;
201                 twrph0 = 8;
202                 twrph1 = 8;
203         }
204
205         if (tacls < 0 || twrph0 < 0 || twrph1 < 0) {
206                 dev_err(info->device, "cannot get suitable timings\n");
207                 return -EINVAL;
208         }
209
210         dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
211                tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), twrph1, to_ns(twrph1, clkrate));
212
213         switch (info->cpu_type) {
214         case TYPE_S3C2410:
215                 cfg = S3C2410_NFCONF_EN;
216                 cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
217                 cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
218                 cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
219                 break;
220
221         case TYPE_S3C2440:
222         case TYPE_S3C2412:
223                 cfg = S3C2440_NFCONF_TACLS(tacls - 1);
224                 cfg |= S3C2440_NFCONF_TWRPH0(twrph0 - 1);
225                 cfg |= S3C2440_NFCONF_TWRPH1(twrph1 - 1);
226
227                 /* enable the controller and de-assert nFCE */
228
229                 writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT);
230         }
231
232         dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg);
233
234         writel(cfg, info->regs + S3C2410_NFCONF);
235         return 0;
236 }
237
238 /* select chip */
239
240 static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip)
241 {
242         struct s3c2410_nand_info *info;
243         struct s3c2410_nand_mtd *nmtd;
244         struct nand_chip *this = mtd->priv;
245         unsigned long cur;
246
247         nmtd = this->priv;
248         info = nmtd->info;
249
250         if (chip != -1 && allow_clk_stop(info))
251                 clk_enable(info->clk);
252
253         cur = readl(info->sel_reg);
254
255         if (chip == -1) {
256                 cur |= info->sel_bit;
257         } else {
258                 if (nmtd->set != NULL && chip > nmtd->set->nr_chips) {
259                         dev_err(info->device, "invalid chip %d\n", chip);
260                         return;
261                 }
262
263                 if (info->platform != NULL) {
264                         if (info->platform->select_chip != NULL)
265                                 (info->platform->select_chip) (nmtd->set, chip);
266                 }
267
268                 cur &= ~info->sel_bit;
269         }
270
271         writel(cur, info->sel_reg);
272
273         if (chip == -1 && allow_clk_stop(info))
274                 clk_disable(info->clk);
275 }
276
277 /* s3c2410_nand_hwcontrol
278  *
279  * Issue command and address cycles to the chip
280 */
281
282 static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd,
283                                    unsigned int ctrl)
284 {
285         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
286
287         if (cmd == NAND_CMD_NONE)
288                 return;
289
290         if (ctrl & NAND_CLE)
291                 writeb(cmd, info->regs + S3C2410_NFCMD);
292         else
293                 writeb(cmd, info->regs + S3C2410_NFADDR);
294 }
295
296 /* command and control functions */
297
298 static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd,
299                                    unsigned int ctrl)
300 {
301         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
302
303         if (cmd == NAND_CMD_NONE)
304                 return;
305
306         if (ctrl & NAND_CLE)
307                 writeb(cmd, info->regs + S3C2440_NFCMD);
308         else
309                 writeb(cmd, info->regs + S3C2440_NFADDR);
310 }
311
312 /* s3c2410_nand_devready()
313  *
314  * returns 0 if the nand is busy, 1 if it is ready
315 */
316
317 static int s3c2410_nand_devready(struct mtd_info *mtd)
318 {
319         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
320         return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;
321 }
322
323 static int s3c2440_nand_devready(struct mtd_info *mtd)
324 {
325         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
326         return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY;
327 }
328
329 static int s3c2412_nand_devready(struct mtd_info *mtd)
330 {
331         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
332         return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY;
333 }
334
335 /* ECC handling functions */
336
337 static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
338                                      u_char *read_ecc, u_char *calc_ecc)
339 {
340         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
341         unsigned int diff0, diff1, diff2;
342         unsigned int bit, byte;
343
344         pr_debug("%s(%p,%p,%p,%p)\n", __func__, mtd, dat, read_ecc, calc_ecc);
345
346         diff0 = read_ecc[0] ^ calc_ecc[0];
347         diff1 = read_ecc[1] ^ calc_ecc[1];
348         diff2 = read_ecc[2] ^ calc_ecc[2];
349
350         pr_debug("%s: rd %02x%02x%02x calc %02x%02x%02x diff %02x%02x%02x\n",
351                  __func__,
352                  read_ecc[0], read_ecc[1], read_ecc[2],
353                  calc_ecc[0], calc_ecc[1], calc_ecc[2],
354                  diff0, diff1, diff2);
355
356         if (diff0 == 0 && diff1 == 0 && diff2 == 0)
357                 return 0;               /* ECC is ok */
358
359         /* Can we correct this ECC (ie, one row and column change).
360          * Note, this is similar to the 256 error code on smartmedia */
361
362         if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 &&
363             ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 &&
364             ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) {
365                 /* calculate the bit position of the error */
366
367                 bit  = (diff2 >> 2) & 1;
368                 bit |= (diff2 >> 3) & 2;
369                 bit |= (diff2 >> 4) & 4;
370
371                 /* calculate the byte position of the error */
372
373                 byte  = (diff1 << 1) & 0x80;
374                 byte |= (diff1 << 2) & 0x40;
375                 byte |= (diff1 << 3) & 0x20;
376                 byte |= (diff1 << 4) & 0x10;
377
378                 byte |= (diff0 >> 3) & 0x08;
379                 byte |= (diff0 >> 2) & 0x04;
380                 byte |= (diff0 >> 1) & 0x02;
381                 byte |= (diff0 >> 0) & 0x01;
382
383                 byte |= (diff2 << 8) & 0x100;
384
385                 dev_dbg(info->device, "correcting error bit %d, byte %d\n",
386                         bit, byte);
387
388                 dat[byte] ^= (1 << bit);
389                 return 1;
390         }
391
392         /* if there is only one bit difference in the ECC, then
393          * one of only a row or column parity has changed, which
394          * means the error is most probably in the ECC itself */
395
396         diff0 |= (diff1 << 8);
397         diff0 |= (diff2 << 16);
398
399         if ((diff0 & ~(1<<fls(diff0))) == 0)
400                 return 1;
401
402         return 0;
403 }
404
405 /* ECC functions
406  *
407  * These allow the s3c2410 and s3c2440 to use the controller's ECC
408  * generator block to ECC the data as it passes through]
409 */
410
411 static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
412 {
413         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
414         unsigned long ctrl;
415
416         ctrl = readl(info->regs + S3C2410_NFCONF);
417         ctrl |= S3C2410_NFCONF_INITECC;
418         writel(ctrl, info->regs + S3C2410_NFCONF);
419 }
420
421 static void s3c2412_nand_enable_hwecc(struct mtd_info *mtd, int mode)
422 {
423         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
424         unsigned long ctrl;
425
426         ctrl = readl(info->regs + S3C2440_NFCONT);
427         writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC, info->regs + S3C2440_NFCONT);
428 }
429
430 static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode)
431 {
432         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
433         unsigned long ctrl;
434
435         ctrl = readl(info->regs + S3C2440_NFCONT);
436         writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT);
437 }
438
439 static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
440 {
441         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
442
443         ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0);
444         ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);
445         ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);
446
447         pr_debug("%s: returning ecc %02x%02x%02x\n", __func__,
448                  ecc_code[0], ecc_code[1], ecc_code[2]);
449
450         return 0;
451 }
452
453 static int s3c2412_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
454 {
455         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
456         unsigned long ecc = readl(info->regs + S3C2412_NFMECC0);
457
458         ecc_code[0] = ecc;
459         ecc_code[1] = ecc >> 8;
460         ecc_code[2] = ecc >> 16;
461
462         pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]);
463
464         return 0;
465 }
466
467 static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
468 {
469         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
470         unsigned long ecc = readl(info->regs + S3C2440_NFMECC0);
471
472         ecc_code[0] = ecc;
473         ecc_code[1] = ecc >> 8;
474         ecc_code[2] = ecc >> 16;
475
476         pr_debug("%s: returning ecc %06lx\n", __func__, ecc);
477
478         return 0;
479 }
480
481 /* over-ride the standard functions for a little more speed. We can
482  * use read/write block to move the data buffers to/from the controller
483 */
484
485 static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
486 {
487         struct nand_chip *this = mtd->priv;
488         readsb(this->IO_ADDR_R, buf, len);
489 }
490
491 static void s3c2440_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
492 {
493         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
494         readsl(info->regs + S3C2440_NFDATA, buf, len / 4);
495 }
496
497 static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
498 {
499         struct nand_chip *this = mtd->priv;
500         writesb(this->IO_ADDR_W, buf, len);
501 }
502
503 static void s3c2440_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
504 {
505         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
506         writesl(info->regs + S3C2440_NFDATA, buf, len / 4);
507 }
508
509 /* device management functions */
510
511 static int s3c2410_nand_remove(struct platform_device *pdev)
512 {
513         struct s3c2410_nand_info *info = to_nand_info(pdev);
514
515         platform_set_drvdata(pdev, NULL);
516
517         if (info == NULL)
518                 return 0;
519
520         /* first thing we need to do is release all our mtds
521          * and their partitions, then go through freeing the
522          * resources used
523          */
524
525         if (info->mtds != NULL) {
526                 struct s3c2410_nand_mtd *ptr = info->mtds;
527                 int mtdno;
528
529                 for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
530                         pr_debug("releasing mtd %d (%p)\n", mtdno, ptr);
531                         nand_release(&ptr->mtd);
532                 }
533
534                 kfree(info->mtds);
535         }
536
537         /* free the common resources */
538
539         if (info->clk != NULL && !IS_ERR(info->clk)) {
540                 if (!allow_clk_stop(info))
541                         clk_disable(info->clk);
542                 clk_put(info->clk);
543         }
544
545         if (info->regs != NULL) {
546                 iounmap(info->regs);
547                 info->regs = NULL;
548         }
549
550         if (info->area != NULL) {
551                 release_resource(info->area);
552                 kfree(info->area);
553                 info->area = NULL;
554         }
555
556         kfree(info);
557
558         return 0;
559 }
560
561 #ifdef CONFIG_MTD_PARTITIONS
562 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
563                                       struct s3c2410_nand_mtd *mtd,
564                                       struct s3c2410_nand_set *set)
565 {
566         if (set == NULL)
567                 return add_mtd_device(&mtd->mtd);
568
569         if (set->nr_partitions > 0 && set->partitions != NULL) {
570                 return add_mtd_partitions(&mtd->mtd, set->partitions, set->nr_partitions);
571         }
572
573         return add_mtd_device(&mtd->mtd);
574 }
575 #else
576 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
577                                       struct s3c2410_nand_mtd *mtd,
578                                       struct s3c2410_nand_set *set)
579 {
580         return add_mtd_device(&mtd->mtd);
581 }
582 #endif
583
584 /* s3c2410_nand_init_chip
585  *
586  * init a single instance of an chip
587 */
588
589 static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
590                                    struct s3c2410_nand_mtd *nmtd,
591                                    struct s3c2410_nand_set *set)
592 {
593         struct nand_chip *chip = &nmtd->chip;
594         void __iomem *regs = info->regs;
595
596         chip->write_buf    = s3c2410_nand_write_buf;
597         chip->read_buf     = s3c2410_nand_read_buf;
598         chip->select_chip  = s3c2410_nand_select_chip;
599         chip->chip_delay   = 50;
600         chip->priv         = nmtd;
601         chip->options      = 0;
602         chip->controller   = &info->controller;
603
604         switch (info->cpu_type) {
605         case TYPE_S3C2410:
606                 chip->IO_ADDR_W = regs + S3C2410_NFDATA;
607                 info->sel_reg   = regs + S3C2410_NFCONF;
608                 info->sel_bit   = S3C2410_NFCONF_nFCE;
609                 chip->cmd_ctrl  = s3c2410_nand_hwcontrol;
610                 chip->dev_ready = s3c2410_nand_devready;
611                 break;
612
613         case TYPE_S3C2440:
614                 chip->IO_ADDR_W = regs + S3C2440_NFDATA;
615                 info->sel_reg   = regs + S3C2440_NFCONT;
616                 info->sel_bit   = S3C2440_NFCONT_nFCE;
617                 chip->cmd_ctrl  = s3c2440_nand_hwcontrol;
618                 chip->dev_ready = s3c2440_nand_devready;
619                 chip->read_buf  = s3c2440_nand_read_buf;
620                 chip->write_buf = s3c2440_nand_write_buf;
621                 break;
622
623         case TYPE_S3C2412:
624                 chip->IO_ADDR_W = regs + S3C2440_NFDATA;
625                 info->sel_reg   = regs + S3C2440_NFCONT;
626                 info->sel_bit   = S3C2412_NFCONT_nFCE0;
627                 chip->cmd_ctrl  = s3c2440_nand_hwcontrol;
628                 chip->dev_ready = s3c2412_nand_devready;
629
630                 if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT)
631                         dev_info(info->device, "System booted from NAND\n");
632
633                 break;
634         }
635
636         chip->IO_ADDR_R = chip->IO_ADDR_W;
637
638         nmtd->info         = info;
639         nmtd->mtd.priv     = chip;
640         nmtd->mtd.owner    = THIS_MODULE;
641         nmtd->set          = set;
642
643         if (hardware_ecc) {
644                 chip->ecc.calculate = s3c2410_nand_calculate_ecc;
645                 chip->ecc.correct   = s3c2410_nand_correct_data;
646                 chip->ecc.mode      = NAND_ECC_HW;
647                 chip->ecc.size      = 512;
648                 chip->ecc.bytes     = 3;
649                 chip->ecc.layout    = &nand_hw_eccoob;
650
651                 switch (info->cpu_type) {
652                 case TYPE_S3C2410:
653                         chip->ecc.hwctl     = s3c2410_nand_enable_hwecc;
654                         chip->ecc.calculate = s3c2410_nand_calculate_ecc;
655                         break;
656
657                 case TYPE_S3C2412:
658                         chip->ecc.hwctl     = s3c2412_nand_enable_hwecc;
659                         chip->ecc.calculate = s3c2412_nand_calculate_ecc;
660                         break;
661
662                 case TYPE_S3C2440:
663                         chip->ecc.hwctl     = s3c2440_nand_enable_hwecc;
664                         chip->ecc.calculate = s3c2440_nand_calculate_ecc;
665                         break;
666
667                 }
668         } else {
669                 chip->ecc.mode      = NAND_ECC_SOFT;
670         }
671 }
672
673 /* s3c2410_nand_probe
674  *
675  * called by device layer when it finds a device matching
676  * one our driver can handled. This code checks to see if
677  * it can allocate all necessary resources then calls the
678  * nand layer to look for devices
679 */
680
681 static int s3c24xx_nand_probe(struct platform_device *pdev,
682                               enum s3c_cpu_type cpu_type)
683 {
684         struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
685         struct s3c2410_nand_info *info;
686         struct s3c2410_nand_mtd *nmtd;
687         struct s3c2410_nand_set *sets;
688         struct resource *res;
689         int err = 0;
690         int size;
691         int nr_sets;
692         int setno;
693
694         pr_debug("s3c2410_nand_probe(%p)\n", pdev);
695
696         info = kmalloc(sizeof(*info), GFP_KERNEL);
697         if (info == NULL) {
698                 dev_err(&pdev->dev, "no memory for flash info\n");
699                 err = -ENOMEM;
700                 goto exit_error;
701         }
702
703         memzero(info, sizeof(*info));
704         platform_set_drvdata(pdev, info);
705
706         spin_lock_init(&info->controller.lock);
707         init_waitqueue_head(&info->controller.wq);
708
709         /* get the clock source and enable it */
710
711         info->clk = clk_get(&pdev->dev, "nand");
712         if (IS_ERR(info->clk)) {
713                 dev_err(&pdev->dev, "failed to get clock\n");
714                 err = -ENOENT;
715                 goto exit_error;
716         }
717
718         clk_enable(info->clk);
719
720         /* allocate and map the resource */
721
722         /* currently we assume we have the one resource */
723         res  = pdev->resource;
724         size = res->end - res->start + 1;
725
726         info->area = request_mem_region(res->start, size, pdev->name);
727
728         if (info->area == NULL) {
729                 dev_err(&pdev->dev, "cannot reserve register region\n");
730                 err = -ENOENT;
731                 goto exit_error;
732         }
733
734         info->device     = &pdev->dev;
735         info->platform   = plat;
736         info->regs       = ioremap(res->start, size);
737         info->cpu_type   = cpu_type;
738
739         if (info->regs == NULL) {
740                 dev_err(&pdev->dev, "cannot reserve register region\n");
741                 err = -EIO;
742                 goto exit_error;
743         }
744
745         dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs);
746
747         /* initialise the hardware */
748
749         err = s3c2410_nand_inithw(info, pdev);
750         if (err != 0)
751                 goto exit_error;
752
753         sets = (plat != NULL) ? plat->sets : NULL;
754         nr_sets = (plat != NULL) ? plat->nr_sets : 1;
755
756         info->mtd_count = nr_sets;
757
758         /* allocate our information */
759
760         size = nr_sets * sizeof(*info->mtds);
761         info->mtds = kmalloc(size, GFP_KERNEL);
762         if (info->mtds == NULL) {
763                 dev_err(&pdev->dev, "failed to allocate mtd storage\n");
764                 err = -ENOMEM;
765                 goto exit_error;
766         }
767
768         memzero(info->mtds, size);
769
770         /* initialise all possible chips */
771
772         nmtd = info->mtds;
773
774         for (setno = 0; setno < nr_sets; setno++, nmtd++) {
775                 pr_debug("initialising set %d (%p, info %p)\n", setno, nmtd, info);
776
777                 s3c2410_nand_init_chip(info, nmtd, sets);
778
779                 nmtd->scan_res = nand_scan(&nmtd->mtd, (sets) ? sets->nr_chips : 1);
780
781                 if (nmtd->scan_res == 0) {
782                         s3c2410_nand_add_partition(info, nmtd, sets);
783                 }
784
785                 if (sets != NULL)
786                         sets++;
787         }
788
789         if (allow_clk_stop(info)) {
790                 dev_info(&pdev->dev, "clock idle support enabled\n");
791                 clk_disable(info->clk);
792         }
793
794         pr_debug("initialised ok\n");
795         return 0;
796
797  exit_error:
798         s3c2410_nand_remove(pdev);
799
800         if (err == 0)
801                 err = -EINVAL;
802         return err;
803 }
804
805 /* PM Support */
806 #ifdef CONFIG_PM
807
808 static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
809 {
810         struct s3c2410_nand_info *info = platform_get_drvdata(dev);
811
812         if (info) {
813                 if (!allow_clk_stop(info))
814                         clk_disable(info->clk);
815         }
816
817         return 0;
818 }
819
820 static int s3c24xx_nand_resume(struct platform_device *dev)
821 {
822         struct s3c2410_nand_info *info = platform_get_drvdata(dev);
823
824         if (info) {
825                 clk_enable(info->clk);
826                 s3c2410_nand_inithw(info, dev);
827
828                 if (allow_clk_stop(info))
829                         clk_disable(info->clk);
830         }
831
832         return 0;
833 }
834
835 #else
836 #define s3c24xx_nand_suspend NULL
837 #define s3c24xx_nand_resume NULL
838 #endif
839
840 /* driver device registration */
841
842 static int s3c2410_nand_probe(struct platform_device *dev)
843 {
844         return s3c24xx_nand_probe(dev, TYPE_S3C2410);
845 }
846
847 static int s3c2440_nand_probe(struct platform_device *dev)
848 {
849         return s3c24xx_nand_probe(dev, TYPE_S3C2440);
850 }
851
852 static int s3c2412_nand_probe(struct platform_device *dev)
853 {
854         return s3c24xx_nand_probe(dev, TYPE_S3C2412);
855 }
856
857 static struct platform_driver s3c2410_nand_driver = {
858         .probe          = s3c2410_nand_probe,
859         .remove         = s3c2410_nand_remove,
860         .suspend        = s3c24xx_nand_suspend,
861         .resume         = s3c24xx_nand_resume,
862         .driver         = {
863                 .name   = "s3c2410-nand",
864                 .owner  = THIS_MODULE,
865         },
866 };
867
868 static struct platform_driver s3c2440_nand_driver = {
869         .probe          = s3c2440_nand_probe,
870         .remove         = s3c2410_nand_remove,
871         .suspend        = s3c24xx_nand_suspend,
872         .resume         = s3c24xx_nand_resume,
873         .driver         = {
874                 .name   = "s3c2440-nand",
875                 .owner  = THIS_MODULE,
876         },
877 };
878
879 static struct platform_driver s3c2412_nand_driver = {
880         .probe          = s3c2412_nand_probe,
881         .remove         = s3c2410_nand_remove,
882         .suspend        = s3c24xx_nand_suspend,
883         .resume         = s3c24xx_nand_resume,
884         .driver         = {
885                 .name   = "s3c2412-nand",
886                 .owner  = THIS_MODULE,
887         },
888 };
889
890 static int __init s3c2410_nand_init(void)
891 {
892         printk("S3C24XX NAND Driver, (c) 2004 Simtec Electronics\n");
893
894         platform_driver_register(&s3c2412_nand_driver);
895         platform_driver_register(&s3c2440_nand_driver);
896         return platform_driver_register(&s3c2410_nand_driver);
897 }
898
899 static void __exit s3c2410_nand_exit(void)
900 {
901         platform_driver_unregister(&s3c2412_nand_driver);
902         platform_driver_unregister(&s3c2440_nand_driver);
903         platform_driver_unregister(&s3c2410_nand_driver);
904 }
905
906 module_init(s3c2410_nand_init);
907 module_exit(s3c2410_nand_exit);
908
909 MODULE_LICENSE("GPL");
910 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
911 MODULE_DESCRIPTION("S3C24XX MTD NAND driver");