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   1 /*
   2  * linux/drivers/ide/pci/serverworks.c          Version 0.8      25 Ebr 2003
   3  *
   4  * Copyright (C) 1998-2000 Michel Aubry
   5  * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
   6  * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
   7  * Portions copyright (c) 2001 Sun Microsystems
   8  *
   9  *
  10  * RCC/ServerWorks IDE driver for Linux
  11  *
  12  *   OSB4: `Open South Bridge' IDE Interface (fn 1)
  13  *         supports UDMA mode 2 (33 MB/s)
  14  *
  15  *   CSB5: `Champion South Bridge' IDE Interface (fn 1)
  16  *         all revisions support UDMA mode 4 (66 MB/s)
  17  *         revision A2.0 and up support UDMA mode 5 (100 MB/s)
  18  *
  19  *         *** The CSB5 does not provide ANY register ***
  20  *         *** to detect 80-conductor cable presence. ***
  21  *
  22  *   CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
  23  *
  24  *   HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
  25  *   controller same as the CSB6. Single channel ATA100 only.
  26  *
  27  * Documentation:
  28  *      Available under NDA only. Errata info very hard to get.
  29  *
  30  */
  31
  32 #include <linux/types.h>
  33 #include <linux/module.h>
  34 #include <linux/kernel.h>
  35 #include <linux/ioport.h>
  36 #include <linux/pci.h>
  37 #include <linux/hdreg.h>
  38 #include <linux/ide.h>
  39 #include <linux/init.h>
  40 #include <linux/delay.h>
  41
  42 #include <asm/io.h>
  43
  44 #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
  45 #define SVWKS_CSB6_REVISION     0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
  46
  47 /* Seagate Barracuda ATA IV Family drives in UDMA mode 5
  48  * can overrun their FIFOs when used with the CSB5 */
  49 static const char *svwks_bad_ata100[] = {
  50         "ST320011A",
  51         "ST340016A",
  52         "ST360021A",
  53         "ST380021A",
  54         NULL
  55 };
  56
  57 static u8 svwks_revision = 0;
  58 static struct pci_dev *isa_dev;
  59
  60 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
  61 {
  62         while (*list)
  63                 if (!strcmp(*list++, drive->id->model))
  64                         return 1;
  65         return 0;
  66 }
  67
  68 static u8 svwks_ratemask (ide_drive_t *drive)
  69 {
  70         struct pci_dev *dev     = HWIF(drive)->pci_dev;
  71         u8 mode = 0;
  72
  73         if (!svwks_revision)
  74                 pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
  75
  76         if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
  77                 return 2;
  78         if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
  79                 u32 reg = 0;
  80                 if (isa_dev)
  81                         pci_read_config_dword(isa_dev, 0x64, &reg);
  82
  83                 /*
  84                  *      Don't enable UDMA on disk devices for the moment
  85                  */
  86                 if(drive->media == ide_disk)
  87                         return 0;
  88                 /* Check the OSB4 DMA33 enable bit */
  89                 return ((reg & 0x00004000) == 0x00004000) ? 1 : 0;
  90         } else if (svwks_revision < SVWKS_CSB5_REVISION_NEW) {
  91                 return 1;
  92         } else if (svwks_revision >= SVWKS_CSB5_REVISION_NEW) {
  93                 u8 btr = 0;
  94                 pci_read_config_byte(dev, 0x5A, &btr);
  95                 mode = btr & 0x3;
  96                 if (!eighty_ninty_three(drive))
  97                         mode = min(mode, (u8)1);
  98                 /* If someone decides to do UDMA133 on CSB5 the same
  99                    issue will bite so be inclusive */
 100                 if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
 101                         mode = 2;
 102         }
 103         if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 104              (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
 105             (!(PCI_FUNC(dev->devfn) & 1)))
 106                 mode = 2;
 107         return mode;
 108 }
 109
 110 static u8 svwks_csb_check (struct pci_dev *dev)
 111 {
 112         switch (dev->device) {
 113                 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
 114                 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
 115                 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
 116                 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
 117                         return 1;
 118                 default:
 119                         break;
 120         }
 121         return 0;
 122 }
 123 static int svwks_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 124 {
 125         static const u8 udma_modes[]            = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
 126         static const u8 dma_modes[]             = { 0x77, 0x21, 0x20 };
 127         static const u8 pio_modes[]             = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
 128         static const u8 drive_pci[]             = { 0x41, 0x40, 0x43, 0x42 };
 129         static const u8 drive_pci2[]            = { 0x45, 0x44, 0x47, 0x46 };
 130
 131         ide_hwif_t *hwif        = HWIF(drive);
 132         struct pci_dev *dev     = hwif->pci_dev;
 133         u8 speed;
 134         u8 pio                  = ide_get_best_pio_mode(drive, 255, 5, NULL);
 135         u8 unit                 = (drive->select.b.unit & 0x01);
 136         u8 csb5                 = svwks_csb_check(dev);
 137         u8 ultra_enable         = 0, ultra_timing = 0;
 138         u8 dma_timing           = 0, pio_timing = 0;
 139         u16 csb5_pio            = 0;
 140
 141         if (xferspeed == 255)   /* PIO auto-tuning */
 142                 speed = XFER_PIO_0 + pio;
 143         else
 144                 speed = ide_rate_filter(svwks_ratemask(drive), xferspeed);
 145
 146         /* If we are about to put a disk into UDMA mode we screwed up.
 147            Our code assumes we never _ever_ do this on an OSB4 */
 148
 149         if(dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4 &&
 150                 drive->media == ide_disk && speed >= XFER_UDMA_0)
 151                         BUG();
 152
 153         pci_read_config_byte(dev, drive_pci[drive->dn], &pio_timing);
 154         pci_read_config_byte(dev, drive_pci2[drive->dn], &dma_timing);
 155         pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
 156         pci_read_config_word(dev, 0x4A, &csb5_pio);
 157         pci_read_config_byte(dev, 0x54, &ultra_enable);
 158
 159         /* Per Specified Design by OEM, and ASIC Architect */
 160         if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 161             (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
 162                 if (!drive->init_speed) {
 163                         u8 dma_stat = inb(hwif->dma_status);
 164
 165 dma_pio:
 166                         if (((ultra_enable << (7-drive->dn) & 0x80) == 0x80) &&
 167                             ((dma_stat & (1<<(5+unit))) == (1<<(5+unit)))) {
 168                                 drive->current_speed = drive->init_speed = XFER_UDMA_0 + udma_modes[(ultra_timing >> (4*unit)) & ~(0xF0)];
 169                                 return 0;
 170                         } else if ((dma_timing) &&
 171                                    ((dma_stat&(1<<(5+unit)))==(1<<(5+unit)))) {
 172                                 u8 dmaspeed = dma_timing;
 173
 174                                 dma_timing &= ~0xFF;
 175                                 if ((dmaspeed & 0x20) == 0x20)
 176                                         dmaspeed = XFER_MW_DMA_2;
 177                                 else if ((dmaspeed & 0x21) == 0x21)
 178                                         dmaspeed = XFER_MW_DMA_1;
 179                                 else if ((dmaspeed & 0x77) == 0x77)
 180                                         dmaspeed = XFER_MW_DMA_0;
 181                                 else
 182                                         goto dma_pio;
 183                                 drive->current_speed = drive->init_speed = dmaspeed;
 184                                 return 0;
 185                         } else if (pio_timing) {
 186                                 u8 piospeed = pio_timing;
 187
 188                                 pio_timing &= ~0xFF;
 189                                 if ((piospeed & 0x20) == 0x20)
 190                                         piospeed = XFER_PIO_4;
 191                                 else if ((piospeed & 0x22) == 0x22)
 192                                         piospeed = XFER_PIO_3;
 193                                 else if ((piospeed & 0x34) == 0x34)
 194                                         piospeed = XFER_PIO_2;
 195                                 else if ((piospeed & 0x47) == 0x47)
 196                                         piospeed = XFER_PIO_1;
 197                                 else if ((piospeed & 0x5d) == 0x5d)
 198                                         piospeed = XFER_PIO_0;
 199                                 else
 200                                         goto oem_setup_failed;
 201                                 drive->current_speed = drive->init_speed = piospeed;
 202                                 return 0;
 203                         }
 204                 }
 205         }
 206
 207 oem_setup_failed:
 208
 209         pio_timing      &= ~0xFF;
 210         dma_timing      &= ~0xFF;
 211         ultra_timing    &= ~(0x0F << (4*unit));
 212         ultra_enable    &= ~(0x01 << drive->dn);
 213         csb5_pio        &= ~(0x0F << (4*drive->dn));
 214
 215         switch(speed) {
 216                 case XFER_PIO_4:
 217                 case XFER_PIO_3:
 218                 case XFER_PIO_2:
 219                 case XFER_PIO_1:
 220                 case XFER_PIO_0:
 221                         pio_timing |= pio_modes[speed - XFER_PIO_0];
 222                         csb5_pio   |= ((speed - XFER_PIO_0) << (4*drive->dn));
 223                         break;
 224
 225                 case XFER_MW_DMA_2:
 226                 case XFER_MW_DMA_1:
 227                 case XFER_MW_DMA_0:
 228                         pio_timing |= pio_modes[pio];
 229                         csb5_pio   |= (pio << (4*drive->dn));
 230                         dma_timing |= dma_modes[speed - XFER_MW_DMA_0];
 231                         break;
 232
 233                 case XFER_UDMA_5:
 234                 case XFER_UDMA_4:
 235                 case XFER_UDMA_3:
 236                 case XFER_UDMA_2:
 237                 case XFER_UDMA_1:
 238                 case XFER_UDMA_0:
 239                         pio_timing   |= pio_modes[pio];
 240                         csb5_pio     |= (pio << (4*drive->dn));
 241                         dma_timing   |= dma_modes[2];
 242                         ultra_timing |= ((udma_modes[speed - XFER_UDMA_0]) << (4*unit));
 243                         ultra_enable |= (0x01 << drive->dn);
 244                 default:
 245                         break;
 246         }
 247
 248         pci_write_config_byte(dev, drive_pci[drive->dn], pio_timing);
 249         if (csb5)
 250                 pci_write_config_word(dev, 0x4A, csb5_pio);
 251
 252         pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
 253         pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
 254         pci_write_config_byte(dev, 0x54, ultra_enable);
 255
 256         return (ide_config_drive_speed(drive, speed));
 257 }
 258
 259 static void config_chipset_for_pio (ide_drive_t *drive)
 260 {
 261         u16 eide_pio_timing[6] = {960, 480, 240, 180, 120, 90};
 262         u16 xfer_pio = drive->id->eide_pio_modes;
 263         u8 timing, speed, pio;
 264
 265         pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
 266
 267         if (xfer_pio > 4)
 268                 xfer_pio = 0;
 269
 270         if (drive->id->eide_pio_iordy > 0)
 271                 for (xfer_pio = 5;
 272                         xfer_pio>0 &&
 273                         drive->id->eide_pio_iordy>eide_pio_timing[xfer_pio];
 274                         xfer_pio--);
 275         else
 276                 xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
 277                            (drive->id->eide_pio_modes & 2) ? 0x04 :
 278                            (drive->id->eide_pio_modes & 1) ? 0x03 :
 279                            (drive->id->tPIO & 2) ? 0x02 :
 280                            (drive->id->tPIO & 1) ? 0x01 : xfer_pio;
 281
 282         timing = (xfer_pio >= pio) ? xfer_pio : pio;
 283
 284         switch(timing) {
 285                 case 4: speed = XFER_PIO_4;break;
 286                 case 3: speed = XFER_PIO_3;break;
 287                 case 2: speed = XFER_PIO_2;break;
 288                 case 1: speed = XFER_PIO_1;break;
 289                 default:
 290                         speed = (!drive->id->tPIO) ? XFER_PIO_0 : XFER_PIO_SLOW;
 291                         break;
 292         }
 293         (void) svwks_tune_chipset(drive, speed);
 294         drive->current_speed = speed;
 295 }
 296
 297 static void svwks_tune_drive (ide_drive_t *drive, u8 pio)
 298 {
 299         if(pio == 255)
 300                 (void) svwks_tune_chipset(drive, 255);
 301         else
 302                 (void) svwks_tune_chipset(drive, (XFER_PIO_0 + pio));
 303 }
 304
 305 static int config_chipset_for_dma (ide_drive_t *drive)
 306 {
 307         u8 speed = ide_dma_speed(drive, svwks_ratemask(drive));
 308
 309         if (!(speed))
 310                 speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL);
 311
 312         (void) svwks_tune_chipset(drive, speed);
 313         return ide_dma_enable(drive);
 314 }
 315
 316 static int svwks_config_drive_xfer_rate (ide_drive_t *drive)
 317 {
 318         drive->init_speed = 0;
 319
 320         if (ide_use_dma(drive) && config_chipset_for_dma(drive))
 321                 return 0;
 322
 323         if (ide_use_fast_pio(drive))
 324                 config_chipset_for_pio(drive);
 325
 326         return -1;
 327 }
 328
 329 static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const char *name)
 330 {
 331         unsigned int reg;
 332         u8 btr;
 333
 334         /* save revision id to determine DMA capability */
 335         pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
 336
 337         /* force Master Latency Timer value to 64 PCICLKs */
 338         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
 339
 340         /* OSB4 : South Bridge and IDE */
 341         if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
 342                 isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 343                           PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
 344                 if (isa_dev) {
 345                         pci_read_config_dword(isa_dev, 0x64, &reg);
 346                         reg &= ~0x00002000; /* disable 600ns interrupt mask */
 347                         if(!(reg & 0x00004000))
 348                                 printk(KERN_DEBUG "%s: UDMA not BIOS enabled.\n", name);
 349                         reg |=  0x00004000; /* enable UDMA/33 support */
 350                         pci_write_config_dword(isa_dev, 0x64, reg);
 351                 }
 352         }
 353
 354         /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
 355         else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
 356                  (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 357                  (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
 358
 359                 /* Third Channel Test */
 360                 if (!(PCI_FUNC(dev->devfn) & 1)) {
 361                         struct pci_dev * findev = NULL;
 362                         u32 reg4c = 0;
 363                         findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 364                                 PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
 365                         if (findev) {
 366                                 pci_read_config_dword(findev, 0x4C, &reg4c);
 367                                 reg4c &= ~0x000007FF;
 368                                 reg4c |=  0x00000040;
 369                                 reg4c |=  0x00000020;
 370                                 pci_write_config_dword(findev, 0x4C, reg4c);
 371                                 pci_dev_put(findev);
 372                         }
 373                         outb_p(0x06, 0x0c00);
 374                         dev->irq = inb_p(0x0c01);
 375                 } else {
 376                         struct pci_dev * findev = NULL;
 377                         u8 reg41 = 0;
 378
 379                         findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 380                                         PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
 381                         if (findev) {
 382                                 pci_read_config_byte(findev, 0x41, &reg41);
 383                                 reg41 &= ~0x40;
 384                                 pci_write_config_byte(findev, 0x41, reg41);
 385                                 pci_dev_put(findev);
 386                         }
 387                         /*
 388                          * This is a device pin issue on CSB6.
 389                          * Since there will be a future raid mode,
 390                          * early versions of the chipset require the
 391                          * interrupt pin to be set, and it is a compatibility
 392                          * mode issue.
 393                          */
 394                         if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
 395                                 dev->irq = 0;
 396                 }
 397 //              pci_read_config_dword(dev, 0x40, &pioreg)
 398 //              pci_write_config_dword(dev, 0x40, 0x99999999);
 399 //              pci_read_config_dword(dev, 0x44, &dmareg);
 400 //              pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
 401                 /* setup the UDMA Control register
 402                  *
 403                  * 1. clear bit 6 to enable DMA
 404                  * 2. enable DMA modes with bits 0-1
 405                  *      00 : legacy
 406                  *      01 : udma2
 407                  *      10 : udma2/udma4
 408                  *      11 : udma2/udma4/udma5
 409                  */
 410                 pci_read_config_byte(dev, 0x5A, &btr);
 411                 btr &= ~0x40;
 412                 if (!(PCI_FUNC(dev->devfn) & 1))
 413                         btr |= 0x2;
 414                 else
 415                         btr |= (svwks_revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
 416                 pci_write_config_byte(dev, 0x5A, btr);
 417         }
 418         /* Setup HT1000 SouthBridge Controller - Single Channel Only */
 419         else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
 420                 pci_read_config_byte(dev, 0x5A, &btr);
 421                 btr &= ~0x40;
 422                 btr |= 0x3;
 423                 pci_write_config_byte(dev, 0x5A, btr);
 424         }
 425
 426         return dev->irq;
 427 }
 428
 429 static unsigned int __devinit ata66_svwks_svwks (ide_hwif_t *hwif)
 430 {
 431         return 1;
 432 }
 433
 434 /* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
 435  * of the subsystem device ID indicate presence of an 80-pin cable.
 436  * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
 437  * Bit 15 set   = secondary IDE channel has 80-pin cable.
 438  * Bit 14 clear = primary IDE channel does not have 80-pin cable.
 439  * Bit 14 set   = primary IDE channel has 80-pin cable.
 440  */
 441 static unsigned int __devinit ata66_svwks_dell (ide_hwif_t *hwif)
 442 {
 443         struct pci_dev *dev = hwif->pci_dev;
 444         if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
 445             dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
 446             (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
 447              dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
 448                 return ((1 << (hwif->channel + 14)) &
 449                         dev->subsystem_device) ? 1 : 0;
 450         return 0;
 451 }
 452
 453 /* Sun Cobalt Alpine hardware avoids the 80-pin cable
 454  * detect issue by attaching the drives directly to the board.
 455  * This check follows the Dell precedent (how scary is that?!)
 456  *
 457  * WARNING: this only works on Alpine hardware!
 458  */
 459 static unsigned int __devinit ata66_svwks_cobalt (ide_hwif_t *hwif)
 460 {
 461         struct pci_dev *dev = hwif->pci_dev;
 462         if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
 463             dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
 464             dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
 465                 return ((1 << (hwif->channel + 14)) &
 466                         dev->subsystem_device) ? 1 : 0;
 467         return 0;
 468 }
 469
 470 static unsigned int __devinit ata66_svwks (ide_hwif_t *hwif)
 471 {
 472         struct pci_dev *dev = hwif->pci_dev;
 473
 474         /* Server Works */
 475         if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
 476                 return ata66_svwks_svwks (hwif);
 477
 478         /* Dell PowerEdge */
 479         if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
 480                 return ata66_svwks_dell (hwif);
 481
 482         /* Cobalt Alpine */
 483         if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
 484                 return ata66_svwks_cobalt (hwif);
 485
 486         /* Per Specified Design by OEM, and ASIC Architect */
 487         if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 488             (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
 489                 return 1;
 490
 491         return 0;
 492 }
 493
 494 static void __devinit init_hwif_svwks (ide_hwif_t *hwif)
 495 {
 496         u8 dma_stat = 0;
 497
 498         if (!hwif->irq)
 499                 hwif->irq = hwif->channel ? 15 : 14;
 500
 501         hwif->tuneproc = &svwks_tune_drive;
 502         hwif->speedproc = &svwks_tune_chipset;
 503
 504         hwif->atapi_dma = 1;
 505
 506         if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE)
 507                 hwif->ultra_mask = 0x3f;
 508
 509         hwif->mwdma_mask = 0x07;
 510
 511         hwif->autodma = 0;
 512
 513         if (!hwif->dma_base) {
 514                 hwif->drives[0].autotune = 1;
 515                 hwif->drives[1].autotune = 1;
 516                 return;
 517         }
 518
 519         hwif->ide_dma_check = &svwks_config_drive_xfer_rate;
 520         if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
 521                 if (!hwif->udma_four)
 522                         hwif->udma_four = ata66_svwks(hwif);
 523         }
 524         if (!noautodma)
 525                 hwif->autodma = 1;
 526
 527         dma_stat = inb(hwif->dma_status);
 528         hwif->drives[0].autodma = (dma_stat & 0x20);
 529         hwif->drives[1].autodma = (dma_stat & 0x40);
 530         hwif->drives[0].autotune = (!(dma_stat & 0x20));
 531         hwif->drives[1].autotune = (!(dma_stat & 0x40));
 532 }
 533
 534 static int __devinit init_setup_svwks (struct pci_dev *dev, ide_pci_device_t *d)
 535 {
 536         return ide_setup_pci_device(dev, d);
 537 }
 538
 539 static int __devinit init_setup_csb6 (struct pci_dev *dev, ide_pci_device_t *d)
 540 {
 541         if (!(PCI_FUNC(dev->devfn) & 1)) {
 542                 d->bootable = NEVER_BOARD;
 543                 if (dev->resource[0].start == 0x01f1)
 544                         d->bootable = ON_BOARD;
 545         }
 546
 547         d->channels = ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE ||
 548                         dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2) &&
 549                        (!(PCI_FUNC(dev->devfn) & 1))) ? 1 : 2;
 550
 551         return ide_setup_pci_device(dev, d);
 552 }
 553
 554 static ide_pci_device_t serverworks_chipsets[] __devinitdata = {
 555         {       /* 0 */
 556                 .name           = "SvrWks OSB4",
 557                 .init_setup     = init_setup_svwks,
 558                 .init_chipset   = init_chipset_svwks,
 559                 .init_hwif      = init_hwif_svwks,
 560                 .channels       = 2,
 561                 .autodma        = AUTODMA,
 562                 .bootable       = ON_BOARD,
 563         },{     /* 1 */
 564                 .name           = "SvrWks CSB5",
 565                 .init_setup     = init_setup_svwks,
 566                 .init_chipset   = init_chipset_svwks,
 567                 .init_hwif      = init_hwif_svwks,
 568                 .channels       = 2,
 569                 .autodma        = AUTODMA,
 570                 .bootable       = ON_BOARD,
 571         },{     /* 2 */
 572                 .name           = "SvrWks CSB6",
 573                 .init_setup     = init_setup_csb6,
 574                 .init_chipset   = init_chipset_svwks,
 575                 .init_hwif      = init_hwif_svwks,
 576                 .channels       = 2,
 577                 .autodma        = AUTODMA,
 578                 .bootable       = ON_BOARD,
 579         },{     /* 3 */
 580                 .name           = "SvrWks CSB6",
 581                 .init_setup     = init_setup_csb6,
 582                 .init_chipset   = init_chipset_svwks,
 583                 .init_hwif      = init_hwif_svwks,
 584                 .channels       = 1,    /* 2 */
 585                 .autodma        = AUTODMA,
 586                 .bootable       = ON_BOARD,
 587         },{     /* 4 */
 588                 .name           = "SvrWks HT1000",
 589                 .init_setup     = init_setup_svwks,
 590                 .init_chipset   = init_chipset_svwks,
 591                 .init_hwif      = init_hwif_svwks,
 592                 .channels       = 1,    /* 2 */
 593                 .autodma        = AUTODMA,
 594                 .bootable       = ON_BOARD,
 595         }
 596 };
 597
 598 /**
 599  *      svwks_init_one  -       called when a OSB/CSB is found
 600  *      @dev: the svwks device
 601  *      @id: the matching pci id
 602  *
 603  *      Called when the PCI registration layer (or the IDE initialization)
 604  *      finds a device matching our IDE device tables.
 605  */
 606
 607 static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 608 {
 609         ide_pci_device_t *d = &serverworks_chipsets[id->driver_data];
 610
 611         return d->init_setup(dev, d);
 612 }
 613
 614 static struct pci_device_id svwks_pci_tbl[] = {
 615         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 616         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
 617         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
 618         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
 619         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
 620         { 0, },
 621 };
 622 MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);
 623
 624 static struct pci_driver driver = {
 625         .name           = "Serverworks_IDE",
 626         .id_table       = svwks_pci_tbl,
 627         .probe          = svwks_init_one,
 628 };
 629
 630 static int __init svwks_ide_init(void)
 631 {
 632         return ide_pci_register_driver(&driver);
 633 }
 634
 635 module_init(svwks_ide_init);
 636
 637 MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick");
 638 MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
 639 MODULE_LICENSE("GPL");