Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[linux-2.6] / drivers / scsi / aic7xxx / aic79xx_pci.c
1 /*
2  * Product specific probe and attach routines for:
3  *      aic7901 and aic7902 SCSI controllers
4  *
5  * Copyright (c) 1994-2001 Justin T. Gibbs.
6  * Copyright (c) 2000-2002 Adaptec Inc.
7  * All rights reserved.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions, and the following disclaimer,
14  *    without modification.
15  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
16  *    substantially similar to the "NO WARRANTY" disclaimer below
17  *    ("Disclaimer") and any redistribution must be conditioned upon
18  *    including a substantially similar Disclaimer requirement for further
19  *    binary redistribution.
20  * 3. Neither the names of the above-listed copyright holders nor the names
21  *    of any contributors may be used to endorse or promote products derived
22  *    from this software without specific prior written permission.
23  *
24  * Alternatively, this software may be distributed under the terms of the
25  * GNU General Public License ("GPL") version 2 as published by the Free
26  * Software Foundation.
27  *
28  * NO WARRANTY
29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
37  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
38  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39  * POSSIBILITY OF SUCH DAMAGES.
40  *
41  * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#92 $
42  */
43
44 #ifdef __linux__
45 #include "aic79xx_osm.h"
46 #include "aic79xx_inline.h"
47 #else
48 #include <dev/aic7xxx/aic79xx_osm.h>
49 #include <dev/aic7xxx/aic79xx_inline.h>
50 #endif
51
52 #include "aic79xx_pci.h"
53
54 static __inline uint64_t
55 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
56 {
57         uint64_t id;
58
59         id = subvendor
60            | (subdevice << 16)
61            | ((uint64_t)vendor << 32)
62            | ((uint64_t)device << 48);
63
64         return (id);
65 }
66
67 #define ID_AIC7902_PCI_REV_A4           0x3
68 #define ID_AIC7902_PCI_REV_B0           0x10
69 #define SUBID_HP                        0x0E11
70
71 #define DEVID_9005_HOSTRAID(id) ((id) & 0x80)
72
73 #define DEVID_9005_TYPE(id) ((id) & 0xF)
74 #define         DEVID_9005_TYPE_HBA             0x0     /* Standard Card */
75 #define         DEVID_9005_TYPE_HBA_2EXT        0x1     /* 2 External Ports */
76 #define         DEVID_9005_TYPE_IROC            0x8     /* Raid(0,1,10) Card */
77 #define         DEVID_9005_TYPE_MB              0xF     /* On Motherboard */
78
79 #define DEVID_9005_MFUNC(id) ((id) & 0x10)
80
81 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000)
82
83 #define SUBID_9005_TYPE(id) ((id) & 0xF)
84 #define         SUBID_9005_TYPE_HBA             0x0     /* Standard Card */
85 #define         SUBID_9005_TYPE_MB              0xF     /* On Motherboard */
86
87 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0)
88
89 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20)
90
91 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6)
92 #define         SUBID_9005_SEEPTYPE_NONE        0x0
93 #define         SUBID_9005_SEEPTYPE_4K          0x1
94
95 static ahd_device_setup_t ahd_aic7901_setup;
96 static ahd_device_setup_t ahd_aic7901A_setup;
97 static ahd_device_setup_t ahd_aic7902_setup;
98 static ahd_device_setup_t ahd_aic790X_setup;
99
100 static struct ahd_pci_identity ahd_pci_ident_table [] =
101 {
102         /* aic7901 based controllers */
103         {
104                 ID_AHA_29320A,
105                 ID_ALL_MASK,
106                 "Adaptec 29320A Ultra320 SCSI adapter",
107                 ahd_aic7901_setup
108         },
109         {
110                 ID_AHA_29320ALP,
111                 ID_ALL_MASK,
112                 "Adaptec 29320ALP Ultra320 SCSI adapter",
113                 ahd_aic7901_setup
114         },
115         /* aic7901A based controllers */
116         {
117                 ID_AHA_29320LP,
118                 ID_ALL_MASK,
119                 "Adaptec 29320LP Ultra320 SCSI adapter",
120                 ahd_aic7901A_setup
121         },
122         /* aic7902 based controllers */ 
123         {
124                 ID_AHA_29320,
125                 ID_ALL_MASK,
126                 "Adaptec 29320 Ultra320 SCSI adapter",
127                 ahd_aic7902_setup
128         },
129         {
130                 ID_AHA_29320B,
131                 ID_ALL_MASK,
132                 "Adaptec 29320B Ultra320 SCSI adapter",
133                 ahd_aic7902_setup
134         },
135         {
136                 ID_AHA_39320,
137                 ID_ALL_MASK,
138                 "Adaptec 39320 Ultra320 SCSI adapter",
139                 ahd_aic7902_setup
140         },
141         {
142                 ID_AHA_39320_B,
143                 ID_ALL_MASK,
144                 "Adaptec 39320 Ultra320 SCSI adapter",
145                 ahd_aic7902_setup
146         },
147         {
148                 ID_AHA_39320_B_DELL,
149                 ID_ALL_MASK,
150                 "Adaptec (Dell OEM) 39320 Ultra320 SCSI adapter",
151                 ahd_aic7902_setup
152         },
153         {
154                 ID_AHA_39320A,
155                 ID_ALL_MASK,
156                 "Adaptec 39320A Ultra320 SCSI adapter",
157                 ahd_aic7902_setup
158         },
159         {
160                 ID_AHA_39320D,
161                 ID_ALL_MASK,
162                 "Adaptec 39320D Ultra320 SCSI adapter",
163                 ahd_aic7902_setup
164         },
165         {
166                 ID_AHA_39320D_HP,
167                 ID_ALL_MASK,
168                 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
169                 ahd_aic7902_setup
170         },
171         {
172                 ID_AHA_39320D_B,
173                 ID_ALL_MASK,
174                 "Adaptec 39320D Ultra320 SCSI adapter",
175                 ahd_aic7902_setup
176         },
177         {
178                 ID_AHA_39320D_B_HP,
179                 ID_ALL_MASK,
180                 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
181                 ahd_aic7902_setup
182         },
183         /* Generic chip probes for devices we don't know 'exactly' */
184         {
185                 ID_AIC7901 & ID_9005_GENERIC_MASK,
186                 ID_9005_GENERIC_MASK,
187                 "Adaptec AIC7901 Ultra320 SCSI adapter",
188                 ahd_aic7901_setup
189         },
190         {
191                 ID_AIC7901A & ID_DEV_VENDOR_MASK,
192                 ID_DEV_VENDOR_MASK,
193                 "Adaptec AIC7901A Ultra320 SCSI adapter",
194                 ahd_aic7901A_setup
195         },
196         {
197                 ID_AIC7902 & ID_9005_GENERIC_MASK,
198                 ID_9005_GENERIC_MASK,
199                 "Adaptec AIC7902 Ultra320 SCSI adapter",
200                 ahd_aic7902_setup
201         }
202 };
203
204 static const u_int ahd_num_pci_devs = ARRAY_SIZE(ahd_pci_ident_table);
205                 
206 #define DEVCONFIG               0x40
207 #define         PCIXINITPAT     0x0000E000ul
208 #define                 PCIXINIT_PCI33_66       0x0000E000ul
209 #define                 PCIXINIT_PCIX50_66      0x0000C000ul
210 #define                 PCIXINIT_PCIX66_100     0x0000A000ul
211 #define                 PCIXINIT_PCIX100_133    0x00008000ul
212 #define PCI_BUS_MODES_INDEX(devconfig)  \
213         (((devconfig) & PCIXINITPAT) >> 13)
214 static const char *pci_bus_modes[] =
215 {
216         "PCI bus mode unknown",
217         "PCI bus mode unknown",
218         "PCI bus mode unknown",
219         "PCI bus mode unknown",
220         "PCI-X 101-133Mhz",
221         "PCI-X 67-100Mhz",
222         "PCI-X 50-66Mhz",
223         "PCI 33 or 66Mhz"
224 };
225
226 #define         TESTMODE        0x00000800ul
227 #define         IRDY_RST        0x00000200ul
228 #define         FRAME_RST       0x00000100ul
229 #define         PCI64BIT        0x00000080ul
230 #define         MRDCEN          0x00000040ul
231 #define         ENDIANSEL       0x00000020ul
232 #define         MIXQWENDIANEN   0x00000008ul
233 #define         DACEN           0x00000004ul
234 #define         STPWLEVEL       0x00000002ul
235 #define         QWENDIANSEL     0x00000001ul
236
237 #define DEVCONFIG1              0x44
238 #define         PREQDIS         0x01
239
240 #define CSIZE_LATTIME           0x0c
241 #define         CACHESIZE       0x000000fful
242 #define         LATTIME         0x0000ff00ul
243
244 static int      ahd_check_extport(struct ahd_softc *ahd);
245 static void     ahd_configure_termination(struct ahd_softc *ahd,
246                                           u_int adapter_control);
247 static void     ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat);
248 static void     ahd_pci_intr(struct ahd_softc *ahd);
249
250 struct ahd_pci_identity *
251 ahd_find_pci_device(ahd_dev_softc_t pci)
252 {
253         uint64_t  full_id;
254         uint16_t  device;
255         uint16_t  vendor;
256         uint16_t  subdevice;
257         uint16_t  subvendor;
258         struct    ahd_pci_identity *entry;
259         u_int     i;
260
261         vendor = ahd_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
262         device = ahd_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
263         subvendor = ahd_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
264         subdevice = ahd_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
265         full_id = ahd_compose_id(device,
266                                  vendor,
267                                  subdevice,
268                                  subvendor);
269
270         /*
271          * Controllers, mask out the IROC/HostRAID bit
272          */
273         
274         full_id &= ID_ALL_IROC_MASK;
275
276         for (i = 0; i < ahd_num_pci_devs; i++) {
277                 entry = &ahd_pci_ident_table[i];
278                 if (entry->full_id == (full_id & entry->id_mask)) {
279                         /* Honor exclusion entries. */
280                         if (entry->name == NULL)
281                                 return (NULL);
282                         return (entry);
283                 }
284         }
285         return (NULL);
286 }
287
288 int
289 ahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry)
290 {
291         struct scb_data *shared_scb_data;
292         u_int            command;
293         uint32_t         devconfig;
294         uint16_t         subvendor; 
295         int              error;
296
297         shared_scb_data = NULL;
298         ahd->description = entry->name;
299         /*
300          * Record if this is an HP board.
301          */
302         subvendor = ahd_pci_read_config(ahd->dev_softc,
303                                         PCIR_SUBVEND_0, /*bytes*/2);
304         if (subvendor == SUBID_HP)
305                 ahd->flags |= AHD_HP_BOARD;
306
307         error = entry->setup(ahd);
308         if (error != 0)
309                 return (error);
310         
311         devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
312         if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) {
313                 ahd->chip |= AHD_PCI;
314                 /* Disable PCIX workarounds when running in PCI mode. */
315                 ahd->bugs &= ~AHD_PCIX_BUG_MASK;
316         } else {
317                 ahd->chip |= AHD_PCIX;
318         }
319         ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)];
320
321         ahd_power_state_change(ahd, AHD_POWER_STATE_D0);
322
323         error = ahd_pci_map_registers(ahd);
324         if (error != 0)
325                 return (error);
326
327         /*
328          * If we need to support high memory, enable dual
329          * address cycles.  This bit must be set to enable
330          * high address bit generation even if we are on a
331          * 64bit bus (PCI64BIT set in devconfig).
332          */
333         if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) {
334                 uint32_t devconfig;
335
336                 if (bootverbose)
337                         printf("%s: Enabling 39Bit Addressing\n",
338                                ahd_name(ahd));
339                 devconfig = ahd_pci_read_config(ahd->dev_softc,
340                                                 DEVCONFIG, /*bytes*/4);
341                 devconfig |= DACEN;
342                 ahd_pci_write_config(ahd->dev_softc, DEVCONFIG,
343                                      devconfig, /*bytes*/4);
344         }
345         
346         /* Ensure busmastering is enabled */
347         command = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
348         command |= PCIM_CMD_BUSMASTEREN;
349         ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
350
351         error = ahd_softc_init(ahd);
352         if (error != 0)
353                 return (error);
354
355         ahd->bus_intr = ahd_pci_intr;
356
357         error = ahd_reset(ahd, /*reinit*/FALSE);
358         if (error != 0)
359                 return (ENXIO);
360
361         ahd->pci_cachesize =
362             ahd_pci_read_config(ahd->dev_softc, CSIZE_LATTIME,
363                                 /*bytes*/1) & CACHESIZE;
364         ahd->pci_cachesize *= 4;
365
366         ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
367         /* See if we have a SEEPROM and perform auto-term */
368         error = ahd_check_extport(ahd);
369         if (error != 0)
370                 return (error);
371
372         /* Core initialization */
373         error = ahd_init(ahd);
374         if (error != 0)
375                 return (error);
376
377         /*
378          * Allow interrupts now that we are completely setup.
379          */
380         error = ahd_pci_map_int(ahd);
381         if (!error)
382                 ahd->init_level++;
383         return error;
384 }
385
386 /*
387  * Perform some simple tests that should catch situations where
388  * our registers are invalidly mapped.
389  */
390 int
391 ahd_pci_test_register_access(struct ahd_softc *ahd)
392 {
393         uint32_t cmd;
394         u_int    targpcistat;
395         u_int    pci_status1;
396         int      error;
397         uint8_t  hcntrl;
398
399         error = EIO;
400
401         /*
402          * Enable PCI error interrupt status, but suppress NMIs
403          * generated by SERR raised due to target aborts.
404          */
405         cmd = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
406         ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
407                              cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
408
409         /*
410          * First a simple test to see if any
411          * registers can be read.  Reading
412          * HCNTRL has no side effects and has
413          * at least one bit that is guaranteed to
414          * be zero so it is a good register to
415          * use for this test.
416          */
417         hcntrl = ahd_inb(ahd, HCNTRL);
418         if (hcntrl == 0xFF)
419                 goto fail;
420
421         /*
422          * Next create a situation where write combining
423          * or read prefetching could be initiated by the
424          * CPU or host bridge.  Our device does not support
425          * either, so look for data corruption and/or flaged
426          * PCI errors.  First pause without causing another
427          * chip reset.
428          */
429         hcntrl &= ~CHIPRST;
430         ahd_outb(ahd, HCNTRL, hcntrl|PAUSE);
431         while (ahd_is_paused(ahd) == 0)
432                 ;
433
434         /* Clear any PCI errors that occurred before our driver attached. */
435         ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
436         targpcistat = ahd_inb(ahd, TARGPCISTAT);
437         ahd_outb(ahd, TARGPCISTAT, targpcistat);
438         pci_status1 = ahd_pci_read_config(ahd->dev_softc,
439                                           PCIR_STATUS + 1, /*bytes*/1);
440         ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
441                              pci_status1, /*bytes*/1);
442         ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
443         ahd_outb(ahd, CLRINT, CLRPCIINT);
444
445         ahd_outb(ahd, SEQCTL0, PERRORDIS);
446         ahd_outl(ahd, SRAM_BASE, 0x5aa555aa);
447         if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa)
448                 goto fail;
449
450         if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
451                 u_int targpcistat;
452
453                 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
454                 targpcistat = ahd_inb(ahd, TARGPCISTAT);
455                 if ((targpcistat & STA) != 0)
456                         goto fail;
457         }
458
459         error = 0;
460
461 fail:
462         if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
463
464                 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
465                 targpcistat = ahd_inb(ahd, TARGPCISTAT);
466
467                 /* Silently clear any latched errors. */
468                 ahd_outb(ahd, TARGPCISTAT, targpcistat);
469                 pci_status1 = ahd_pci_read_config(ahd->dev_softc,
470                                                   PCIR_STATUS + 1, /*bytes*/1);
471                 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
472                                      pci_status1, /*bytes*/1);
473                 ahd_outb(ahd, CLRINT, CLRPCIINT);
474         }
475         ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS);
476         ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
477         return (error);
478 }
479
480 /*
481  * Check the external port logic for a serial eeprom
482  * and termination/cable detection contrls.
483  */
484 static int
485 ahd_check_extport(struct ahd_softc *ahd)
486 {
487         struct  vpd_config vpd;
488         struct  seeprom_config *sc;
489         u_int   adapter_control;
490         int     have_seeprom;
491         int     error;
492
493         sc = ahd->seep_config;
494         have_seeprom = ahd_acquire_seeprom(ahd);
495         if (have_seeprom) {
496                 u_int start_addr;
497
498                 /*
499                  * Fetch VPD for this function and parse it.
500                  */
501                 if (bootverbose) 
502                         printf("%s: Reading VPD from SEEPROM...",
503                                ahd_name(ahd));
504
505                 /* Address is always in units of 16bit words */
506                 start_addr = ((2 * sizeof(*sc))
507                             + (sizeof(vpd) * (ahd->channel - 'A'))) / 2;
508
509                 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd,
510                                          start_addr, sizeof(vpd)/2,
511                                          /*bytestream*/TRUE);
512                 if (error == 0)
513                         error = ahd_parse_vpddata(ahd, &vpd);
514                 if (bootverbose) 
515                         printf("%s: VPD parsing %s\n",
516                                ahd_name(ahd),
517                                error == 0 ? "successful" : "failed");
518
519                 if (bootverbose) 
520                         printf("%s: Reading SEEPROM...", ahd_name(ahd));
521
522                 /* Address is always in units of 16bit words */
523                 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A');
524
525                 error = ahd_read_seeprom(ahd, (uint16_t *)sc,
526                                          start_addr, sizeof(*sc)/2,
527                                          /*bytestream*/FALSE);
528
529                 if (error != 0) {
530                         printf("Unable to read SEEPROM\n");
531                         have_seeprom = 0;
532                 } else {
533                         have_seeprom = ahd_verify_cksum(sc);
534
535                         if (bootverbose) {
536                                 if (have_seeprom == 0)
537                                         printf ("checksum error\n");
538                                 else
539                                         printf ("done.\n");
540                         }
541                 }
542                 ahd_release_seeprom(ahd);
543         }
544
545         if (!have_seeprom) {
546                 u_int     nvram_scb;
547
548                 /*
549                  * Pull scratch ram settings and treat them as
550                  * if they are the contents of an seeprom if
551                  * the 'ADPT', 'BIOS', or 'ASPI' signature is found
552                  * in SCB 0xFF.  We manually compose the data as 16bit
553                  * values to avoid endian issues.
554                  */
555                 ahd_set_scbptr(ahd, 0xFF);
556                 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET);
557                 if (nvram_scb != 0xFF
558                  && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
559                    && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D'
560                    && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
561                    && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T')
562                   || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B'
563                    && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I'
564                    && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O'
565                    && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S')
566                   || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
567                    && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S'
568                    && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
569                    && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) {
570                         uint16_t *sc_data;
571                         int       i;
572
573                         ahd_set_scbptr(ahd, nvram_scb);
574                         sc_data = (uint16_t *)sc;
575                         for (i = 0; i < 64; i += 2)
576                                 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i);
577                         have_seeprom = ahd_verify_cksum(sc);
578                         if (have_seeprom)
579                                 ahd->flags |= AHD_SCB_CONFIG_USED;
580                 }
581         }
582
583 #ifdef AHD_DEBUG
584         if (have_seeprom != 0
585          && (ahd_debug & AHD_DUMP_SEEPROM) != 0) {
586                 uint16_t *sc_data;
587                 int       i;
588
589                 printf("%s: Seeprom Contents:", ahd_name(ahd));
590                 sc_data = (uint16_t *)sc;
591                 for (i = 0; i < (sizeof(*sc)); i += 2)
592                         printf("\n\t0x%.4x", sc_data[i]);
593                 printf("\n");
594         }
595 #endif
596
597         if (!have_seeprom) {
598                 if (bootverbose)
599                         printf("%s: No SEEPROM available.\n", ahd_name(ahd));
600                 ahd->flags |= AHD_USEDEFAULTS;
601                 error = ahd_default_config(ahd);
602                 adapter_control = CFAUTOTERM|CFSEAUTOTERM;
603                 free(ahd->seep_config, M_DEVBUF);
604                 ahd->seep_config = NULL;
605         } else {
606                 error = ahd_parse_cfgdata(ahd, sc);
607                 adapter_control = sc->adapter_control;
608         }
609         if (error != 0)
610                 return (error);
611
612         ahd_configure_termination(ahd, adapter_control);
613
614         return (0);
615 }
616
617 static void
618 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control)
619 {
620         int      error;
621         u_int    sxfrctl1;
622         uint8_t  termctl;
623         uint32_t devconfig;
624
625         devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
626         devconfig &= ~STPWLEVEL;
627         if ((ahd->flags & AHD_STPWLEVEL_A) != 0)
628                 devconfig |= STPWLEVEL;
629         if (bootverbose)
630                 printf("%s: STPWLEVEL is %s\n",
631                        ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off");
632         ahd_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
633  
634         /* Make sure current sensing is off. */
635         if ((ahd->flags & AHD_CURRENT_SENSING) != 0) {
636                 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0);
637         }
638
639         /*
640          * Read to sense.  Write to set.
641          */
642         error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl);
643         if ((adapter_control & CFAUTOTERM) == 0) {
644                 if (bootverbose)
645                         printf("%s: Manual Primary Termination\n",
646                                ahd_name(ahd));
647                 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH);
648                 if ((adapter_control & CFSTERM) != 0)
649                         termctl |= FLX_TERMCTL_ENPRILOW;
650                 if ((adapter_control & CFWSTERM) != 0)
651                         termctl |= FLX_TERMCTL_ENPRIHIGH;
652         } else if (error != 0) {
653                 printf("%s: Primary Auto-Term Sensing failed! "
654                        "Using Defaults.\n", ahd_name(ahd));
655                 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH;
656         }
657
658         if ((adapter_control & CFSEAUTOTERM) == 0) {
659                 if (bootverbose)
660                         printf("%s: Manual Secondary Termination\n",
661                                ahd_name(ahd));
662                 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH);
663                 if ((adapter_control & CFSELOWTERM) != 0)
664                         termctl |= FLX_TERMCTL_ENSECLOW;
665                 if ((adapter_control & CFSEHIGHTERM) != 0)
666                         termctl |= FLX_TERMCTL_ENSECHIGH;
667         } else if (error != 0) {
668                 printf("%s: Secondary Auto-Term Sensing failed! "
669                        "Using Defaults.\n", ahd_name(ahd));
670                 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH;
671         }
672
673         /*
674          * Now set the termination based on what we found.
675          */
676         sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN;
677         ahd->flags &= ~AHD_TERM_ENB_A;
678         if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) {
679                 ahd->flags |= AHD_TERM_ENB_A;
680                 sxfrctl1 |= STPWEN;
681         }
682         /* Must set the latch once in order to be effective. */
683         ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN);
684         ahd_outb(ahd, SXFRCTL1, sxfrctl1);
685
686         error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl);
687         if (error != 0) {
688                 printf("%s: Unable to set termination settings!\n",
689                        ahd_name(ahd));
690         } else if (bootverbose) {
691                 printf("%s: Primary High byte termination %sabled\n",
692                        ahd_name(ahd),
693                        (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis");
694
695                 printf("%s: Primary Low byte termination %sabled\n",
696                        ahd_name(ahd),
697                        (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis");
698
699                 printf("%s: Secondary High byte termination %sabled\n",
700                        ahd_name(ahd),
701                        (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis");
702
703                 printf("%s: Secondary Low byte termination %sabled\n",
704                        ahd_name(ahd),
705                        (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis");
706         }
707         return;
708 }
709
710 #define DPE     0x80
711 #define SSE     0x40
712 #define RMA     0x20
713 #define RTA     0x10
714 #define STA     0x08
715 #define DPR     0x01
716
717 static const char *split_status_source[] =
718 {
719         "DFF0",
720         "DFF1",
721         "OVLY",
722         "CMC",
723 };
724
725 static const char *pci_status_source[] =
726 {
727         "DFF0",
728         "DFF1",
729         "SG",
730         "CMC",
731         "OVLY",
732         "NONE",
733         "MSI",
734         "TARG"
735 };
736
737 static const char *split_status_strings[] =
738 {
739         "%s: Received split response in %s.\n",
740         "%s: Received split completion error message in %s\n",
741         "%s: Receive overrun in %s\n",
742         "%s: Count not complete in %s\n",
743         "%s: Split completion data bucket in %s\n",
744         "%s: Split completion address error in %s\n",
745         "%s: Split completion byte count error in %s\n",
746         "%s: Signaled Target-abort to early terminate a split in %s\n"
747 };
748
749 static const char *pci_status_strings[] =
750 {
751         "%s: Data Parity Error has been reported via PERR# in %s\n",
752         "%s: Target initial wait state error in %s\n",
753         "%s: Split completion read data parity error in %s\n",
754         "%s: Split completion address attribute parity error in %s\n",
755         "%s: Received a Target Abort in %s\n",
756         "%s: Received a Master Abort in %s\n",
757         "%s: Signal System Error Detected in %s\n",
758         "%s: Address or Write Phase Parity Error Detected in %s.\n"
759 };
760
761 static void
762 ahd_pci_intr(struct ahd_softc *ahd)
763 {
764         uint8_t         pci_status[8];
765         ahd_mode_state  saved_modes;
766         u_int           pci_status1;
767         u_int           intstat;
768         u_int           i;
769         u_int           reg;
770         
771         intstat = ahd_inb(ahd, INTSTAT);
772
773         if ((intstat & SPLTINT) != 0)
774                 ahd_pci_split_intr(ahd, intstat);
775
776         if ((intstat & PCIINT) == 0)
777                 return;
778
779         printf("%s: PCI error Interrupt\n", ahd_name(ahd));
780         saved_modes = ahd_save_modes(ahd);
781         ahd_dump_card_state(ahd);
782         ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
783         for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) {
784
785                 if (i == 5)
786                         continue;
787                 pci_status[i] = ahd_inb(ahd, reg);
788                 /* Clear latched errors.  So our interrupt deasserts. */
789                 ahd_outb(ahd, reg, pci_status[i]);
790         }
791
792         for (i = 0; i < 8; i++) {
793                 u_int bit;
794         
795                 if (i == 5)
796                         continue;
797
798                 for (bit = 0; bit < 8; bit++) {
799
800                         if ((pci_status[i] & (0x1 << bit)) != 0) {
801                                 static const char *s;
802
803                                 s = pci_status_strings[bit];
804                                 if (i == 7/*TARG*/ && bit == 3)
805                                         s = "%s: Signaled Target Abort\n";
806                                 printf(s, ahd_name(ahd), pci_status_source[i]);
807                         }
808                 }       
809         }
810         pci_status1 = ahd_pci_read_config(ahd->dev_softc,
811                                           PCIR_STATUS + 1, /*bytes*/1);
812         ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
813                              pci_status1, /*bytes*/1);
814         ahd_restore_modes(ahd, saved_modes);
815         ahd_outb(ahd, CLRINT, CLRPCIINT);
816         ahd_unpause(ahd);
817 }
818
819 static void
820 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat)
821 {
822         uint8_t         split_status[4];
823         uint8_t         split_status1[4];
824         uint8_t         sg_split_status[2];
825         uint8_t         sg_split_status1[2];
826         ahd_mode_state  saved_modes;
827         u_int           i;
828         uint16_t        pcix_status;
829
830         /*
831          * Check for splits in all modes.  Modes 0 and 1
832          * additionally have SG engine splits to look at.
833          */
834         pcix_status = ahd_pci_read_config(ahd->dev_softc, PCIXR_STATUS,
835                                           /*bytes*/2);
836         printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n",
837                ahd_name(ahd), pcix_status);
838         saved_modes = ahd_save_modes(ahd);
839         for (i = 0; i < 4; i++) {
840                 ahd_set_modes(ahd, i, i);
841
842                 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0);
843                 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1);
844                 /* Clear latched errors.  So our interrupt deasserts. */
845                 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]);
846                 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]);
847                 if (i > 1)
848                         continue;
849                 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0);
850                 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1);
851                 /* Clear latched errors.  So our interrupt deasserts. */
852                 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]);
853                 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]);
854         }
855
856         for (i = 0; i < 4; i++) {
857                 u_int bit;
858
859                 for (bit = 0; bit < 8; bit++) {
860
861                         if ((split_status[i] & (0x1 << bit)) != 0) {
862                                 static const char *s;
863
864                                 s = split_status_strings[bit];
865                                 printf(s, ahd_name(ahd),
866                                        split_status_source[i]);
867                         }
868
869                         if (i > 1)
870                                 continue;
871
872                         if ((sg_split_status[i] & (0x1 << bit)) != 0) {
873                                 static const char *s;
874
875                                 s = split_status_strings[bit];
876                                 printf(s, ahd_name(ahd), "SG");
877                         }
878                 }
879         }
880         /*
881          * Clear PCI-X status bits.
882          */
883         ahd_pci_write_config(ahd->dev_softc, PCIXR_STATUS,
884                              pcix_status, /*bytes*/2);
885         ahd_outb(ahd, CLRINT, CLRSPLTINT);
886         ahd_restore_modes(ahd, saved_modes);
887 }
888
889 static int
890 ahd_aic7901_setup(struct ahd_softc *ahd)
891 {
892
893         ahd->chip = AHD_AIC7901;
894         ahd->features = AHD_AIC7901_FE;
895         return (ahd_aic790X_setup(ahd));
896 }
897
898 static int
899 ahd_aic7901A_setup(struct ahd_softc *ahd)
900 {
901
902         ahd->chip = AHD_AIC7901A;
903         ahd->features = AHD_AIC7901A_FE;
904         return (ahd_aic790X_setup(ahd));
905 }
906
907 static int
908 ahd_aic7902_setup(struct ahd_softc *ahd)
909 {
910         ahd->chip = AHD_AIC7902;
911         ahd->features = AHD_AIC7902_FE;
912         return (ahd_aic790X_setup(ahd));
913 }
914
915 static int
916 ahd_aic790X_setup(struct ahd_softc *ahd)
917 {
918         ahd_dev_softc_t pci;
919         u_int rev;
920
921         pci = ahd->dev_softc;
922         rev = ahd_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
923         if (rev < ID_AIC7902_PCI_REV_A4) {
924                 printf("%s: Unable to attach to unsupported chip revision %d\n",
925                        ahd_name(ahd), rev);
926                 ahd_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/2);
927                 return (ENXIO);
928         }
929         ahd->channel = ahd_get_pci_function(pci) + 'A';
930         if (rev < ID_AIC7902_PCI_REV_B0) {
931                 /*
932                  * Enable A series workarounds.
933                  */
934                 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG
935                           |  AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG
936                           |  AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG
937                           |  AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG
938                           |  AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG
939                           |  AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG
940                           |  AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG
941                           |  AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG
942                           |  AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG
943                           |  AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG
944                           |  AHD_FAINT_LED_BUG;
945
946                 /*
947                  * IO Cell paramter setup.
948                  */
949                 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
950
951                 if ((ahd->flags & AHD_HP_BOARD) == 0)
952                         AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA);
953         } else {
954                 /* This is revision B and newer. */
955                 extern uint32_t aic79xx_slowcrc;
956                 u_int devconfig1;
957
958                 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS
959                               |  AHD_NEW_DFCNTRL_OPTS|AHD_FAST_CDB_DELIVERY
960                               |  AHD_BUSFREEREV_BUG;
961                 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG;
962
963                 /* If the user requested the the SLOWCRC bit to be set. */
964                 if (aic79xx_slowcrc)
965                         ahd->features |= AHD_AIC79XXB_SLOWCRC;
966
967                 /*
968                  * Some issues have been resolved in the 7901B.
969                  */
970                 if ((ahd->features & AHD_MULTI_FUNC) != 0)
971                         ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG;
972
973                 /*
974                  * IO Cell paramter setup.
975                  */
976                 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
977                 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB);
978                 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF);
979
980                 /*
981                  * Set the PREQDIS bit for H2B which disables some workaround
982                  * that doesn't work on regular PCI busses.
983                  * XXX - Find out exactly what this does from the hardware
984                  *       folks!
985                  */
986                 devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
987                 ahd_pci_write_config(pci, DEVCONFIG1,
988                                      devconfig1|PREQDIS, /*bytes*/1);
989                 devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
990         }
991
992         return (0);
993 }