2 * MPC8569E MDS Device Tree Source
4 * Copyright (C) 2009 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
15 model = "MPC8569EMDS";
16 compatible = "fsl,MPC8569EMDS";
38 d-cache-line-size = <32>; // 32 bytes
39 i-cache-line-size = <32>; // 32 bytes
40 d-cache-size = <0x8000>; // L1, 32K
41 i-cache-size = <0x8000>; // L1, 32K
42 timebase-frequency = <0>;
44 clock-frequency = <0>;
45 next-level-cache = <&L2>;
50 device_type = "memory";
56 compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus";
57 reg = <0xe0005000 0x1000>;
59 interrupt-parent = <&mpic>;
61 ranges = <0x0 0x0 0xfe000000 0x02000000
62 0x1 0x0 0xf8000000 0x00008000
63 0x2 0x0 0xf0000000 0x04000000
64 0x3 0x0 0xfc000000 0x00008000
65 0x4 0x0 0xf8008000 0x00008000
66 0x5 0x0 0xf8010000 0x00008000>;
71 compatible = "cfi-flash";
72 reg = <0x0 0x0 0x02000000>;
78 compatible = "fsl,mpc8569mds-bcsr";
83 compatible = "fsl,mpc8569-fcm-nand",
89 compatible = "fsl,mpc8569mds-pib";
94 compatible = "fsl,mpc8569mds-pib";
100 #address-cells = <1>;
103 compatible = "fsl,mpc8569-immr", "simple-bus";
104 ranges = <0x0 0xe0000000 0x100000>;
108 compatible = "fsl,ecm-law";
114 compatible = "fsl,mpc8569-ecm", "fsl,ecm";
115 reg = <0x1000 0x1000>;
117 interrupt-parent = <&mpic>;
120 memory-controller@2000 {
121 compatible = "fsl,mpc8569-memory-controller";
122 reg = <0x2000 0x1000>;
123 interrupt-parent = <&mpic>;
128 #address-cells = <1>;
131 compatible = "fsl-i2c";
132 reg = <0x3000 0x100>;
134 interrupt-parent = <&mpic>;
138 compatible = "dallas,ds1374";
144 #address-cells = <1>;
147 compatible = "fsl-i2c";
148 reg = <0x3100 0x100>;
150 interrupt-parent = <&mpic>;
154 serial0: serial@4500 {
156 device_type = "serial";
157 compatible = "ns16550";
158 reg = <0x4500 0x100>;
159 clock-frequency = <0>;
161 interrupt-parent = <&mpic>;
164 serial1: serial@4600 {
166 device_type = "serial";
167 compatible = "ns16550";
168 reg = <0x4600 0x100>;
169 clock-frequency = <0>;
171 interrupt-parent = <&mpic>;
174 L2: l2-cache-controller@20000 {
175 compatible = "fsl,mpc8569-l2-cache-controller";
176 reg = <0x20000 0x1000>;
177 cache-line-size = <32>; // 32 bytes
178 cache-size = <0x80000>; // L2, 512K
179 interrupt-parent = <&mpic>;
184 #address-cells = <1>;
186 compatible = "fsl,mpc8569-dma", "fsl,eloplus-dma";
188 ranges = <0x0 0x21100 0x200>;
191 compatible = "fsl,mpc8569-dma-channel",
192 "fsl,eloplus-dma-channel";
195 interrupt-parent = <&mpic>;
199 compatible = "fsl,mpc8569-dma-channel",
200 "fsl,eloplus-dma-channel";
203 interrupt-parent = <&mpic>;
207 compatible = "fsl,mpc8569-dma-channel",
208 "fsl,eloplus-dma-channel";
211 interrupt-parent = <&mpic>;
215 compatible = "fsl,mpc8569-dma-channel",
216 "fsl,eloplus-dma-channel";
219 interrupt-parent = <&mpic>;
225 compatible = "fsl,mpc8569-esdhc", "fsl,esdhc";
226 reg = <0x2e000 0x1000>;
227 interrupts = <72 0x8>;
228 interrupt-parent = <&mpic>;
229 /* Filled in by U-Boot */
230 clock-frequency = <0>;
235 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
236 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
237 reg = <0x30000 0x10000>;
238 interrupts = <45 2 58 2>;
239 interrupt-parent = <&mpic>;
240 fsl,num-channels = <4>;
241 fsl,channel-fifo-len = <24>;
242 fsl,exec-units-mask = <0xbfe>;
243 fsl,descriptor-types-mask = <0x3ab0ebf>;
247 interrupt-controller;
248 #address-cells = <0>;
249 #interrupt-cells = <2>;
250 reg = <0x40000 0x40000>;
251 compatible = "chrp,open-pic";
252 device_type = "open-pic";
255 global-utilities@e0000 {
256 compatible = "fsl,mpc8569-guts";
257 reg = <0xe0000 0x1000>;
262 #address-cells = <1>;
264 reg = <0xe0100 0x100>;
265 ranges = <0x0 0xe0100 0x100>;
266 device_type = "par_io";
269 qe_pio_e: gpio-controller@80 {
271 compatible = "fsl,mpc8569-qe-pario-bank",
272 "fsl,mpc8323-qe-pario-bank";
279 /* port pin dir open_drain assignment has_irq */
280 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
281 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
282 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/
283 0x0 0x0 0x1 0x0 0x3 0x0 /* ENET1_TXD0_SER1_TXD0 */
284 0x0 0x1 0x1 0x0 0x3 0x0 /* ENET1_TXD1_SER1_TXD1 */
285 0x0 0x2 0x1 0x0 0x1 0x0 /* ENET1_TXD2_SER1_TXD2 */
286 0x0 0x3 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
287 0x0 0x6 0x2 0x0 0x3 0x0 /* ENET1_RXD0_SER1_RXD0 */
288 0x0 0x7 0x2 0x0 0x1 0x0 /* ENET1_RXD1_SER1_RXD1 */
289 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
290 0x0 0x9 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
291 0x0 0x4 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
292 0x0 0xc 0x2 0x0 0x3 0x0 /* ENET1_RX_DV_SER1_CTS_B */
293 0x2 0x8 0x2 0x0 0x1 0x0 /* ENET1_GRXCLK */
294 0x2 0x14 0x1 0x0 0x2 0x0>; /* ENET1_GTXCLK */
299 /* port pin dir open_drain assignment has_irq */
300 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
301 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
302 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */
303 0x0 0xe 0x1 0x0 0x2 0x0 /* ENET2_TXD0_SER2_TXD0 */
304 0x0 0xf 0x1 0x0 0x2 0x0 /* ENET2_TXD1_SER2_TXD1 */
305 0x0 0x10 0x1 0x0 0x1 0x0 /* ENET2_TXD2_SER2_TXD2 */
306 0x0 0x11 0x1 0x0 0x1 0x0 /* ENET2_TXD3_SER2_TXD3 */
307 0x0 0x14 0x2 0x0 0x2 0x0 /* ENET2_RXD0_SER2_RXD0 */
308 0x0 0x15 0x2 0x0 0x1 0x0 /* ENET2_RXD1_SER2_RXD1 */
309 0x0 0x16 0x2 0x0 0x1 0x0 /* ENET2_RXD2_SER2_RXD2 */
310 0x0 0x17 0x2 0x0 0x1 0x0 /* ENET2_RXD3_SER2_RXD3 */
311 0x0 0x12 0x1 0x0 0x2 0x0 /* ENET2_TX_EN_SER2_RTS_B */
312 0x0 0x1a 0x2 0x0 0x3 0x0 /* ENET2_RX_DV_SER2_CTS_B */
313 0x2 0x3 0x2 0x0 0x1 0x0 /* ENET2_GRXCLK */
314 0x2 0x2 0x1 0x0 0x2 0x0>; /* ENET2_GTXCLK */
319 /* port pin dir open_drain assignment has_irq */
320 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
321 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
322 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/
323 0x0 0x1d 0x1 0x0 0x2 0x0 /* ENET3_TXD0_SER3_TXD0 */
324 0x0 0x1e 0x1 0x0 0x3 0x0 /* ENET3_TXD1_SER3_TXD1 */
325 0x0 0x1f 0x1 0x0 0x2 0x0 /* ENET3_TXD2_SER3_TXD2 */
326 0x1 0x0 0x1 0x0 0x3 0x0 /* ENET3_TXD3_SER3_TXD3 */
327 0x1 0x3 0x2 0x0 0x3 0x0 /* ENET3_RXD0_SER3_RXD0 */
328 0x1 0x4 0x2 0x0 0x1 0x0 /* ENET3_RXD1_SER3_RXD1 */
329 0x1 0x5 0x2 0x0 0x2 0x0 /* ENET3_RXD2_SER3_RXD2 */
330 0x1 0x6 0x2 0x0 0x3 0x0 /* ENET3_RXD3_SER3_RXD3 */
331 0x1 0x1 0x1 0x0 0x1 0x0 /* ENET3_TX_EN_SER3_RTS_B */
332 0x1 0x9 0x2 0x0 0x3 0x0 /* ENET3_RX_DV_SER3_CTS_B */
333 0x2 0x9 0x2 0x0 0x2 0x0 /* ENET3_GRXCLK */
334 0x2 0x19 0x1 0x0 0x2 0x0>; /* ENET3_GTXCLK */
339 /* port pin dir open_drain assignment has_irq */
340 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
341 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
342 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */
343 0x1 0xc 0x1 0x0 0x2 0x0 /* ENET4_TXD0_SER4_TXD0 */
344 0x1 0xd 0x1 0x0 0x2 0x0 /* ENET4_TXD1_SER4_TXD1 */
345 0x1 0xe 0x1 0x0 0x1 0x0 /* ENET4_TXD2_SER4_TXD2 */
346 0x1 0xf 0x1 0x0 0x2 0x0 /* ENET4_TXD3_SER4_TXD3 */
347 0x1 0x12 0x2 0x0 0x2 0x0 /* ENET4_RXD0_SER4_RXD0 */
348 0x1 0x13 0x2 0x0 0x1 0x0 /* ENET4_RXD1_SER4_RXD1 */
349 0x1 0x14 0x2 0x0 0x1 0x0 /* ENET4_RXD2_SER4_RXD2 */
350 0x1 0x15 0x2 0x0 0x2 0x0 /* ENET4_RXD3_SER4_RXD3 */
351 0x1 0x10 0x1 0x0 0x2 0x0 /* ENET4_TX_EN_SER4_RTS_B */
352 0x1 0x18 0x2 0x0 0x3 0x0 /* ENET4_RX_DV_SER4_CTS_B */
353 0x2 0x11 0x2 0x0 0x2 0x0 /* ENET4_GRXCLK */
354 0x2 0x18 0x1 0x0 0x2 0x0>; /* ENET4_GTXCLK */
360 #address-cells = <1>;
363 compatible = "fsl,qe";
364 ranges = <0x0 0xe0080000 0x40000>;
365 reg = <0xe0080000 0x480>;
368 fsl,qe-num-riscs = <4>;
369 fsl,qe-num-snums = <46>;
371 qeic: interrupt-controller@80 {
372 interrupt-controller;
373 compatible = "fsl,qe-ic";
374 #address-cells = <0>;
375 #interrupt-cells = <1>;
377 interrupts = <46 2 46 2>; //high:30 low:30
378 interrupt-parent = <&mpic>;
382 #address-cells = <1>;
384 compatible = "fsl,mpc8569-qe-spi", "fsl,spi";
388 interrupt-parent = <&qeic>;
389 gpios = <&qe_pio_e 30 0>;
393 compatible = "stm,m25p40";
395 spi-max-frequency = <25000000>;
401 compatible = "fsl,spi";
404 interrupt-parent = <&qeic>;
409 device_type = "network";
410 compatible = "ucc_geth";
412 reg = <0x2000 0x200>;
414 interrupt-parent = <&qeic>;
415 local-mac-address = [ 00 00 00 00 00 00 ];
416 rx-clock-name = "none";
417 tx-clock-name = "clk12";
418 pio-handle = <&pio1>;
419 phy-handle = <&qe_phy0>;
420 phy-connection-type = "rgmii-id";
424 #address-cells = <1>;
427 compatible = "fsl,ucc-mdio";
429 qe_phy0: ethernet-phy@07 {
430 interrupt-parent = <&mpic>;
433 device_type = "ethernet-phy";
435 qe_phy1: ethernet-phy@01 {
436 interrupt-parent = <&mpic>;
439 device_type = "ethernet-phy";
441 qe_phy2: ethernet-phy@02 {
442 interrupt-parent = <&mpic>;
445 device_type = "ethernet-phy";
447 qe_phy3: ethernet-phy@03 {
448 interrupt-parent = <&mpic>;
451 device_type = "ethernet-phy";
456 device_type = "network";
457 compatible = "ucc_geth";
459 reg = <0x2200 0x200>;
461 interrupt-parent = <&qeic>;
462 local-mac-address = [ 00 00 00 00 00 00 ];
463 rx-clock-name = "none";
464 tx-clock-name = "clk12";
465 pio-handle = <&pio3>;
466 phy-handle = <&qe_phy2>;
467 phy-connection-type = "rgmii-id";
471 device_type = "network";
472 compatible = "ucc_geth";
474 reg = <0x3000 0x200>;
476 interrupt-parent = <&qeic>;
477 local-mac-address = [ 00 00 00 00 00 00 ];
478 rx-clock-name = "none";
479 tx-clock-name = "clk17";
480 pio-handle = <&pio2>;
481 phy-handle = <&qe_phy1>;
482 phy-connection-type = "rgmii-id";
486 device_type = "network";
487 compatible = "ucc_geth";
489 reg = <0x3200 0x200>;
491 interrupt-parent = <&qeic>;
492 local-mac-address = [ 00 00 00 00 00 00 ];
493 rx-clock-name = "none";
494 tx-clock-name = "clk17";
495 pio-handle = <&pio4>;
496 phy-handle = <&qe_phy3>;
497 phy-connection-type = "rgmii-id";
501 #address-cells = <1>;
503 compatible = "fsl,qe-muram", "fsl,cpm-muram";
504 ranges = <0x0 0x10000 0x20000>;
507 compatible = "fsl,qe-muram-data",
508 "fsl,cpm-muram-data";
516 pci1: pcie@e000a000 {
517 compatible = "fsl,mpc8548-pcie";
519 #interrupt-cells = <1>;
521 #address-cells = <3>;
522 reg = <0xe000a000 0x1000>;
523 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
525 /* IDSEL 0x0 (PEX) */
526 00000 0x0 0x0 0x1 &mpic 0x0 0x1
527 00000 0x0 0x0 0x2 &mpic 0x1 0x1
528 00000 0x0 0x0 0x3 &mpic 0x2 0x1
529 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
531 interrupt-parent = <&mpic>;
534 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
535 0x1000000 0x0 0x00000000 0xe2800000 0x0 0x00800000>;
536 clock-frequency = <33333333>;
538 reg = <0x0 0x0 0x0 0x0 0x0>;
540 #address-cells = <3>;
542 ranges = <0x2000000 0x0 0xa0000000
543 0x2000000 0x0 0xa0000000
552 rio0: rapidio@e00c00000 {
553 #address-cells = <2>;
555 compatible = "fsl,mpc8569-rapidio", "fsl,rapidio-delta";
556 reg = <0xe00c0000 0x20000>;
557 ranges = <0x0 0x0 0xc0000000 0x0 0x20000000>;
558 interrupts = <48 2 /* error */
565 interrupt-parent = <&mpic>;