oprofile: op_model_athlon.c support for AMD family 10h barcelona performance counters
[linux-2.6] / arch / x86 / oprofile / op_model_athlon.c
1 /**
2  * @file op_model_athlon.h
3  * athlon / K7 / K8 / Family 10h model-specific MSR operations
4  *
5  * @remark Copyright 2002 OProfile authors
6  * @remark Read the file COPYING
7  *
8  * @author John Levon
9  * @author Philippe Elie
10  * @author Graydon Hoare
11  */
12
13 #include <linux/oprofile.h>
14 #include <asm/ptrace.h>
15 #include <asm/msr.h>
16 #include <asm/nmi.h>
17  
18 #include "op_x86_model.h"
19 #include "op_counter.h"
20
21 #define NUM_COUNTERS 4
22 #define NUM_CONTROLS 4
23
24 #define CTR_IS_RESERVED(msrs,c) (msrs->counters[(c)].addr ? 1 : 0)
25 #define CTR_READ(l,h,msrs,c) do {rdmsr(msrs->counters[(c)].addr, (l), (h));} while (0)
26 #define CTR_WRITE(l,msrs,c) do {wrmsr(msrs->counters[(c)].addr, -(unsigned int)(l), -1);} while (0)
27 #define CTR_OVERFLOWED(n) (!((n) & (1U<<31)))
28
29 #define CTRL_IS_RESERVED(msrs,c) (msrs->controls[(c)].addr ? 1 : 0)
30 #define CTRL_READ(l,h,msrs,c) do {rdmsr(msrs->controls[(c)].addr, (l), (h));} while (0)
31 #define CTRL_WRITE(l,h,msrs,c) do {wrmsr(msrs->controls[(c)].addr, (l), (h));} while (0)
32 #define CTRL_SET_ACTIVE(n) (n |= (1<<22))
33 #define CTRL_SET_INACTIVE(n) (n &= ~(1<<22))
34 #define CTRL_CLEAR_LO(x) (x &= (1<<21))
35 #define CTRL_CLEAR_HI(x) (x &= 0xfffffcf0)
36 #define CTRL_SET_ENABLE(val) (val |= 1<<20)
37 #define CTRL_SET_USR(val,u) (val |= ((u & 1) << 16))
38 #define CTRL_SET_KERN(val,k) (val |= ((k & 1) << 17))
39 #define CTRL_SET_UM(val, m) (val |= (m << 8))
40 #define CTRL_SET_EVENT_LOW(val, e) (val |= (e & 0xff))
41 #define CTRL_SET_EVENT_HIGH(val, e) (val |= ((e >> 8) & 0xf))
42 #define CTRL_SET_HOST_ONLY(val, h) (val |= ((h & 1) << 9))
43 #define CTRL_SET_GUEST_ONLY(val, h) (val |= ((h & 1) << 8))
44
45 static unsigned long reset_value[NUM_COUNTERS];
46  
47 static void athlon_fill_in_addresses(struct op_msrs * const msrs)
48 {
49         int i;
50
51         for (i=0; i < NUM_COUNTERS; i++) {
52                 if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
53                         msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
54                 else
55                         msrs->counters[i].addr = 0;
56         }
57
58         for (i=0; i < NUM_CONTROLS; i++) {
59                 if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i))
60                         msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
61                 else
62                         msrs->controls[i].addr = 0;
63         }
64 }
65
66  
67 static void athlon_setup_ctrs(struct op_msrs const * const msrs)
68 {
69         unsigned int low, high;
70         int i;
71  
72         /* clear all counters */
73         for (i = 0 ; i < NUM_CONTROLS; ++i) {
74                 if (unlikely(!CTRL_IS_RESERVED(msrs,i)))
75                         continue;
76                 CTRL_READ(low, high, msrs, i);
77                 CTRL_CLEAR_LO(low);
78                 CTRL_CLEAR_HI(high);
79                 CTRL_WRITE(low, high, msrs, i);
80         }
81
82         /* avoid a false detection of ctr overflows in NMI handler */
83         for (i = 0; i < NUM_COUNTERS; ++i) {
84                 if (unlikely(!CTR_IS_RESERVED(msrs,i)))
85                         continue;
86                 CTR_WRITE(1, msrs, i);
87         }
88
89         /* enable active counters */
90         for (i = 0; i < NUM_COUNTERS; ++i) {
91                 if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs,i))) {
92                         reset_value[i] = counter_config[i].count;
93
94                         CTR_WRITE(counter_config[i].count, msrs, i);
95
96                         CTRL_READ(low, high, msrs, i);
97                         CTRL_CLEAR_LO(low);
98                         CTRL_CLEAR_HI(high);
99                         CTRL_SET_ENABLE(low);
100                         CTRL_SET_USR(low, counter_config[i].user);
101                         CTRL_SET_KERN(low, counter_config[i].kernel);
102                         CTRL_SET_UM(low, counter_config[i].unit_mask);
103                         CTRL_SET_EVENT_LOW(low, counter_config[i].event);
104                         CTRL_SET_EVENT_HIGH(high, counter_config[i].event);
105                         CTRL_SET_HOST_ONLY(high, 0);
106                         CTRL_SET_GUEST_ONLY(high, 0);
107
108                         CTRL_WRITE(low, high, msrs, i);
109                 } else {
110                         reset_value[i] = 0;
111                 }
112         }
113 }
114
115  
116 static int athlon_check_ctrs(struct pt_regs * const regs,
117                              struct op_msrs const * const msrs)
118 {
119         unsigned int low, high;
120         int i;
121
122         for (i = 0 ; i < NUM_COUNTERS; ++i) {
123                 if (!reset_value[i])
124                         continue;
125                 CTR_READ(low, high, msrs, i);
126                 if (CTR_OVERFLOWED(low)) {
127                         oprofile_add_sample(regs, i);
128                         CTR_WRITE(reset_value[i], msrs, i);
129                 }
130         }
131
132         /* See op_model_ppro.c */
133         return 1;
134 }
135
136  
137 static void athlon_start(struct op_msrs const * const msrs)
138 {
139         unsigned int low, high;
140         int i;
141         for (i = 0 ; i < NUM_COUNTERS ; ++i) {
142                 if (reset_value[i]) {
143                         CTRL_READ(low, high, msrs, i);
144                         CTRL_SET_ACTIVE(low);
145                         CTRL_WRITE(low, high, msrs, i);
146                 }
147         }
148 }
149
150
151 static void athlon_stop(struct op_msrs const * const msrs)
152 {
153         unsigned int low,high;
154         int i;
155
156         /* Subtle: stop on all counters to avoid race with
157          * setting our pm callback */
158         for (i = 0 ; i < NUM_COUNTERS ; ++i) {
159                 if (!reset_value[i])
160                         continue;
161                 CTRL_READ(low, high, msrs, i);
162                 CTRL_SET_INACTIVE(low);
163                 CTRL_WRITE(low, high, msrs, i);
164         }
165 }
166
167 static void athlon_shutdown(struct op_msrs const * const msrs)
168 {
169         int i;
170
171         for (i = 0 ; i < NUM_COUNTERS ; ++i) {
172                 if (CTR_IS_RESERVED(msrs,i))
173                         release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
174         }
175         for (i = 0 ; i < NUM_CONTROLS ; ++i) {
176                 if (CTRL_IS_RESERVED(msrs,i))
177                         release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
178         }
179 }
180
181 struct op_x86_model_spec const op_athlon_spec = {
182         .num_counters = NUM_COUNTERS,
183         .num_controls = NUM_CONTROLS,
184         .fill_in_addresses = &athlon_fill_in_addresses,
185         .setup_ctrs = &athlon_setup_ctrs,
186         .check_ctrs = &athlon_check_ctrs,
187         .start = &athlon_start,
188         .stop = &athlon_stop,
189         .shutdown = &athlon_shutdown
190 };