git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "ath9k.h"
  21 #include "initvals.h"
  22
  23 static int btcoex_enable;
  24 module_param(btcoex_enable, bool, 0);
  25 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
  26
  27 #define ATH9K_CLOCK_RATE_CCK            22
  28 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  29 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  30
  31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  32 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
  33                               enum ath9k_ht_macmode macmode);
  34 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
  35                               struct ar5416_eeprom_def *pEepData,
  36                               u32 reg, u32 value);
  37 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  38 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  39
  40 /********************/
  41 /* Helper Functions */
  42 /********************/
  43
  44 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
  45 {
  46         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  47
  48         if (!ah->curchan) /* should really check for CCK instead */
  49                 return clks / ATH9K_CLOCK_RATE_CCK;
  50         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  51                 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
  52
  53         return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
  54 }
  55
  56 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
  57 {
  58         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  59
  60         if (conf_is_ht40(conf))
  61                 return ath9k_hw_mac_usec(ah, clks) / 2;
  62         else
  63                 return ath9k_hw_mac_usec(ah, clks);
  64 }
  65
  66 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  67 {
  68         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  69
  70         if (!ah->curchan) /* should really check for CCK instead */
  71                 return usecs *ATH9K_CLOCK_RATE_CCK;
  72         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  73                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  74         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  75 }
  76
  77 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
  78 {
  79         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  80
  81         if (conf_is_ht40(conf))
  82                 return ath9k_hw_mac_clks(ah, usecs) * 2;
  83         else
  84                 return ath9k_hw_mac_clks(ah, usecs);
  85 }
  86
  87 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
  88 {
  89         int i;
  90
  91         BUG_ON(timeout < AH_TIME_QUANTUM);
  92
  93         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
  94                 if ((REG_READ(ah, reg) & mask) == val)
  95                         return true;
  96
  97                 udelay(AH_TIME_QUANTUM);
  98         }
  99
 100         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 101                 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 102                 timeout, reg, REG_READ(ah, reg), mask, val);
 103
 104         return false;
 105 }
 106
 107 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 108 {
 109         u32 retval;
 110         int i;
 111
 112         for (i = 0, retval = 0; i < n; i++) {
 113                 retval = (retval << 1) | (val & 1);
 114                 val >>= 1;
 115         }
 116         return retval;
 117 }
 118
 119 bool ath9k_get_channel_edges(struct ath_hw *ah,
 120                              u16 flags, u16 *low,
 121                              u16 *high)
 122 {
 123         struct ath9k_hw_capabilities *pCap = &ah->caps;
 124
 125         if (flags & CHANNEL_5GHZ) {
 126                 *low = pCap->low_5ghz_chan;
 127                 *high = pCap->high_5ghz_chan;
 128                 return true;
 129         }
 130         if ((flags & CHANNEL_2GHZ)) {
 131                 *low = pCap->low_2ghz_chan;
 132                 *high = pCap->high_2ghz_chan;
 133                 return true;
 134         }
 135         return false;
 136 }
 137
 138 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 139                            struct ath_rate_table *rates,
 140                            u32 frameLen, u16 rateix,
 141                            bool shortPreamble)
 142 {
 143         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 144         u32 kbps;
 145
 146         kbps = rates->info[rateix].ratekbps;
 147
 148         if (kbps == 0)
 149                 return 0;
 150
 151         switch (rates->info[rateix].phy) {
 152         case WLAN_RC_PHY_CCK:
 153                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 154                 if (shortPreamble && rates->info[rateix].short_preamble)
 155                         phyTime >>= 1;
 156                 numBits = frameLen << 3;
 157                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 158                 break;
 159         case WLAN_RC_PHY_OFDM:
 160                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 161                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 162                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 163                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 164                         txTime = OFDM_SIFS_TIME_QUARTER
 165                                 + OFDM_PREAMBLE_TIME_QUARTER
 166                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 167                 } else if (ah->curchan &&
 168                            IS_CHAN_HALF_RATE(ah->curchan)) {
 169                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 170                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 171                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 172                         txTime = OFDM_SIFS_TIME_HALF +
 173                                 OFDM_PREAMBLE_TIME_HALF
 174                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 175                 } else {
 176                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 177                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 178                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 179                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 180                                 + (numSymbols * OFDM_SYMBOL_TIME);
 181                 }
 182                 break;
 183         default:
 184                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 185                         "Unknown phy %u (rate ix %u)\n",
 186                         rates->info[rateix].phy, rateix);
 187                 txTime = 0;
 188                 break;
 189         }
 190
 191         return txTime;
 192 }
 193
 194 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 195                                   struct ath9k_channel *chan,
 196                                   struct chan_centers *centers)
 197 {
 198         int8_t extoff;
 199
 200         if (!IS_CHAN_HT40(chan)) {
 201                 centers->ctl_center = centers->ext_center =
 202                         centers->synth_center = chan->channel;
 203                 return;
 204         }
 205
 206         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 207             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 208                 centers->synth_center =
 209                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 210                 extoff = 1;
 211         } else {
 212                 centers->synth_center =
 213                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 214                 extoff = -1;
 215         }
 216
 217         centers->ctl_center =
 218                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 219         centers->ext_center =
 220                 centers->synth_center + (extoff *
 221                          ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
 222                           HT40_CHANNEL_CENTER_SHIFT : 15));
 223 }
 224
 225 /******************/
 226 /* Chip Revisions */
 227 /******************/
 228
 229 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 230 {
 231         u32 val;
 232
 233         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 234
 235         if (val == 0xFF) {
 236                 val = REG_READ(ah, AR_SREV);
 237                 ah->hw_version.macVersion =
 238                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 239                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 240                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 241         } else {
 242                 if (!AR_SREV_9100(ah))
 243                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 244
 245                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 246
 247                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 248                         ah->is_pciexpress = true;
 249         }
 250 }
 251
 252 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
 253 {
 254         u32 val;
 255         int i;
 256
 257         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 258
 259         for (i = 0; i < 8; i++)
 260                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 261         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 262         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 263
 264         return ath9k_hw_reverse_bits(val, 8);
 265 }
 266
 267 /************************************/
 268 /* HW Attach, Detach, Init Routines */
 269 /************************************/
 270
 271 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 272 {
 273         if (AR_SREV_9100(ah))
 274                 return;
 275
 276         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 277         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 278         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 279         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 280         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 281         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 282         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 283         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 284         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 285
 286         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 287 }
 288
 289 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 290 {
 291         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 292         u32 regHold[2];
 293         u32 patternData[4] = { 0x55555555,
 294                                0xaaaaaaaa,
 295                                0x66666666,
 296                                0x99999999 };
 297         int i, j;
 298
 299         for (i = 0; i < 2; i++) {
 300                 u32 addr = regAddr[i];
 301                 u32 wrData, rdData;
 302
 303                 regHold[i] = REG_READ(ah, addr);
 304                 for (j = 0; j < 0x100; j++) {
 305                         wrData = (j << 16) | j;
 306                         REG_WRITE(ah, addr, wrData);
 307                         rdData = REG_READ(ah, addr);
 308                         if (rdData != wrData) {
 309                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 310                                         "address test failed "
 311                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 312                                         addr, wrData, rdData);
 313                                 return false;
 314                         }
 315                 }
 316                 for (j = 0; j < 4; j++) {
 317                         wrData = patternData[j];
 318                         REG_WRITE(ah, addr, wrData);
 319                         rdData = REG_READ(ah, addr);
 320                         if (wrData != rdData) {
 321                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 322                                         "address test failed "
 323                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 324                                         addr, wrData, rdData);
 325                                 return false;
 326                         }
 327                 }
 328                 REG_WRITE(ah, regAddr[i], regHold[i]);
 329         }
 330         udelay(100);
 331
 332         return true;
 333 }
 334
 335 static const char *ath9k_hw_devname(u16 devid)
 336 {
 337         switch (devid) {
 338         case AR5416_DEVID_PCI:
 339                 return "Atheros 5416";
 340         case AR5416_DEVID_PCIE:
 341                 return "Atheros 5418";
 342         case AR9160_DEVID_PCI:
 343                 return "Atheros 9160";
 344         case AR5416_AR9100_DEVID:
 345                 return "Atheros 9100";
 346         case AR9280_DEVID_PCI:
 347         case AR9280_DEVID_PCIE:
 348                 return "Atheros 9280";
 349         case AR9285_DEVID_PCIE:
 350                 return "Atheros 9285";
 351         }
 352
 353         return NULL;
 354 }
 355
 356 static void ath9k_hw_set_defaults(struct ath_hw *ah)
 357 {
 358         int i;
 359
 360         ah->config.dma_beacon_response_time = 2;
 361         ah->config.sw_beacon_response_time = 10;
 362         ah->config.additional_swba_backoff = 0;
 363         ah->config.ack_6mb = 0x0;
 364         ah->config.cwm_ignore_extcca = 0;
 365         ah->config.pcie_powersave_enable = 0;
 366         ah->config.pcie_clock_req = 0;
 367         ah->config.pcie_waen = 0;
 368         ah->config.analog_shiftreg = 1;
 369         ah->config.ht_enable = 1;
 370         ah->config.ofdm_trig_low = 200;
 371         ah->config.ofdm_trig_high = 500;
 372         ah->config.cck_trig_high = 200;
 373         ah->config.cck_trig_low = 100;
 374         ah->config.enable_ani = 1;
 375         ah->config.diversity_control = 0;
 376         ah->config.antenna_switch_swap = 0;
 377
 378         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 379                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 380                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 381         }
 382
 383         ah->config.intr_mitigation = 1;
 384
 385         /*
 386          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 387          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 388          * This means we use it for all AR5416 devices, and the few
 389          * minor PCI AR9280 devices out there.
 390          *
 391          * Serialization is required because these devices do not handle
 392          * well the case of two concurrent reads/writes due to the latency
 393          * involved. During one read/write another read/write can be issued
 394          * on another CPU while the previous read/write may still be working
 395          * on our hardware, if we hit this case the hardware poops in a loop.
 396          * We prevent this by serializing reads and writes.
 397          *
 398          * This issue is not present on PCI-Express devices or pre-AR5416
 399          * devices (legacy, 802.11abg).
 400          */
 401         if (num_possible_cpus() > 1)
 402                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 403 }
 404
 405 static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc,
 406                                         int *status)
 407 {
 408         struct ath_hw *ah;
 409
 410         ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
 411         if (ah == NULL) {
 412                 DPRINTF(sc, ATH_DBG_FATAL,
 413                         "Cannot allocate memory for state block\n");
 414                 *status = -ENOMEM;
 415                 return NULL;
 416         }
 417
 418         ah->ah_sc = sc;
 419         ah->hw_version.magic = AR5416_MAGIC;
 420         ah->regulatory.country_code = CTRY_DEFAULT;
 421         ah->hw_version.devid = devid;
 422         ah->hw_version.subvendorid = 0;
 423
 424         ah->ah_flags = 0;
 425         if ((devid == AR5416_AR9100_DEVID))
 426                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 427         if (!AR_SREV_9100(ah))
 428                 ah->ah_flags = AH_USE_EEPROM;
 429
 430         ah->regulatory.power_limit = MAX_RATE_POWER;
 431         ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
 432         ah->atim_window = 0;
 433         ah->diversity_control = ah->config.diversity_control;
 434         ah->antenna_switch_swap =
 435                 ah->config.antenna_switch_swap;
 436         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 437         ah->beacon_interval = 100;
 438         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 439         ah->slottime = (u32) -1;
 440         ah->acktimeout = (u32) -1;
 441         ah->ctstimeout = (u32) -1;
 442         ah->globaltxtimeout = (u32) -1;
 443
 444         ah->gbeacon_rate = 0;
 445
 446         return ah;
 447 }
 448
 449 static int ath9k_hw_rfattach(struct ath_hw *ah)
 450 {
 451         bool rfStatus = false;
 452         int ecode = 0;
 453
 454         rfStatus = ath9k_hw_init_rf(ah, &ecode);
 455         if (!rfStatus) {
 456                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 457                         "RF setup failed, status %u\n", ecode);
 458                 return ecode;
 459         }
 460
 461         return 0;
 462 }
 463
 464 static int ath9k_hw_rf_claim(struct ath_hw *ah)
 465 {
 466         u32 val;
 467
 468         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 469
 470         val = ath9k_hw_get_radiorev(ah);
 471         switch (val & AR_RADIO_SREV_MAJOR) {
 472         case 0:
 473                 val = AR_RAD5133_SREV_MAJOR;
 474                 break;
 475         case AR_RAD5133_SREV_MAJOR:
 476         case AR_RAD5122_SREV_MAJOR:
 477         case AR_RAD2133_SREV_MAJOR:
 478         case AR_RAD2122_SREV_MAJOR:
 479                 break;
 480         default:
 481                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
 482                         "5G Radio Chip Rev 0x%02X is not "
 483                         "supported by this driver\n",
 484                         ah->hw_version.analog5GhzRev);
 485                 return -EOPNOTSUPP;
 486         }
 487
 488         ah->hw_version.analog5GhzRev = val;
 489
 490         return 0;
 491 }
 492
 493 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 494 {
 495         u32 sum;
 496         int i;
 497         u16 eeval;
 498
 499         sum = 0;
 500         for (i = 0; i < 3; i++) {
 501                 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
 502                 sum += eeval;
 503                 ah->macaddr[2 * i] = eeval >> 8;
 504                 ah->macaddr[2 * i + 1] = eeval & 0xff;
 505         }
 506         if (sum == 0 || sum == 0xffff * 3) {
 507                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 508                         "mac address read failed: %pM\n",
 509                         ah->macaddr);
 510                 return -EADDRNOTAVAIL;
 511         }
 512
 513         return 0;
 514 }
 515
 516 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
 517 {
 518         u32 rxgain_type;
 519
 520         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 521                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
 522
 523                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 524                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 525                         ar9280Modes_backoff_13db_rxgain_9280_2,
 526                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 527                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 528                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 529                         ar9280Modes_backoff_23db_rxgain_9280_2,
 530                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 531                 else
 532                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 533                         ar9280Modes_original_rxgain_9280_2,
 534                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 535         } else {
 536                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 537                         ar9280Modes_original_rxgain_9280_2,
 538                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 539         }
 540 }
 541
 542 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
 543 {
 544         u32 txgain_type;
 545
 546         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 547                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 548
 549                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 550                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 551                         ar9280Modes_high_power_tx_gain_9280_2,
 552                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 553                 else
 554                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 555                         ar9280Modes_original_tx_gain_9280_2,
 556                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 557         } else {
 558                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 559                 ar9280Modes_original_tx_gain_9280_2,
 560                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 561         }
 562 }
 563
 564 static int ath9k_hw_post_attach(struct ath_hw *ah)
 565 {
 566         int ecode;
 567
 568         if (!ath9k_hw_chip_test(ah)) {
 569                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 570                         "hardware self-test failed\n");
 571                 return -ENODEV;
 572         }
 573
 574         ecode = ath9k_hw_rf_claim(ah);
 575         if (ecode != 0)
 576                 return ecode;
 577
 578         ecode = ath9k_hw_eeprom_attach(ah);
 579         if (ecode != 0)
 580                 return ecode;
 581
 582         DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
 583                 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
 584
 585         ecode = ath9k_hw_rfattach(ah);
 586         if (ecode != 0)
 587                 return ecode;
 588
 589         if (!AR_SREV_9100(ah)) {
 590                 ath9k_hw_ani_setup(ah);
 591                 ath9k_hw_ani_attach(ah);
 592         }
 593
 594         return 0;
 595 }
 596
 597 static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
 598                                          int *status)
 599 {
 600         struct ath_hw *ah;
 601         int ecode;
 602         u32 i, j;
 603
 604         ah = ath9k_hw_newstate(devid, sc, status);
 605         if (ah == NULL)
 606                 return NULL;
 607
 608         ath9k_hw_set_defaults(ah);
 609
 610         if (ah->config.intr_mitigation != 0)
 611                 ah->intr_mitigation = true;
 612
 613         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 614                 DPRINTF(sc, ATH_DBG_RESET, "Couldn't reset chip\n");
 615                 ecode = -EIO;
 616                 goto bad;
 617         }
 618
 619         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 620                 DPRINTF(sc, ATH_DBG_RESET, "Couldn't wakeup chip\n");
 621                 ecode = -EIO;
 622                 goto bad;
 623         }
 624
 625         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 626                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 627                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
 628                         ah->config.serialize_regmode =
 629                                 SER_REG_MODE_ON;
 630                 } else {
 631                         ah->config.serialize_regmode =
 632                                 SER_REG_MODE_OFF;
 633                 }
 634         }
 635
 636         DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
 637                 ah->config.serialize_regmode);
 638
 639         if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) &&
 640             (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) &&
 641             (ah->hw_version.macVersion != AR_SREV_VERSION_9160) &&
 642             (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
 643                 DPRINTF(sc, ATH_DBG_RESET,
 644                         "Mac Chip Rev 0x%02x.%x is not supported by "
 645                         "this driver\n", ah->hw_version.macVersion,
 646                         ah->hw_version.macRev);
 647                 ecode = -EOPNOTSUPP;
 648                 goto bad;
 649         }
 650
 651         if (AR_SREV_9100(ah)) {
 652                 ah->iq_caldata.calData = &iq_cal_multi_sample;
 653                 ah->supp_cals = IQ_MISMATCH_CAL;
 654                 ah->is_pciexpress = false;
 655         }
 656         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 657
 658         if (AR_SREV_9160_10_OR_LATER(ah)) {
 659                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 660                         ah->iq_caldata.calData = &iq_cal_single_sample;
 661                         ah->adcgain_caldata.calData =
 662                                 &adc_gain_cal_single_sample;
 663                         ah->adcdc_caldata.calData =
 664                                 &adc_dc_cal_single_sample;
 665                         ah->adcdc_calinitdata.calData =
 666                                 &adc_init_dc_cal;
 667                 } else {
 668                         ah->iq_caldata.calData = &iq_cal_multi_sample;
 669                         ah->adcgain_caldata.calData =
 670                                 &adc_gain_cal_multi_sample;
 671                         ah->adcdc_caldata.calData =
 672                                 &adc_dc_cal_multi_sample;
 673                         ah->adcdc_calinitdata.calData =
 674                                 &adc_init_dc_cal;
 675                 }
 676                 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 677         }
 678
 679         ah->ani_function = ATH9K_ANI_ALL;
 680         if (AR_SREV_9280_10_OR_LATER(ah))
 681                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 682
 683         DPRINTF(sc, ATH_DBG_RESET,
 684                 "This Mac Chip Rev 0x%02x.%x is \n",
 685                 ah->hw_version.macVersion, ah->hw_version.macRev);
 686
 687         if (AR_SREV_9285_12_OR_LATER(ah)) {
 688
 689                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
 690                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 691                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
 692                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 693
 694                 if (ah->config.pcie_clock_req) {
 695                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 696                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 697                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 698                 } else {
 699                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 700                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 701                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 702                                   2);
 703                 }
 704         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 705                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
 706                                ARRAY_SIZE(ar9285Modes_9285), 6);
 707                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
 708                                ARRAY_SIZE(ar9285Common_9285), 2);
 709
 710                 if (ah->config.pcie_clock_req) {
 711                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 712                         ar9285PciePhy_clkreq_off_L1_9285,
 713                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 714                 } else {
 715                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 716                         ar9285PciePhy_clkreq_always_on_L1_9285,
 717                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 718                 }
 719         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 720                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
 721                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 722                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
 723                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 724
 725                 if (ah->config.pcie_clock_req) {
 726                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 727                                ar9280PciePhy_clkreq_off_L1_9280,
 728                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 729                 } else {
 730                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 731                                ar9280PciePhy_clkreq_always_on_L1_9280,
 732                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 733                 }
 734                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 735                                ar9280Modes_fast_clock_9280_2,
 736                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 737         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 738                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
 739                                ARRAY_SIZE(ar9280Modes_9280), 6);
 740                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
 741                                ARRAY_SIZE(ar9280Common_9280), 2);
 742         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 743                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
 744                                ARRAY_SIZE(ar5416Modes_9160), 6);
 745                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
 746                                ARRAY_SIZE(ar5416Common_9160), 2);
 747                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
 748                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 749                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
 750                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 751                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
 752                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 753                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
 754                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 755                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
 756                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 757                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
 758                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 759                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
 760                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 761                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
 762                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 763                 if (AR_SREV_9160_11(ah)) {
 764                         INIT_INI_ARRAY(&ah->iniAddac,
 765                                        ar5416Addac_91601_1,
 766                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 767                 } else {
 768                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
 769                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 770                 }
 771         } else if (AR_SREV_9100_OR_LATER(ah)) {
 772                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
 773                                ARRAY_SIZE(ar5416Modes_9100), 6);
 774                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
 775                                ARRAY_SIZE(ar5416Common_9100), 2);
 776                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
 777                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 778                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
 779                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 780                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
 781                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 782                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
 783                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 784                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
 785                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 786                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
 787                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 788                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
 789                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 790                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
 791                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 792                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
 793                                ARRAY_SIZE(ar5416Addac_9100), 2);
 794         } else {
 795                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
 796                                ARRAY_SIZE(ar5416Modes), 6);
 797                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
 798                                ARRAY_SIZE(ar5416Common), 2);
 799                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
 800                                ARRAY_SIZE(ar5416Bank0), 2);
 801                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
 802                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 803                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
 804                                ARRAY_SIZE(ar5416Bank1), 2);
 805                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
 806                                ARRAY_SIZE(ar5416Bank2), 2);
 807                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
 808                                ARRAY_SIZE(ar5416Bank3), 3);
 809                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
 810                                ARRAY_SIZE(ar5416Bank6), 3);
 811                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
 812                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 813                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
 814                                ARRAY_SIZE(ar5416Bank7), 2);
 815                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
 816                                ARRAY_SIZE(ar5416Addac), 2);
 817         }
 818
 819         if (ah->is_pciexpress)
 820                 ath9k_hw_configpcipowersave(ah, 0);
 821         else
 822                 ath9k_hw_disablepcie(ah);
 823
 824         ecode = ath9k_hw_post_attach(ah);
 825         if (ecode != 0)
 826                 goto bad;
 827
 828         if (AR_SREV_9285_12_OR_LATER(ah)) {
 829                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 830
 831                 /* txgain table */
 832                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
 833                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 834                         ar9285Modes_high_power_tx_gain_9285_1_2,
 835                         ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
 836                 } else {
 837                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 838                         ar9285Modes_original_tx_gain_9285_1_2,
 839                         ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
 840                 }
 841
 842         }
 843
 844         /* rxgain table */
 845         if (AR_SREV_9280_20(ah))
 846                 ath9k_hw_init_rxgain_ini(ah);
 847
 848         /* txgain table */
 849         if (AR_SREV_9280_20(ah))
 850                 ath9k_hw_init_txgain_ini(ah);
 851
 852         if (!ath9k_hw_fill_cap_info(ah)) {
 853                 DPRINTF(sc, ATH_DBG_RESET, "failed ath9k_hw_fill_cap_info\n");
 854                 ecode = -EINVAL;
 855                 goto bad;
 856         }
 857
 858         if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
 859             test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
 860
 861                 /* EEPROM Fixup */
 862                 for (i = 0; i < ah->iniModes.ia_rows; i++) {
 863                         u32 reg = INI_RA(&ah->iniModes, i, 0);
 864
 865                         for (j = 1; j < ah->iniModes.ia_columns; j++) {
 866                                 u32 val = INI_RA(&ah->iniModes, i, j);
 867
 868                                 INI_RA(&ah->iniModes, i, j) =
 869                                         ath9k_hw_ini_fixup(ah,
 870                                                            &ah->eeprom.def,
 871                                                            reg, val);
 872                         }
 873                 }
 874         }
 875
 876         ecode = ath9k_hw_init_macaddr(ah);
 877         if (ecode != 0) {
 878                 DPRINTF(sc, ATH_DBG_RESET,
 879                         "failed initializing mac address\n");
 880                 goto bad;
 881         }
 882
 883         if (AR_SREV_9285(ah))
 884                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 885         else
 886                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 887
 888         ath9k_init_nfcal_hist_buffer(ah);
 889
 890         return ah;
 891 bad:
 892         if (ah)
 893                 ath9k_hw_detach(ah);
 894         if (status)
 895                 *status = ecode;
 896
 897         return NULL;
 898 }
 899
 900 static void ath9k_hw_init_bb(struct ath_hw *ah,
 901                              struct ath9k_channel *chan)
 902 {
 903         u32 synthDelay;
 904
 905         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 906         if (IS_CHAN_B(chan))
 907                 synthDelay = (4 * synthDelay) / 22;
 908         else
 909                 synthDelay /= 10;
 910
 911         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 912
 913         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 914 }
 915
 916 static void ath9k_hw_init_qos(struct ath_hw *ah)
 917 {
 918         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 919         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 920
 921         REG_WRITE(ah, AR_QOS_NO_ACK,
 922                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 923                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 924                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 925
 926         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 927         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 928         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 929         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 930         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 931 }
 932
 933 static void ath9k_hw_init_pll(struct ath_hw *ah,
 934                               struct ath9k_channel *chan)
 935 {
 936         u32 pll;
 937
 938         if (AR_SREV_9100(ah)) {
 939                 if (chan && IS_CHAN_5GHZ(chan))
 940                         pll = 0x1450;
 941                 else
 942                         pll = 0x1458;
 943         } else {
 944                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 945                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
 946
 947                         if (chan && IS_CHAN_HALF_RATE(chan))
 948                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
 949                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 950                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
 951
 952                         if (chan && IS_CHAN_5GHZ(chan)) {
 953                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
 954
 955
 956                                 if (AR_SREV_9280_20(ah)) {
 957                                         if (((chan->channel % 20) == 0)
 958                                             || ((chan->channel % 10) == 0))
 959                                                 pll = 0x2850;
 960                                         else
 961                                                 pll = 0x142c;
 962                                 }
 963                         } else {
 964                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
 965                         }
 966
 967                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 968
 969                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
 970
 971                         if (chan && IS_CHAN_HALF_RATE(chan))
 972                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
 973                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 974                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
 975
 976                         if (chan && IS_CHAN_5GHZ(chan))
 977                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
 978                         else
 979                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
 980                 } else {
 981                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
 982
 983                         if (chan && IS_CHAN_HALF_RATE(chan))
 984                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
 985                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 986                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
 987
 988                         if (chan && IS_CHAN_5GHZ(chan))
 989                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
 990                         else
 991                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
 992                 }
 993         }
 994         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
 995
 996         udelay(RTC_PLL_SETTLE_DELAY);
 997
 998         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
 999 }
1000
1001 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1002 {
1003         int rx_chainmask, tx_chainmask;
1004
1005         rx_chainmask = ah->rxchainmask;
1006         tx_chainmask = ah->txchainmask;
1007
1008         switch (rx_chainmask) {
1009         case 0x5:
1010                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1011                             AR_PHY_SWAP_ALT_CHAIN);
1012         case 0x3:
1013                 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1014                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1015                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1016                         break;
1017                 }
1018         case 0x1:
1019         case 0x2:
1020         case 0x7:
1021                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1022                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1023                 break;
1024         default:
1025                 break;
1026         }
1027
1028         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1029         if (tx_chainmask == 0x5) {
1030                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1031                             AR_PHY_SWAP_ALT_CHAIN);
1032         }
1033         if (AR_SREV_9100(ah))
1034                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1035                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1036 }
1037
1038 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1039                                           enum nl80211_iftype opmode)
1040 {
1041         ah->mask_reg = AR_IMR_TXERR |
1042                 AR_IMR_TXURN |
1043                 AR_IMR_RXERR |
1044                 AR_IMR_RXORN |
1045                 AR_IMR_BCNMISC;
1046
1047         if (ah->intr_mitigation)
1048                 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1049         else
1050                 ah->mask_reg |= AR_IMR_RXOK;
1051
1052         ah->mask_reg |= AR_IMR_TXOK;
1053
1054         if (opmode == NL80211_IFTYPE_AP)
1055                 ah->mask_reg |= AR_IMR_MIB;
1056
1057         REG_WRITE(ah, AR_IMR, ah->mask_reg);
1058         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1059
1060         if (!AR_SREV_9100(ah)) {
1061                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1062                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1063                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1064         }
1065 }
1066
1067 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1068 {
1069         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1070                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1071                 ah->acktimeout = (u32) -1;
1072                 return false;
1073         } else {
1074                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1075                               AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1076                 ah->acktimeout = us;
1077                 return true;
1078         }
1079 }
1080
1081 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1082 {
1083         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1084                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1085                 ah->ctstimeout = (u32) -1;
1086                 return false;
1087         } else {
1088                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1089                               AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1090                 ah->ctstimeout = us;
1091                 return true;
1092         }
1093 }
1094
1095 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1096 {
1097         if (tu > 0xFFFF) {
1098                 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1099                         "bad global tx timeout %u\n", tu);
1100                 ah->globaltxtimeout = (u32) -1;
1101                 return false;
1102         } else {
1103                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1104                 ah->globaltxtimeout = tu;
1105                 return true;
1106         }
1107 }
1108
1109 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1110 {
1111         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1112                 ah->misc_mode);
1113
1114         if (ah->misc_mode != 0)
1115                 REG_WRITE(ah, AR_PCU_MISC,
1116                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1117         if (ah->slottime != (u32) -1)
1118                 ath9k_hw_setslottime(ah, ah->slottime);
1119         if (ah->acktimeout != (u32) -1)
1120                 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1121         if (ah->ctstimeout != (u32) -1)
1122                 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1123         if (ah->globaltxtimeout != (u32) -1)
1124                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1125 }
1126
1127 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1128 {
1129         return vendorid == ATHEROS_VENDOR_ID ?
1130                 ath9k_hw_devname(devid) : NULL;
1131 }
1132
1133 void ath9k_hw_detach(struct ath_hw *ah)
1134 {
1135         if (!AR_SREV_9100(ah))
1136                 ath9k_hw_ani_detach(ah);
1137
1138         ath9k_hw_rfdetach(ah);
1139         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1140         kfree(ah);
1141 }
1142
1143 struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error)
1144 {
1145         struct ath_hw *ah = NULL;
1146
1147         switch (devid) {
1148         case AR5416_DEVID_PCI:
1149         case AR5416_DEVID_PCIE:
1150         case AR5416_AR9100_DEVID:
1151         case AR9160_DEVID_PCI:
1152         case AR9280_DEVID_PCI:
1153         case AR9280_DEVID_PCIE:
1154         case AR9285_DEVID_PCIE:
1155                 ah = ath9k_hw_do_attach(devid, sc, error);
1156                 break;
1157         default:
1158                 *error = -ENXIO;
1159                 break;
1160         }
1161
1162         return ah;
1163 }
1164
1165 /*******/
1166 /* INI */
1167 /*******/
1168
1169 static void ath9k_hw_override_ini(struct ath_hw *ah,
1170                                   struct ath9k_channel *chan)
1171 {
1172         /*
1173          * Set the RX_ABORT and RX_DIS and clear if off only after
1174          * RXE is set for MAC. This prevents frames with corrupted
1175          * descriptor status.
1176          */
1177         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1178
1179
1180         if (!AR_SREV_5416_20_OR_LATER(ah) ||
1181             AR_SREV_9280_10_OR_LATER(ah))
1182                 return;
1183
1184         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1185 }
1186
1187 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1188                               struct ar5416_eeprom_def *pEepData,
1189                               u32 reg, u32 value)
1190 {
1191         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1192
1193         switch (ah->hw_version.devid) {
1194         case AR9280_DEVID_PCI:
1195                 if (reg == 0x7894) {
1196                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1197                                 "ini VAL: %x  EEPROM: %x\n", value,
1198                                 (pBase->version & 0xff));
1199
1200                         if ((pBase->version & 0xff) > 0x0a) {
1201                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1202                                         "PWDCLKIND: %d\n",
1203                                         pBase->pwdclkind);
1204                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1205                                 value |= AR_AN_TOP2_PWDCLKIND &
1206                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1207                         } else {
1208                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1209                                         "PWDCLKIND Earlier Rev\n");
1210                         }
1211
1212                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1213                                 "final ini VAL: %x\n", value);
1214                 }
1215                 break;
1216         }
1217
1218         return value;
1219 }
1220
1221 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1222                               struct ar5416_eeprom_def *pEepData,
1223                               u32 reg, u32 value)
1224 {
1225         if (ah->eep_map == EEP_MAP_4KBITS)
1226                 return value;
1227         else
1228                 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1229 }
1230
1231 static void ath9k_olc_init(struct ath_hw *ah)
1232 {
1233         u32 i;
1234
1235         for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1236                 ah->originalGain[i] =
1237                         MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1238                                         AR_PHY_TX_GAIN);
1239         ah->PDADCdelta = 0;
1240 }
1241
1242 static int ath9k_hw_process_ini(struct ath_hw *ah,
1243                                 struct ath9k_channel *chan,
1244                                 enum ath9k_ht_macmode macmode)
1245 {
1246         int i, regWrites = 0;
1247         struct ieee80211_channel *channel = chan->chan;
1248         u32 modesIndex, freqIndex;
1249         int status;
1250
1251         switch (chan->chanmode) {
1252         case CHANNEL_A:
1253         case CHANNEL_A_HT20:
1254                 modesIndex = 1;
1255                 freqIndex = 1;
1256                 break;
1257         case CHANNEL_A_HT40PLUS:
1258         case CHANNEL_A_HT40MINUS:
1259                 modesIndex = 2;
1260                 freqIndex = 1;
1261                 break;
1262         case CHANNEL_G:
1263         case CHANNEL_G_HT20:
1264         case CHANNEL_B:
1265                 modesIndex = 4;
1266                 freqIndex = 2;
1267                 break;
1268         case CHANNEL_G_HT40PLUS:
1269         case CHANNEL_G_HT40MINUS:
1270                 modesIndex = 3;
1271                 freqIndex = 2;
1272                 break;
1273
1274         default:
1275                 return -EINVAL;
1276         }
1277
1278         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1279         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1280         ah->eep_ops->set_addac(ah, chan);
1281
1282         if (AR_SREV_5416_22_OR_LATER(ah)) {
1283                 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1284         } else {
1285                 struct ar5416IniArray temp;
1286                 u32 addacSize =
1287                         sizeof(u32) * ah->iniAddac.ia_rows *
1288                         ah->iniAddac.ia_columns;
1289
1290                 memcpy(ah->addac5416_21,
1291                        ah->iniAddac.ia_array, addacSize);
1292
1293                 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1294
1295                 temp.ia_array = ah->addac5416_21;
1296                 temp.ia_columns = ah->iniAddac.ia_columns;
1297                 temp.ia_rows = ah->iniAddac.ia_rows;
1298                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1299         }
1300
1301         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1302
1303         for (i = 0; i < ah->iniModes.ia_rows; i++) {
1304                 u32 reg = INI_RA(&ah->iniModes, i, 0);
1305                 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1306
1307                 REG_WRITE(ah, reg, val);
1308
1309                 if (reg >= 0x7800 && reg < 0x78a0
1310                     && ah->config.analog_shiftreg) {
1311                         udelay(100);
1312                 }
1313
1314                 DO_DELAY(regWrites);
1315         }
1316
1317         if (AR_SREV_9280(ah))
1318                 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1319
1320         if (AR_SREV_9280(ah) || (AR_SREV_9285(ah) &&
1321             AR_SREV_9285_12_OR_LATER(ah)))
1322                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1323
1324         for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1325                 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1326                 u32 val = INI_RA(&ah->iniCommon, i, 1);
1327
1328                 REG_WRITE(ah, reg, val);
1329
1330                 if (reg >= 0x7800 && reg < 0x78a0
1331                     && ah->config.analog_shiftreg) {
1332                         udelay(100);
1333                 }
1334
1335                 DO_DELAY(regWrites);
1336         }
1337
1338         ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1339
1340         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1341                 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1342                                 regWrites);
1343         }
1344
1345         ath9k_hw_override_ini(ah, chan);
1346         ath9k_hw_set_regs(ah, chan, macmode);
1347         ath9k_hw_init_chain_masks(ah);
1348
1349         if (OLC_FOR_AR9280_20_LATER)
1350                 ath9k_olc_init(ah);
1351
1352         status = ah->eep_ops->set_txpower(ah, chan,
1353                                   ath9k_regd_get_ctl(ah, chan),
1354                                   channel->max_antenna_gain * 2,
1355                                   channel->max_power * 2,
1356                                   min((u32) MAX_RATE_POWER,
1357                                       (u32) ah->regulatory.power_limit));
1358         if (status != 0) {
1359                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1360                         "error init'ing transmit power\n");
1361                 return -EIO;
1362         }
1363
1364         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1365                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1366                         "ar5416SetRfRegs failed\n");
1367                 return -EIO;
1368         }
1369
1370         return 0;
1371 }
1372
1373 /****************************************/
1374 /* Reset and Channel Switching Routines */
1375 /****************************************/
1376
1377 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1378 {
1379         u32 rfMode = 0;
1380
1381         if (chan == NULL)
1382                 return;
1383
1384         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1385                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1386
1387         if (!AR_SREV_9280_10_OR_LATER(ah))
1388                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1389                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1390
1391         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1392                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1393
1394         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1395 }
1396
1397 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1398 {
1399         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1400 }
1401
1402 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1403 {
1404         u32 regval;
1405
1406         regval = REG_READ(ah, AR_AHB_MODE);
1407         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1408
1409         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1410         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1411
1412         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1413
1414         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1415         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1416
1417         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1418
1419         if (AR_SREV_9285(ah)) {
1420                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1421                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1422         } else {
1423                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1424                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1425         }
1426 }
1427
1428 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1429 {
1430         u32 val;
1431
1432         val = REG_READ(ah, AR_STA_ID1);
1433         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1434         switch (opmode) {
1435         case NL80211_IFTYPE_AP:
1436                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1437                           | AR_STA_ID1_KSRCH_MODE);
1438                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1439                 break;
1440         case NL80211_IFTYPE_ADHOC:
1441         case NL80211_IFTYPE_MESH_POINT:
1442                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1443                           | AR_STA_ID1_KSRCH_MODE);
1444                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1445                 break;
1446         case NL80211_IFTYPE_STATION:
1447         case NL80211_IFTYPE_MONITOR:
1448                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1449                 break;
1450         }
1451 }
1452
1453 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1454                                                  u32 coef_scaled,
1455                                                  u32 *coef_mantissa,
1456                                                  u32 *coef_exponent)
1457 {
1458         u32 coef_exp, coef_man;
1459
1460         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1461                 if ((coef_scaled >> coef_exp) & 0x1)
1462                         break;
1463
1464         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1465
1466         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1467
1468         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1469         *coef_exponent = coef_exp - 16;
1470 }
1471
1472 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1473                                      struct ath9k_channel *chan)
1474 {
1475         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1476         u32 clockMhzScaled = 0x64000000;
1477         struct chan_centers centers;
1478
1479         if (IS_CHAN_HALF_RATE(chan))
1480                 clockMhzScaled = clockMhzScaled >> 1;
1481         else if (IS_CHAN_QUARTER_RATE(chan))
1482                 clockMhzScaled = clockMhzScaled >> 2;
1483
1484         ath9k_hw_get_channel_centers(ah, chan, &centers);
1485         coef_scaled = clockMhzScaled / centers.synth_center;
1486
1487         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1488                                       &ds_coef_exp);
1489
1490         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1491                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1492         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1493                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1494
1495         coef_scaled = (9 * coef_scaled) / 10;
1496
1497         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1498                                       &ds_coef_exp);
1499
1500         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1501                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1502         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1503                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1504 }
1505
1506 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1507 {
1508         u32 rst_flags;
1509         u32 tmpReg;
1510
1511         if (AR_SREV_9100(ah)) {
1512                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1513                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1514                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1515                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1516                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1517         }
1518
1519         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1520                   AR_RTC_FORCE_WAKE_ON_INT);
1521
1522         if (AR_SREV_9100(ah)) {
1523                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1524                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1525         } else {
1526                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1527                 if (tmpReg &
1528                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1529                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1530                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1531                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1532                 } else {
1533                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1534                 }
1535
1536                 rst_flags = AR_RTC_RC_MAC_WARM;
1537                 if (type == ATH9K_RESET_COLD)
1538                         rst_flags |= AR_RTC_RC_MAC_COLD;
1539         }
1540
1541         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1542         udelay(50);
1543
1544         REG_WRITE(ah, AR_RTC_RC, 0);
1545         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1546                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1547                         "RTC stuck in MAC reset\n");
1548                 return false;
1549         }
1550
1551         if (!AR_SREV_9100(ah))
1552                 REG_WRITE(ah, AR_RC, 0);
1553
1554         ath9k_hw_init_pll(ah, NULL);
1555
1556         if (AR_SREV_9100(ah))
1557                 udelay(50);
1558
1559         return true;
1560 }
1561
1562 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1563 {
1564         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1565                   AR_RTC_FORCE_WAKE_ON_INT);
1566
1567         REG_WRITE(ah, AR_RTC_RESET, 0);
1568         udelay(2);
1569         REG_WRITE(ah, AR_RTC_RESET, 1);
1570
1571         if (!ath9k_hw_wait(ah,
1572                            AR_RTC_STATUS,
1573                            AR_RTC_STATUS_M,
1574                            AR_RTC_STATUS_ON,
1575                            AH_WAIT_TIMEOUT)) {
1576                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1577                 return false;
1578         }
1579
1580         ath9k_hw_read_revisions(ah);
1581
1582         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1583 }
1584
1585 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1586 {
1587         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1588                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1589
1590         switch (type) {
1591         case ATH9K_RESET_POWER_ON:
1592                 return ath9k_hw_set_reset_power_on(ah);
1593                 break;
1594         case ATH9K_RESET_WARM:
1595         case ATH9K_RESET_COLD:
1596                 return ath9k_hw_set_reset(ah, type);
1597                 break;
1598         default:
1599                 return false;
1600         }
1601 }
1602
1603 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1604                               enum ath9k_ht_macmode macmode)
1605 {
1606         u32 phymode;
1607         u32 enableDacFifo = 0;
1608
1609         if (AR_SREV_9285_10_OR_LATER(ah))
1610                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1611                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1612
1613         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1614                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1615
1616         if (IS_CHAN_HT40(chan)) {
1617                 phymode |= AR_PHY_FC_DYN2040_EN;
1618
1619                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1620                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1621                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1622
1623                 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1624                         phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1625         }
1626         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1627
1628         ath9k_hw_set11nmac2040(ah, macmode);
1629
1630         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1631         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1632 }
1633
1634 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1635                                 struct ath9k_channel *chan)
1636 {
1637         if (OLC_FOR_AR9280_20_LATER) {
1638                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1639                         return false;
1640         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1641                 return false;
1642
1643         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1644                 return false;
1645
1646         ah->chip_fullsleep = false;
1647         ath9k_hw_init_pll(ah, chan);
1648         ath9k_hw_set_rfmode(ah, chan);
1649
1650         return true;
1651 }
1652
1653 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1654                                     struct ath9k_channel *chan,
1655                                     enum ath9k_ht_macmode macmode)
1656 {
1657         struct ieee80211_channel *channel = chan->chan;
1658         u32 synthDelay, qnum;
1659
1660         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1661                 if (ath9k_hw_numtxpending(ah, qnum)) {
1662                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1663                                 "Transmit frames pending on queue %d\n", qnum);
1664                         return false;
1665                 }
1666         }
1667
1668         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1669         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1670                            AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1671                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1672                         "Could not kill baseband RX\n");
1673                 return false;
1674         }
1675
1676         ath9k_hw_set_regs(ah, chan, macmode);
1677
1678         if (AR_SREV_9280_10_OR_LATER(ah)) {
1679                 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1680                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1681                                 "failed to set channel\n");
1682                         return false;
1683                 }
1684         } else {
1685                 if (!(ath9k_hw_set_channel(ah, chan))) {
1686                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1687                                 "failed to set channel\n");
1688                         return false;
1689                 }
1690         }
1691
1692         if (ah->eep_ops->set_txpower(ah, chan,
1693                              ath9k_regd_get_ctl(ah, chan),
1694                              channel->max_antenna_gain * 2,
1695                              channel->max_power * 2,
1696                              min((u32) MAX_RATE_POWER,
1697                                  (u32) ah->regulatory.power_limit)) != 0) {
1698                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1699                         "error init'ing transmit power\n");
1700                 return false;
1701         }
1702
1703         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1704         if (IS_CHAN_B(chan))
1705                 synthDelay = (4 * synthDelay) / 22;
1706         else
1707                 synthDelay /= 10;
1708
1709         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1710
1711         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1712
1713         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1714                 ath9k_hw_set_delta_slope(ah, chan);
1715
1716         if (AR_SREV_9280_10_OR_LATER(ah))
1717                 ath9k_hw_9280_spur_mitigate(ah, chan);
1718         else
1719                 ath9k_hw_spur_mitigate(ah, chan);
1720
1721         if (!chan->oneTimeCalsDone)
1722                 chan->oneTimeCalsDone = true;
1723
1724         return true;
1725 }
1726
1727 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1728 {
1729         int bb_spur = AR_NO_SPUR;
1730         int freq;
1731         int bin, cur_bin;
1732         int bb_spur_off, spur_subchannel_sd;
1733         int spur_freq_sd;
1734         int spur_delta_phase;
1735         int denominator;
1736         int upper, lower, cur_vit_mask;
1737         int tmp, newVal;
1738         int i;
1739         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1740                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1741         };
1742         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1743                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1744         };
1745         int inc[4] = { 0, 100, 0, 0 };
1746         struct chan_centers centers;
1747
1748         int8_t mask_m[123];
1749         int8_t mask_p[123];
1750         int8_t mask_amt;
1751         int tmp_mask;
1752         int cur_bb_spur;
1753         bool is2GHz = IS_CHAN_2GHZ(chan);
1754
1755         memset(&mask_m, 0, sizeof(int8_t) * 123);
1756         memset(&mask_p, 0, sizeof(int8_t) * 123);
1757
1758         ath9k_hw_get_channel_centers(ah, chan, &centers);
1759         freq = centers.synth_center;
1760
1761         ah->config.spurmode = SPUR_ENABLE_EEPROM;
1762         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1763                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1764
1765                 if (is2GHz)
1766                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1767                 else
1768                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1769
1770                 if (AR_NO_SPUR == cur_bb_spur)
1771                         break;
1772                 cur_bb_spur = cur_bb_spur - freq;
1773
1774                 if (IS_CHAN_HT40(chan)) {
1775                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1776                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1777                                 bb_spur = cur_bb_spur;
1778                                 break;
1779                         }
1780                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1781                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1782                         bb_spur = cur_bb_spur;
1783                         break;
1784                 }
1785         }
1786
1787         if (AR_NO_SPUR == bb_spur) {
1788                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1789                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1790                 return;
1791         } else {
1792                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1793                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1794         }
1795
1796         bin = bb_spur * 320;
1797
1798         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1799
1800         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1801                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1802                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1803                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1804         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1805
1806         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1807                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1808                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1809                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1810                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1811         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1812
1813         if (IS_CHAN_HT40(chan)) {
1814                 if (bb_spur < 0) {
1815                         spur_subchannel_sd = 1;
1816                         bb_spur_off = bb_spur + 10;
1817                 } else {
1818                         spur_subchannel_sd = 0;
1819                         bb_spur_off = bb_spur - 10;
1820                 }
1821         } else {
1822                 spur_subchannel_sd = 0;
1823                 bb_spur_off = bb_spur;
1824         }
1825
1826         if (IS_CHAN_HT40(chan))
1827                 spur_delta_phase =
1828                         ((bb_spur * 262144) /
1829                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1830         else
1831                 spur_delta_phase =
1832                         ((bb_spur * 524288) /
1833                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1834
1835         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1836         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1837
1838         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1839                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1840                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1841         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1842
1843         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1844         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1845
1846         cur_bin = -6000;
1847         upper = bin + 100;
1848         lower = bin - 100;
1849
1850         for (i = 0; i < 4; i++) {
1851                 int pilot_mask = 0;
1852                 int chan_mask = 0;
1853                 int bp = 0;
1854                 for (bp = 0; bp < 30; bp++) {
1855                         if ((cur_bin > lower) && (cur_bin < upper)) {
1856                                 pilot_mask = pilot_mask | 0x1 << bp;
1857                                 chan_mask = chan_mask | 0x1 << bp;
1858                         }
1859                         cur_bin += 100;
1860                 }
1861                 cur_bin += inc[i];
1862                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1863                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1864         }
1865
1866         cur_vit_mask = 6100;
1867         upper = bin + 120;
1868         lower = bin - 120;
1869
1870         for (i = 0; i < 123; i++) {
1871                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1872
1873                         /* workaround for gcc bug #37014 */
1874                         volatile int tmp_v = abs(cur_vit_mask - bin);
1875
1876                         if (tmp_v < 75)
1877                                 mask_amt = 1;
1878                         else
1879                                 mask_amt = 0;
1880                         if (cur_vit_mask < 0)
1881                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1882                         else
1883                                 mask_p[cur_vit_mask / 100] = mask_amt;
1884                 }
1885                 cur_vit_mask -= 100;
1886         }
1887
1888         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1889                 | (mask_m[48] << 26) | (mask_m[49] << 24)
1890                 | (mask_m[50] << 22) | (mask_m[51] << 20)
1891                 | (mask_m[52] << 18) | (mask_m[53] << 16)
1892                 | (mask_m[54] << 14) | (mask_m[55] << 12)
1893                 | (mask_m[56] << 10) | (mask_m[57] << 8)
1894                 | (mask_m[58] << 6) | (mask_m[59] << 4)
1895                 | (mask_m[60] << 2) | (mask_m[61] << 0);
1896         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1897         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1898
1899         tmp_mask = (mask_m[31] << 28)
1900                 | (mask_m[32] << 26) | (mask_m[33] << 24)
1901                 | (mask_m[34] << 22) | (mask_m[35] << 20)
1902                 | (mask_m[36] << 18) | (mask_m[37] << 16)
1903                 | (mask_m[48] << 14) | (mask_m[39] << 12)
1904                 | (mask_m[40] << 10) | (mask_m[41] << 8)
1905                 | (mask_m[42] << 6) | (mask_m[43] << 4)
1906                 | (mask_m[44] << 2) | (mask_m[45] << 0);
1907         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1908         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1909
1910         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1911                 | (mask_m[18] << 26) | (mask_m[18] << 24)
1912                 | (mask_m[20] << 22) | (mask_m[20] << 20)
1913                 | (mask_m[22] << 18) | (mask_m[22] << 16)
1914                 | (mask_m[24] << 14) | (mask_m[24] << 12)
1915                 | (mask_m[25] << 10) | (mask_m[26] << 8)
1916                 | (mask_m[27] << 6) | (mask_m[28] << 4)
1917                 | (mask_m[29] << 2) | (mask_m[30] << 0);
1918         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1919         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1920
1921         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1922                 | (mask_m[2] << 26) | (mask_m[3] << 24)
1923                 | (mask_m[4] << 22) | (mask_m[5] << 20)
1924                 | (mask_m[6] << 18) | (mask_m[7] << 16)
1925                 | (mask_m[8] << 14) | (mask_m[9] << 12)
1926                 | (mask_m[10] << 10) | (mask_m[11] << 8)
1927                 | (mask_m[12] << 6) | (mask_m[13] << 4)
1928                 | (mask_m[14] << 2) | (mask_m[15] << 0);
1929         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1930         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1931
1932         tmp_mask = (mask_p[15] << 28)
1933                 | (mask_p[14] << 26) | (mask_p[13] << 24)
1934                 | (mask_p[12] << 22) | (mask_p[11] << 20)
1935                 | (mask_p[10] << 18) | (mask_p[9] << 16)
1936                 | (mask_p[8] << 14) | (mask_p[7] << 12)
1937                 | (mask_p[6] << 10) | (mask_p[5] << 8)
1938                 | (mask_p[4] << 6) | (mask_p[3] << 4)
1939                 | (mask_p[2] << 2) | (mask_p[1] << 0);
1940         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1941         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1942
1943         tmp_mask = (mask_p[30] << 28)
1944                 | (mask_p[29] << 26) | (mask_p[28] << 24)
1945                 | (mask_p[27] << 22) | (mask_p[26] << 20)
1946                 | (mask_p[25] << 18) | (mask_p[24] << 16)
1947                 | (mask_p[23] << 14) | (mask_p[22] << 12)
1948                 | (mask_p[21] << 10) | (mask_p[20] << 8)
1949                 | (mask_p[19] << 6) | (mask_p[18] << 4)
1950                 | (mask_p[17] << 2) | (mask_p[16] << 0);
1951         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1952         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1953
1954         tmp_mask = (mask_p[45] << 28)
1955                 | (mask_p[44] << 26) | (mask_p[43] << 24)
1956                 | (mask_p[42] << 22) | (mask_p[41] << 20)
1957                 | (mask_p[40] << 18) | (mask_p[39] << 16)
1958                 | (mask_p[38] << 14) | (mask_p[37] << 12)
1959                 | (mask_p[36] << 10) | (mask_p[35] << 8)
1960                 | (mask_p[34] << 6) | (mask_p[33] << 4)
1961                 | (mask_p[32] << 2) | (mask_p[31] << 0);
1962         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1963         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1964
1965         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1966                 | (mask_p[59] << 26) | (mask_p[58] << 24)
1967                 | (mask_p[57] << 22) | (mask_p[56] << 20)
1968                 | (mask_p[55] << 18) | (mask_p[54] << 16)
1969                 | (mask_p[53] << 14) | (mask_p[52] << 12)
1970                 | (mask_p[51] << 10) | (mask_p[50] << 8)
1971                 | (mask_p[49] << 6) | (mask_p[48] << 4)
1972                 | (mask_p[47] << 2) | (mask_p[46] << 0);
1973         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1974         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1975 }
1976
1977 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1978 {
1979         int bb_spur = AR_NO_SPUR;
1980         int bin, cur_bin;
1981         int spur_freq_sd;
1982         int spur_delta_phase;
1983         int denominator;
1984         int upper, lower, cur_vit_mask;
1985         int tmp, new;
1986         int i;
1987         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1988                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1989         };
1990         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1991                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1992         };
1993         int inc[4] = { 0, 100, 0, 0 };
1994
1995         int8_t mask_m[123];
1996         int8_t mask_p[123];
1997         int8_t mask_amt;
1998         int tmp_mask;
1999         int cur_bb_spur;
2000         bool is2GHz = IS_CHAN_2GHZ(chan);
2001
2002         memset(&mask_m, 0, sizeof(int8_t) * 123);
2003         memset(&mask_p, 0, sizeof(int8_t) * 123);
2004
2005         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2006                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2007                 if (AR_NO_SPUR == cur_bb_spur)
2008                         break;
2009                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2010                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2011                         bb_spur = cur_bb_spur;
2012                         break;
2013                 }
2014         }
2015
2016         if (AR_NO_SPUR == bb_spur)
2017                 return;
2018
2019         bin = bb_spur * 32;
2020
2021         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2022         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2023                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2024                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2025                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2026
2027         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2028
2029         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2030                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2031                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2032                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2033                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2034         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2035
2036         spur_delta_phase = ((bb_spur * 524288) / 100) &
2037                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2038
2039         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2040         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2041
2042         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2043                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2044                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2045         REG_WRITE(ah, AR_PHY_TIMING11, new);
2046
2047         cur_bin = -6000;
2048         upper = bin + 100;
2049         lower = bin - 100;
2050
2051         for (i = 0; i < 4; i++) {
2052                 int pilot_mask = 0;
2053                 int chan_mask = 0;
2054                 int bp = 0;
2055                 for (bp = 0; bp < 30; bp++) {
2056                         if ((cur_bin > lower) && (cur_bin < upper)) {
2057                                 pilot_mask = pilot_mask | 0x1 << bp;
2058                                 chan_mask = chan_mask | 0x1 << bp;
2059                         }
2060                         cur_bin += 100;
2061                 }
2062                 cur_bin += inc[i];
2063                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2064                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2065         }
2066
2067         cur_vit_mask = 6100;
2068         upper = bin + 120;
2069         lower = bin - 120;
2070
2071         for (i = 0; i < 123; i++) {
2072                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2073
2074                         /* workaround for gcc bug #37014 */
2075                         volatile int tmp_v = abs(cur_vit_mask - bin);
2076
2077                         if (tmp_v < 75)
2078                                 mask_amt = 1;
2079                         else
2080                                 mask_amt = 0;
2081                         if (cur_vit_mask < 0)
2082                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2083                         else
2084                                 mask_p[cur_vit_mask / 100] = mask_amt;
2085                 }
2086                 cur_vit_mask -= 100;
2087         }
2088
2089         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2090                 | (mask_m[48] << 26) | (mask_m[49] << 24)
2091                 | (mask_m[50] << 22) | (mask_m[51] << 20)
2092                 | (mask_m[52] << 18) | (mask_m[53] << 16)
2093                 | (mask_m[54] << 14) | (mask_m[55] << 12)
2094                 | (mask_m[56] << 10) | (mask_m[57] << 8)
2095                 | (mask_m[58] << 6) | (mask_m[59] << 4)
2096                 | (mask_m[60] << 2) | (mask_m[61] << 0);
2097         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2098         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2099
2100         tmp_mask = (mask_m[31] << 28)
2101                 | (mask_m[32] << 26) | (mask_m[33] << 24)
2102                 | (mask_m[34] << 22) | (mask_m[35] << 20)
2103                 | (mask_m[36] << 18) | (mask_m[37] << 16)
2104                 | (mask_m[48] << 14) | (mask_m[39] << 12)
2105                 | (mask_m[40] << 10) | (mask_m[41] << 8)
2106                 | (mask_m[42] << 6) | (mask_m[43] << 4)
2107                 | (mask_m[44] << 2) | (mask_m[45] << 0);
2108         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2109         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2110
2111         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2112                 | (mask_m[18] << 26) | (mask_m[18] << 24)
2113                 | (mask_m[20] << 22) | (mask_m[20] << 20)
2114                 | (mask_m[22] << 18) | (mask_m[22] << 16)
2115                 | (mask_m[24] << 14) | (mask_m[24] << 12)
2116                 | (mask_m[25] << 10) | (mask_m[26] << 8)
2117                 | (mask_m[27] << 6) | (mask_m[28] << 4)
2118                 | (mask_m[29] << 2) | (mask_m[30] << 0);
2119         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2120         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2121
2122         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2123                 | (mask_m[2] << 26) | (mask_m[3] << 24)
2124                 | (mask_m[4] << 22) | (mask_m[5] << 20)
2125                 | (mask_m[6] << 18) | (mask_m[7] << 16)
2126                 | (mask_m[8] << 14) | (mask_m[9] << 12)
2127                 | (mask_m[10] << 10) | (mask_m[11] << 8)
2128                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2129                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2130         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2131         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2132
2133         tmp_mask = (mask_p[15] << 28)
2134                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2135                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2136                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2137                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2138                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2139                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2140                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2141         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2142         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2143
2144         tmp_mask = (mask_p[30] << 28)
2145                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2146                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2147                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2148                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2149                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2150                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2151                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2152         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2153         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2154
2155         tmp_mask = (mask_p[45] << 28)
2156                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2157                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2158                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2159                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2160                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2161                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2162                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2163         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2164         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2165
2166         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2167                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2168                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2169                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2170                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2171                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2172                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2173                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2174         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2175         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2176 }
2177
2178 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2179                     bool bChannelChange)
2180 {
2181         u32 saveLedState;
2182         struct ath_softc *sc = ah->ah_sc;
2183         struct ath9k_channel *curchan = ah->curchan;
2184         u32 saveDefAntenna;
2185         u32 macStaId1;
2186         int i, rx_chainmask, r;
2187
2188         ah->extprotspacing = sc->ht_extprotspacing;
2189         ah->txchainmask = sc->tx_chainmask;
2190         ah->rxchainmask = sc->rx_chainmask;
2191
2192         if (AR_SREV_9285(ah)) {
2193                 ah->txchainmask &= 0x1;
2194                 ah->rxchainmask &= 0x1;
2195         } else if (AR_SREV_9280(ah)) {
2196                 ah->txchainmask &= 0x3;
2197                 ah->rxchainmask &= 0x3;
2198         }
2199
2200         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2201                 return -EIO;
2202
2203         if (curchan)
2204                 ath9k_hw_getnf(ah, curchan);
2205
2206         if (bChannelChange &&
2207             (ah->chip_fullsleep != true) &&
2208             (ah->curchan != NULL) &&
2209             (chan->channel != ah->curchan->channel) &&
2210             ((chan->channelFlags & CHANNEL_ALL) ==
2211              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2212             (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2213                                    !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
2214
2215                 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2216                         ath9k_hw_loadnf(ah, ah->curchan);
2217                         ath9k_hw_start_nfcal(ah);
2218                         return 0;
2219                 }
2220         }
2221
2222         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2223         if (saveDefAntenna == 0)
2224                 saveDefAntenna = 1;
2225
2226         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2227
2228         saveLedState = REG_READ(ah, AR_CFG_LED) &
2229                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2230                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2231
2232         ath9k_hw_mark_phy_inactive(ah);
2233
2234         if (!ath9k_hw_chip_reset(ah, chan)) {
2235                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n");
2236                 return -EINVAL;
2237         }
2238
2239         if (AR_SREV_9280_10_OR_LATER(ah))
2240                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2241
2242         r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2243         if (r)
2244                 return r;
2245
2246         /* Setup MFP options for CCMP */
2247         if (AR_SREV_9280_20_OR_LATER(ah)) {
2248                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2249                  * frames when constructing CCMP AAD. */
2250                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2251                               0xc7ff);
2252                 ah->sw_mgmt_crypto = false;
2253         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2254                 /* Disable hardware crypto for management frames */
2255                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2256                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2257                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2258                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2259                 ah->sw_mgmt_crypto = true;
2260         } else
2261                 ah->sw_mgmt_crypto = true;
2262
2263         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2264                 ath9k_hw_set_delta_slope(ah, chan);
2265
2266         if (AR_SREV_9280_10_OR_LATER(ah))
2267                 ath9k_hw_9280_spur_mitigate(ah, chan);
2268         else
2269                 ath9k_hw_spur_mitigate(ah, chan);
2270
2271         ah->eep_ops->set_board_values(ah, chan);
2272
2273         ath9k_hw_decrease_chain_power(ah, chan);
2274
2275         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2276         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2277                   | macStaId1
2278                   | AR_STA_ID1_RTS_USE_DEF
2279                   | (ah->config.
2280                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2281                   | ah->sta_id1_defaults);
2282         ath9k_hw_set_operating_mode(ah, ah->opmode);
2283
2284         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2285         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2286
2287         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2288
2289         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2290         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2291                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2292
2293         REG_WRITE(ah, AR_ISR, ~0);
2294
2295         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2296
2297         if (AR_SREV_9280_10_OR_LATER(ah)) {
2298                 if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
2299                         return -EIO;
2300         } else {
2301                 if (!(ath9k_hw_set_channel(ah, chan)))
2302                         return -EIO;
2303         }
2304
2305         for (i = 0; i < AR_NUM_DCU; i++)
2306                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2307
2308         ah->intr_txqs = 0;
2309         for (i = 0; i < ah->caps.total_queues; i++)
2310                 ath9k_hw_resettxqueue(ah, i);
2311
2312         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2313         ath9k_hw_init_qos(ah);
2314
2315 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2316         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2317                 ath9k_enable_rfkill(ah);
2318 #endif
2319         ath9k_hw_init_user_settings(ah);
2320
2321         REG_WRITE(ah, AR_STA_ID1,
2322                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2323
2324         ath9k_hw_set_dma(ah);
2325
2326         REG_WRITE(ah, AR_OBS, 8);
2327
2328         if (ah->intr_mitigation) {
2329
2330                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2331                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2332         }
2333
2334         ath9k_hw_init_bb(ah, chan);
2335
2336         if (!ath9k_hw_init_cal(ah, chan))
2337                 return -EIO;;
2338
2339         rx_chainmask = ah->rxchainmask;
2340         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2341                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2342                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2343         }
2344
2345         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2346
2347         if (AR_SREV_9100(ah)) {
2348                 u32 mask;
2349                 mask = REG_READ(ah, AR_CFG);
2350                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2351                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2352                                 "CFG Byte Swap Set 0x%x\n", mask);
2353                 } else {
2354                         mask =
2355                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2356                         REG_WRITE(ah, AR_CFG, mask);
2357                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2358                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2359                 }
2360         } else {
2361 #ifdef __BIG_ENDIAN
2362                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2363 #endif
2364         }
2365
2366         return 0;
2367 }
2368
2369 /************************/
2370 /* Key Cache Management */
2371 /************************/
2372
2373 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2374 {
2375         u32 keyType;
2376
2377         if (entry >= ah->caps.keycache_size) {
2378                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2379                         "entry %u out of range\n", entry);
2380                 return false;
2381         }
2382
2383         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2384
2385         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2386         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2387         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2388         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2389         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2390         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2391         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2392         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2393
2394         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2395                 u16 micentry = entry + 64;
2396
2397                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2398                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2399                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2400                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2401
2402         }
2403
2404         if (ah->curchan == NULL)
2405                 return true;
2406
2407         return true;
2408 }
2409
2410 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2411 {
2412         u32 macHi, macLo;
2413
2414         if (entry >= ah->caps.keycache_size) {
2415                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2416                         "entry %u out of range\n", entry);
2417                 return false;
2418         }
2419
2420         if (mac != NULL) {
2421                 macHi = (mac[5] << 8) | mac[4];
2422                 macLo = (mac[3] << 24) |
2423                         (mac[2] << 16) |
2424                         (mac[1] << 8) |
2425                         mac[0];
2426                 macLo >>= 1;
2427                 macLo |= (macHi & 1) << 31;
2428                 macHi >>= 1;
2429         } else {
2430                 macLo = macHi = 0;
2431         }
2432         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2433         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2434
2435         return true;
2436 }
2437
2438 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2439                                  const struct ath9k_keyval *k,
2440                                  const u8 *mac)
2441 {
2442         const struct ath9k_hw_capabilities *pCap = &ah->caps;
2443         u32 key0, key1, key2, key3, key4;
2444         u32 keyType;
2445
2446         if (entry >= pCap->keycache_size) {
2447                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2448                         "entry %u out of range\n", entry);
2449                 return false;
2450         }
2451
2452         switch (k->kv_type) {
2453         case ATH9K_CIPHER_AES_OCB:
2454                 keyType = AR_KEYTABLE_TYPE_AES;
2455                 break;
2456         case ATH9K_CIPHER_AES_CCM:
2457                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2458                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2459                                 "AES-CCM not supported by mac rev 0x%x\n",
2460                                 ah->hw_version.macRev);
2461                         return false;
2462                 }
2463                 keyType = AR_KEYTABLE_TYPE_CCM;
2464                 break;
2465         case ATH9K_CIPHER_TKIP:
2466                 keyType = AR_KEYTABLE_TYPE_TKIP;
2467                 if (ATH9K_IS_MIC_ENABLED(ah)
2468                     && entry + 64 >= pCap->keycache_size) {
2469                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2470                                 "entry %u inappropriate for TKIP\n", entry);
2471                         return false;
2472                 }
2473                 break;
2474         case ATH9K_CIPHER_WEP:
2475                 if (k->kv_len < LEN_WEP40) {
2476                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2477                                 "WEP key length %u too small\n", k->kv_len);
2478                         return false;
2479                 }
2480                 if (k->kv_len <= LEN_WEP40)
2481                         keyType = AR_KEYTABLE_TYPE_40;
2482                 else if (k->kv_len <= LEN_WEP104)
2483                         keyType = AR_KEYTABLE_TYPE_104;
2484                 else
2485                         keyType = AR_KEYTABLE_TYPE_128;
2486                 break;
2487         case ATH9K_CIPHER_CLR:
2488                 keyType = AR_KEYTABLE_TYPE_CLR;
2489                 break;
2490         default:
2491                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2492                         "cipher %u not supported\n", k->kv_type);
2493                 return false;
2494         }
2495
2496         key0 = get_unaligned_le32(k->kv_val + 0);
2497         key1 = get_unaligned_le16(k->kv_val + 4);
2498         key2 = get_unaligned_le32(k->kv_val + 6);
2499         key3 = get_unaligned_le16(k->kv_val + 10);
2500         key4 = get_unaligned_le32(k->kv_val + 12);
2501         if (k->kv_len <= LEN_WEP104)
2502                 key4 &= 0xff;
2503
2504         /*
2505          * Note: Key cache registers access special memory area that requires
2506          * two 32-bit writes to actually update the values in the internal
2507          * memory. Consequently, the exact order and pairs used here must be
2508          * maintained.
2509          */
2510
2511         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2512                 u16 micentry = entry + 64;
2513
2514                 /*
2515                  * Write inverted key[47:0] first to avoid Michael MIC errors
2516                  * on frames that could be sent or received at the same time.
2517                  * The correct key will be written in the end once everything
2518                  * else is ready.
2519                  */
2520                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2521                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2522
2523                 /* Write key[95:48] */
2524                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2525                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2526
2527                 /* Write key[127:96] and key type */
2528                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2529                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2530
2531                 /* Write MAC address for the entry */
2532                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2533
2534                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2535                         /*
2536                          * TKIP uses two key cache entries:
2537                          * Michael MIC TX/RX keys in the same key cache entry
2538                          * (idx = main index + 64):
2539                          * key0 [31:0] = RX key [31:0]
2540                          * key1 [15:0] = TX key [31:16]
2541                          * key1 [31:16] = reserved
2542                          * key2 [31:0] = RX key [63:32]
2543                          * key3 [15:0] = TX key [15:0]
2544                          * key3 [31:16] = reserved
2545                          * key4 [31:0] = TX key [63:32]
2546                          */
2547                         u32 mic0, mic1, mic2, mic3, mic4;
2548
2549                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2550                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2551                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2552                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2553                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2554
2555                         /* Write RX[31:0] and TX[31:16] */
2556                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2557                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2558
2559                         /* Write RX[63:32] and TX[15:0] */
2560                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2561                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2562
2563                         /* Write TX[63:32] and keyType(reserved) */
2564                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2565                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2566                                   AR_KEYTABLE_TYPE_CLR);
2567
2568                 } else {
2569                         /*
2570                          * TKIP uses four key cache entries (two for group
2571                          * keys):
2572                          * Michael MIC TX/RX keys are in different key cache
2573                          * entries (idx = main index + 64 for TX and
2574                          * main index + 32 + 96 for RX):
2575                          * key0 [31:0] = TX/RX MIC key [31:0]
2576                          * key1 [31:0] = reserved
2577                          * key2 [31:0] = TX/RX MIC key [63:32]
2578                          * key3 [31:0] = reserved
2579                          * key4 [31:0] = reserved
2580                          *
2581                          * Upper layer code will call this function separately
2582                          * for TX and RX keys when these registers offsets are
2583                          * used.
2584                          */
2585                         u32 mic0, mic2;
2586
2587                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2588                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2589
2590                         /* Write MIC key[31:0] */
2591                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2592                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2593
2594                         /* Write MIC key[63:32] */
2595                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2596                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2597
2598                         /* Write TX[63:32] and keyType(reserved) */
2599                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2600                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2601                                   AR_KEYTABLE_TYPE_CLR);
2602                 }
2603
2604                 /* MAC address registers are reserved for the MIC entry */
2605                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2606                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2607
2608                 /*
2609                  * Write the correct (un-inverted) key[47:0] last to enable
2610                  * TKIP now that all other registers are set with correct
2611                  * values.
2612                  */
2613                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2614                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2615         } else {
2616                 /* Write key[47:0] */
2617                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2618                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2619
2620                 /* Write key[95:48] */
2621                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2622                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2623
2624                 /* Write key[127:96] and key type */
2625                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2626                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2627
2628                 /* Write MAC address for the entry */
2629                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2630         }
2631
2632         return true;
2633 }
2634
2635 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2636 {
2637         if (entry < ah->caps.keycache_size) {
2638                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2639                 if (val & AR_KEYTABLE_VALID)
2640                         return true;
2641         }
2642         return false;
2643 }
2644
2645 /******************************/
2646 /* Power Management (Chipset) */
2647 /******************************/
2648
2649 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2650 {
2651         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2652         if (setChip) {
2653                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2654                             AR_RTC_FORCE_WAKE_EN);
2655                 if (!AR_SREV_9100(ah))
2656                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2657
2658                 REG_CLR_BIT(ah, (AR_RTC_RESET),
2659                             AR_RTC_RESET_EN);
2660         }
2661 }
2662
2663 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2664 {
2665         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2666         if (setChip) {
2667                 struct ath9k_hw_capabilities *pCap = &ah->caps;
2668
2669                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2670                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2671                                   AR_RTC_FORCE_WAKE_ON_INT);
2672                 } else {
2673                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2674                                     AR_RTC_FORCE_WAKE_EN);
2675                 }
2676         }
2677 }
2678
2679 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2680 {
2681         u32 val;
2682         int i;
2683
2684         if (setChip) {
2685                 if ((REG_READ(ah, AR_RTC_STATUS) &
2686                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2687                         if (ath9k_hw_set_reset_reg(ah,
2688                                            ATH9K_RESET_POWER_ON) != true) {
2689                                 return false;
2690                         }
2691                 }
2692                 if (AR_SREV_9100(ah))
2693                         REG_SET_BIT(ah, AR_RTC_RESET,
2694                                     AR_RTC_RESET_EN);
2695
2696                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2697                             AR_RTC_FORCE_WAKE_EN);
2698                 udelay(50);
2699
2700                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2701                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2702                         if (val == AR_RTC_STATUS_ON)
2703                                 break;
2704                         udelay(50);
2705                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2706                                     AR_RTC_FORCE_WAKE_EN);
2707                 }
2708                 if (i == 0) {
2709                         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2710                                 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2711                         return false;
2712                 }
2713         }
2714
2715         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2716
2717         return true;
2718 }
2719
2720 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2721 {
2722         int status = true, setChip = true;
2723         static const char *modes[] = {
2724                 "AWAKE",
2725                 "FULL-SLEEP",
2726                 "NETWORK SLEEP",
2727                 "UNDEFINED"
2728         };
2729
2730         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
2731                 modes[ah->power_mode], modes[mode],
2732                 setChip ? "set chip " : "");
2733
2734         switch (mode) {
2735         case ATH9K_PM_AWAKE:
2736                 status = ath9k_hw_set_power_awake(ah, setChip);
2737                 break;
2738         case ATH9K_PM_FULL_SLEEP:
2739                 ath9k_set_power_sleep(ah, setChip);
2740                 ah->chip_fullsleep = true;
2741                 break;
2742         case ATH9K_PM_NETWORK_SLEEP:
2743                 ath9k_set_power_network_sleep(ah, setChip);
2744                 break;
2745         default:
2746                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2747                         "Unknown power mode %u\n", mode);
2748                 return false;
2749         }
2750         ah->power_mode = mode;
2751
2752         return status;
2753 }
2754
2755 /*
2756  * Helper for ASPM support.
2757  *
2758  * Disable PLL when in L0s as well as receiver clock when in L1.
2759  * This power saving option must be enabled through the SerDes.
2760  *
2761  * Programming the SerDes must go through the same 288 bit serial shift
2762  * register as the other analog registers.  Hence the 9 writes.
2763  */
2764 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2765 {
2766         u8 i;
2767
2768         if (ah->is_pciexpress != true)
2769                 return;
2770
2771         /* Do not touch SerDes registers */
2772         if (ah->config.pcie_powersave_enable == 2)
2773                 return;
2774
2775         /* Nothing to do on restore for 11N */
2776         if (restore)
2777                 return;
2778
2779         if (AR_SREV_9280_20_OR_LATER(ah)) {
2780                 /*
2781                  * AR9280 2.0 or later chips use SerDes values from the
2782                  * initvals.h initialized depending on chipset during
2783                  * ath9k_hw_do_attach()
2784                  */
2785                 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2786                         REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2787                                   INI_RA(&ah->iniPcieSerdes, i, 1));
2788                 }
2789         } else if (AR_SREV_9280(ah) &&
2790                    (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2791                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2792                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2793
2794                 /* RX shut off when elecidle is asserted */
2795                 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2796                 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2797                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2798
2799                 /* Shut off CLKREQ active in L1 */
2800                 if (ah->config.pcie_clock_req)
2801                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2802                 else
2803                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2804
2805                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2806                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2807                 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2808
2809                 /* Load the new settings */
2810                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2811
2812         } else {
2813                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2814                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2815
2816                 /* RX shut off when elecidle is asserted */
2817                 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2818                 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2819                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2820
2821                 /*
2822                  * Ignore ah->ah_config.pcie_clock_req setting for
2823                  * pre-AR9280 11n
2824                  */
2825                 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2826
2827                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2828                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2829                 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2830
2831                 /* Load the new settings */
2832                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2833         }
2834
2835         udelay(1000);
2836
2837         /* set bit 19 to allow forcing of pcie core into L1 state */
2838         REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2839
2840         /* Several PCIe massages to ensure proper behaviour */
2841         if (ah->config.pcie_waen) {
2842                 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
2843         } else {
2844                 if (AR_SREV_9285(ah))
2845                         REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2846                 /*
2847                  * On AR9280 chips bit 22 of 0x4004 needs to be set to
2848                  * otherwise card may disappear.
2849                  */
2850                 else if (AR_SREV_9280(ah))
2851                         REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2852                 else
2853                         REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2854         }
2855 }
2856
2857 /**********************/
2858 /* Interrupt Handling */
2859 /**********************/
2860
2861 bool ath9k_hw_intrpend(struct ath_hw *ah)
2862 {
2863         u32 host_isr;
2864
2865         if (AR_SREV_9100(ah))
2866                 return true;
2867
2868         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2869         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2870                 return true;
2871
2872         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2873         if ((host_isr & AR_INTR_SYNC_DEFAULT)
2874             && (host_isr != AR_INTR_SPURIOUS))
2875                 return true;
2876
2877         return false;
2878 }
2879
2880 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2881 {
2882         u32 isr = 0;
2883         u32 mask2 = 0;
2884         struct ath9k_hw_capabilities *pCap = &ah->caps;
2885         u32 sync_cause = 0;
2886         bool fatal_int = false;
2887
2888         if (!AR_SREV_9100(ah)) {
2889                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2890                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2891                             == AR_RTC_STATUS_ON) {
2892                                 isr = REG_READ(ah, AR_ISR);
2893                         }
2894                 }
2895
2896                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2897                         AR_INTR_SYNC_DEFAULT;
2898
2899                 *masked = 0;
2900
2901                 if (!isr && !sync_cause)
2902                         return false;
2903         } else {
2904                 *masked = 0;
2905                 isr = REG_READ(ah, AR_ISR);
2906         }
2907
2908         if (isr) {
2909                 if (isr & AR_ISR_BCNMISC) {
2910                         u32 isr2;
2911                         isr2 = REG_READ(ah, AR_ISR_S2);
2912                         if (isr2 & AR_ISR_S2_TIM)
2913                                 mask2 |= ATH9K_INT_TIM;
2914                         if (isr2 & AR_ISR_S2_DTIM)
2915                                 mask2 |= ATH9K_INT_DTIM;
2916                         if (isr2 & AR_ISR_S2_DTIMSYNC)
2917                                 mask2 |= ATH9K_INT_DTIMSYNC;
2918                         if (isr2 & (AR_ISR_S2_CABEND))
2919                                 mask2 |= ATH9K_INT_CABEND;
2920                         if (isr2 & AR_ISR_S2_GTT)
2921                                 mask2 |= ATH9K_INT_GTT;
2922                         if (isr2 & AR_ISR_S2_CST)
2923                                 mask2 |= ATH9K_INT_CST;
2924                         if (isr2 & AR_ISR_S2_TSFOOR)
2925                                 mask2 |= ATH9K_INT_TSFOOR;
2926                 }
2927
2928                 isr = REG_READ(ah, AR_ISR_RAC);
2929                 if (isr == 0xffffffff) {
2930                         *masked = 0;
2931                         return false;
2932                 }
2933
2934                 *masked = isr & ATH9K_INT_COMMON;
2935
2936                 if (ah->intr_mitigation) {
2937                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2938                                 *masked |= ATH9K_INT_RX;
2939                 }
2940
2941                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2942                         *masked |= ATH9K_INT_RX;
2943                 if (isr &
2944                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2945                      AR_ISR_TXEOL)) {
2946                         u32 s0_s, s1_s;
2947
2948                         *masked |= ATH9K_INT_TX;
2949
2950                         s0_s = REG_READ(ah, AR_ISR_S0_S);
2951                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2952                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2953
2954                         s1_s = REG_READ(ah, AR_ISR_S1_S);
2955                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2956                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2957                 }
2958
2959                 if (isr & AR_ISR_RXORN) {
2960                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2961                                 "receive FIFO overrun interrupt\n");
2962                 }
2963
2964                 if (!AR_SREV_9100(ah)) {
2965                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2966                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2967                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
2968                                         *masked |= ATH9K_INT_TIM_TIMER;
2969                         }
2970                 }
2971
2972                 *masked |= mask2;
2973         }
2974
2975         if (AR_SREV_9100(ah))
2976                 return true;
2977
2978         if (sync_cause) {
2979                 fatal_int =
2980                         (sync_cause &
2981                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2982                         ? true : false;
2983
2984                 if (fatal_int) {
2985                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2986                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2987                                         "received PCI FATAL interrupt\n");
2988                         }
2989                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2990                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2991                                         "received PCI PERR interrupt\n");
2992                         }
2993                 }
2994                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2995                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2996                                 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2997                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2998                         REG_WRITE(ah, AR_RC, 0);
2999                         *masked |= ATH9K_INT_FATAL;
3000                 }
3001                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3002                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3003                                 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3004                 }
3005
3006                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3007                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3008         }
3009
3010         return true;
3011 }
3012
3013 enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah)
3014 {
3015         return ah->mask_reg;
3016 }
3017
3018 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3019 {
3020         u32 omask = ah->mask_reg;
3021         u32 mask, mask2;
3022         struct ath9k_hw_capabilities *pCap = &ah->caps;
3023
3024         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3025
3026         if (omask & ATH9K_INT_GLOBAL) {
3027                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
3028                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3029                 (void) REG_READ(ah, AR_IER);
3030                 if (!AR_SREV_9100(ah)) {
3031                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3032                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3033
3034                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3035                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3036                 }
3037         }
3038
3039         mask = ints & ATH9K_INT_COMMON;
3040         mask2 = 0;
3041
3042         if (ints & ATH9K_INT_TX) {
3043                 if (ah->txok_interrupt_mask)
3044                         mask |= AR_IMR_TXOK;
3045                 if (ah->txdesc_interrupt_mask)
3046                         mask |= AR_IMR_TXDESC;
3047                 if (ah->txerr_interrupt_mask)
3048                         mask |= AR_IMR_TXERR;
3049                 if (ah->txeol_interrupt_mask)
3050                         mask |= AR_IMR_TXEOL;
3051         }
3052         if (ints & ATH9K_INT_RX) {
3053                 mask |= AR_IMR_RXERR;
3054                 if (ah->intr_mitigation)
3055                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3056                 else
3057                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3058                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3059                         mask |= AR_IMR_GENTMR;
3060         }
3061
3062         if (ints & (ATH9K_INT_BMISC)) {
3063                 mask |= AR_IMR_BCNMISC;
3064                 if (ints & ATH9K_INT_TIM)
3065                         mask2 |= AR_IMR_S2_TIM;
3066                 if (ints & ATH9K_INT_DTIM)
3067                         mask2 |= AR_IMR_S2_DTIM;
3068                 if (ints & ATH9K_INT_DTIMSYNC)
3069                         mask2 |= AR_IMR_S2_DTIMSYNC;
3070                 if (ints & ATH9K_INT_CABEND)
3071                         mask2 |= AR_IMR_S2_CABEND;
3072                 if (ints & ATH9K_INT_TSFOOR)
3073                         mask2 |= AR_IMR_S2_TSFOOR;
3074         }
3075
3076         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3077                 mask |= AR_IMR_BCNMISC;
3078                 if (ints & ATH9K_INT_GTT)
3079                         mask2 |= AR_IMR_S2_GTT;
3080                 if (ints & ATH9K_INT_CST)
3081                         mask2 |= AR_IMR_S2_CST;
3082         }
3083
3084         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3085         REG_WRITE(ah, AR_IMR, mask);
3086         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3087                                            AR_IMR_S2_DTIM |
3088                                            AR_IMR_S2_DTIMSYNC |
3089                                            AR_IMR_S2_CABEND |
3090                                            AR_IMR_S2_CABTO |
3091                                            AR_IMR_S2_TSFOOR |
3092                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
3093         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3094         ah->mask_reg = ints;
3095
3096         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3097                 if (ints & ATH9K_INT_TIM_TIMER)
3098                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3099                 else
3100                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3101         }
3102
3103         if (ints & ATH9K_INT_GLOBAL) {
3104                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3105                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3106                 if (!AR_SREV_9100(ah)) {
3107                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3108                                   AR_INTR_MAC_IRQ);
3109                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3110
3111
3112                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3113                                   AR_INTR_SYNC_DEFAULT);
3114                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
3115                                   AR_INTR_SYNC_DEFAULT);
3116                 }
3117                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3118                          REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3119         }
3120
3121         return omask;
3122 }
3123
3124 /*******************/
3125 /* Beacon Handling */
3126 /*******************/
3127
3128 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3129 {
3130         int flags = 0;
3131
3132         ah->beacon_interval = beacon_period;
3133
3134         switch (ah->opmode) {
3135         case NL80211_IFTYPE_STATION:
3136         case NL80211_IFTYPE_MONITOR:
3137                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3138                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3139                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3140                 flags |= AR_TBTT_TIMER_EN;
3141                 break;
3142         case NL80211_IFTYPE_ADHOC:
3143         case NL80211_IFTYPE_MESH_POINT:
3144                 REG_SET_BIT(ah, AR_TXCFG,
3145                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3146                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3147                           TU_TO_USEC(next_beacon +
3148                                      (ah->atim_window ? ah->
3149                                       atim_window : 1)));
3150                 flags |= AR_NDP_TIMER_EN;
3151         case NL80211_IFTYPE_AP:
3152                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3153                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3154                           TU_TO_USEC(next_beacon -
3155                                      ah->config.
3156                                      dma_beacon_response_time));
3157                 REG_WRITE(ah, AR_NEXT_SWBA,
3158                           TU_TO_USEC(next_beacon -
3159                                      ah->config.
3160                                      sw_beacon_response_time));
3161                 flags |=
3162                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3163                 break;
3164         default:
3165                 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3166                         "%s: unsupported opmode: %d\n",
3167                         __func__, ah->opmode);
3168                 return;
3169                 break;
3170         }
3171
3172         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3173         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3174         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3175         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3176
3177         beacon_period &= ~ATH9K_BEACON_ENA;
3178         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3179                 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3180                 ath9k_hw_reset_tsf(ah);
3181         }
3182
3183         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3184 }
3185
3186 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3187                                     const struct ath9k_beacon_state *bs)
3188 {
3189         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3190         struct ath9k_hw_capabilities *pCap = &ah->caps;
3191
3192         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3193
3194         REG_WRITE(ah, AR_BEACON_PERIOD,
3195                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3196         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3197                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3198
3199         REG_RMW_FIELD(ah, AR_RSSI_THR,
3200                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3201
3202         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3203
3204         if (bs->bs_sleepduration > beaconintval)
3205                 beaconintval = bs->bs_sleepduration;
3206
3207         dtimperiod = bs->bs_dtimperiod;
3208         if (bs->bs_sleepduration > dtimperiod)
3209                 dtimperiod = bs->bs_sleepduration;
3210
3211         if (beaconintval == dtimperiod)
3212                 nextTbtt = bs->bs_nextdtim;
3213         else
3214                 nextTbtt = bs->bs_nexttbtt;
3215
3216         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3217         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3218         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3219         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3220
3221         REG_WRITE(ah, AR_NEXT_DTIM,
3222                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3223         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3224
3225         REG_WRITE(ah, AR_SLEEP1,
3226                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3227                   | AR_SLEEP1_ASSUME_DTIM);
3228
3229         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3230                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3231         else
3232                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3233
3234         REG_WRITE(ah, AR_SLEEP2,
3235                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3236
3237         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3238         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3239
3240         REG_SET_BIT(ah, AR_TIMER_MODE,
3241                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3242                     AR_DTIM_TIMER_EN);
3243
3244         /* TSF Out of Range Threshold */
3245         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3246 }
3247
3248 /*******************/
3249 /* HW Capabilities */
3250 /*******************/
3251
3252 bool ath9k_hw_fill_cap_info(struct ath_hw *ah)
3253 {
3254         struct ath9k_hw_capabilities *pCap = &ah->caps;
3255         u16 capField = 0, eeval;
3256
3257         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3258         ah->regulatory.current_rd = eeval;
3259
3260         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3261         if (AR_SREV_9285_10_OR_LATER(ah))
3262                 eeval |= AR9285_RDEXT_DEFAULT;
3263         ah->regulatory.current_rd_ext = eeval;
3264
3265         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3266
3267         if (ah->opmode != NL80211_IFTYPE_AP &&
3268             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3269                 if (ah->regulatory.current_rd == 0x64 ||
3270                     ah->regulatory.current_rd == 0x65)
3271                         ah->regulatory.current_rd += 5;
3272                 else if (ah->regulatory.current_rd == 0x41)
3273                         ah->regulatory.current_rd = 0x43;
3274                 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3275                         "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
3276         }
3277
3278         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3279         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3280
3281         if (eeval & AR5416_OPFLAGS_11A) {
3282                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3283                 if (ah->config.ht_enable) {
3284                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3285                                 set_bit(ATH9K_MODE_11NA_HT20,
3286                                         pCap->wireless_modes);
3287                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3288                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3289                                         pCap->wireless_modes);
3290                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3291                                         pCap->wireless_modes);
3292                         }
3293                 }
3294         }
3295
3296         if (eeval & AR5416_OPFLAGS_11G) {
3297                 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3298                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3299                 if (ah->config.ht_enable) {
3300                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3301                                 set_bit(ATH9K_MODE_11NG_HT20,
3302                                         pCap->wireless_modes);
3303                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3304                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3305                                         pCap->wireless_modes);
3306                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3307                                         pCap->wireless_modes);
3308                         }
3309                 }
3310         }
3311
3312         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3313         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3314             !(eeval & AR5416_OPFLAGS_11A))
3315                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3316         else
3317                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3318
3319         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3320                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3321
3322         pCap->low_2ghz_chan = 2312;
3323         pCap->high_2ghz_chan = 2732;
3324
3325         pCap->low_5ghz_chan = 4920;
3326         pCap->high_5ghz_chan = 6100;
3327
3328         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3329         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3330         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3331
3332         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3333         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3334         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3335
3336         if (ah->config.ht_enable)
3337                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3338         else
3339                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3340
3341         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3342         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3343         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3344         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3345
3346         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3347                 pCap->total_queues =
3348                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3349         else
3350                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3351
3352         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3353                 pCap->keycache_size =
3354                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3355         else
3356                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3357
3358         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3359         pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3360
3361         if (AR_SREV_9285_10_OR_LATER(ah))
3362                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3363         else if (AR_SREV_9280_10_OR_LATER(ah))
3364                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3365         else
3366                 pCap->num_gpio_pins = AR_NUM_GPIO;
3367
3368         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3369                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3370                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3371         } else {
3372                 pCap->rts_aggr_limit = (8 * 1024);
3373         }
3374
3375         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3376
3377 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3378         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3379         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3380                 ah->rfkill_gpio =
3381                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3382                 ah->rfkill_polarity =
3383                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3384
3385                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3386         }
3387 #endif
3388
3389         if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3390             (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3391             (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3392             (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3393             (ah->hw_version.macVersion == AR_SREV_VERSION_9280))
3394                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3395         else
3396                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3397
3398         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3399                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3400         else
3401                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3402
3403         if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3404                 pCap->reg_cap =
3405                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3406                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3407                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3408                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3409         } else {
3410                 pCap->reg_cap =
3411                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3412                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3413         }
3414
3415         pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3416
3417         pCap->num_antcfg_5ghz =
3418                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3419         pCap->num_antcfg_2ghz =
3420                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3421
3422         if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3423                 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3424                 ah->btactive_gpio = 6;
3425                 ah->wlanactive_gpio = 5;
3426         }
3427
3428         return true;
3429 }
3430
3431 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3432                             u32 capability, u32 *result)
3433 {
3434         switch (type) {
3435         case ATH9K_CAP_CIPHER:
3436                 switch (capability) {
3437                 case ATH9K_CIPHER_AES_CCM:
3438                 case ATH9K_CIPHER_AES_OCB:
3439                 case ATH9K_CIPHER_TKIP:
3440                 case ATH9K_CIPHER_WEP:
3441                 case ATH9K_CIPHER_MIC:
3442                 case ATH9K_CIPHER_CLR:
3443                         return true;
3444                 default:
3445                         return false;
3446                 }
3447         case ATH9K_CAP_TKIP_MIC:
3448                 switch (capability) {
3449                 case 0:
3450                         return true;
3451                 case 1:
3452                         return (ah->sta_id1_defaults &
3453                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3454                         false;
3455                 }
3456         case ATH9K_CAP_TKIP_SPLIT:
3457                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3458                         false : true;
3459         case ATH9K_CAP_DIVERSITY:
3460                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3461                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3462                         true : false;
3463         case ATH9K_CAP_MCAST_KEYSRCH:
3464                 switch (capability) {
3465                 case 0:
3466                         return true;
3467                 case 1:
3468                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3469                                 return false;
3470                         } else {
3471                                 return (ah->sta_id1_defaults &
3472                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3473                                         false;
3474                         }
3475                 }
3476                 return false;
3477         case ATH9K_CAP_TXPOW:
3478                 switch (capability) {
3479                 case 0:
3480                         return 0;
3481                 case 1:
3482                         *result = ah->regulatory.power_limit;
3483                         return 0;
3484                 case 2:
3485                         *result = ah->regulatory.max_power_level;
3486                         return 0;
3487                 case 3:
3488                         *result = ah->regulatory.tp_scale;
3489                         return 0;
3490                 }
3491                 return false;
3492         case ATH9K_CAP_DS:
3493                 return (AR_SREV_9280_20_OR_LATER(ah) &&
3494                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3495                         ? false : true;
3496         default:
3497                 return false;
3498         }
3499 }
3500
3501 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3502                             u32 capability, u32 setting, int *status)
3503 {
3504         u32 v;
3505
3506         switch (type) {
3507         case ATH9K_CAP_TKIP_MIC:
3508                 if (setting)
3509                         ah->sta_id1_defaults |=
3510                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3511                 else
3512                         ah->sta_id1_defaults &=
3513                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3514                 return true;
3515         case ATH9K_CAP_DIVERSITY:
3516                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3517                 if (setting)
3518                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3519                 else
3520                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3521                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3522                 return true;
3523         case ATH9K_CAP_MCAST_KEYSRCH:
3524                 if (setting)
3525                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3526                 else
3527                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3528                 return true;
3529         default:
3530                 return false;
3531         }
3532 }
3533
3534 /****************************/
3535 /* GPIO / RFKILL / Antennae */
3536 /****************************/
3537
3538 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3539                                          u32 gpio, u32 type)
3540 {
3541         int addr;
3542         u32 gpio_shift, tmp;
3543
3544         if (gpio > 11)
3545                 addr = AR_GPIO_OUTPUT_MUX3;
3546         else if (gpio > 5)
3547                 addr = AR_GPIO_OUTPUT_MUX2;
3548         else
3549                 addr = AR_GPIO_OUTPUT_MUX1;
3550
3551         gpio_shift = (gpio % 6) * 5;
3552
3553         if (AR_SREV_9280_20_OR_LATER(ah)
3554             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3555                 REG_RMW(ah, addr, (type << gpio_shift),
3556                         (0x1f << gpio_shift));
3557         } else {
3558                 tmp = REG_READ(ah, addr);
3559                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3560                 tmp &= ~(0x1f << gpio_shift);
3561                 tmp |= (type << gpio_shift);
3562                 REG_WRITE(ah, addr, tmp);
3563         }
3564 }
3565
3566 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3567 {
3568         u32 gpio_shift;
3569
3570         ASSERT(gpio < ah->caps.num_gpio_pins);
3571
3572         gpio_shift = gpio << 1;
3573
3574         REG_RMW(ah,
3575                 AR_GPIO_OE_OUT,
3576                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3577                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3578 }
3579
3580 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3581 {
3582 #define MS_REG_READ(x, y) \
3583         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3584
3585         if (gpio >= ah->caps.num_gpio_pins)
3586                 return 0xffffffff;
3587
3588         if (AR_SREV_9285_10_OR_LATER(ah))
3589                 return MS_REG_READ(AR9285, gpio) != 0;
3590         else if (AR_SREV_9280_10_OR_LATER(ah))
3591                 return MS_REG_READ(AR928X, gpio) != 0;
3592         else
3593                 return MS_REG_READ(AR, gpio) != 0;
3594 }
3595
3596 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3597                          u32 ah_signal_type)
3598 {
3599         u32 gpio_shift;
3600
3601         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3602
3603         gpio_shift = 2 * gpio;
3604
3605         REG_RMW(ah,
3606                 AR_GPIO_OE_OUT,
3607                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3608                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3609 }
3610
3611 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3612 {
3613         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3614                 AR_GPIO_BIT(gpio));
3615 }
3616
3617 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3618 void ath9k_enable_rfkill(struct ath_hw *ah)
3619 {
3620         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3621                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
3622
3623         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3624                     AR_GPIO_INPUT_MUX2_RFSILENT);
3625
3626         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3627         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3628 }
3629 #endif
3630
3631 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3632 {
3633         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3634 }
3635
3636 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3637 {
3638         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3639 }
3640
3641 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3642                                enum ath9k_ant_setting settings,
3643                                struct ath9k_channel *chan,
3644                                u8 *tx_chainmask,
3645                                u8 *rx_chainmask,
3646                                u8 *antenna_cfgd)
3647 {
3648         static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3649
3650         if (AR_SREV_9280(ah)) {
3651                 if (!tx_chainmask_cfg) {
3652
3653                         tx_chainmask_cfg = *tx_chainmask;
3654                         rx_chainmask_cfg = *rx_chainmask;
3655                 }
3656
3657                 switch (settings) {
3658                 case ATH9K_ANT_FIXED_A:
3659                         *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3660                         *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3661                         *antenna_cfgd = true;
3662                         break;
3663                 case ATH9K_ANT_FIXED_B:
3664                         if (ah->caps.tx_chainmask >
3665                             ATH9K_ANTENNA1_CHAINMASK) {
3666                                 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3667                         }
3668                         *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3669                         *antenna_cfgd = true;
3670                         break;
3671                 case ATH9K_ANT_VARIABLE:
3672                         *tx_chainmask = tx_chainmask_cfg;
3673                         *rx_chainmask = rx_chainmask_cfg;
3674                         *antenna_cfgd = true;
3675                         break;
3676                 default:
3677                         break;
3678                 }
3679         } else {
3680                 ah->diversity_control = settings;
3681         }
3682
3683         return true;
3684 }
3685
3686 /*********************/
3687 /* General Operation */
3688 /*********************/
3689
3690 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3691 {
3692         u32 bits = REG_READ(ah, AR_RX_FILTER);
3693         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3694
3695         if (phybits & AR_PHY_ERR_RADAR)
3696                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3697         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3698                 bits |= ATH9K_RX_FILTER_PHYERR;
3699
3700         return bits;
3701 }
3702
3703 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3704 {
3705         u32 phybits;
3706
3707         REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3708         phybits = 0;
3709         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3710                 phybits |= AR_PHY_ERR_RADAR;
3711         if (bits & ATH9K_RX_FILTER_PHYERR)
3712                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3713         REG_WRITE(ah, AR_PHY_ERR, phybits);
3714
3715         if (phybits)
3716                 REG_WRITE(ah, AR_RXCFG,
3717                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3718         else
3719                 REG_WRITE(ah, AR_RXCFG,
3720                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3721 }
3722
3723 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3724 {
3725         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3726 }
3727
3728 bool ath9k_hw_disable(struct ath_hw *ah)
3729 {
3730         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3731                 return false;
3732
3733         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3734 }
3735
3736 bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3737 {
3738         struct ath9k_channel *chan = ah->curchan;
3739         struct ieee80211_channel *channel = chan->chan;
3740
3741         ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
3742
3743         if (ah->eep_ops->set_txpower(ah, chan,
3744                              ath9k_regd_get_ctl(ah, chan),
3745                              channel->max_antenna_gain * 2,
3746                              channel->max_power * 2,
3747                              min((u32) MAX_RATE_POWER,
3748                                  (u32) ah->regulatory.power_limit)) != 0)
3749                 return false;
3750
3751         return true;
3752 }
3753
3754 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3755 {
3756         memcpy(ah->macaddr, mac, ETH_ALEN);
3757 }
3758
3759 void ath9k_hw_setopmode(struct ath_hw *ah)
3760 {
3761         ath9k_hw_set_operating_mode(ah, ah->opmode);
3762 }
3763
3764 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3765 {
3766         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3767         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3768 }
3769
3770 void ath9k_hw_setbssidmask(struct ath_softc *sc)
3771 {
3772         REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
3773         REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
3774 }
3775
3776 void ath9k_hw_write_associd(struct ath_softc *sc)
3777 {
3778         REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
3779         REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
3780                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3781 }
3782
3783 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3784 {
3785         u64 tsf;
3786
3787         tsf = REG_READ(ah, AR_TSF_U32);
3788         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3789
3790         return tsf;
3791 }
3792
3793 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3794 {
3795         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3796         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3797 }
3798
3799 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3800 {
3801         int count;
3802
3803         count = 0;
3804         while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3805                 count++;
3806                 if (count > 10) {
3807                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3808                                 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3809                         break;
3810                 }
3811                 udelay(10);
3812         }
3813         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3814 }
3815
3816 bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3817 {
3818         if (setting)
3819                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3820         else
3821                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3822
3823         return true;
3824 }
3825
3826 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
3827 {
3828         if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3829                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3830                 ah->slottime = (u32) -1;
3831                 return false;
3832         } else {
3833                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3834                 ah->slottime = us;
3835                 return true;
3836         }
3837 }
3838
3839 void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
3840 {
3841         u32 macmode;
3842
3843         if (mode == ATH9K_HT_MACMODE_2040 &&
3844             !ah->config.cwm_ignore_extcca)
3845                 macmode = AR_2040_JOINED_RX_CLEAR;
3846         else
3847                 macmode = 0;
3848
3849         REG_WRITE(ah, AR_2040_MODE, macmode);
3850 }
3851
3852 /***************************/
3853 /*  Bluetooth Coexistence  */
3854 /***************************/
3855
3856 void ath9k_hw_btcoex_enable(struct ath_hw *ah)
3857 {
3858         /* connect bt_active to baseband */
3859         REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3860                         (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3861                          AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3862
3863         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3864                         AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3865
3866         /* Set input mux for bt_active to gpio pin */
3867         REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3868                         AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3869                         ah->btactive_gpio);
3870
3871         /* Configure the desired gpio port for input */
3872         ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
3873
3874         /* Configure the desired GPIO port for TX_FRAME output */
3875         ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
3876                             AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
3877 }