git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "ath9k.h"
  19
  20 #define ATH_PCI_VERSION "0.1"
  21
  22 static char *dev_info = "ath9k";
  23
  24 MODULE_AUTHOR("Atheros Communications");
  25 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  26 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  27 MODULE_LICENSE("Dual BSD/GPL");
  28
  29 static int modparam_nohwcrypt;
  30 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  31 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
  32
  33 /* We use the hw_value as an index into our private channel structure */
  34
  35 #define CHAN2G(_freq, _idx)  { \
  36         .center_freq = (_freq), \
  37         .hw_value = (_idx), \
  38         .max_power = 30, \
  39 }
  40
  41 #define CHAN5G(_freq, _idx) { \
  42         .band = IEEE80211_BAND_5GHZ, \
  43         .center_freq = (_freq), \
  44         .hw_value = (_idx), \
  45         .max_power = 30, \
  46 }
  47
  48 /* Some 2 GHz radios are actually tunable on 2312-2732
  49  * on 5 MHz steps, we support the channels which we know
  50  * we have calibration data for all cards though to make
  51  * this static */
  52 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
  53         CHAN2G(2412, 0), /* Channel 1 */
  54         CHAN2G(2417, 1), /* Channel 2 */
  55         CHAN2G(2422, 2), /* Channel 3 */
  56         CHAN2G(2427, 3), /* Channel 4 */
  57         CHAN2G(2432, 4), /* Channel 5 */
  58         CHAN2G(2437, 5), /* Channel 6 */
  59         CHAN2G(2442, 6), /* Channel 7 */
  60         CHAN2G(2447, 7), /* Channel 8 */
  61         CHAN2G(2452, 8), /* Channel 9 */
  62         CHAN2G(2457, 9), /* Channel 10 */
  63         CHAN2G(2462, 10), /* Channel 11 */
  64         CHAN2G(2467, 11), /* Channel 12 */
  65         CHAN2G(2472, 12), /* Channel 13 */
  66         CHAN2G(2484, 13), /* Channel 14 */
  67 };
  68
  69 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
  70  * on 5 MHz steps, we support the channels which we know
  71  * we have calibration data for all cards though to make
  72  * this static */
  73 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
  74         /* _We_ call this UNII 1 */
  75         CHAN5G(5180, 14), /* Channel 36 */
  76         CHAN5G(5200, 15), /* Channel 40 */
  77         CHAN5G(5220, 16), /* Channel 44 */
  78         CHAN5G(5240, 17), /* Channel 48 */
  79         /* _We_ call this UNII 2 */
  80         CHAN5G(5260, 18), /* Channel 52 */
  81         CHAN5G(5280, 19), /* Channel 56 */
  82         CHAN5G(5300, 20), /* Channel 60 */
  83         CHAN5G(5320, 21), /* Channel 64 */
  84         /* _We_ call this "Middle band" */
  85         CHAN5G(5500, 22), /* Channel 100 */
  86         CHAN5G(5520, 23), /* Channel 104 */
  87         CHAN5G(5540, 24), /* Channel 108 */
  88         CHAN5G(5560, 25), /* Channel 112 */
  89         CHAN5G(5580, 26), /* Channel 116 */
  90         CHAN5G(5600, 27), /* Channel 120 */
  91         CHAN5G(5620, 28), /* Channel 124 */
  92         CHAN5G(5640, 29), /* Channel 128 */
  93         CHAN5G(5660, 30), /* Channel 132 */
  94         CHAN5G(5680, 31), /* Channel 136 */
  95         CHAN5G(5700, 32), /* Channel 140 */
  96         /* _We_ call this UNII 3 */
  97         CHAN5G(5745, 33), /* Channel 149 */
  98         CHAN5G(5765, 34), /* Channel 153 */
  99         CHAN5G(5785, 35), /* Channel 157 */
 100         CHAN5G(5805, 36), /* Channel 161 */
 101         CHAN5G(5825, 37), /* Channel 165 */
 102 };
 103
 104 static void ath_cache_conf_rate(struct ath_softc *sc,
 105                                 struct ieee80211_conf *conf)
 106 {
 107         switch (conf->channel->band) {
 108         case IEEE80211_BAND_2GHZ:
 109                 if (conf_is_ht20(conf))
 110                         sc->cur_rate_table =
 111                           sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
 112                 else if (conf_is_ht40_minus(conf))
 113                         sc->cur_rate_table =
 114                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
 115                 else if (conf_is_ht40_plus(conf))
 116                         sc->cur_rate_table =
 117                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
 118                 else
 119                         sc->cur_rate_table =
 120                           sc->hw_rate_table[ATH9K_MODE_11G];
 121                 break;
 122         case IEEE80211_BAND_5GHZ:
 123                 if (conf_is_ht20(conf))
 124                         sc->cur_rate_table =
 125                           sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
 126                 else if (conf_is_ht40_minus(conf))
 127                         sc->cur_rate_table =
 128                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
 129                 else if (conf_is_ht40_plus(conf))
 130                         sc->cur_rate_table =
 131                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
 132                 else
 133                         sc->cur_rate_table =
 134                           sc->hw_rate_table[ATH9K_MODE_11A];
 135                 break;
 136         default:
 137                 BUG_ON(1);
 138                 break;
 139         }
 140 }
 141
 142 static void ath_update_txpow(struct ath_softc *sc)
 143 {
 144         struct ath_hw *ah = sc->sc_ah;
 145         u32 txpow;
 146
 147         if (sc->curtxpow != sc->config.txpowlimit) {
 148                 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
 149                 /* read back in case value is clamped */
 150                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
 151                 sc->curtxpow = txpow;
 152         }
 153 }
 154
 155 static u8 parse_mpdudensity(u8 mpdudensity)
 156 {
 157         /*
 158          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
 159          *   0 for no restriction
 160          *   1 for 1/4 us
 161          *   2 for 1/2 us
 162          *   3 for 1 us
 163          *   4 for 2 us
 164          *   5 for 4 us
 165          *   6 for 8 us
 166          *   7 for 16 us
 167          */
 168         switch (mpdudensity) {
 169         case 0:
 170                 return 0;
 171         case 1:
 172         case 2:
 173         case 3:
 174                 /* Our lower layer calculations limit our precision to
 175                    1 microsecond */
 176                 return 1;
 177         case 4:
 178                 return 2;
 179         case 5:
 180                 return 4;
 181         case 6:
 182                 return 8;
 183         case 7:
 184                 return 16;
 185         default:
 186                 return 0;
 187         }
 188 }
 189
 190 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
 191 {
 192         struct ath_rate_table *rate_table = NULL;
 193         struct ieee80211_supported_band *sband;
 194         struct ieee80211_rate *rate;
 195         int i, maxrates;
 196
 197         switch (band) {
 198         case IEEE80211_BAND_2GHZ:
 199                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
 200                 break;
 201         case IEEE80211_BAND_5GHZ:
 202                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
 203                 break;
 204         default:
 205                 break;
 206         }
 207
 208         if (rate_table == NULL)
 209                 return;
 210
 211         sband = &sc->sbands[band];
 212         rate = sc->rates[band];
 213
 214         if (rate_table->rate_cnt > ATH_RATE_MAX)
 215                 maxrates = ATH_RATE_MAX;
 216         else
 217                 maxrates = rate_table->rate_cnt;
 218
 219         for (i = 0; i < maxrates; i++) {
 220                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
 221                 rate[i].hw_value = rate_table->info[i].ratecode;
 222                 if (rate_table->info[i].short_preamble) {
 223                         rate[i].hw_value_short = rate_table->info[i].ratecode |
 224                                 rate_table->info[i].short_preamble;
 225                         rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
 226                 }
 227                 sband->n_bitrates++;
 228
 229                 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
 230                         rate[i].bitrate / 10, rate[i].hw_value);
 231         }
 232 }
 233
 234 /*
 235  * Set/change channels.  If the channel is really being changed, it's done
 236  * by reseting the chip.  To accomplish this we must first cleanup any pending
 237  * DMA, then restart stuff.
 238 */
 239 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
 240                     struct ath9k_channel *hchan)
 241 {
 242         struct ath_hw *ah = sc->sc_ah;
 243         bool fastcc = true, stopped;
 244         struct ieee80211_channel *channel = hw->conf.channel;
 245         int r;
 246
 247         if (sc->sc_flags & SC_OP_INVALID)
 248                 return -EIO;
 249
 250         ath9k_ps_wakeup(sc);
 251
 252         /*
 253          * This is only performed if the channel settings have
 254          * actually changed.
 255          *
 256          * To switch channels clear any pending DMA operations;
 257          * wait long enough for the RX fifo to drain, reset the
 258          * hardware at the new frequency, and then re-enable
 259          * the relevant bits of the h/w.
 260          */
 261         ath9k_hw_set_interrupts(ah, 0);
 262         ath_drain_all_txq(sc, false);
 263         stopped = ath_stoprecv(sc);
 264
 265         /* XXX: do not flush receive queue here. We don't want
 266          * to flush data frames already in queue because of
 267          * changing channel. */
 268
 269         if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
 270                 fastcc = false;
 271
 272         DPRINTF(sc, ATH_DBG_CONFIG,
 273                 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
 274                 sc->sc_ah->curchan->channel,
 275                 channel->center_freq, sc->tx_chan_width);
 276
 277         spin_lock_bh(&sc->sc_resetlock);
 278
 279         r = ath9k_hw_reset(ah, hchan, fastcc);
 280         if (r) {
 281                 DPRINTF(sc, ATH_DBG_FATAL,
 282                         "Unable to reset channel (%u Mhz) "
 283                         "reset status %u\n",
 284                         channel->center_freq, r);
 285                 spin_unlock_bh(&sc->sc_resetlock);
 286                 return r;
 287         }
 288         spin_unlock_bh(&sc->sc_resetlock);
 289
 290         sc->sc_flags &= ~SC_OP_FULL_RESET;
 291
 292         if (ath_startrecv(sc) != 0) {
 293                 DPRINTF(sc, ATH_DBG_FATAL,
 294                         "Unable to restart recv logic\n");
 295                 return -EIO;
 296         }
 297
 298         ath_cache_conf_rate(sc, &hw->conf);
 299         ath_update_txpow(sc);
 300         ath9k_hw_set_interrupts(ah, sc->imask);
 301         ath9k_ps_restore(sc);
 302         return 0;
 303 }
 304
 305 /*
 306  *  This routine performs the periodic noise floor calibration function
 307  *  that is used to adjust and optimize the chip performance.  This
 308  *  takes environmental changes (location, temperature) into account.
 309  *  When the task is complete, it reschedules itself depending on the
 310  *  appropriate interval that was calculated.
 311  */
 312 static void ath_ani_calibrate(unsigned long data)
 313 {
 314         struct ath_softc *sc = (struct ath_softc *)data;
 315         struct ath_hw *ah = sc->sc_ah;
 316         bool longcal = false;
 317         bool shortcal = false;
 318         bool aniflag = false;
 319         unsigned int timestamp = jiffies_to_msecs(jiffies);
 320         u32 cal_interval, short_cal_interval;
 321
 322         short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
 323                 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
 324
 325         /*
 326         * don't calibrate when we're scanning.
 327         * we are most likely not on our home channel.
 328         */
 329         if (sc->sc_flags & SC_OP_SCANNING)
 330                 goto set_timer;
 331
 332         /* Long calibration runs independently of short calibration. */
 333         if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
 334                 longcal = true;
 335                 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
 336                 sc->ani.longcal_timer = timestamp;
 337         }
 338
 339         /* Short calibration applies only while caldone is false */
 340         if (!sc->ani.caldone) {
 341                 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
 342                         shortcal = true;
 343                         DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
 344                         sc->ani.shortcal_timer = timestamp;
 345                         sc->ani.resetcal_timer = timestamp;
 346                 }
 347         } else {
 348                 if ((timestamp - sc->ani.resetcal_timer) >=
 349                     ATH_RESTART_CALINTERVAL) {
 350                         sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
 351                         if (sc->ani.caldone)
 352                                 sc->ani.resetcal_timer = timestamp;
 353                 }
 354         }
 355
 356         /* Verify whether we must check ANI */
 357         if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
 358                 aniflag = true;
 359                 sc->ani.checkani_timer = timestamp;
 360         }
 361
 362         /* Skip all processing if there's nothing to do. */
 363         if (longcal || shortcal || aniflag) {
 364                 /* Call ANI routine if necessary */
 365                 if (aniflag)
 366                         ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
 367
 368                 /* Perform calibration if necessary */
 369                 if (longcal || shortcal) {
 370                         bool iscaldone = false;
 371
 372                         if (ath9k_hw_calibrate(ah, ah->curchan,
 373                                                sc->rx_chainmask, longcal,
 374                                                &iscaldone)) {
 375                                 if (longcal)
 376                                         sc->ani.noise_floor =
 377                                                 ath9k_hw_getchan_noise(ah,
 378                                                                ah->curchan);
 379
 380                                 DPRINTF(sc, ATH_DBG_ANI,
 381                                         "calibrate chan %u/%x nf: %d\n",
 382                                         ah->curchan->channel,
 383                                         ah->curchan->channelFlags,
 384                                         sc->ani.noise_floor);
 385                         } else {
 386                                 DPRINTF(sc, ATH_DBG_ANY,
 387                                         "calibrate chan %u/%x failed\n",
 388                                         ah->curchan->channel,
 389                                         ah->curchan->channelFlags);
 390                         }
 391                         sc->ani.caldone = iscaldone;
 392                 }
 393         }
 394
 395 set_timer:
 396         /*
 397         * Set timer interval based on previous results.
 398         * The interval must be the shortest necessary to satisfy ANI,
 399         * short calibration and long calibration.
 400         */
 401         cal_interval = ATH_LONG_CALINTERVAL;
 402         if (sc->sc_ah->config.enable_ani)
 403                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
 404         if (!sc->ani.caldone)
 405                 cal_interval = min(cal_interval, (u32)short_cal_interval);
 406
 407         mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 408 }
 409
 410 /*
 411  * Update tx/rx chainmask. For legacy association,
 412  * hard code chainmask to 1x1, for 11n association, use
 413  * the chainmask configuration, for bt coexistence, use
 414  * the chainmask configuration even in legacy mode.
 415  */
 416 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 417 {
 418         if (is_ht ||
 419             (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
 420                 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
 421                 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
 422         } else {
 423                 sc->tx_chainmask = 1;
 424                 sc->rx_chainmask = 1;
 425         }
 426
 427         DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
 428                 sc->tx_chainmask, sc->rx_chainmask);
 429 }
 430
 431 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 432 {
 433         struct ath_node *an;
 434
 435         an = (struct ath_node *)sta->drv_priv;
 436
 437         if (sc->sc_flags & SC_OP_TXAGGR)
 438                 ath_tx_node_init(sc, an);
 439
 440         an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
 441                              sta->ht_cap.ampdu_factor);
 442         an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 443 }
 444
 445 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 446 {
 447         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 448
 449         if (sc->sc_flags & SC_OP_TXAGGR)
 450                 ath_tx_node_cleanup(sc, an);
 451 }
 452
 453 static void ath9k_tasklet(unsigned long data)
 454 {
 455         struct ath_softc *sc = (struct ath_softc *)data;
 456         u32 status = sc->intrstatus;
 457
 458         if (status & ATH9K_INT_FATAL) {
 459                 /* need a chip reset */
 460                 ath_reset(sc, false);
 461                 return;
 462         } else {
 463
 464                 if (status &
 465                     (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 466                         spin_lock_bh(&sc->rx.rxflushlock);
 467                         ath_rx_tasklet(sc, 0);
 468                         spin_unlock_bh(&sc->rx.rxflushlock);
 469                 }
 470                 /* XXX: optimize this */
 471                 if (status & ATH9K_INT_TX)
 472                         ath_tx_tasklet(sc);
 473         }
 474
 475         /* re-enable hardware interrupt */
 476         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
 477 }
 478
 479 irqreturn_t ath_isr(int irq, void *dev)
 480 {
 481         struct ath_softc *sc = dev;
 482         struct ath_hw *ah = sc->sc_ah;
 483         enum ath9k_int status;
 484         bool sched = false;
 485
 486         do {
 487                 if (sc->sc_flags & SC_OP_INVALID) {
 488                         /*
 489                          * The hardware is not ready/present, don't
 490                          * touch anything. Note this can happen early
 491                          * on if the IRQ is shared.
 492                          */
 493                         return IRQ_NONE;
 494                 }
 495                 if (!ath9k_hw_intrpend(ah)) {   /* shared irq, not for us */
 496                         return IRQ_NONE;
 497                 }
 498
 499                 /*
 500                  * Figure out the reason(s) for the interrupt.  Note
 501                  * that the hal returns a pseudo-ISR that may include
 502                  * bits we haven't explicitly enabled so we mask the
 503                  * value to insure we only process bits we requested.
 504                  */
 505                 ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 506
 507                 status &= sc->imask;    /* discard unasked-for bits */
 508
 509                 /*
 510                  * If there are no status bits set, then this interrupt was not
 511                  * for me (should have been caught above).
 512                  */
 513                 if (!status)
 514                         return IRQ_NONE;
 515
 516                 sc->intrstatus = status;
 517                 ath9k_ps_wakeup(sc);
 518
 519                 if (status & ATH9K_INT_FATAL) {
 520                         /* need a chip reset */
 521                         sched = true;
 522                 } else if (status & ATH9K_INT_RXORN) {
 523                         /* need a chip reset */
 524                         sched = true;
 525                 } else {
 526                         if (status & ATH9K_INT_SWBA) {
 527                                 /* schedule a tasklet for beacon handling */
 528                                 tasklet_schedule(&sc->bcon_tasklet);
 529                         }
 530                         if (status & ATH9K_INT_RXEOL) {
 531                                 /*
 532                                  * NB: the hardware should re-read the link when
 533                                  *     RXE bit is written, but it doesn't work
 534                                  *     at least on older hardware revs.
 535                                  */
 536                                 sched = true;
 537                         }
 538
 539                         if (status & ATH9K_INT_TXURN)
 540                                 /* bump tx trigger level */
 541                                 ath9k_hw_updatetxtriglevel(ah, true);
 542                         /* XXX: optimize this */
 543                         if (status & ATH9K_INT_RX)
 544                                 sched = true;
 545                         if (status & ATH9K_INT_TX)
 546                                 sched = true;
 547                         if (status & ATH9K_INT_BMISS)
 548                                 sched = true;
 549                         /* carrier sense timeout */
 550                         if (status & ATH9K_INT_CST)
 551                                 sched = true;
 552                         if (status & ATH9K_INT_MIB) {
 553                                 /*
 554                                  * Disable interrupts until we service the MIB
 555                                  * interrupt; otherwise it will continue to
 556                                  * fire.
 557                                  */
 558                                 ath9k_hw_set_interrupts(ah, 0);
 559                                 /*
 560                                  * Let the hal handle the event. We assume
 561                                  * it will clear whatever condition caused
 562                                  * the interrupt.
 563                                  */
 564                                 ath9k_hw_procmibevent(ah, &sc->nodestats);
 565                                 ath9k_hw_set_interrupts(ah, sc->imask);
 566                         }
 567                         if (status & ATH9K_INT_TIM_TIMER) {
 568                                 if (!(ah->caps.hw_caps &
 569                                       ATH9K_HW_CAP_AUTOSLEEP)) {
 570                                         /* Clear RxAbort bit so that we can
 571                                          * receive frames */
 572                                         ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
 573                                         ath9k_hw_setrxabort(ah, 0);
 574                                         sched = true;
 575                                         sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
 576                                 }
 577                         }
 578                         if (status & ATH9K_INT_TSFOOR) {
 579                                 /* FIXME: Handle this interrupt for power save */
 580                                 sched = true;
 581                         }
 582                 }
 583                 ath9k_ps_restore(sc);
 584         } while (0);
 585
 586         ath_debug_stat_interrupt(sc, status);
 587
 588         if (sched) {
 589                 /* turn off every interrupt except SWBA */
 590                 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
 591                 tasklet_schedule(&sc->intr_tq);
 592         }
 593
 594         return IRQ_HANDLED;
 595 }
 596
 597 static u32 ath_get_extchanmode(struct ath_softc *sc,
 598                                struct ieee80211_channel *chan,
 599                                enum nl80211_channel_type channel_type)
 600 {
 601         u32 chanmode = 0;
 602
 603         switch (chan->band) {
 604         case IEEE80211_BAND_2GHZ:
 605                 switch(channel_type) {
 606                 case NL80211_CHAN_NO_HT:
 607                 case NL80211_CHAN_HT20:
 608                         chanmode = CHANNEL_G_HT20;
 609                         break;
 610                 case NL80211_CHAN_HT40PLUS:
 611                         chanmode = CHANNEL_G_HT40PLUS;
 612                         break;
 613                 case NL80211_CHAN_HT40MINUS:
 614                         chanmode = CHANNEL_G_HT40MINUS;
 615                         break;
 616                 }
 617                 break;
 618         case IEEE80211_BAND_5GHZ:
 619                 switch(channel_type) {
 620                 case NL80211_CHAN_NO_HT:
 621                 case NL80211_CHAN_HT20:
 622                         chanmode = CHANNEL_A_HT20;
 623                         break;
 624                 case NL80211_CHAN_HT40PLUS:
 625                         chanmode = CHANNEL_A_HT40PLUS;
 626                         break;
 627                 case NL80211_CHAN_HT40MINUS:
 628                         chanmode = CHANNEL_A_HT40MINUS;
 629                         break;
 630                 }
 631                 break;
 632         default:
 633                 break;
 634         }
 635
 636         return chanmode;
 637 }
 638
 639 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
 640                            struct ath9k_keyval *hk, const u8 *addr,
 641                            bool authenticator)
 642 {
 643         const u8 *key_rxmic;
 644         const u8 *key_txmic;
 645
 646         key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
 647         key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
 648
 649         if (addr == NULL) {
 650                 /*
 651                  * Group key installation - only two key cache entries are used
 652                  * regardless of splitmic capability since group key is only
 653                  * used either for TX or RX.
 654                  */
 655                 if (authenticator) {
 656                         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 657                         memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
 658                 } else {
 659                         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 660                         memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
 661                 }
 662                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
 663         }
 664         if (!sc->splitmic) {
 665                 /* TX and RX keys share the same key cache entry. */
 666                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 667                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
 668                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
 669         }
 670
 671         /* Separate key cache entries for TX and RX */
 672
 673         /* TX key goes at first index, RX key at +32. */
 674         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 675         if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
 676                 /* TX MIC entry failed. No need to proceed further */
 677                 DPRINTF(sc, ATH_DBG_KEYCACHE,
 678                         "Setting TX MIC Key Failed\n");
 679                 return 0;
 680         }
 681
 682         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 683         /* XXX delete tx key on failure? */
 684         return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
 685 }
 686
 687 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
 688 {
 689         int i;
 690
 691         for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
 692                 if (test_bit(i, sc->keymap) ||
 693                     test_bit(i + 64, sc->keymap))
 694                         continue; /* At least one part of TKIP key allocated */
 695                 if (sc->splitmic &&
 696                     (test_bit(i + 32, sc->keymap) ||
 697                      test_bit(i + 64 + 32, sc->keymap)))
 698                         continue; /* At least one part of TKIP key allocated */
 699
 700                 /* Found a free slot for a TKIP key */
 701                 return i;
 702         }
 703         return -1;
 704 }
 705
 706 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
 707 {
 708         int i;
 709
 710         /* First, try to find slots that would not be available for TKIP. */
 711         if (sc->splitmic) {
 712                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
 713                         if (!test_bit(i, sc->keymap) &&
 714                             (test_bit(i + 32, sc->keymap) ||
 715                              test_bit(i + 64, sc->keymap) ||
 716                              test_bit(i + 64 + 32, sc->keymap)))
 717                                 return i;
 718                         if (!test_bit(i + 32, sc->keymap) &&
 719                             (test_bit(i, sc->keymap) ||
 720                              test_bit(i + 64, sc->keymap) ||
 721                              test_bit(i + 64 + 32, sc->keymap)))
 722                                 return i + 32;
 723                         if (!test_bit(i + 64, sc->keymap) &&
 724                             (test_bit(i , sc->keymap) ||
 725                              test_bit(i + 32, sc->keymap) ||
 726                              test_bit(i + 64 + 32, sc->keymap)))
 727                                 return i + 64;
 728                         if (!test_bit(i + 64 + 32, sc->keymap) &&
 729                             (test_bit(i, sc->keymap) ||
 730                              test_bit(i + 32, sc->keymap) ||
 731                              test_bit(i + 64, sc->keymap)))
 732                                 return i + 64 + 32;
 733                 }
 734         } else {
 735                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
 736                         if (!test_bit(i, sc->keymap) &&
 737                             test_bit(i + 64, sc->keymap))
 738                                 return i;
 739                         if (test_bit(i, sc->keymap) &&
 740                             !test_bit(i + 64, sc->keymap))
 741                                 return i + 64;
 742                 }
 743         }
 744
 745         /* No partially used TKIP slots, pick any available slot */
 746         for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
 747                 /* Do not allow slots that could be needed for TKIP group keys
 748                  * to be used. This limitation could be removed if we know that
 749                  * TKIP will not be used. */
 750                 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
 751                         continue;
 752                 if (sc->splitmic) {
 753                         if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
 754                                 continue;
 755                         if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
 756                                 continue;
 757                 }
 758
 759                 if (!test_bit(i, sc->keymap))
 760                         return i; /* Found a free slot for a key */
 761         }
 762
 763         /* No free slot found */
 764         return -1;
 765 }
 766
 767 static int ath_key_config(struct ath_softc *sc,
 768                           struct ieee80211_vif *vif,
 769                           struct ieee80211_sta *sta,
 770                           struct ieee80211_key_conf *key)
 771 {
 772         struct ath9k_keyval hk;
 773         const u8 *mac = NULL;
 774         int ret = 0;
 775         int idx;
 776
 777         memset(&hk, 0, sizeof(hk));
 778
 779         switch (key->alg) {
 780         case ALG_WEP:
 781                 hk.kv_type = ATH9K_CIPHER_WEP;
 782                 break;
 783         case ALG_TKIP:
 784                 hk.kv_type = ATH9K_CIPHER_TKIP;
 785                 break;
 786         case ALG_CCMP:
 787                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
 788                 break;
 789         default:
 790                 return -EOPNOTSUPP;
 791         }
 792
 793         hk.kv_len = key->keylen;
 794         memcpy(hk.kv_val, key->key, key->keylen);
 795
 796         if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
 797                 /* For now, use the default keys for broadcast keys. This may
 798                  * need to change with virtual interfaces. */
 799                 idx = key->keyidx;
 800         } else if (key->keyidx) {
 801                 if (WARN_ON(!sta))
 802                         return -EOPNOTSUPP;
 803                 mac = sta->addr;
 804
 805                 if (vif->type != NL80211_IFTYPE_AP) {
 806                         /* Only keyidx 0 should be used with unicast key, but
 807                          * allow this for client mode for now. */
 808                         idx = key->keyidx;
 809                 } else
 810                         return -EIO;
 811         } else {
 812                 if (WARN_ON(!sta))
 813                         return -EOPNOTSUPP;
 814                 mac = sta->addr;
 815
 816                 if (key->alg == ALG_TKIP)
 817                         idx = ath_reserve_key_cache_slot_tkip(sc);
 818                 else
 819                         idx = ath_reserve_key_cache_slot(sc);
 820                 if (idx < 0)
 821                         return -ENOSPC; /* no free key cache entries */
 822         }
 823
 824         if (key->alg == ALG_TKIP)
 825                 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
 826                                       vif->type == NL80211_IFTYPE_AP);
 827         else
 828                 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
 829
 830         if (!ret)
 831                 return -EIO;
 832
 833         set_bit(idx, sc->keymap);
 834         if (key->alg == ALG_TKIP) {
 835                 set_bit(idx + 64, sc->keymap);
 836                 if (sc->splitmic) {
 837                         set_bit(idx + 32, sc->keymap);
 838                         set_bit(idx + 64 + 32, sc->keymap);
 839                 }
 840         }
 841
 842         return idx;
 843 }
 844
 845 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
 846 {
 847         ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
 848         if (key->hw_key_idx < IEEE80211_WEP_NKID)
 849                 return;
 850
 851         clear_bit(key->hw_key_idx, sc->keymap);
 852         if (key->alg != ALG_TKIP)
 853                 return;
 854
 855         clear_bit(key->hw_key_idx + 64, sc->keymap);
 856         if (sc->splitmic) {
 857                 clear_bit(key->hw_key_idx + 32, sc->keymap);
 858                 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
 859         }
 860 }
 861
 862 static void setup_ht_cap(struct ath_softc *sc,
 863                          struct ieee80211_sta_ht_cap *ht_info)
 864 {
 865 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3       /* 2 ^ 16 */
 866 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6          /* 8 usec */
 867
 868         ht_info->ht_supported = true;
 869         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 870                        IEEE80211_HT_CAP_SM_PS |
 871                        IEEE80211_HT_CAP_SGI_40 |
 872                        IEEE80211_HT_CAP_DSSSCCK40;
 873
 874         ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
 875         ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
 876
 877         /* set up supported mcs set */
 878         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 879
 880         switch(sc->rx_chainmask) {
 881         case 1:
 882                 ht_info->mcs.rx_mask[0] = 0xff;
 883                 break;
 884         case 3:
 885         case 5:
 886         case 7:
 887         default:
 888                 ht_info->mcs.rx_mask[0] = 0xff;
 889                 ht_info->mcs.rx_mask[1] = 0xff;
 890                 break;
 891         }
 892
 893         ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
 894 }
 895
 896 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 897                                  struct ieee80211_vif *vif,
 898                                  struct ieee80211_bss_conf *bss_conf)
 899 {
 900         struct ath_vif *avp = (void *)vif->drv_priv;
 901
 902         if (bss_conf->assoc) {
 903                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
 904                         bss_conf->aid, sc->curbssid);
 905
 906                 /* New association, store aid */
 907                 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
 908                         sc->curaid = bss_conf->aid;
 909                         ath9k_hw_write_associd(sc);
 910                 }
 911
 912                 /* Configure the beacon */
 913                 ath_beacon_config(sc, vif);
 914
 915                 /* Reset rssi stats */
 916                 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
 917                 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
 918                 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
 919                 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
 920
 921                 /* Start ANI */
 922                 mod_timer(&sc->ani.timer,
 923                           jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 924         } else {
 925                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
 926                 sc->curaid = 0;
 927         }
 928 }
 929
 930 /********************************/
 931 /*       LED functions          */
 932 /********************************/
 933
 934 static void ath_led_blink_work(struct work_struct *work)
 935 {
 936         struct ath_softc *sc = container_of(work, struct ath_softc,
 937                                             ath_led_blink_work.work);
 938
 939         if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
 940                 return;
 941
 942         if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
 943             (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
 944                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
 945         else
 946                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 947                                   (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
 948
 949         queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
 950                            (sc->sc_flags & SC_OP_LED_ON) ?
 951                            msecs_to_jiffies(sc->led_off_duration) :
 952                            msecs_to_jiffies(sc->led_on_duration));
 953
 954         sc->led_on_duration = sc->led_on_cnt ?
 955                         max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
 956                         ATH_LED_ON_DURATION_IDLE;
 957         sc->led_off_duration = sc->led_off_cnt ?
 958                         max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
 959                         ATH_LED_OFF_DURATION_IDLE;
 960         sc->led_on_cnt = sc->led_off_cnt = 0;
 961         if (sc->sc_flags & SC_OP_LED_ON)
 962                 sc->sc_flags &= ~SC_OP_LED_ON;
 963         else
 964                 sc->sc_flags |= SC_OP_LED_ON;
 965 }
 966
 967 static void ath_led_brightness(struct led_classdev *led_cdev,
 968                                enum led_brightness brightness)
 969 {
 970         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
 971         struct ath_softc *sc = led->sc;
 972
 973         switch (brightness) {
 974         case LED_OFF:
 975                 if (led->led_type == ATH_LED_ASSOC ||
 976                     led->led_type == ATH_LED_RADIO) {
 977                         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 978                                 (led->led_type == ATH_LED_RADIO));
 979                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 980                         if (led->led_type == ATH_LED_RADIO)
 981                                 sc->sc_flags &= ~SC_OP_LED_ON;
 982                 } else {
 983                         sc->led_off_cnt++;
 984                 }
 985                 break;
 986         case LED_FULL:
 987                 if (led->led_type == ATH_LED_ASSOC) {
 988                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
 989                         queue_delayed_work(sc->hw->workqueue,
 990                                            &sc->ath_led_blink_work, 0);
 991                 } else if (led->led_type == ATH_LED_RADIO) {
 992                         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
 993                         sc->sc_flags |= SC_OP_LED_ON;
 994                 } else {
 995                         sc->led_on_cnt++;
 996                 }
 997                 break;
 998         default:
 999                 break;
1000         }
1001 }
1002
1003 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1004                             char *trigger)
1005 {
1006         int ret;
1007
1008         led->sc = sc;
1009         led->led_cdev.name = led->name;
1010         led->led_cdev.default_trigger = trigger;
1011         led->led_cdev.brightness_set = ath_led_brightness;
1012
1013         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1014         if (ret)
1015                 DPRINTF(sc, ATH_DBG_FATAL,
1016                         "Failed to register led:%s", led->name);
1017         else
1018                 led->registered = 1;
1019         return ret;
1020 }
1021
1022 static void ath_unregister_led(struct ath_led *led)
1023 {
1024         if (led->registered) {
1025                 led_classdev_unregister(&led->led_cdev);
1026                 led->registered = 0;
1027         }
1028 }
1029
1030 static void ath_deinit_leds(struct ath_softc *sc)
1031 {
1032         cancel_delayed_work_sync(&sc->ath_led_blink_work);
1033         ath_unregister_led(&sc->assoc_led);
1034         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1035         ath_unregister_led(&sc->tx_led);
1036         ath_unregister_led(&sc->rx_led);
1037         ath_unregister_led(&sc->radio_led);
1038         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1039 }
1040
1041 static void ath_init_leds(struct ath_softc *sc)
1042 {
1043         char *trigger;
1044         int ret;
1045
1046         /* Configure gpio 1 for output */
1047         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1048                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1049         /* LED off, active low */
1050         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1051
1052         INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1053
1054         trigger = ieee80211_get_radio_led_name(sc->hw);
1055         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1056                 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1057         ret = ath_register_led(sc, &sc->radio_led, trigger);
1058         sc->radio_led.led_type = ATH_LED_RADIO;
1059         if (ret)
1060                 goto fail;
1061
1062         trigger = ieee80211_get_assoc_led_name(sc->hw);
1063         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1064                 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1065         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1066         sc->assoc_led.led_type = ATH_LED_ASSOC;
1067         if (ret)
1068                 goto fail;
1069
1070         trigger = ieee80211_get_tx_led_name(sc->hw);
1071         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1072                 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1073         ret = ath_register_led(sc, &sc->tx_led, trigger);
1074         sc->tx_led.led_type = ATH_LED_TX;
1075         if (ret)
1076                 goto fail;
1077
1078         trigger = ieee80211_get_rx_led_name(sc->hw);
1079         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1080                 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1081         ret = ath_register_led(sc, &sc->rx_led, trigger);
1082         sc->rx_led.led_type = ATH_LED_RX;
1083         if (ret)
1084                 goto fail;
1085
1086         return;
1087
1088 fail:
1089         ath_deinit_leds(sc);
1090 }
1091
1092 void ath_radio_enable(struct ath_softc *sc)
1093 {
1094         struct ath_hw *ah = sc->sc_ah;
1095         struct ieee80211_channel *channel = sc->hw->conf.channel;
1096         int r;
1097
1098         ath9k_ps_wakeup(sc);
1099         spin_lock_bh(&sc->sc_resetlock);
1100
1101         r = ath9k_hw_reset(ah, ah->curchan, false);
1102
1103         if (r) {
1104                 DPRINTF(sc, ATH_DBG_FATAL,
1105                         "Unable to reset channel %u (%uMhz) ",
1106                         "reset status %u\n",
1107                         channel->center_freq, r);
1108         }
1109         spin_unlock_bh(&sc->sc_resetlock);
1110
1111         ath_update_txpow(sc);
1112         if (ath_startrecv(sc) != 0) {
1113                 DPRINTF(sc, ATH_DBG_FATAL,
1114                         "Unable to restart recv logic\n");
1115                 return;
1116         }
1117
1118         if (sc->sc_flags & SC_OP_BEACONS)
1119                 ath_beacon_config(sc, NULL);    /* restart beacons */
1120
1121         /* Re-Enable  interrupts */
1122         ath9k_hw_set_interrupts(ah, sc->imask);
1123
1124         /* Enable LED */
1125         ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1126                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1127         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1128
1129         ieee80211_wake_queues(sc->hw);
1130         ath9k_ps_restore(sc);
1131 }
1132
1133 void ath_radio_disable(struct ath_softc *sc)
1134 {
1135         struct ath_hw *ah = sc->sc_ah;
1136         struct ieee80211_channel *channel = sc->hw->conf.channel;
1137         int r;
1138
1139         ath9k_ps_wakeup(sc);
1140         ieee80211_stop_queues(sc->hw);
1141
1142         /* Disable LED */
1143         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1144         ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1145
1146         /* Disable interrupts */
1147         ath9k_hw_set_interrupts(ah, 0);
1148
1149         ath_drain_all_txq(sc, false);   /* clear pending tx frames */
1150         ath_stoprecv(sc);               /* turn off frame recv */
1151         ath_flushrecv(sc);              /* flush recv queue */
1152
1153         spin_lock_bh(&sc->sc_resetlock);
1154         r = ath9k_hw_reset(ah, ah->curchan, false);
1155         if (r) {
1156                 DPRINTF(sc, ATH_DBG_FATAL,
1157                         "Unable to reset channel %u (%uMhz) "
1158                         "reset status %u\n",
1159                         channel->center_freq, r);
1160         }
1161         spin_unlock_bh(&sc->sc_resetlock);
1162
1163         ath9k_hw_phy_disable(ah);
1164         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1165         ath9k_ps_restore(sc);
1166 }
1167
1168 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1169
1170 /*******************/
1171 /*      Rfkill     */
1172 /*******************/
1173
1174 static bool ath_is_rfkill_set(struct ath_softc *sc)
1175 {
1176         struct ath_hw *ah = sc->sc_ah;
1177
1178         return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1179                                   ah->rfkill_polarity;
1180 }
1181
1182 /* h/w rfkill poll function */
1183 static void ath_rfkill_poll(struct work_struct *work)
1184 {
1185         struct ath_softc *sc = container_of(work, struct ath_softc,
1186                                             rf_kill.rfkill_poll.work);
1187         bool radio_on;
1188
1189         if (sc->sc_flags & SC_OP_INVALID)
1190                 return;
1191
1192         radio_on = !ath_is_rfkill_set(sc);
1193
1194         /*
1195          * enable/disable radio only when there is a
1196          * state change in RF switch
1197          */
1198         if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1199                 enum rfkill_state state;
1200
1201                 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1202                         state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1203                                 : RFKILL_STATE_HARD_BLOCKED;
1204                 } else if (radio_on) {
1205                         ath_radio_enable(sc);
1206                         state = RFKILL_STATE_UNBLOCKED;
1207                 } else {
1208                         ath_radio_disable(sc);
1209                         state = RFKILL_STATE_HARD_BLOCKED;
1210                 }
1211
1212                 if (state == RFKILL_STATE_HARD_BLOCKED)
1213                         sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1214                 else
1215                         sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1216
1217                 rfkill_force_state(sc->rf_kill.rfkill, state);
1218         }
1219
1220         queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1221                            msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1222 }
1223
1224 /* s/w rfkill handler */
1225 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1226 {
1227         struct ath_softc *sc = data;
1228
1229         switch (state) {
1230         case RFKILL_STATE_SOFT_BLOCKED:
1231                 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1232                     SC_OP_RFKILL_SW_BLOCKED)))
1233                         ath_radio_disable(sc);
1234                 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1235                 return 0;
1236         case RFKILL_STATE_UNBLOCKED:
1237                 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1238                         sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1239                         if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1240                                 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1241                                         "radio as it is disabled by h/w\n");
1242                                 return -EPERM;
1243                         }
1244                         ath_radio_enable(sc);
1245                 }
1246                 return 0;
1247         default:
1248                 return -EINVAL;
1249         }
1250 }
1251
1252 /* Init s/w rfkill */
1253 static int ath_init_sw_rfkill(struct ath_softc *sc)
1254 {
1255         sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1256                                              RFKILL_TYPE_WLAN);
1257         if (!sc->rf_kill.rfkill) {
1258                 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1259                 return -ENOMEM;
1260         }
1261
1262         snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1263                 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
1264         sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1265         sc->rf_kill.rfkill->data = sc;
1266         sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1267         sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1268
1269         return 0;
1270 }
1271
1272 /* Deinitialize rfkill */
1273 static void ath_deinit_rfkill(struct ath_softc *sc)
1274 {
1275         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1276                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1277
1278         if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1279                 rfkill_unregister(sc->rf_kill.rfkill);
1280                 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1281                 sc->rf_kill.rfkill = NULL;
1282         }
1283 }
1284
1285 static int ath_start_rfkill_poll(struct ath_softc *sc)
1286 {
1287         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1288                 queue_delayed_work(sc->hw->workqueue,
1289                                    &sc->rf_kill.rfkill_poll, 0);
1290
1291         if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1292                 if (rfkill_register(sc->rf_kill.rfkill)) {
1293                         DPRINTF(sc, ATH_DBG_FATAL,
1294                                 "Unable to register rfkill\n");
1295                         rfkill_free(sc->rf_kill.rfkill);
1296
1297                         /* Deinitialize the device */
1298                         ath_cleanup(sc);
1299                         return -EIO;
1300                 } else {
1301                         sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1302                 }
1303         }
1304
1305         return 0;
1306 }
1307 #endif /* CONFIG_RFKILL */
1308
1309 void ath_cleanup(struct ath_softc *sc)
1310 {
1311         ath_detach(sc);
1312         free_irq(sc->irq, sc);
1313         ath_bus_cleanup(sc);
1314         kfree(sc->sec_wiphy);
1315         ieee80211_free_hw(sc->hw);
1316 }
1317
1318 void ath_detach(struct ath_softc *sc)
1319 {
1320         struct ieee80211_hw *hw = sc->hw;
1321         int i = 0;
1322
1323         ath9k_ps_wakeup(sc);
1324
1325         DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1326
1327 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1328         ath_deinit_rfkill(sc);
1329 #endif
1330         ath_deinit_leds(sc);
1331         cancel_work_sync(&sc->chan_work);
1332         cancel_delayed_work_sync(&sc->wiphy_work);
1333
1334         for (i = 0; i < sc->num_sec_wiphy; i++) {
1335                 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1336                 if (aphy == NULL)
1337                         continue;
1338                 sc->sec_wiphy[i] = NULL;
1339                 ieee80211_unregister_hw(aphy->hw);
1340                 ieee80211_free_hw(aphy->hw);
1341         }
1342         ieee80211_unregister_hw(hw);
1343         ath_rx_cleanup(sc);
1344         ath_tx_cleanup(sc);
1345
1346         tasklet_kill(&sc->intr_tq);
1347         tasklet_kill(&sc->bcon_tasklet);
1348
1349         if (!(sc->sc_flags & SC_OP_INVALID))
1350                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1351
1352         /* cleanup tx queues */
1353         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1354                 if (ATH_TXQ_SETUP(sc, i))
1355                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1356
1357         ath9k_hw_detach(sc->sc_ah);
1358         ath9k_exit_debug(sc);
1359         ath9k_ps_restore(sc);
1360 }
1361
1362 static int ath_init(u16 devid, struct ath_softc *sc)
1363 {
1364         struct ath_hw *ah = NULL;
1365         int status;
1366         int error = 0, i;
1367         int csz = 0;
1368
1369         /* XXX: hardware will not be ready until ath_open() being called */
1370         sc->sc_flags |= SC_OP_INVALID;
1371
1372         if (ath9k_init_debug(sc) < 0)
1373                 printk(KERN_ERR "Unable to create debugfs files\n");
1374
1375         spin_lock_init(&sc->wiphy_lock);
1376         spin_lock_init(&sc->sc_resetlock);
1377         spin_lock_init(&sc->sc_serial_rw);
1378         mutex_init(&sc->mutex);
1379         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1380         tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1381                      (unsigned long)sc);
1382
1383         /*
1384          * Cache line size is used to size and align various
1385          * structures used to communicate with the hardware.
1386          */
1387         ath_read_cachesize(sc, &csz);
1388         /* XXX assert csz is non-zero */
1389         sc->cachelsz = csz << 2;        /* convert to bytes */
1390
1391         ah = ath9k_hw_attach(devid, sc, &status);
1392         if (ah == NULL) {
1393                 DPRINTF(sc, ATH_DBG_FATAL,
1394                         "Unable to attach hardware; HAL status %d\n", status);
1395                 error = -ENXIO;
1396                 goto bad;
1397         }
1398         sc->sc_ah = ah;
1399
1400         /* Get the hardware key cache size. */
1401         sc->keymax = ah->caps.keycache_size;
1402         if (sc->keymax > ATH_KEYMAX) {
1403                 DPRINTF(sc, ATH_DBG_KEYCACHE,
1404                         "Warning, using only %u entries in %u key cache\n",
1405                         ATH_KEYMAX, sc->keymax);
1406                 sc->keymax = ATH_KEYMAX;
1407         }
1408
1409         /*
1410          * Reset the key cache since some parts do not
1411          * reset the contents on initial power up.
1412          */
1413         for (i = 0; i < sc->keymax; i++)
1414                 ath9k_hw_keyreset(ah, (u16) i);
1415
1416         if (ath9k_regd_init(sc->sc_ah))
1417                 goto bad;
1418
1419         /* default to MONITOR mode */
1420         sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1421
1422         /* Setup rate tables */
1423
1424         ath_rate_attach(sc);
1425         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1426         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1427
1428         /*
1429          * Allocate hardware transmit queues: one queue for
1430          * beacon frames and one data queue for each QoS
1431          * priority.  Note that the hal handles reseting
1432          * these queues at the needed time.
1433          */
1434         sc->beacon.beaconq = ath_beaconq_setup(ah);
1435         if (sc->beacon.beaconq == -1) {
1436                 DPRINTF(sc, ATH_DBG_FATAL,
1437                         "Unable to setup a beacon xmit queue\n");
1438                 error = -EIO;
1439                 goto bad2;
1440         }
1441         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1442         if (sc->beacon.cabq == NULL) {
1443                 DPRINTF(sc, ATH_DBG_FATAL,
1444                         "Unable to setup CAB xmit queue\n");
1445                 error = -EIO;
1446                 goto bad2;
1447         }
1448
1449         sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1450         ath_cabq_update(sc);
1451
1452         for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1453                 sc->tx.hwq_map[i] = -1;
1454
1455         /* Setup data queues */
1456         /* NB: ensure BK queue is the lowest priority h/w queue */
1457         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1458                 DPRINTF(sc, ATH_DBG_FATAL,
1459                         "Unable to setup xmit queue for BK traffic\n");
1460                 error = -EIO;
1461                 goto bad2;
1462         }
1463
1464         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1465                 DPRINTF(sc, ATH_DBG_FATAL,
1466                         "Unable to setup xmit queue for BE traffic\n");
1467                 error = -EIO;
1468                 goto bad2;
1469         }
1470         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1471                 DPRINTF(sc, ATH_DBG_FATAL,
1472                         "Unable to setup xmit queue for VI traffic\n");
1473                 error = -EIO;
1474                 goto bad2;
1475         }
1476         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1477                 DPRINTF(sc, ATH_DBG_FATAL,
1478                         "Unable to setup xmit queue for VO traffic\n");
1479                 error = -EIO;
1480                 goto bad2;
1481         }
1482
1483         /* Initializes the noise floor to a reasonable default value.
1484          * Later on this will be updated during ANI processing. */
1485
1486         sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1487         setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1488
1489         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1490                                    ATH9K_CIPHER_TKIP, NULL)) {
1491                 /*
1492                  * Whether we should enable h/w TKIP MIC.
1493                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1494                  * report WMM capable, so it's always safe to turn on
1495                  * TKIP MIC in this case.
1496                  */
1497                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1498                                        0, 1, NULL);
1499         }
1500
1501         /*
1502          * Check whether the separate key cache entries
1503          * are required to handle both tx+rx MIC keys.
1504          * With split mic keys the number of stations is limited
1505          * to 27 otherwise 59.
1506          */
1507         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1508                                    ATH9K_CIPHER_TKIP, NULL)
1509             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1510                                       ATH9K_CIPHER_MIC, NULL)
1511             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1512                                       0, NULL))
1513                 sc->splitmic = 1;
1514
1515         /* turn on mcast key search if possible */
1516         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1517                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1518                                              1, NULL);
1519
1520         sc->config.txpowlimit = ATH_TXPOWER_MAX;
1521
1522         /* 11n Capabilities */
1523         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1524                 sc->sc_flags |= SC_OP_TXAGGR;
1525                 sc->sc_flags |= SC_OP_RXAGGR;
1526         }
1527
1528         sc->tx_chainmask = ah->caps.tx_chainmask;
1529         sc->rx_chainmask = ah->caps.rx_chainmask;
1530
1531         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1532         sc->rx.defant = ath9k_hw_getdefantenna(ah);
1533
1534         if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1535                 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
1536
1537         sc->beacon.slottime = ATH9K_SLOT_TIME_9;        /* default to short slot time */
1538
1539         /* initialize beacon slots */
1540         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1541                 sc->beacon.bslot[i] = NULL;
1542                 sc->beacon.bslot_aphy[i] = NULL;
1543         }
1544
1545         /* save MISC configurations */
1546         sc->config.swBeaconProcess = 1;
1547
1548         /* setup channels and rates */
1549
1550         sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1551         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1552                 sc->rates[IEEE80211_BAND_2GHZ];
1553         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1554         sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1555                 ARRAY_SIZE(ath9k_2ghz_chantable);
1556
1557         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1558                 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1559                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1560                         sc->rates[IEEE80211_BAND_5GHZ];
1561                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1562                 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1563                         ARRAY_SIZE(ath9k_5ghz_chantable);
1564         }
1565
1566         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1567                 ath9k_hw_btcoex_enable(sc->sc_ah);
1568
1569         return 0;
1570 bad2:
1571         /* cleanup tx queues */
1572         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1573                 if (ATH_TXQ_SETUP(sc, i))
1574                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1575 bad:
1576         if (ah)
1577                 ath9k_hw_detach(ah);
1578         ath9k_exit_debug(sc);
1579
1580         return error;
1581 }
1582
1583 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1584 {
1585         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1586                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1587                 IEEE80211_HW_SIGNAL_DBM |
1588                 IEEE80211_HW_AMPDU_AGGREGATION |
1589                 IEEE80211_HW_SUPPORTS_PS |
1590                 IEEE80211_HW_PS_NULLFUNC_STACK |
1591                 IEEE80211_HW_SPECTRUM_MGMT;
1592
1593         if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1594                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1595
1596         hw->wiphy->interface_modes =
1597                 BIT(NL80211_IFTYPE_AP) |
1598                 BIT(NL80211_IFTYPE_STATION) |
1599                 BIT(NL80211_IFTYPE_ADHOC) |
1600                 BIT(NL80211_IFTYPE_MESH_POINT);
1601
1602         hw->wiphy->reg_notifier = ath9k_reg_notifier;
1603         hw->wiphy->strict_regulatory = true;
1604
1605         hw->queues = 4;
1606         hw->max_rates = 4;
1607         hw->channel_change_time = 5000;
1608         hw->max_listen_interval = 10;
1609         hw->max_rate_tries = ATH_11N_TXMAXTRY;
1610         hw->sta_data_size = sizeof(struct ath_node);
1611         hw->vif_data_size = sizeof(struct ath_vif);
1612
1613         hw->rate_control_algorithm = "ath9k_rate_control";
1614
1615         hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1616                 &sc->sbands[IEEE80211_BAND_2GHZ];
1617         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1618                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1619                         &sc->sbands[IEEE80211_BAND_5GHZ];
1620 }
1621
1622 int ath_attach(u16 devid, struct ath_softc *sc)
1623 {
1624         struct ieee80211_hw *hw = sc->hw;
1625         const struct ieee80211_regdomain *regd;
1626         int error = 0, i;
1627
1628         DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1629
1630         error = ath_init(devid, sc);
1631         if (error != 0)
1632                 return error;
1633
1634         /* get mac address from hardware and set in mac80211 */
1635
1636         SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1637
1638         ath_set_hw_capab(sc, hw);
1639
1640         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1641                 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1642                 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1643                         setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1644         }
1645
1646         /* initialize tx/rx engine */
1647         error = ath_tx_init(sc, ATH_TXBUF);
1648         if (error != 0)
1649                 goto error_attach;
1650
1651         error = ath_rx_init(sc, ATH_RXBUF);
1652         if (error != 0)
1653                 goto error_attach;
1654
1655 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1656         /* Initialze h/w Rfkill */
1657         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1658                 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1659
1660         /* Initialize s/w rfkill */
1661         error = ath_init_sw_rfkill(sc);
1662         if (error)
1663                 goto error_attach;
1664 #endif
1665
1666         if (ath9k_is_world_regd(sc->sc_ah)) {
1667                 /* Anything applied here (prior to wiphy registration) gets
1668                  * saved on the wiphy orig_* parameters */
1669                 regd = ath9k_world_regdomain(sc->sc_ah);
1670                 hw->wiphy->custom_regulatory = true;
1671                 hw->wiphy->strict_regulatory = false;
1672         } else {
1673                 /* This gets applied in the case of the absense of CRDA,
1674                  * it's our own custom world regulatory domain, similar to
1675                  * cfg80211's but we enable passive scanning */
1676                 regd = ath9k_default_world_regdomain();
1677         }
1678         wiphy_apply_custom_regulatory(hw->wiphy, regd);
1679         ath9k_reg_apply_radar_flags(hw->wiphy);
1680         ath9k_reg_apply_world_flags(hw->wiphy, NL80211_REGDOM_SET_BY_DRIVER);
1681
1682         INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1683         INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1684         sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1685
1686         error = ieee80211_register_hw(hw);
1687
1688         if (!ath9k_is_world_regd(sc->sc_ah)) {
1689                 error = regulatory_hint(hw->wiphy,
1690                         sc->sc_ah->regulatory.alpha2);
1691                 if (error)
1692                         goto error_attach;
1693         }
1694
1695         /* Initialize LED control */
1696         ath_init_leds(sc);
1697
1698
1699         return 0;
1700
1701 error_attach:
1702         /* cleanup tx queues */
1703         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1704                 if (ATH_TXQ_SETUP(sc, i))
1705                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1706
1707         ath9k_hw_detach(sc->sc_ah);
1708         ath9k_exit_debug(sc);
1709
1710         return error;
1711 }
1712
1713 int ath_reset(struct ath_softc *sc, bool retry_tx)
1714 {
1715         struct ath_hw *ah = sc->sc_ah;
1716         struct ieee80211_hw *hw = sc->hw;
1717         int r;
1718
1719         ath9k_hw_set_interrupts(ah, 0);
1720         ath_drain_all_txq(sc, retry_tx);
1721         ath_stoprecv(sc);
1722         ath_flushrecv(sc);
1723
1724         spin_lock_bh(&sc->sc_resetlock);
1725         r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1726         if (r)
1727                 DPRINTF(sc, ATH_DBG_FATAL,
1728                         "Unable to reset hardware; reset status %u\n", r);
1729         spin_unlock_bh(&sc->sc_resetlock);
1730
1731         if (ath_startrecv(sc) != 0)
1732                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1733
1734         /*
1735          * We may be doing a reset in response to a request
1736          * that changes the channel so update any state that
1737          * might change as a result.
1738          */
1739         ath_cache_conf_rate(sc, &hw->conf);
1740
1741         ath_update_txpow(sc);
1742
1743         if (sc->sc_flags & SC_OP_BEACONS)
1744                 ath_beacon_config(sc, NULL);    /* restart beacons */
1745
1746         ath9k_hw_set_interrupts(ah, sc->imask);
1747
1748         if (retry_tx) {
1749                 int i;
1750                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1751                         if (ATH_TXQ_SETUP(sc, i)) {
1752                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1753                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
1754                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1755                         }
1756                 }
1757         }
1758
1759         return r;
1760 }
1761
1762 /*
1763  *  This function will allocate both the DMA descriptor structure, and the
1764  *  buffers it contains.  These are used to contain the descriptors used
1765  *  by the system.
1766 */
1767 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1768                       struct list_head *head, const char *name,
1769                       int nbuf, int ndesc)
1770 {
1771 #define DS2PHYS(_dd, _ds)                                               \
1772         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1773 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1774 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1775
1776         struct ath_desc *ds;
1777         struct ath_buf *bf;
1778         int i, bsize, error;
1779
1780         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1781                 name, nbuf, ndesc);
1782
1783         INIT_LIST_HEAD(head);
1784         /* ath_desc must be a multiple of DWORDs */
1785         if ((sizeof(struct ath_desc) % 4) != 0) {
1786                 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1787                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1788                 error = -ENOMEM;
1789                 goto fail;
1790         }
1791
1792         dd->dd_name = name;
1793         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1794
1795         /*
1796          * Need additional DMA memory because we can't use
1797          * descriptors that cross the 4K page boundary. Assume
1798          * one skipped descriptor per 4K page.
1799          */
1800         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1801                 u32 ndesc_skipped =
1802                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1803                 u32 dma_len;
1804
1805                 while (ndesc_skipped) {
1806                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1807                         dd->dd_desc_len += dma_len;
1808
1809                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1810                 };
1811         }
1812
1813         /* allocate descriptors */
1814         dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1815                                          &dd->dd_desc_paddr, GFP_KERNEL);
1816         if (dd->dd_desc == NULL) {
1817                 error = -ENOMEM;
1818                 goto fail;
1819         }
1820         ds = dd->dd_desc;
1821         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1822                 dd->dd_name, ds, (u32) dd->dd_desc_len,
1823                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1824
1825         /* allocate buffers */
1826         bsize = sizeof(struct ath_buf) * nbuf;
1827         bf = kzalloc(bsize, GFP_KERNEL);
1828         if (bf == NULL) {
1829                 error = -ENOMEM;
1830                 goto fail2;
1831         }
1832         dd->dd_bufptr = bf;
1833
1834         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1835                 bf->bf_desc = ds;
1836                 bf->bf_daddr = DS2PHYS(dd, ds);
1837
1838                 if (!(sc->sc_ah->caps.hw_caps &
1839                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1840                         /*
1841                          * Skip descriptor addresses which can cause 4KB
1842                          * boundary crossing (addr + length) with a 32 dword
1843                          * descriptor fetch.
1844                          */
1845                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1846                                 ASSERT((caddr_t) bf->bf_desc <
1847                                        ((caddr_t) dd->dd_desc +
1848                                         dd->dd_desc_len));
1849
1850                                 ds += ndesc;
1851                                 bf->bf_desc = ds;
1852                                 bf->bf_daddr = DS2PHYS(dd, ds);
1853                         }
1854                 }
1855                 list_add_tail(&bf->list, head);
1856         }
1857         return 0;
1858 fail2:
1859         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1860                           dd->dd_desc_paddr);
1861 fail:
1862         memset(dd, 0, sizeof(*dd));
1863         return error;
1864 #undef ATH_DESC_4KB_BOUND_CHECK
1865 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1866 #undef DS2PHYS
1867 }
1868
1869 void ath_descdma_cleanup(struct ath_softc *sc,
1870                          struct ath_descdma *dd,
1871                          struct list_head *head)
1872 {
1873         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1874                           dd->dd_desc_paddr);
1875
1876         INIT_LIST_HEAD(head);
1877         kfree(dd->dd_bufptr);
1878         memset(dd, 0, sizeof(*dd));
1879 }
1880
1881 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1882 {
1883         int qnum;
1884
1885         switch (queue) {
1886         case 0:
1887                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1888                 break;
1889         case 1:
1890                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1891                 break;
1892         case 2:
1893                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1894                 break;
1895         case 3:
1896                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1897                 break;
1898         default:
1899                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1900                 break;
1901         }
1902
1903         return qnum;
1904 }
1905
1906 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1907 {
1908         int qnum;
1909
1910         switch (queue) {
1911         case ATH9K_WME_AC_VO:
1912                 qnum = 0;
1913                 break;
1914         case ATH9K_WME_AC_VI:
1915                 qnum = 1;
1916                 break;
1917         case ATH9K_WME_AC_BE:
1918                 qnum = 2;
1919                 break;
1920         case ATH9K_WME_AC_BK:
1921                 qnum = 3;
1922                 break;
1923         default:
1924                 qnum = -1;
1925                 break;
1926         }
1927
1928         return qnum;
1929 }
1930
1931 /* XXX: Remove me once we don't depend on ath9k_channel for all
1932  * this redundant data */
1933 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1934                            struct ath9k_channel *ichan)
1935 {
1936         struct ieee80211_channel *chan = hw->conf.channel;
1937         struct ieee80211_conf *conf = &hw->conf;
1938
1939         ichan->channel = chan->center_freq;
1940         ichan->chan = chan;
1941
1942         if (chan->band == IEEE80211_BAND_2GHZ) {
1943                 ichan->chanmode = CHANNEL_G;
1944                 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1945         } else {
1946                 ichan->chanmode = CHANNEL_A;
1947                 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1948         }
1949
1950         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1951
1952         if (conf_is_ht(conf)) {
1953                 if (conf_is_ht40(conf))
1954                         sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1955
1956                 ichan->chanmode = ath_get_extchanmode(sc, chan,
1957                                             conf->channel_type);
1958         }
1959 }
1960
1961 /**********************/
1962 /* mac80211 callbacks */
1963 /**********************/
1964
1965 static int ath9k_start(struct ieee80211_hw *hw)
1966 {
1967         struct ath_wiphy *aphy = hw->priv;
1968         struct ath_softc *sc = aphy->sc;
1969         struct ieee80211_channel *curchan = hw->conf.channel;
1970         struct ath9k_channel *init_channel;
1971         int r, pos;
1972
1973         DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1974                 "initial channel: %d MHz\n", curchan->center_freq);
1975
1976         mutex_lock(&sc->mutex);
1977
1978         if (ath9k_wiphy_started(sc)) {
1979                 if (sc->chan_idx == curchan->hw_value) {
1980                         /*
1981                          * Already on the operational channel, the new wiphy
1982                          * can be marked active.
1983                          */
1984                         aphy->state = ATH_WIPHY_ACTIVE;
1985                         ieee80211_wake_queues(hw);
1986                 } else {
1987                         /*
1988                          * Another wiphy is on another channel, start the new
1989                          * wiphy in paused state.
1990                          */
1991                         aphy->state = ATH_WIPHY_PAUSED;
1992                         ieee80211_stop_queues(hw);
1993                 }
1994                 mutex_unlock(&sc->mutex);
1995                 return 0;
1996         }
1997         aphy->state = ATH_WIPHY_ACTIVE;
1998
1999         /* setup initial channel */
2000
2001         pos = curchan->hw_value;
2002
2003         sc->chan_idx = pos;
2004         init_channel = &sc->sc_ah->channels[pos];
2005         ath9k_update_ichannel(sc, hw, init_channel);
2006
2007         /* Reset SERDES registers */
2008         ath9k_hw_configpcipowersave(sc->sc_ah, 0);
2009
2010         /*
2011          * The basic interface to setting the hardware in a good
2012          * state is ``reset''.  On return the hardware is known to
2013          * be powered up and with interrupts disabled.  This must
2014          * be followed by initialization of the appropriate bits
2015          * and then setup of the interrupt mask.
2016          */
2017         spin_lock_bh(&sc->sc_resetlock);
2018         r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
2019         if (r) {
2020                 DPRINTF(sc, ATH_DBG_FATAL,
2021                         "Unable to reset hardware; reset status %u "
2022                         "(freq %u MHz)\n", r,
2023                         curchan->center_freq);
2024                 spin_unlock_bh(&sc->sc_resetlock);
2025                 goto mutex_unlock;
2026         }
2027         spin_unlock_bh(&sc->sc_resetlock);
2028
2029         /*
2030          * This is needed only to setup initial state
2031          * but it's best done after a reset.
2032          */
2033         ath_update_txpow(sc);
2034
2035         /*
2036          * Setup the hardware after reset:
2037          * The receive engine is set going.
2038          * Frame transmit is handled entirely
2039          * in the frame output path; there's nothing to do
2040          * here except setup the interrupt mask.
2041          */
2042         if (ath_startrecv(sc) != 0) {
2043                 DPRINTF(sc, ATH_DBG_FATAL,
2044                         "Unable to start recv logic\n");
2045                 r = -EIO;
2046                 goto mutex_unlock;
2047         }
2048
2049         /* Setup our intr mask. */
2050         sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
2051                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2052                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2053
2054         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
2055                 sc->imask |= ATH9K_INT_GTT;
2056
2057         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2058                 sc->imask |= ATH9K_INT_CST;
2059
2060         ath_cache_conf_rate(sc, &hw->conf);
2061
2062         sc->sc_flags &= ~SC_OP_INVALID;
2063
2064         /* Disable BMISS interrupt when we're not associated */
2065         sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2066         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2067
2068         ieee80211_wake_queues(hw);
2069
2070 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2071         r = ath_start_rfkill_poll(sc);
2072 #endif
2073
2074 mutex_unlock:
2075         mutex_unlock(&sc->mutex);
2076
2077         return r;
2078 }
2079
2080 static int ath9k_tx(struct ieee80211_hw *hw,
2081                     struct sk_buff *skb)
2082 {
2083         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2084         struct ath_wiphy *aphy = hw->priv;
2085         struct ath_softc *sc = aphy->sc;
2086         struct ath_tx_control txctl;
2087         int hdrlen, padsize;
2088
2089         if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2090                 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2091                        "%d\n", wiphy_name(hw->wiphy), aphy->state);
2092                 goto exit;
2093         }
2094
2095         memset(&txctl, 0, sizeof(struct ath_tx_control));
2096
2097         /*
2098          * As a temporary workaround, assign seq# here; this will likely need
2099          * to be cleaned up to work better with Beacon transmission and virtual
2100          * BSSes.
2101          */
2102         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2103                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2104                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2105                         sc->tx.seq_no += 0x10;
2106                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2107                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2108         }
2109
2110         /* Add the padding after the header if this is not already done */
2111         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2112         if (hdrlen & 3) {
2113                 padsize = hdrlen % 4;
2114                 if (skb_headroom(skb) < padsize)
2115                         return -1;
2116                 skb_push(skb, padsize);
2117                 memmove(skb->data, skb->data + padsize, hdrlen);
2118         }
2119
2120         /* Check if a tx queue is available */
2121
2122         txctl.txq = ath_test_get_txq(sc, skb);
2123         if (!txctl.txq)
2124                 goto exit;
2125
2126         DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2127
2128         if (ath_tx_start(hw, skb, &txctl) != 0) {
2129                 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2130                 goto exit;
2131         }
2132
2133         return 0;
2134 exit:
2135         dev_kfree_skb_any(skb);
2136         return 0;
2137 }
2138
2139 static void ath9k_stop(struct ieee80211_hw *hw)
2140 {
2141         struct ath_wiphy *aphy = hw->priv;
2142         struct ath_softc *sc = aphy->sc;
2143
2144         aphy->state = ATH_WIPHY_INACTIVE;
2145
2146         if (sc->sc_flags & SC_OP_INVALID) {
2147                 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2148                 return;
2149         }
2150
2151         mutex_lock(&sc->mutex);
2152
2153         ieee80211_stop_queues(hw);
2154
2155         if (ath9k_wiphy_started(sc)) {
2156                 mutex_unlock(&sc->mutex);
2157                 return; /* another wiphy still in use */
2158         }
2159
2160         /* make sure h/w will not generate any interrupt
2161          * before setting the invalid flag. */
2162         ath9k_hw_set_interrupts(sc->sc_ah, 0);
2163
2164         if (!(sc->sc_flags & SC_OP_INVALID)) {
2165                 ath_drain_all_txq(sc, false);
2166                 ath_stoprecv(sc);
2167                 ath9k_hw_phy_disable(sc->sc_ah);
2168         } else
2169                 sc->rx.rxlink = NULL;
2170
2171 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2172         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2173                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2174 #endif
2175         /* disable HAL and put h/w to sleep */
2176         ath9k_hw_disable(sc->sc_ah);
2177         ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2178
2179         sc->sc_flags |= SC_OP_INVALID;
2180
2181         mutex_unlock(&sc->mutex);
2182
2183         DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2184 }
2185
2186 static int ath9k_add_interface(struct ieee80211_hw *hw,
2187                                struct ieee80211_if_init_conf *conf)
2188 {
2189         struct ath_wiphy *aphy = hw->priv;
2190         struct ath_softc *sc = aphy->sc;
2191         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2192         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2193         int ret = 0;
2194
2195         mutex_lock(&sc->mutex);
2196
2197         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2198             sc->nvifs > 0) {
2199                 ret = -ENOBUFS;
2200                 goto out;
2201         }
2202
2203         switch (conf->type) {
2204         case NL80211_IFTYPE_STATION:
2205                 ic_opmode = NL80211_IFTYPE_STATION;
2206                 break;
2207         case NL80211_IFTYPE_ADHOC:
2208         case NL80211_IFTYPE_AP:
2209         case NL80211_IFTYPE_MESH_POINT:
2210                 if (sc->nbcnvifs >= ATH_BCBUF) {
2211                         ret = -ENOBUFS;
2212                         goto out;
2213                 }
2214                 ic_opmode = conf->type;
2215                 break;
2216         default:
2217                 DPRINTF(sc, ATH_DBG_FATAL,
2218                         "Interface type %d not yet supported\n", conf->type);
2219                 ret = -EOPNOTSUPP;
2220                 goto out;
2221         }
2222
2223         DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2224
2225         /* Set the VIF opmode */
2226         avp->av_opmode = ic_opmode;
2227         avp->av_bslot = -1;
2228
2229         sc->nvifs++;
2230
2231         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2232                 ath9k_set_bssid_mask(hw);
2233
2234         if (sc->nvifs > 1)
2235                 goto out; /* skip global settings for secondary vif */
2236
2237         if (ic_opmode == NL80211_IFTYPE_AP) {
2238                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2239                 sc->sc_flags |= SC_OP_TSF_RESET;
2240         }
2241
2242         /* Set the device opmode */
2243         sc->sc_ah->opmode = ic_opmode;
2244
2245         /*
2246          * Enable MIB interrupts when there are hardware phy counters.
2247          * Note we only do this (at the moment) for station mode.
2248          */
2249         if ((conf->type == NL80211_IFTYPE_STATION) ||
2250             (conf->type == NL80211_IFTYPE_ADHOC) ||
2251             (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2252                 if (ath9k_hw_phycounters(sc->sc_ah))
2253                         sc->imask |= ATH9K_INT_MIB;
2254                 sc->imask |= ATH9K_INT_TSFOOR;
2255         }
2256
2257         /*
2258          * Some hardware processes the TIM IE and fires an
2259          * interrupt when the TIM bit is set.  For hardware
2260          * that does, if not overridden by configuration,
2261          * enable the TIM interrupt when operating as station.
2262          */
2263         if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
2264             (conf->type == NL80211_IFTYPE_STATION) &&
2265             !sc->config.swBeaconProcess)
2266                 sc->imask |= ATH9K_INT_TIM;
2267
2268         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2269
2270         if (conf->type == NL80211_IFTYPE_AP) {
2271                 /* TODO: is this a suitable place to start ANI for AP mode? */
2272                 /* Start ANI */
2273                 mod_timer(&sc->ani.timer,
2274                           jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2275         }
2276
2277 out:
2278         mutex_unlock(&sc->mutex);
2279         return ret;
2280 }
2281
2282 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2283                                    struct ieee80211_if_init_conf *conf)
2284 {
2285         struct ath_wiphy *aphy = hw->priv;
2286         struct ath_softc *sc = aphy->sc;
2287         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2288         int i;
2289
2290         DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2291
2292         mutex_lock(&sc->mutex);
2293
2294         /* Stop ANI */
2295         del_timer_sync(&sc->ani.timer);
2296
2297         /* Reclaim beacon resources */
2298         if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2299             (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2300             (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2301                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2302                 ath_beacon_return(sc, avp);
2303         }
2304
2305         sc->sc_flags &= ~SC_OP_BEACONS;
2306
2307         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2308                 if (sc->beacon.bslot[i] == conf->vif) {
2309                         printk(KERN_DEBUG "%s: vif had allocated beacon "
2310                                "slot\n", __func__);
2311                         sc->beacon.bslot[i] = NULL;
2312                         sc->beacon.bslot_aphy[i] = NULL;
2313                 }
2314         }
2315
2316         sc->nvifs--;
2317
2318         mutex_unlock(&sc->mutex);
2319 }
2320
2321 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2322 {
2323         struct ath_wiphy *aphy = hw->priv;
2324         struct ath_softc *sc = aphy->sc;
2325         struct ieee80211_conf *conf = &hw->conf;
2326         struct ath_hw *ah = sc->sc_ah;
2327
2328         mutex_lock(&sc->mutex);
2329
2330         if (changed & IEEE80211_CONF_CHANGE_PS) {
2331                 if (conf->flags & IEEE80211_CONF_PS) {
2332                         if (!(ah->caps.hw_caps &
2333                               ATH9K_HW_CAP_AUTOSLEEP)) {
2334                                 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2335                                         sc->imask |= ATH9K_INT_TIM_TIMER;
2336                                         ath9k_hw_set_interrupts(sc->sc_ah,
2337                                                         sc->imask);
2338                                 }
2339                                 ath9k_hw_setrxabort(sc->sc_ah, 1);
2340                         }
2341                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2342                 } else {
2343                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2344                         if (!(ah->caps.hw_caps &
2345                               ATH9K_HW_CAP_AUTOSLEEP)) {
2346                                 ath9k_hw_setrxabort(sc->sc_ah, 0);
2347                                 sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
2348                                 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2349                                         sc->imask &= ~ATH9K_INT_TIM_TIMER;
2350                                         ath9k_hw_set_interrupts(sc->sc_ah,
2351                                                         sc->imask);
2352                                 }
2353                         }
2354                 }
2355         }
2356
2357         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2358                 struct ieee80211_channel *curchan = hw->conf.channel;
2359                 int pos = curchan->hw_value;
2360
2361                 aphy->chan_idx = pos;
2362                 aphy->chan_is_ht = conf_is_ht(conf);
2363
2364                 if (aphy->state == ATH_WIPHY_SCAN ||
2365                     aphy->state == ATH_WIPHY_ACTIVE)
2366                         ath9k_wiphy_pause_all_forced(sc, aphy);
2367                 else {
2368                         /*
2369                          * Do not change operational channel based on a paused
2370                          * wiphy changes.
2371                          */
2372                         goto skip_chan_change;
2373                 }
2374
2375                 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2376                         curchan->center_freq);
2377
2378                 /* XXX: remove me eventualy */
2379                 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2380
2381                 ath_update_chainmask(sc, conf_is_ht(conf));
2382
2383                 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2384                         DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2385                         mutex_unlock(&sc->mutex);
2386                         return -EINVAL;
2387                 }
2388         }
2389
2390 skip_chan_change:
2391         if (changed & IEEE80211_CONF_CHANGE_POWER)
2392                 sc->config.txpowlimit = 2 * conf->power_level;
2393
2394         /*
2395          * The HW TSF has to be reset when the beacon interval changes.
2396          * We set the flag here, and ath_beacon_config_ap() would take this
2397          * into account when it gets called through the subsequent
2398          * config_interface() call - with IFCC_BEACON in the changed field.
2399          */
2400
2401         if (changed & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
2402                 sc->sc_flags |= SC_OP_TSF_RESET;
2403
2404         mutex_unlock(&sc->mutex);
2405
2406         return 0;
2407 }
2408
2409 static int ath9k_config_interface(struct ieee80211_hw *hw,
2410                                   struct ieee80211_vif *vif,
2411                                   struct ieee80211_if_conf *conf)
2412 {
2413         struct ath_wiphy *aphy = hw->priv;
2414         struct ath_softc *sc = aphy->sc;
2415         struct ath_hw *ah = sc->sc_ah;
2416         struct ath_vif *avp = (void *)vif->drv_priv;
2417         u32 rfilt = 0;
2418         int error, i;
2419
2420         mutex_lock(&sc->mutex);
2421
2422         /* TODO: Need to decide which hw opmode to use for multi-interface
2423          * cases */
2424         if (vif->type == NL80211_IFTYPE_AP &&
2425             ah->opmode != NL80211_IFTYPE_AP) {
2426                 ah->opmode = NL80211_IFTYPE_STATION;
2427                 ath9k_hw_setopmode(ah);
2428                 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2429                 sc->curaid = 0;
2430                 ath9k_hw_write_associd(sc);
2431                 /* Request full reset to get hw opmode changed properly */
2432                 sc->sc_flags |= SC_OP_FULL_RESET;
2433         }
2434
2435         if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2436             !is_zero_ether_addr(conf->bssid)) {
2437                 switch (vif->type) {
2438                 case NL80211_IFTYPE_STATION:
2439                 case NL80211_IFTYPE_ADHOC:
2440                 case NL80211_IFTYPE_MESH_POINT:
2441                         /* Set BSSID */
2442                         memcpy(sc->curbssid, conf->bssid, ETH_ALEN);
2443                         memcpy(avp->bssid, conf->bssid, ETH_ALEN);
2444                         sc->curaid = 0;
2445                         ath9k_hw_write_associd(sc);
2446
2447                         /* Set aggregation protection mode parameters */
2448                         sc->config.ath_aggr_prot = 0;
2449
2450                         DPRINTF(sc, ATH_DBG_CONFIG,
2451                                 "RX filter 0x%x bssid %pM aid 0x%x\n",
2452                                 rfilt, sc->curbssid, sc->curaid);
2453
2454                         /* need to reconfigure the beacon */
2455                         sc->sc_flags &= ~SC_OP_BEACONS ;
2456
2457                         break;
2458                 default:
2459                         break;
2460                 }
2461         }
2462
2463         if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2464             (vif->type == NL80211_IFTYPE_AP) ||
2465             (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2466                 if ((conf->changed & IEEE80211_IFCC_BEACON) ||
2467                     (conf->changed & IEEE80211_IFCC_BEACON_ENABLED &&
2468                      conf->enable_beacon)) {
2469                         /*
2470                          * Allocate and setup the beacon frame.
2471                          *
2472                          * Stop any previous beacon DMA.  This may be
2473                          * necessary, for example, when an ibss merge
2474                          * causes reconfiguration; we may be called
2475                          * with beacon transmission active.
2476                          */
2477                         ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2478
2479                         error = ath_beacon_alloc(aphy, vif);
2480                         if (error != 0) {
2481                                 mutex_unlock(&sc->mutex);
2482                                 return error;
2483                         }
2484
2485                         ath_beacon_config(sc, vif);
2486                 }
2487         }
2488
2489         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2490         if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2491                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2492                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2493                                 ath9k_hw_keysetmac(sc->sc_ah,
2494                                                    (u16)i,
2495                                                    sc->curbssid);
2496         }
2497
2498         /* Only legacy IBSS for now */
2499         if (vif->type == NL80211_IFTYPE_ADHOC)
2500                 ath_update_chainmask(sc, 0);
2501
2502         mutex_unlock(&sc->mutex);
2503
2504         return 0;
2505 }
2506
2507 #define SUPPORTED_FILTERS                       \
2508         (FIF_PROMISC_IN_BSS |                   \
2509         FIF_ALLMULTI |                          \
2510         FIF_CONTROL |                           \
2511         FIF_OTHER_BSS |                         \
2512         FIF_BCN_PRBRESP_PROMISC |               \
2513         FIF_FCSFAIL)
2514
2515 /* FIXME: sc->sc_full_reset ? */
2516 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2517                                    unsigned int changed_flags,
2518                                    unsigned int *total_flags,
2519                                    int mc_count,
2520                                    struct dev_mc_list *mclist)
2521 {
2522         struct ath_wiphy *aphy = hw->priv;
2523         struct ath_softc *sc = aphy->sc;
2524         u32 rfilt;
2525
2526         changed_flags &= SUPPORTED_FILTERS;
2527         *total_flags &= SUPPORTED_FILTERS;
2528
2529         sc->rx.rxfilter = *total_flags;
2530         rfilt = ath_calcrxfilter(sc);
2531         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2532
2533         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2534 }
2535
2536 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2537                              struct ieee80211_vif *vif,
2538                              enum sta_notify_cmd cmd,
2539                              struct ieee80211_sta *sta)
2540 {
2541         struct ath_wiphy *aphy = hw->priv;
2542         struct ath_softc *sc = aphy->sc;
2543
2544         switch (cmd) {
2545         case STA_NOTIFY_ADD:
2546                 ath_node_attach(sc, sta);
2547                 break;
2548         case STA_NOTIFY_REMOVE:
2549                 ath_node_detach(sc, sta);
2550                 break;
2551         default:
2552                 break;
2553         }
2554 }
2555
2556 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2557                          const struct ieee80211_tx_queue_params *params)
2558 {
2559         struct ath_wiphy *aphy = hw->priv;
2560         struct ath_softc *sc = aphy->sc;
2561         struct ath9k_tx_queue_info qi;
2562         int ret = 0, qnum;
2563
2564         if (queue >= WME_NUM_AC)
2565                 return 0;
2566
2567         mutex_lock(&sc->mutex);
2568
2569         qi.tqi_aifs = params->aifs;
2570         qi.tqi_cwmin = params->cw_min;
2571         qi.tqi_cwmax = params->cw_max;
2572         qi.tqi_burstTime = params->txop;
2573         qnum = ath_get_hal_qnum(queue, sc);
2574
2575         DPRINTF(sc, ATH_DBG_CONFIG,
2576                 "Configure tx [queue/halq] [%d/%d],  "
2577                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2578                 queue, qnum, params->aifs, params->cw_min,
2579                 params->cw_max, params->txop);
2580
2581         ret = ath_txq_update(sc, qnum, &qi);
2582         if (ret)
2583                 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2584
2585         mutex_unlock(&sc->mutex);
2586
2587         return ret;
2588 }
2589
2590 static int ath9k_set_key(struct ieee80211_hw *hw,
2591                          enum set_key_cmd cmd,
2592                          struct ieee80211_vif *vif,
2593                          struct ieee80211_sta *sta,
2594                          struct ieee80211_key_conf *key)
2595 {
2596         struct ath_wiphy *aphy = hw->priv;
2597         struct ath_softc *sc = aphy->sc;
2598         int ret = 0;
2599
2600         if (modparam_nohwcrypt)
2601                 return -ENOSPC;
2602
2603         mutex_lock(&sc->mutex);
2604         ath9k_ps_wakeup(sc);
2605         DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
2606
2607         switch (cmd) {
2608         case SET_KEY:
2609                 ret = ath_key_config(sc, vif, sta, key);
2610                 if (ret >= 0) {
2611                         key->hw_key_idx = ret;
2612                         /* push IV and Michael MIC generation to stack */
2613                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2614                         if (key->alg == ALG_TKIP)
2615                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2616                         if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2617                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2618                         ret = 0;
2619                 }
2620                 break;
2621         case DISABLE_KEY:
2622                 ath_key_delete(sc, key);
2623                 break;
2624         default:
2625                 ret = -EINVAL;
2626         }
2627
2628         ath9k_ps_restore(sc);
2629         mutex_unlock(&sc->mutex);
2630
2631         return ret;
2632 }
2633
2634 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2635                                    struct ieee80211_vif *vif,
2636                                    struct ieee80211_bss_conf *bss_conf,
2637                                    u32 changed)
2638 {
2639         struct ath_wiphy *aphy = hw->priv;
2640         struct ath_softc *sc = aphy->sc;
2641
2642         mutex_lock(&sc->mutex);
2643
2644         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2645                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2646                         bss_conf->use_short_preamble);
2647                 if (bss_conf->use_short_preamble)
2648                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2649                 else
2650                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2651         }
2652
2653         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2654                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2655                         bss_conf->use_cts_prot);
2656                 if (bss_conf->use_cts_prot &&
2657                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2658                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2659                 else
2660                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2661         }
2662
2663         if (changed & BSS_CHANGED_ASSOC) {
2664                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2665                         bss_conf->assoc);
2666                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2667         }
2668
2669         mutex_unlock(&sc->mutex);
2670 }
2671
2672 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2673 {
2674         u64 tsf;
2675         struct ath_wiphy *aphy = hw->priv;
2676         struct ath_softc *sc = aphy->sc;
2677
2678         mutex_lock(&sc->mutex);
2679         tsf = ath9k_hw_gettsf64(sc->sc_ah);
2680         mutex_unlock(&sc->mutex);
2681
2682         return tsf;
2683 }
2684
2685 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2686 {
2687         struct ath_wiphy *aphy = hw->priv;
2688         struct ath_softc *sc = aphy->sc;
2689
2690         mutex_lock(&sc->mutex);
2691         ath9k_hw_settsf64(sc->sc_ah, tsf);
2692         mutex_unlock(&sc->mutex);
2693 }
2694
2695 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2696 {
2697         struct ath_wiphy *aphy = hw->priv;
2698         struct ath_softc *sc = aphy->sc;
2699
2700         mutex_lock(&sc->mutex);
2701         ath9k_hw_reset_tsf(sc->sc_ah);
2702         mutex_unlock(&sc->mutex);
2703 }
2704
2705 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2706                               enum ieee80211_ampdu_mlme_action action,
2707                               struct ieee80211_sta *sta,
2708                               u16 tid, u16 *ssn)
2709 {
2710         struct ath_wiphy *aphy = hw->priv;
2711         struct ath_softc *sc = aphy->sc;
2712         int ret = 0;
2713
2714         switch (action) {
2715         case IEEE80211_AMPDU_RX_START:
2716                 if (!(sc->sc_flags & SC_OP_RXAGGR))
2717                         ret = -ENOTSUPP;
2718                 break;
2719         case IEEE80211_AMPDU_RX_STOP:
2720                 break;
2721         case IEEE80211_AMPDU_TX_START:
2722                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2723                 if (ret < 0)
2724                         DPRINTF(sc, ATH_DBG_FATAL,
2725                                 "Unable to start TX aggregation\n");
2726                 else
2727                         ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2728                 break;
2729         case IEEE80211_AMPDU_TX_STOP:
2730                 ret = ath_tx_aggr_stop(sc, sta, tid);
2731                 if (ret < 0)
2732                         DPRINTF(sc, ATH_DBG_FATAL,
2733                                 "Unable to stop TX aggregation\n");
2734
2735                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2736                 break;
2737         case IEEE80211_AMPDU_TX_OPERATIONAL:
2738                 ath_tx_aggr_resume(sc, sta, tid);
2739                 break;
2740         default:
2741                 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2742         }
2743
2744         return ret;
2745 }
2746
2747 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2748 {
2749         struct ath_wiphy *aphy = hw->priv;
2750         struct ath_softc *sc = aphy->sc;
2751
2752         if (ath9k_wiphy_scanning(sc)) {
2753                 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2754                        "same time\n");
2755                 /*
2756                  * Do not allow the concurrent scanning state for now. This
2757                  * could be improved with scanning control moved into ath9k.
2758                  */
2759                 return;
2760         }
2761
2762         aphy->state = ATH_WIPHY_SCAN;
2763         ath9k_wiphy_pause_all_forced(sc, aphy);
2764
2765         mutex_lock(&sc->mutex);
2766         sc->sc_flags |= SC_OP_SCANNING;
2767         mutex_unlock(&sc->mutex);
2768 }
2769
2770 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2771 {
2772         struct ath_wiphy *aphy = hw->priv;
2773         struct ath_softc *sc = aphy->sc;
2774
2775         mutex_lock(&sc->mutex);
2776         aphy->state = ATH_WIPHY_ACTIVE;
2777         sc->sc_flags &= ~SC_OP_SCANNING;
2778         mutex_unlock(&sc->mutex);
2779 }
2780
2781 struct ieee80211_ops ath9k_ops = {
2782         .tx                 = ath9k_tx,
2783         .start              = ath9k_start,
2784         .stop               = ath9k_stop,
2785         .add_interface      = ath9k_add_interface,
2786         .remove_interface   = ath9k_remove_interface,
2787         .config             = ath9k_config,
2788         .config_interface   = ath9k_config_interface,
2789         .configure_filter   = ath9k_configure_filter,
2790         .sta_notify         = ath9k_sta_notify,
2791         .conf_tx            = ath9k_conf_tx,
2792         .bss_info_changed   = ath9k_bss_info_changed,
2793         .set_key            = ath9k_set_key,
2794         .get_tsf            = ath9k_get_tsf,
2795         .set_tsf            = ath9k_set_tsf,
2796         .reset_tsf          = ath9k_reset_tsf,
2797         .ampdu_action       = ath9k_ampdu_action,
2798         .sw_scan_start      = ath9k_sw_scan_start,
2799         .sw_scan_complete   = ath9k_sw_scan_complete,
2800 };
2801
2802 static struct {
2803         u32 version;
2804         const char * name;
2805 } ath_mac_bb_names[] = {
2806         { AR_SREV_VERSION_5416_PCI,     "5416" },
2807         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2808         { AR_SREV_VERSION_9100,         "9100" },
2809         { AR_SREV_VERSION_9160,         "9160" },
2810         { AR_SREV_VERSION_9280,         "9280" },
2811         { AR_SREV_VERSION_9285,         "9285" }
2812 };
2813
2814 static struct {
2815         u16 version;
2816         const char * name;
2817 } ath_rf_names[] = {
2818         { 0,                            "5133" },
2819         { AR_RAD5133_SREV_MAJOR,        "5133" },
2820         { AR_RAD5122_SREV_MAJOR,        "5122" },
2821         { AR_RAD2133_SREV_MAJOR,        "2133" },
2822         { AR_RAD2122_SREV_MAJOR,        "2122" }
2823 };
2824
2825 /*
2826  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2827  */
2828 const char *
2829 ath_mac_bb_name(u32 mac_bb_version)
2830 {
2831         int i;
2832
2833         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2834                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2835                         return ath_mac_bb_names[i].name;
2836                 }
2837         }
2838
2839         return "????";
2840 }
2841
2842 /*
2843  * Return the RF name. "????" is returned if the RF is unknown.
2844  */
2845 const char *
2846 ath_rf_name(u16 rf_version)
2847 {
2848         int i;
2849
2850         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2851                 if (ath_rf_names[i].version == rf_version) {
2852                         return ath_rf_names[i].name;
2853                 }
2854         }
2855
2856         return "????";
2857 }
2858
2859 static int __init ath9k_init(void)
2860 {
2861         int error;
2862
2863         /* Register rate control algorithm */
2864         error = ath_rate_control_register();
2865         if (error != 0) {
2866                 printk(KERN_ERR
2867                         "ath9k: Unable to register rate control "
2868                         "algorithm: %d\n",
2869                         error);
2870                 goto err_out;
2871         }
2872
2873         error = ath9k_debug_create_root();
2874         if (error) {
2875                 printk(KERN_ERR
2876                         "ath9k: Unable to create debugfs root: %d\n",
2877                         error);
2878                 goto err_rate_unregister;
2879         }
2880
2881         error = ath_pci_init();
2882         if (error < 0) {
2883                 printk(KERN_ERR
2884                         "ath9k: No PCI devices found, driver not installed.\n");
2885                 error = -ENODEV;
2886                 goto err_remove_root;
2887         }
2888
2889         error = ath_ahb_init();
2890         if (error < 0) {
2891                 error = -ENODEV;
2892                 goto err_pci_exit;
2893         }
2894
2895         return 0;
2896
2897  err_pci_exit:
2898         ath_pci_exit();
2899
2900  err_remove_root:
2901         ath9k_debug_remove_root();
2902  err_rate_unregister:
2903         ath_rate_control_unregister();
2904  err_out:
2905         return error;
2906 }
2907 module_init(ath9k_init);
2908
2909 static void __exit ath9k_exit(void)
2910 {
2911         ath_ahb_exit();
2912         ath_pci_exit();
2913         ath9k_debug_remove_root();
2914         ath_rate_control_unregister();
2915         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2916 }
2917 module_exit(ath9k_exit);