2 * Copyright 2002 Momentum Computer
3 * Author: mdharm@momenco.com
5 * arch/mips/momentum/ocelot_c/uart-irq.c
6 * Interrupt routines for UARTs. Interrupt numbers are assigned from
7 * 80 to 81 (2 interrupt sources).
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/kernel.h>
19 #include <linux/sched.h>
20 #include <linux/kernel_stat.h>
23 #include "ocelot_c_fpga.h"
25 static inline int ls1bit8(unsigned int x)
29 s = 4; if (((unsigned char)(x << 4)) == 0) s = 0; b -= s; x <<= s;
30 s = 2; if (((unsigned char)(x << 2)) == 0) s = 0; b -= s; x <<= s;
31 s = 1; if (((unsigned char)(x << 1)) == 0) s = 0; b -= s;
36 /* mask off an interrupt -- 0 is enable, 1 is disable */
37 static inline void mask_uart_irq(unsigned int irq)
41 value = OCELOT_FPGA_READ(UART_INTMASK);
42 value |= 1 << (irq - 74);
43 OCELOT_FPGA_WRITE(value, UART_INTMASK);
45 /* read the value back to assure that it's really been written */
46 value = OCELOT_FPGA_READ(UART_INTMASK);
49 /* unmask an interrupt -- 0 is enable, 1 is disable */
50 static inline void unmask_uart_irq(unsigned int irq)
54 value = OCELOT_FPGA_READ(UART_INTMASK);
55 value &= ~(1 << (irq - 74));
56 OCELOT_FPGA_WRITE(value, UART_INTMASK);
58 /* read the value back to assure that it's really been written */
59 value = OCELOT_FPGA_READ(UART_INTMASK);
63 * Enables the IRQ in the FPGA
65 static void enable_uart_irq(unsigned int irq)
71 * Initialize the IRQ in the FPGA
73 static unsigned int startup_uart_irq(unsigned int irq)
80 * Disables the IRQ in the FPGA
82 static void disable_uart_irq(unsigned int irq)
88 * Masks and ACKs an IRQ
90 static void mask_and_ack_uart_irq(unsigned int irq)
98 static void end_uart_irq(unsigned int irq)
100 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
101 unmask_uart_irq(irq);
105 * Interrupt handler for interrupts coming from the FPGA chip.
107 void ll_uart_irq(void)
109 unsigned int irq_src, irq_mask;
111 /* read the interrupt status registers */
112 irq_src = OCELOT_FPGA_READ(UART_INTSTAT);
113 irq_mask = OCELOT_FPGA_READ(UART_INTMASK);
115 /* mask for just the interrupts we want */
116 irq_src &= ~irq_mask;
118 do_IRQ(ls1bit8(irq_src) + 74);
121 #define shutdown_uart_irq disable_uart_irq
123 struct irq_chip uart_irq_type = {
124 .typename = "UART/FPGA",
125 .startup = startup_uart_irq,
126 .shutdown = shutdown_uart_irq,
127 .enable = enable_uart_irq,
128 .disable = disable_uart_irq,
129 .ack = mask_and_ack_uart_irq,
133 void uart_irq_init(void)
135 /* Reset irq handlers pointers to NULL */
136 irq_desc[80].status = IRQ_DISABLED;
137 irq_desc[80].action = 0;
138 irq_desc[80].depth = 2;
139 irq_desc[80].chip = &uart_irq_type;
141 irq_desc[81].status = IRQ_DISABLED;
142 irq_desc[81].action = 0;
143 irq_desc[81].depth = 2;
144 irq_desc[81].chip = &uart_irq_type;