1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
32 #include "ixgbe_common.h"
33 #include "ixgbe_phy.h"
35 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
36 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
37 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
38 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
39 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
40 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
41 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
42 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
43 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
44 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
45 static bool ixgbe_get_i2c_data(u32 *i2cctl);
46 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
47 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
48 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
51 * ixgbe_identify_phy_generic - Get physical layer module
52 * @hw: pointer to hardware structure
54 * Determines the physical layer module found on the current adapter.
56 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
58 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
61 if (hw->phy.type == ixgbe_phy_unknown) {
62 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
63 if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) {
66 ixgbe_get_phy_type_from_id(hw->phy.id);
79 * ixgbe_get_phy_id - Get the phy type
80 * @hw: pointer to hardware structure
83 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
89 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
93 hw->phy.id = (u32)(phy_id_high << 16);
94 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
96 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
97 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
103 * ixgbe_get_phy_type_from_id - Get the phy type
104 * @hw: pointer to hardware structure
107 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
109 enum ixgbe_phy_type phy_type;
113 phy_type = ixgbe_phy_tn;
116 phy_type = ixgbe_phy_qt;
119 phy_type = ixgbe_phy_nl;
122 phy_type = ixgbe_phy_unknown;
130 * ixgbe_reset_phy_generic - Performs a PHY reset
131 * @hw: pointer to hardware structure
133 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
136 * Perform soft PHY reset to the PHY_XS.
137 * This will cause a soft reset to the PHY
139 return hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
144 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
145 * @hw: pointer to hardware structure
146 * @reg_addr: 32 bit address of PHY register to read
147 * @phy_data: Pointer to read data from PHY register
149 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
150 u32 device_type, u16 *phy_data)
158 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
159 gssr = IXGBE_GSSR_PHY1_SM;
161 gssr = IXGBE_GSSR_PHY0_SM;
163 if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
164 status = IXGBE_ERR_SWFW_SYNC;
167 /* Setup and write the address cycle command */
168 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
169 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
170 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
171 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
173 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
176 * Check every 10 usec to see if the address cycle completed.
177 * The MDI Command bit will clear when the operation is
180 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
183 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
185 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
189 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
190 hw_dbg(hw, "PHY address command did not complete.\n");
191 status = IXGBE_ERR_PHY;
196 * Address cycle complete, setup and write the read
199 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
200 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
201 (hw->phy.mdio.prtad <<
202 IXGBE_MSCA_PHY_ADDR_SHIFT) |
203 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
205 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
208 * Check every 10 usec to see if the address cycle
209 * completed. The MDI Command bit will clear when the
210 * operation is complete
212 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
215 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
217 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
221 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
222 hw_dbg(hw, "PHY read command didn't complete\n");
223 status = IXGBE_ERR_PHY;
226 * Read operation is complete. Get the data
229 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
230 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
231 *phy_data = (u16)(data);
235 ixgbe_release_swfw_sync(hw, gssr);
242 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
243 * @hw: pointer to hardware structure
244 * @reg_addr: 32 bit PHY register to write
245 * @device_type: 5 bit device type
246 * @phy_data: Data to write to the PHY register
248 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
249 u32 device_type, u16 phy_data)
256 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
257 gssr = IXGBE_GSSR_PHY1_SM;
259 gssr = IXGBE_GSSR_PHY0_SM;
261 if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
262 status = IXGBE_ERR_SWFW_SYNC;
265 /* Put the data in the MDI single read and write data register*/
266 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
268 /* Setup and write the address cycle command */
269 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
270 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
271 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
272 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
274 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
277 * Check every 10 usec to see if the address cycle completed.
278 * The MDI Command bit will clear when the operation is
281 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
284 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
286 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
290 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
291 hw_dbg(hw, "PHY address cmd didn't complete\n");
292 status = IXGBE_ERR_PHY;
297 * Address cycle complete, setup and write the write
300 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
301 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
302 (hw->phy.mdio.prtad <<
303 IXGBE_MSCA_PHY_ADDR_SHIFT) |
304 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
306 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
309 * Check every 10 usec to see if the address cycle
310 * completed. The MDI Command bit will clear when the
311 * operation is complete
313 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
316 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
318 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
322 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
323 hw_dbg(hw, "PHY address cmd didn't complete\n");
324 status = IXGBE_ERR_PHY;
328 ixgbe_release_swfw_sync(hw, gssr);
335 * ixgbe_setup_phy_link_generic - Set and restart autoneg
336 * @hw: pointer to hardware structure
338 * Restart autonegotiation and PHY and waits for completion.
340 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
342 s32 status = IXGBE_NOT_IMPLEMENTED;
344 u32 max_time_out = 10;
348 * Set advertisement settings in PHY based on autoneg_advertised
349 * settings. If autoneg_advertised = 0, then advertise default values
350 * tnx devices cannot be "forced" to a autoneg 10G and fail. But can
353 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg);
355 if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL)
356 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
358 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
360 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg);
362 /* Restart PHY autonegotiation and wait for completion */
363 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, &autoneg_reg);
365 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
367 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, autoneg_reg);
369 /* Wait for autonegotiation to finish */
370 for (time_out = 0; time_out < max_time_out; time_out++) {
372 /* Restart PHY autonegotiation and wait for completion */
373 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
376 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
377 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) {
383 if (time_out == max_time_out)
384 status = IXGBE_ERR_LINK_SETUP;
390 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
391 * @hw: pointer to hardware structure
392 * @speed: new link speed
393 * @autoneg: true if autonegotiation enabled
395 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
396 ixgbe_link_speed speed,
398 bool autoneg_wait_to_complete)
402 * Clear autoneg_advertised and set new values based on input link
405 hw->phy.autoneg_advertised = 0;
407 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
408 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
410 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
411 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
413 /* Setup link based on the new speed settings */
414 hw->phy.ops.setup_link(hw);
420 * ixgbe_reset_phy_nl - Performs a PHY reset
421 * @hw: pointer to hardware structure
423 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
425 u16 phy_offset, control, eword, edata, block_crc;
426 bool end_data = false;
427 u16 list_offset, data_offset;
432 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
434 /* reset the PHY and poll for completion */
435 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
436 (phy_data | MDIO_CTRL1_RESET));
438 for (i = 0; i < 100; i++) {
439 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
441 if ((phy_data & MDIO_CTRL1_RESET) == 0)
446 if ((phy_data & MDIO_CTRL1_RESET) != 0) {
447 hw_dbg(hw, "PHY reset did not complete.\n");
448 ret_val = IXGBE_ERR_PHY;
452 /* Get init offsets */
453 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
458 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
462 * Read control word from PHY init contents offset
464 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
465 control = (eword & IXGBE_CONTROL_MASK_NL) >>
466 IXGBE_CONTROL_SHIFT_NL;
467 edata = eword & IXGBE_DATA_MASK_NL;
471 hw_dbg(hw, "DELAY: %d MS\n", edata);
475 hw_dbg(hw, "DATA: \n");
477 hw->eeprom.ops.read(hw, data_offset++,
479 for (i = 0; i < edata; i++) {
480 hw->eeprom.ops.read(hw, data_offset, &eword);
481 hw->phy.ops.write_reg(hw, phy_offset,
482 MDIO_MMD_PMAPMD, eword);
483 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
489 case IXGBE_CONTROL_NL:
491 hw_dbg(hw, "CONTROL: \n");
492 if (edata == IXGBE_CONTROL_EOL_NL) {
495 } else if (edata == IXGBE_CONTROL_SOL_NL) {
498 hw_dbg(hw, "Bad control value\n");
499 ret_val = IXGBE_ERR_PHY;
504 hw_dbg(hw, "Bad control type\n");
505 ret_val = IXGBE_ERR_PHY;
515 * ixgbe_identify_sfp_module_generic - Identifies SFP module and assigns
517 * @hw: pointer to hardware structure
519 * Searches for and indentifies the SFP module. Assings appropriate PHY type.
521 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
523 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
525 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
527 u8 comp_codes_1g = 0;
528 u8 comp_codes_10g = 0;
529 u8 oui_bytes[3] = {0, 0, 0};
533 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
534 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
535 status = IXGBE_ERR_SFP_NOT_PRESENT;
539 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
542 if (status == IXGBE_ERR_SFP_NOT_PRESENT || status == IXGBE_ERR_I2C) {
543 status = IXGBE_ERR_SFP_NOT_PRESENT;
544 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
545 if (hw->phy.type != ixgbe_phy_nl) {
547 hw->phy.type = ixgbe_phy_unknown;
552 if (identifier == IXGBE_SFF_IDENTIFIER_SFP) {
553 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES,
555 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES,
557 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_CABLE_TECHNOLOGY,
565 * 3 SFP_DA_CORE0 - 82599-specific
566 * 4 SFP_DA_CORE1 - 82599-specific
567 * 5 SFP_SR/LR_CORE0 - 82599-specific
568 * 6 SFP_SR/LR_CORE1 - 82599-specific
570 if (hw->mac.type == ixgbe_mac_82598EB) {
571 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
572 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
573 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
574 hw->phy.sfp_type = ixgbe_sfp_type_sr;
575 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
576 hw->phy.sfp_type = ixgbe_sfp_type_lr;
578 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
579 } else if (hw->mac.type == ixgbe_mac_82599EB) {
580 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
581 if (hw->bus.lan_id == 0)
583 ixgbe_sfp_type_da_cu_core0;
586 ixgbe_sfp_type_da_cu_core1;
587 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
588 if (hw->bus.lan_id == 0)
590 ixgbe_sfp_type_srlr_core0;
593 ixgbe_sfp_type_srlr_core1;
594 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
595 if (hw->bus.lan_id == 0)
597 ixgbe_sfp_type_srlr_core0;
600 ixgbe_sfp_type_srlr_core1;
602 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
605 if (hw->phy.sfp_type != stored_sfp_type)
606 hw->phy.sfp_setup_needed = true;
608 /* Determine if the SFP+ PHY is dual speed or not. */
609 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
610 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
611 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
612 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
613 hw->phy.multispeed_fiber = true;
615 /* Determine PHY vendor */
616 if (hw->phy.type != ixgbe_phy_nl) {
617 hw->phy.id = identifier;
618 hw->phy.ops.read_i2c_eeprom(hw,
619 IXGBE_SFF_VENDOR_OUI_BYTE0,
621 hw->phy.ops.read_i2c_eeprom(hw,
622 IXGBE_SFF_VENDOR_OUI_BYTE1,
624 hw->phy.ops.read_i2c_eeprom(hw,
625 IXGBE_SFF_VENDOR_OUI_BYTE2,
629 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
630 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
631 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
633 switch (vendor_oui) {
634 case IXGBE_SFF_VENDOR_OUI_TYCO:
635 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
636 hw->phy.type = ixgbe_phy_tw_tyco;
638 case IXGBE_SFF_VENDOR_OUI_FTL:
639 hw->phy.type = ixgbe_phy_sfp_ftl;
641 case IXGBE_SFF_VENDOR_OUI_AVAGO:
642 hw->phy.type = ixgbe_phy_sfp_avago;
644 case IXGBE_SFF_VENDOR_OUI_INTEL:
645 hw->phy.type = ixgbe_phy_sfp_intel;
648 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
649 hw->phy.type = ixgbe_phy_tw_unknown;
651 hw->phy.type = ixgbe_phy_sfp_unknown;
656 /* All passive DA cables are supported */
657 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
662 /* 1G SFP modules are not supported */
663 if (comp_codes_10g == 0) {
664 hw->phy.type = ixgbe_phy_sfp_unsupported;
665 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
669 /* Anything else 82598-based is supported */
670 if (hw->mac.type == ixgbe_mac_82598EB) {
675 /* This is guaranteed to be 82599, no need to check for NULL */
676 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
677 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
678 /* Make sure we're a supported PHY type */
679 if (hw->phy.type == ixgbe_phy_sfp_intel) {
682 hw_dbg(hw, "SFP+ module not supported\n");
683 hw->phy.type = ixgbe_phy_sfp_unsupported;
684 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
696 * ixgbe_get_sfp_init_sequence_offsets - Checks the MAC's EEPROM to see
697 * if it supports a given SFP+ module type, if so it returns the offsets to the
698 * phy init sequence block.
699 * @hw: pointer to hardware structure
700 * @list_offset: offset to the SFP ID list
701 * @data_offset: offset to the SFP data block
703 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
709 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
710 return IXGBE_ERR_SFP_NOT_SUPPORTED;
712 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
713 return IXGBE_ERR_SFP_NOT_PRESENT;
715 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
716 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
717 return IXGBE_ERR_SFP_NOT_SUPPORTED;
719 /* Read offset to PHY init contents */
720 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
722 if ((!*list_offset) || (*list_offset == 0xFFFF))
723 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
725 /* Shift offset to first ID word */
729 * Find the matching SFP ID in the EEPROM
730 * and program the init sequence
732 hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
734 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
735 if (sfp_id == hw->phy.sfp_type) {
737 hw->eeprom.ops.read(hw, *list_offset, data_offset);
738 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
739 hw_dbg(hw, "SFP+ module not supported\n");
740 return IXGBE_ERR_SFP_NOT_SUPPORTED;
746 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
747 return IXGBE_ERR_PHY;
751 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
752 hw_dbg(hw, "No matching SFP+ module found\n");
753 return IXGBE_ERR_SFP_NOT_SUPPORTED;
760 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
761 * @hw: pointer to hardware structure
762 * @byte_offset: EEPROM byte offset to read
763 * @eeprom_data: value read
765 * Performs byte read operation to SFP module's EEPROM over I2C interface.
767 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
770 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
771 IXGBE_I2C_EEPROM_DEV_ADDR,
776 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
777 * @hw: pointer to hardware structure
778 * @byte_offset: EEPROM byte offset to write
779 * @eeprom_data: value to write
781 * Performs byte write operation to SFP module's EEPROM over I2C interface.
783 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
786 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
787 IXGBE_I2C_EEPROM_DEV_ADDR,
792 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
793 * @hw: pointer to hardware structure
794 * @byte_offset: byte offset to read
797 * Performs byte read operation to SFP module's EEPROM over I2C interface at
798 * a specified deivce address.
800 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
801 u8 dev_addr, u8 *data)
811 /* Device Address and write indication */
812 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
816 status = ixgbe_get_i2c_ack(hw);
820 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
824 status = ixgbe_get_i2c_ack(hw);
830 /* Device Address and read indication */
831 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
835 status = ixgbe_get_i2c_ack(hw);
839 status = ixgbe_clock_in_i2c_byte(hw, data);
843 status = ixgbe_clock_out_i2c_bit(hw, nack);
851 ixgbe_i2c_bus_clear(hw);
853 if (retry < max_retry)
854 hw_dbg(hw, "I2C byte read error - Retrying.\n");
856 hw_dbg(hw, "I2C byte read error.\n");
858 } while (retry < max_retry);
864 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
865 * @hw: pointer to hardware structure
866 * @byte_offset: byte offset to write
867 * @data: value to write
869 * Performs byte write operation to SFP module's EEPROM over I2C interface at
870 * a specified device address.
872 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
873 u8 dev_addr, u8 data)
882 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
886 status = ixgbe_get_i2c_ack(hw);
890 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
894 status = ixgbe_get_i2c_ack(hw);
898 status = ixgbe_clock_out_i2c_byte(hw, data);
902 status = ixgbe_get_i2c_ack(hw);
910 ixgbe_i2c_bus_clear(hw);
912 if (retry < max_retry)
913 hw_dbg(hw, "I2C byte write error - Retrying.\n");
915 hw_dbg(hw, "I2C byte write error.\n");
916 } while (retry < max_retry);
922 * ixgbe_i2c_start - Sets I2C start condition
923 * @hw: pointer to hardware structure
925 * Sets I2C start condition (High -> Low on SDA while SCL is High)
927 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
929 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
931 /* Start condition must begin with data and clock high */
932 ixgbe_set_i2c_data(hw, &i2cctl, 1);
933 ixgbe_raise_i2c_clk(hw, &i2cctl);
935 /* Setup time for start condition (4.7us) */
936 udelay(IXGBE_I2C_T_SU_STA);
938 ixgbe_set_i2c_data(hw, &i2cctl, 0);
940 /* Hold time for start condition (4us) */
941 udelay(IXGBE_I2C_T_HD_STA);
943 ixgbe_lower_i2c_clk(hw, &i2cctl);
945 /* Minimum low period of clock is 4.7 us */
946 udelay(IXGBE_I2C_T_LOW);
951 * ixgbe_i2c_stop - Sets I2C stop condition
952 * @hw: pointer to hardware structure
954 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
956 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
958 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
960 /* Stop condition must begin with data low and clock high */
961 ixgbe_set_i2c_data(hw, &i2cctl, 0);
962 ixgbe_raise_i2c_clk(hw, &i2cctl);
964 /* Setup time for stop condition (4us) */
965 udelay(IXGBE_I2C_T_SU_STO);
967 ixgbe_set_i2c_data(hw, &i2cctl, 1);
969 /* bus free time between stop and start (4.7us)*/
970 udelay(IXGBE_I2C_T_BUF);
974 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
975 * @hw: pointer to hardware structure
976 * @data: data byte to clock in
978 * Clocks in one byte data via I2C data/clock
980 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
986 for (i = 7; i >= 0; i--) {
987 status = ixgbe_clock_in_i2c_bit(hw, &bit);
998 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
999 * @hw: pointer to hardware structure
1000 * @data: data byte clocked out
1002 * Clocks out one byte data via I2C data/clock
1004 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1011 for (i = 7; i >= 0; i--) {
1012 bit = (data >> i) & 0x1;
1013 status = ixgbe_clock_out_i2c_bit(hw, bit);
1019 /* Release SDA line (set high) */
1020 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1021 i2cctl |= IXGBE_I2C_DATA_OUT;
1022 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1028 * ixgbe_get_i2c_ack - Polls for I2C ACK
1029 * @hw: pointer to hardware structure
1031 * Clocks in/out one bit via I2C data/clock
1033 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1037 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1041 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1046 /* Minimum high period of clock is 4us */
1047 udelay(IXGBE_I2C_T_HIGH);
1049 /* Poll for ACK. Note that ACK in I2C spec is
1050 * transition from 1 to 0 */
1051 for (i = 0; i < timeout; i++) {
1052 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1053 ack = ixgbe_get_i2c_data(&i2cctl);
1061 hw_dbg(hw, "I2C ack was not received.\n");
1062 status = IXGBE_ERR_I2C;
1065 ixgbe_lower_i2c_clk(hw, &i2cctl);
1067 /* Minimum low period of clock is 4.7 us */
1068 udelay(IXGBE_I2C_T_LOW);
1075 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1076 * @hw: pointer to hardware structure
1077 * @data: read data value
1079 * Clocks in one bit via I2C data/clock
1081 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1084 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1086 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1088 /* Minimum high period of clock is 4us */
1089 udelay(IXGBE_I2C_T_HIGH);
1091 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1092 *data = ixgbe_get_i2c_data(&i2cctl);
1094 ixgbe_lower_i2c_clk(hw, &i2cctl);
1096 /* Minimum low period of clock is 4.7 us */
1097 udelay(IXGBE_I2C_T_LOW);
1103 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1104 * @hw: pointer to hardware structure
1105 * @data: data value to write
1107 * Clocks out one bit via I2C data/clock
1109 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1112 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1114 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1116 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1118 /* Minimum high period of clock is 4us */
1119 udelay(IXGBE_I2C_T_HIGH);
1121 ixgbe_lower_i2c_clk(hw, &i2cctl);
1123 /* Minimum low period of clock is 4.7 us.
1124 * This also takes care of the data hold time.
1126 udelay(IXGBE_I2C_T_LOW);
1128 status = IXGBE_ERR_I2C;
1129 hw_dbg(hw, "I2C data was not set to %X\n", data);
1135 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1136 * @hw: pointer to hardware structure
1137 * @i2cctl: Current value of I2CCTL register
1139 * Raises the I2C clock line '0'->'1'
1141 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1145 *i2cctl |= IXGBE_I2C_CLK_OUT;
1147 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1149 /* SCL rise time (1000ns) */
1150 udelay(IXGBE_I2C_T_RISE);
1156 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1157 * @hw: pointer to hardware structure
1158 * @i2cctl: Current value of I2CCTL register
1160 * Lowers the I2C clock line '1'->'0'
1162 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1165 *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1167 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1169 /* SCL fall time (300ns) */
1170 udelay(IXGBE_I2C_T_FALL);
1174 * ixgbe_set_i2c_data - Sets the I2C data bit
1175 * @hw: pointer to hardware structure
1176 * @i2cctl: Current value of I2CCTL register
1177 * @data: I2C data value (0 or 1) to set
1179 * Sets the I2C data bit
1181 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1186 *i2cctl |= IXGBE_I2C_DATA_OUT;
1188 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1190 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1192 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1193 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1195 /* Verify data was set correctly */
1196 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1197 if (data != ixgbe_get_i2c_data(i2cctl)) {
1198 status = IXGBE_ERR_I2C;
1199 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
1206 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1207 * @hw: pointer to hardware structure
1208 * @i2cctl: Current value of I2CCTL register
1210 * Returns the I2C data bit value
1212 static bool ixgbe_get_i2c_data(u32 *i2cctl)
1216 if (*i2cctl & IXGBE_I2C_DATA_IN)
1225 * ixgbe_i2c_bus_clear - Clears the I2C bus
1226 * @hw: pointer to hardware structure
1228 * Clears the I2C bus by sending nine clock pulses.
1229 * Used when data line is stuck low.
1231 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1233 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1236 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1238 for (i = 0; i < 9; i++) {
1239 ixgbe_raise_i2c_clk(hw, &i2cctl);
1241 /* Min high period of clock is 4us */
1242 udelay(IXGBE_I2C_T_HIGH);
1244 ixgbe_lower_i2c_clk(hw, &i2cctl);
1246 /* Min low period of clock is 4.7us*/
1247 udelay(IXGBE_I2C_T_LOW);
1250 /* Put the i2c bus back to default state */
1255 * ixgbe_check_phy_link_tnx - Determine link and speed status
1256 * @hw: pointer to hardware structure
1258 * Reads the VS1 register to determine if link is up and the current speed for
1261 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1266 u32 max_time_out = 10;
1271 /* Initialize speed and link to default case */
1273 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1276 * Check current speed and link status of the PHY register.
1277 * This is a vendor specific register and may have to
1278 * be changed for other copper PHYs.
1280 for (time_out = 0; time_out < max_time_out; time_out++) {
1282 status = hw->phy.ops.read_reg(hw,
1283 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1286 phy_link = phy_data &
1287 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1288 phy_speed = phy_data &
1289 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1290 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1293 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1294 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1303 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1304 * @hw: pointer to hardware structure
1305 * @firmware_version: pointer to the PHY Firmware Version
1307 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1308 u16 *firmware_version)
1312 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, MDIO_MMD_VEND1,