2 * arch/sh/kernel/cpu/sh2a/clock-sh7201.c
4 * SH7201 support for the clock framework
6 * Copyright (C) 2008 Peter Griffin <pgriffin@mpc-data.co.uk>
9 * Copyright (C) 2005 Paul Mundt
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
15 #include <linux/init.h>
16 #include <linux/kernel.h>
17 #include <asm/clock.h>
21 const static int pll1rate[]={1,2,3,4,6,8};
22 const static int pfc_divisors[]={1,2,3,4,6,8,12};
23 #define ifc_divisors pfc_divisors
25 #if (CONFIG_SH_CLK_MD == 0)
27 #elif (CONFIG_SH_CLK_MD == 2)
29 #elif (CONFIG_SH_CLK_MD == 3)
32 #error "Illegal Clock Mode!"
35 static void master_clk_init(struct clk *clk)
37 clk->rate = 10000000 * PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007];
40 static struct clk_ops sh7201_master_clk_ops = {
41 .init = master_clk_init,
44 static void module_clk_recalc(struct clk *clk)
46 int idx = (ctrl_inw(FREQCR) & 0x0007);
47 clk->rate = clk->parent->rate / pfc_divisors[idx];
50 static struct clk_ops sh7201_module_clk_ops = {
51 .recalc = module_clk_recalc,
54 static void bus_clk_recalc(struct clk *clk)
56 int idx = (ctrl_inw(FREQCR) & 0x0007);
57 clk->rate = clk->parent->rate / pfc_divisors[idx];
60 static struct clk_ops sh7201_bus_clk_ops = {
61 .recalc = bus_clk_recalc,
64 static void cpu_clk_recalc(struct clk *clk)
66 int idx = ((ctrl_inw(FREQCR) >> 4) & 0x0007);
67 clk->rate = clk->parent->rate / ifc_divisors[idx];
70 static struct clk_ops sh7201_cpu_clk_ops = {
71 .recalc = cpu_clk_recalc,
74 static struct clk_ops *sh7201_clk_ops[] = {
75 &sh7201_master_clk_ops,
76 &sh7201_module_clk_ops,
81 void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
83 if (idx < ARRAY_SIZE(sh7201_clk_ops))
84 *ops = sh7201_clk_ops[idx];