git.oblomov.eu Git - linux-2.6/blob - arch/ppc/platforms/4xx/sycamore.c

   1 /*
   2  * Architecture- / platform-specific boot-time initialization code for
   3  * IBM PowerPC 4xx based boards.
   4  *
   5  * Author: Armin Kuster <akuster@mvista.com>
   6  *
   7  * 2000-2002 (c) MontaVista, Software, Inc.  This file is licensed under
   8  * the terms of the GNU General Public License version 2.  This program
   9  * is licensed "as is" without any warranty of any kind, whether express
  10  * or implied.
  11  */
  12 #include <linux/config.h>
  13 #include <linux/init.h>
  14 #include <linux/smp.h>
  15 #include <linux/threads.h>
  16 #include <linux/param.h>
  17 #include <linux/string.h>
  18 #include <linux/pci.h>
  19 #include <linux/rtc.h>
  20
  21 #include <asm/ocp.h>
  22 #include <asm/ppc4xx_pic.h>
  23 #include <asm/system.h>
  24 #include <asm/pci-bridge.h>
  25 #include <asm/machdep.h>
  26 #include <asm/page.h>
  27 #include <asm/time.h>
  28 #include <asm/io.h>
  29 #include <asm/ibm_ocp_pci.h>
  30 #include <asm/todc.h>
  31
  32 #undef DEBUG
  33
  34 #ifdef DEBUG
  35 #define DBG(x...) printk(x)
  36 #else
  37 #define DBG(x...)
  38 #endif
  39
  40 void *kb_cs;
  41 void *kb_data;
  42 void *sycamore_rtc_base;
  43
  44 /*
  45  * Define external IRQ senses and polarities.
  46  */
  47 unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
  48         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 7 */
  49         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 8 */
  50         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 9 */
  51         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 10 */
  52         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 11 */
  53         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 12 */
  54         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 0 */
  55         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 1 */
  56         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 2 */
  57         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 3 */
  58         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 4 */
  59         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 5 */
  60         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* Ext Int 6 */
  61 };
  62
  63
  64 /* Some IRQs unique to Sycamore.
  65  * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
  66  */
  67 int __init
  68 ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  69 {
  70         static char pci_irq_table[][4] =
  71             /*
  72              *      PCI IDSEL/INTPIN->INTLINE
  73              *      A       B       C       D
  74              */
  75         {
  76                 {28, 28, 28, 28},       /* IDSEL 1 - PCI slot 1 */
  77                 {29, 29, 29, 29},       /* IDSEL 2 - PCI slot 2 */
  78                 {30, 30, 30, 30},       /* IDSEL 3 - PCI slot 3 */
  79                 {31, 31, 31, 31},       /* IDSEL 4 - PCI slot 4 */
  80         };
  81
  82         const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
  83         return PCI_IRQ_TABLE_LOOKUP;
  84 };
  85
  86 void __init
  87 sycamore_setup_arch(void)
  88 {
  89         void *fpga_brdc;
  90         unsigned char fpga_brdc_data;
  91         void *fpga_enable;
  92         void *fpga_polarity;
  93         void *fpga_status;
  94         void *fpga_trigger;
  95
  96         ppc4xx_setup_arch();
  97
  98         ibm_ocp_set_emac(0, 0);
  99
 100         kb_data = ioremap(SYCAMORE_PS2_BASE, 8);
 101         if (!kb_data) {
 102                 printk(KERN_CRIT
 103                        "sycamore_setup_arch() kb_data ioremap failed\n");
 104                 return;
 105         }
 106
 107         kb_cs = kb_data + 1;
 108
 109         fpga_status = ioremap(PPC40x_FPGA_BASE, 8);
 110         if (!fpga_status) {
 111                 printk(KERN_CRIT
 112                        "sycamore_setup_arch() fpga_status ioremap failed\n");
 113                 return;
 114         }
 115
 116         fpga_enable = fpga_status + 1;
 117         fpga_polarity = fpga_status + 2;
 118         fpga_trigger = fpga_status + 3;
 119         fpga_brdc = fpga_status + 4;
 120
 121         /* split the keyboard and mouse interrupts */
 122         fpga_brdc_data = readb(fpga_brdc);
 123         fpga_brdc_data |= 0x80;
 124         writeb(fpga_brdc_data, fpga_brdc);
 125
 126         writeb(0x3, fpga_enable);
 127
 128         writeb(0x3, fpga_polarity);
 129
 130         writeb(0x3, fpga_trigger);
 131
 132         /* RTC step for the sycamore */
 133         sycamore_rtc_base = (void *) SYCAMORE_RTC_VADDR;
 134         TODC_INIT(TODC_TYPE_DS1743, sycamore_rtc_base, sycamore_rtc_base,
 135                   sycamore_rtc_base, 8);
 136
 137         /* Identify the system */
 138         printk(KERN_INFO "IBM Sycamore (IBM405GPr) Platform\n");
 139         printk(KERN_INFO
 140                "Port by MontaVista Software, Inc. (source@mvista.com)\n");
 141 }
 142
 143 void __init
 144 bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
 145 {
 146 #ifdef CONFIG_PCI
 147         unsigned int bar_response, bar;
 148         /*
 149          * Expected PCI mapping:
 150          *
 151          *  PLB addr             PCI memory addr
 152          *  ---------------------       ---------------------
 153          *  0000'0000 - 7fff'ffff <---  0000'0000 - 7fff'ffff
 154          *  8000'0000 - Bfff'ffff --->  8000'0000 - Bfff'ffff
 155          *
 156          *  PLB addr             PCI io addr
 157          *  ---------------------       ---------------------
 158          *  e800'0000 - e800'ffff --->  0000'0000 - 0001'0000
 159          *
 160          * The following code is simplified by assuming that the bootrom
 161          * has been well behaved in following this mapping.
 162          */
 163
 164 #ifdef DEBUG
 165         int i;
 166
 167         printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
 168         printk("PCI bridge regs before fixup \n");
 169         for (i = 0; i <= 3; i++) {
 170                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
 171                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
 172                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
 173                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
 174         }
 175         printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
 176         printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
 177         printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
 178         printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
 179
 180 #endif
 181
 182         /* added for IBM boot rom version 1.15 bios bar changes  -AK */
 183
 184         /* Disable region first */
 185         out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
 186         /* PLB starting addr, PCI: 0x80000000 */
 187         out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
 188         /* PCI start addr, 0x80000000 */
 189         out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
 190         /* 512MB range of PLB to PCI */
 191         out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
 192         /* Enable no pre-fetch, enable region */
 193         out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
 194                                                 (PPC405_PCI_UPPER_MEM -
 195                                                  PPC405_PCI_MEM_BASE)) | 0x01));
 196
 197         /* Enable inbound region one - 1GB size */
 198         out_le32((void *) &(pcip->ptm1ms), 0xc0000001);
 199
 200         /* Disable outbound region one */
 201         out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
 202         out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
 203         out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
 204         out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
 205         out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
 206
 207         /* Disable inbound region two */
 208         out_le32((void *) &(pcip->ptm2ms), 0x00000000);
 209
 210         /* Disable outbound region two */
 211         out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
 212         out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
 213         out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
 214         out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
 215         out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
 216
 217         /* Zero config bars */
 218         for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
 219                 early_write_config_dword(hose, hose->first_busno,
 220                                          PCI_FUNC(hose->first_busno), bar,
 221                                          0x00000000);
 222                 early_read_config_dword(hose, hose->first_busno,
 223                                         PCI_FUNC(hose->first_busno), bar,
 224                                         &bar_response);
 225                 DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
 226                     hose->first_busno, PCI_SLOT(hose->first_busno),
 227                     PCI_FUNC(hose->first_busno), bar, bar_response);
 228         }
 229         /* end work arround */
 230
 231 #ifdef DEBUG
 232         printk("PCI bridge regs after fixup \n");
 233         for (i = 0; i <= 3; i++) {
 234                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
 235                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
 236                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
 237                 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
 238         }
 239         printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
 240         printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
 241         printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
 242         printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
 243
 244 #endif
 245 #endif
 246
 247 }
 248
 249 void __init
 250 sycamore_map_io(void)
 251 {
 252         ppc4xx_map_io();
 253         io_block_mapping(SYCAMORE_RTC_VADDR,
 254                          SYCAMORE_RTC_PADDR, SYCAMORE_RTC_SIZE, _PAGE_IO);
 255 }
 256
 257 void __init
 258 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 259               unsigned long r6, unsigned long r7)
 260 {
 261         ppc4xx_init(r3, r4, r5, r6, r7);
 262
 263         ppc_md.setup_arch = sycamore_setup_arch;
 264         ppc_md.setup_io_mappings = sycamore_map_io;
 265
 266 #ifdef CONFIG_GEN_RTC
 267         ppc_md.time_init = todc_time_init;
 268         ppc_md.set_rtc_time = todc_set_rtc_time;
 269         ppc_md.get_rtc_time = todc_get_rtc_time;
 270         ppc_md.nvram_read_val = todc_direct_read_val;
 271         ppc_md.nvram_write_val = todc_direct_write_val;
 272 #endif
 273 }