2 * MPC8xxx SPI controller driver.
4 * Maintainer: Kumar Gala
6 * Copyright (C) 2006 Polycom, Inc.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/bug.h>
18 #include <linux/errno.h>
19 #include <linux/err.h>
21 #include <linux/completion.h>
22 #include <linux/interrupt.h>
23 #include <linux/delay.h>
24 #include <linux/irq.h>
25 #include <linux/device.h>
26 #include <linux/spi/spi.h>
27 #include <linux/spi/spi_bitbang.h>
28 #include <linux/platform_device.h>
29 #include <linux/fsl_devices.h>
31 #include <linux/of_platform.h>
32 #include <linux/gpio.h>
33 #include <linux/of_gpio.h>
34 #include <linux/of_spi.h>
36 #include <sysdev/fsl_soc.h>
39 /* SPI Controller registers */
40 struct mpc8xxx_spi_reg {
50 /* SPI Controller mode register definitions */
51 #define SPMODE_LOOP (1 << 30)
52 #define SPMODE_CI_INACTIVEHIGH (1 << 29)
53 #define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
54 #define SPMODE_DIV16 (1 << 27)
55 #define SPMODE_REV (1 << 26)
56 #define SPMODE_MS (1 << 25)
57 #define SPMODE_ENABLE (1 << 24)
58 #define SPMODE_LEN(x) ((x) << 20)
59 #define SPMODE_PM(x) ((x) << 16)
60 #define SPMODE_OP (1 << 14)
61 #define SPMODE_CG(x) ((x) << 7)
64 * Default for SPI Mode:
65 * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
67 #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
68 SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
70 /* SPIE register values */
71 #define SPIE_NE 0x00000200 /* Not empty */
72 #define SPIE_NF 0x00000100 /* Not full */
74 /* SPIM register values */
75 #define SPIM_NE 0x00000200 /* Not empty */
76 #define SPIM_NF 0x00000100 /* Not full */
78 /* SPI Controller driver's private data. */
80 struct mpc8xxx_spi_reg __iomem *base;
82 /* rx & tx bufs from the spi_transfer */
86 /* functions to deal with different sized buffers */
87 void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
88 u32(*get_tx) (struct mpc8xxx_spi *);
93 unsigned nsecs; /* (clock cycle time)/2 */
95 u32 spibrg; /* SPIBRG input clock */
96 u32 rx_shift; /* RX data reg shift when in qe mode */
97 u32 tx_shift; /* TX data reg shift when in qe mode */
101 struct workqueue_struct *workqueue;
102 struct work_struct work;
104 struct list_head queue;
107 struct completion done;
110 struct spi_mpc8xxx_cs {
111 /* functions to deal with different sized buffers */
112 void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
113 u32 (*get_tx) (struct mpc8xxx_spi *);
114 u32 rx_shift; /* RX data reg shift when in qe mode */
115 u32 tx_shift; /* TX data reg shift when in qe mode */
116 u32 hw_mode; /* Holds HW mode register settings */
119 static inline void mpc8xxx_spi_write_reg(__be32 __iomem *reg, u32 val)
124 static inline u32 mpc8xxx_spi_read_reg(__be32 __iomem *reg)
129 #define MPC83XX_SPI_RX_BUF(type) \
131 void mpc8xxx_spi_rx_buf_##type(u32 data, struct mpc8xxx_spi *mpc8xxx_spi) \
133 type *rx = mpc8xxx_spi->rx; \
134 *rx++ = (type)(data >> mpc8xxx_spi->rx_shift); \
135 mpc8xxx_spi->rx = rx; \
138 #define MPC83XX_SPI_TX_BUF(type) \
140 u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi) \
143 const type *tx = mpc8xxx_spi->tx; \
146 data = *tx++ << mpc8xxx_spi->tx_shift; \
147 mpc8xxx_spi->tx = tx; \
151 MPC83XX_SPI_RX_BUF(u8)
152 MPC83XX_SPI_RX_BUF(u16)
153 MPC83XX_SPI_RX_BUF(u32)
154 MPC83XX_SPI_TX_BUF(u8)
155 MPC83XX_SPI_TX_BUF(u16)
156 MPC83XX_SPI_TX_BUF(u32)
158 static void mpc8xxx_spi_chipselect(struct spi_device *spi, int value)
160 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
161 struct fsl_spi_platform_data *pdata = spi->dev.parent->platform_data;
162 bool pol = spi->mode & SPI_CS_HIGH;
163 struct spi_mpc8xxx_cs *cs = spi->controller_state;
165 if (value == BITBANG_CS_INACTIVE) {
166 if (pdata->cs_control)
167 pdata->cs_control(spi, !pol);
170 if (value == BITBANG_CS_ACTIVE) {
171 u32 regval = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->mode);
173 mpc8xxx_spi->rx_shift = cs->rx_shift;
174 mpc8xxx_spi->tx_shift = cs->tx_shift;
175 mpc8xxx_spi->get_rx = cs->get_rx;
176 mpc8xxx_spi->get_tx = cs->get_tx;
178 if (cs->hw_mode != regval) {
180 __be32 __iomem *mode = &mpc8xxx_spi->base->mode;
182 regval = cs->hw_mode;
183 /* Turn off IRQs locally to minimize time that
186 local_irq_save(flags);
187 /* Turn off SPI unit prior changing mode */
188 mpc8xxx_spi_write_reg(mode, regval & ~SPMODE_ENABLE);
189 mpc8xxx_spi_write_reg(mode, regval);
190 local_irq_restore(flags);
192 if (pdata->cs_control)
193 pdata->cs_control(spi, pol);
198 int mpc8xxx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
200 struct mpc8xxx_spi *mpc8xxx_spi;
202 u8 bits_per_word, pm;
204 struct spi_mpc8xxx_cs *cs = spi->controller_state;
206 mpc8xxx_spi = spi_master_get_devdata(spi->master);
209 bits_per_word = t->bits_per_word;
216 /* spi_transfer level calls that work per-word */
218 bits_per_word = spi->bits_per_word;
220 /* Make sure its a bit width we support [4..16, 32] */
221 if ((bits_per_word < 4)
222 || ((bits_per_word > 16) && (bits_per_word != 32)))
226 hz = spi->max_speed_hz;
230 if (bits_per_word <= 8) {
231 cs->get_rx = mpc8xxx_spi_rx_buf_u8;
232 cs->get_tx = mpc8xxx_spi_tx_buf_u8;
233 if (mpc8xxx_spi->qe_mode) {
237 } else if (bits_per_word <= 16) {
238 cs->get_rx = mpc8xxx_spi_rx_buf_u16;
239 cs->get_tx = mpc8xxx_spi_tx_buf_u16;
240 if (mpc8xxx_spi->qe_mode) {
244 } else if (bits_per_word <= 32) {
245 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
246 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
250 if (mpc8xxx_spi->qe_mode && spi->mode & SPI_LSB_FIRST) {
252 if (bits_per_word <= 8)
258 mpc8xxx_spi->rx_shift = cs->rx_shift;
259 mpc8xxx_spi->tx_shift = cs->tx_shift;
260 mpc8xxx_spi->get_rx = cs->get_rx;
261 mpc8xxx_spi->get_tx = cs->get_tx;
263 if (bits_per_word == 32)
266 bits_per_word = bits_per_word - 1;
268 /* mask out bits we are going to set */
269 cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
272 cs->hw_mode |= SPMODE_LEN(bits_per_word);
274 if ((mpc8xxx_spi->spibrg / hz) > 64) {
275 cs->hw_mode |= SPMODE_DIV16;
276 pm = mpc8xxx_spi->spibrg / (hz * 64);
278 WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
279 "Will use %d Hz instead.\n", dev_name(&spi->dev),
280 hz, mpc8xxx_spi->spibrg / 1024);
284 pm = mpc8xxx_spi->spibrg / (hz * 4);
288 cs->hw_mode |= SPMODE_PM(pm);
289 regval = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->mode);
290 if (cs->hw_mode != regval) {
292 __be32 __iomem *mode = &mpc8xxx_spi->base->mode;
294 regval = cs->hw_mode;
295 /* Turn off IRQs locally to minimize time
296 * that SPI is disabled
298 local_irq_save(flags);
299 /* Turn off SPI unit prior changing mode */
300 mpc8xxx_spi_write_reg(mode, regval & ~SPMODE_ENABLE);
301 mpc8xxx_spi_write_reg(mode, regval);
302 local_irq_restore(flags);
307 static int mpc8xxx_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
309 struct mpc8xxx_spi *mpc8xxx_spi;
310 u32 word, len, bits_per_word;
312 mpc8xxx_spi = spi_master_get_devdata(spi->master);
314 mpc8xxx_spi->tx = t->tx_buf;
315 mpc8xxx_spi->rx = t->rx_buf;
316 bits_per_word = spi->bits_per_word;
317 if (t->bits_per_word)
318 bits_per_word = t->bits_per_word;
320 if (bits_per_word > 8) {
321 /* invalid length? */
326 if (bits_per_word > 16) {
327 /* invalid length? */
332 mpc8xxx_spi->count = len;
334 INIT_COMPLETION(mpc8xxx_spi->done);
337 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, SPIM_NE);
340 word = mpc8xxx_spi->get_tx(mpc8xxx_spi);
341 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->transmit, word);
343 wait_for_completion(&mpc8xxx_spi->done);
345 /* disable rx ints */
346 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0);
348 return mpc8xxx_spi->count;
351 static void mpc8xxx_spi_do_one_msg(struct spi_message *m)
353 struct spi_device *spi = m->spi;
354 struct spi_transfer *t;
355 unsigned int cs_change;
356 const int nsecs = 50;
361 list_for_each_entry(t, &m->transfers, transfer_list) {
362 if (t->bits_per_word || t->speed_hz) {
363 /* Don't allow changes if CS is active */
367 status = mpc8xxx_spi_setup_transfer(spi, t);
373 mpc8xxx_spi_chipselect(spi, BITBANG_CS_ACTIVE);
376 cs_change = t->cs_change;
378 status = mpc8xxx_spi_bufs(spi, t);
383 m->actual_length += t->len;
386 udelay(t->delay_usecs);
390 mpc8xxx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
396 m->complete(m->context);
398 if (status || !cs_change) {
400 mpc8xxx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
403 mpc8xxx_spi_setup_transfer(spi, NULL);
406 static void mpc8xxx_spi_work(struct work_struct *work)
408 struct mpc8xxx_spi *mpc8xxx_spi = container_of(work, struct mpc8xxx_spi,
411 spin_lock_irq(&mpc8xxx_spi->lock);
412 while (!list_empty(&mpc8xxx_spi->queue)) {
413 struct spi_message *m = container_of(mpc8xxx_spi->queue.next,
414 struct spi_message, queue);
416 list_del_init(&m->queue);
417 spin_unlock_irq(&mpc8xxx_spi->lock);
419 mpc8xxx_spi_do_one_msg(m);
421 spin_lock_irq(&mpc8xxx_spi->lock);
423 spin_unlock_irq(&mpc8xxx_spi->lock);
426 static int mpc8xxx_spi_setup(struct spi_device *spi)
428 struct mpc8xxx_spi *mpc8xxx_spi;
431 struct spi_mpc8xxx_cs *cs = spi->controller_state;
433 if (!spi->max_speed_hz)
437 cs = kzalloc(sizeof *cs, GFP_KERNEL);
440 spi->controller_state = cs;
442 mpc8xxx_spi = spi_master_get_devdata(spi->master);
444 hw_mode = cs->hw_mode; /* Save orginal settings */
445 cs->hw_mode = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->mode);
446 /* mask out bits we are going to set */
447 cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
448 | SPMODE_REV | SPMODE_LOOP);
450 if (spi->mode & SPI_CPHA)
451 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
452 if (spi->mode & SPI_CPOL)
453 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
454 if (!(spi->mode & SPI_LSB_FIRST))
455 cs->hw_mode |= SPMODE_REV;
456 if (spi->mode & SPI_LOOP)
457 cs->hw_mode |= SPMODE_LOOP;
459 retval = mpc8xxx_spi_setup_transfer(spi, NULL);
461 cs->hw_mode = hw_mode; /* Restore settings */
467 static irqreturn_t mpc8xxx_spi_irq(s32 irq, void *context_data)
469 struct mpc8xxx_spi *mpc8xxx_spi = context_data;
471 irqreturn_t ret = IRQ_NONE;
473 /* Get interrupt events(tx/rx) */
474 event = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->event);
476 /* We need handle RX first */
477 if (event & SPIE_NE) {
478 u32 rx_data = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->receive);
481 mpc8xxx_spi->get_rx(rx_data, mpc8xxx_spi);
486 if ((event & SPIE_NF) == 0)
487 /* spin until TX is done */
489 mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->event)) &
493 mpc8xxx_spi->count -= 1;
494 if (mpc8xxx_spi->count) {
495 u32 word = mpc8xxx_spi->get_tx(mpc8xxx_spi);
496 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->transmit, word);
498 complete(&mpc8xxx_spi->done);
501 /* Clear the events */
502 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->event, event);
506 static int mpc8xxx_spi_transfer(struct spi_device *spi,
507 struct spi_message *m)
509 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
512 m->actual_length = 0;
513 m->status = -EINPROGRESS;
515 spin_lock_irqsave(&mpc8xxx_spi->lock, flags);
516 list_add_tail(&m->queue, &mpc8xxx_spi->queue);
517 queue_work(mpc8xxx_spi->workqueue, &mpc8xxx_spi->work);
518 spin_unlock_irqrestore(&mpc8xxx_spi->lock, flags);
524 static void mpc8xxx_spi_cleanup(struct spi_device *spi)
526 kfree(spi->controller_state);
529 static struct spi_master * __devinit
530 mpc8xxx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq)
532 struct fsl_spi_platform_data *pdata = dev->platform_data;
533 struct spi_master *master;
534 struct mpc8xxx_spi *mpc8xxx_spi;
538 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
539 if (master == NULL) {
544 dev_set_drvdata(dev, master);
546 /* the spi->mode bits understood by this driver: */
547 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH
548 | SPI_LSB_FIRST | SPI_LOOP;
550 master->setup = mpc8xxx_spi_setup;
551 master->transfer = mpc8xxx_spi_transfer;
552 master->cleanup = mpc8xxx_spi_cleanup;
554 mpc8xxx_spi = spi_master_get_devdata(master);
555 mpc8xxx_spi->qe_mode = pdata->qe_mode;
556 mpc8xxx_spi->get_rx = mpc8xxx_spi_rx_buf_u8;
557 mpc8xxx_spi->get_tx = mpc8xxx_spi_tx_buf_u8;
558 mpc8xxx_spi->spibrg = pdata->sysclk;
560 mpc8xxx_spi->rx_shift = 0;
561 mpc8xxx_spi->tx_shift = 0;
562 if (mpc8xxx_spi->qe_mode) {
563 mpc8xxx_spi->rx_shift = 16;
564 mpc8xxx_spi->tx_shift = 24;
567 init_completion(&mpc8xxx_spi->done);
569 mpc8xxx_spi->base = ioremap(mem->start, mem->end - mem->start + 1);
570 if (mpc8xxx_spi->base == NULL) {
575 mpc8xxx_spi->irq = irq;
577 /* Register for SPI Interrupt */
578 ret = request_irq(mpc8xxx_spi->irq, mpc8xxx_spi_irq,
579 0, "mpc8xxx_spi", mpc8xxx_spi);
584 master->bus_num = pdata->bus_num;
585 master->num_chipselect = pdata->max_chipselect;
587 /* SPI controller initializations */
588 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, 0);
589 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0);
590 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->command, 0);
591 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->event, 0xffffffff);
593 /* Enable SPI interface */
594 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
598 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, regval);
599 spin_lock_init(&mpc8xxx_spi->lock);
600 init_completion(&mpc8xxx_spi->done);
601 INIT_WORK(&mpc8xxx_spi->work, mpc8xxx_spi_work);
602 INIT_LIST_HEAD(&mpc8xxx_spi->queue);
604 mpc8xxx_spi->workqueue = create_singlethread_workqueue(
605 dev_name(master->dev.parent));
606 if (mpc8xxx_spi->workqueue == NULL) {
611 ret = spi_register_master(master);
616 "%s: MPC8xxx SPI Controller driver at 0x%p (irq = %d)\n",
617 dev_name(dev), mpc8xxx_spi->base, mpc8xxx_spi->irq);
622 destroy_workqueue(mpc8xxx_spi->workqueue);
624 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
626 iounmap(mpc8xxx_spi->base);
628 spi_master_put(master);
633 static int __devexit mpc8xxx_spi_remove(struct device *dev)
635 struct mpc8xxx_spi *mpc8xxx_spi;
636 struct spi_master *master;
638 master = dev_get_drvdata(dev);
639 mpc8xxx_spi = spi_master_get_devdata(master);
641 flush_workqueue(mpc8xxx_spi->workqueue);
642 destroy_workqueue(mpc8xxx_spi->workqueue);
643 spi_unregister_master(master);
645 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
646 iounmap(mpc8xxx_spi->base);
651 struct mpc8xxx_spi_probe_info {
652 struct fsl_spi_platform_data pdata;
657 static struct mpc8xxx_spi_probe_info *
658 to_of_pinfo(struct fsl_spi_platform_data *pdata)
660 return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata);
663 static void mpc8xxx_spi_cs_control(struct spi_device *spi, bool on)
665 struct device *dev = spi->dev.parent;
666 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data);
667 u16 cs = spi->chip_select;
668 int gpio = pinfo->gpios[cs];
669 bool alow = pinfo->alow_flags[cs];
671 gpio_set_value(gpio, on ^ alow);
674 static int of_mpc8xxx_spi_get_chipselects(struct device *dev)
676 struct device_node *np = dev_archdata_get_node(&dev->archdata);
677 struct fsl_spi_platform_data *pdata = dev->platform_data;
678 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
683 ngpios = of_gpio_count(np);
686 * SPI w/o chip-select line. One SPI device is still permitted
689 pdata->max_chipselect = 1;
693 pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL);
696 memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios));
698 pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags),
700 if (!pinfo->alow_flags) {
702 goto err_alloc_flags;
705 for (; i < ngpios; i++) {
707 enum of_gpio_flags flags;
709 gpio = of_get_gpio_flags(np, i, &flags);
710 if (!gpio_is_valid(gpio)) {
711 dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
715 ret = gpio_request(gpio, dev_name(dev));
717 dev_err(dev, "can't request gpio #%d: %d\n", i, ret);
721 pinfo->gpios[i] = gpio;
722 pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW;
724 ret = gpio_direction_output(pinfo->gpios[i],
725 pinfo->alow_flags[i]);
727 dev_err(dev, "can't set output direction for gpio "
728 "#%d: %d\n", i, ret);
733 pdata->max_chipselect = ngpios;
734 pdata->cs_control = mpc8xxx_spi_cs_control;
740 if (gpio_is_valid(pinfo->gpios[i]))
741 gpio_free(pinfo->gpios[i]);
745 kfree(pinfo->alow_flags);
746 pinfo->alow_flags = NULL;
753 static int of_mpc8xxx_spi_free_chipselects(struct device *dev)
755 struct fsl_spi_platform_data *pdata = dev->platform_data;
756 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
762 for (i = 0; i < pdata->max_chipselect; i++) {
763 if (gpio_is_valid(pinfo->gpios[i]))
764 gpio_free(pinfo->gpios[i]);
768 kfree(pinfo->alow_flags);
772 static int __devinit of_mpc8xxx_spi_probe(struct of_device *ofdev,
773 const struct of_device_id *ofid)
775 struct device *dev = &ofdev->dev;
776 struct device_node *np = ofdev->node;
777 struct mpc8xxx_spi_probe_info *pinfo;
778 struct fsl_spi_platform_data *pdata;
779 struct spi_master *master;
785 pinfo = kzalloc(sizeof(*pinfo), GFP_KERNEL);
789 pdata = &pinfo->pdata;
790 dev->platform_data = pdata;
792 /* Allocate bus num dynamically. */
795 /* SPI controller is either clocked from QE or SoC clock. */
796 pdata->sysclk = get_brgfreq();
797 if (pdata->sysclk == -1) {
798 pdata->sysclk = fsl_get_sys_freq();
799 if (pdata->sysclk == -1) {
805 prop = of_get_property(np, "mode", NULL);
806 if (prop && !strcmp(prop, "cpu-qe"))
809 ret = of_mpc8xxx_spi_get_chipselects(dev);
813 ret = of_address_to_resource(np, 0, &mem);
817 ret = of_irq_to_resource(np, 0, &irq);
823 master = mpc8xxx_spi_probe(dev, &mem, irq.start);
824 if (IS_ERR(master)) {
825 ret = PTR_ERR(master);
829 of_register_spi_devices(master, np);
834 of_mpc8xxx_spi_free_chipselects(dev);
840 static int __devexit of_mpc8xxx_spi_remove(struct of_device *ofdev)
844 ret = mpc8xxx_spi_remove(&ofdev->dev);
847 of_mpc8xxx_spi_free_chipselects(&ofdev->dev);
851 static const struct of_device_id of_mpc8xxx_spi_match[] = {
852 { .compatible = "fsl,spi" },
855 MODULE_DEVICE_TABLE(of, of_mpc8xxx_spi_match);
857 static struct of_platform_driver of_mpc8xxx_spi_driver = {
858 .name = "mpc8xxx_spi",
859 .match_table = of_mpc8xxx_spi_match,
860 .probe = of_mpc8xxx_spi_probe,
861 .remove = __devexit_p(of_mpc8xxx_spi_remove),
864 #ifdef CONFIG_MPC832x_RDB
867 * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
868 * only. The driver should go away soon, since newer MPC8323E-RDB's device
869 * tree can work with OpenFirmware driver. But for now we support old trees
872 static int __devinit plat_mpc8xxx_spi_probe(struct platform_device *pdev)
874 struct resource *mem;
876 struct spi_master *master;
878 if (!pdev->dev.platform_data)
881 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
885 irq = platform_get_irq(pdev, 0);
889 master = mpc8xxx_spi_probe(&pdev->dev, mem, irq);
891 return PTR_ERR(master);
895 static int __devexit plat_mpc8xxx_spi_remove(struct platform_device *pdev)
897 return mpc8xxx_spi_remove(&pdev->dev);
900 MODULE_ALIAS("platform:mpc8xxx_spi");
901 static struct platform_driver mpc8xxx_spi_driver = {
902 .probe = plat_mpc8xxx_spi_probe,
903 .remove = __exit_p(plat_mpc8xxx_spi_remove),
905 .name = "mpc8xxx_spi",
906 .owner = THIS_MODULE,
910 static bool legacy_driver_failed;
912 static void __init legacy_driver_register(void)
914 legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
917 static void __exit legacy_driver_unregister(void)
919 if (legacy_driver_failed)
921 platform_driver_unregister(&mpc8xxx_spi_driver);
924 static void __init legacy_driver_register(void) {}
925 static void __exit legacy_driver_unregister(void) {}
926 #endif /* CONFIG_MPC832x_RDB */
928 static int __init mpc8xxx_spi_init(void)
930 legacy_driver_register();
931 return of_register_platform_driver(&of_mpc8xxx_spi_driver);
934 static void __exit mpc8xxx_spi_exit(void)
936 of_unregister_platform_driver(&of_mpc8xxx_spi_driver);
937 legacy_driver_unregister();
940 module_init(mpc8xxx_spi_init);
941 module_exit(mpc8xxx_spi_exit);
943 MODULE_AUTHOR("Kumar Gala");
944 MODULE_DESCRIPTION("Simple MPC8xxx SPI Driver");
945 MODULE_LICENSE("GPL");