2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/netdevice.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/pci.h>
35 #include <linux/tcp.h>
37 #include <linux/delay.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/debugfs.h>
42 #include <linux/mii.h>
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.22"
54 #define PFX DRV_NAME " "
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
62 #define RX_LE_SIZE 1024
63 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
64 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
65 #define RX_DEF_PENDING RX_MAX_PENDING
67 #define TX_RING_SIZE 512
68 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
69 #define TX_MIN_PENDING 64
70 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
72 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
73 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
74 #define TX_WATCHDOG (5 * HZ)
75 #define NAPI_WEIGHT 64
76 #define PHY_RETRIES 1000
78 #define SKY2_EEPROM_MAGIC 0x9955aabb
81 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83 static const u32 default_msg =
84 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
85 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
86 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
88 static int debug = -1; /* defaults above */
89 module_param(debug, int, 0);
90 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92 static int copybreak __read_mostly = 128;
93 module_param(copybreak, int, 0);
94 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96 static int disable_msi = 0;
97 module_param(disable_msi, int, 0);
98 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
143 MODULE_DEVICE_TABLE(pci, sky2_id_table);
145 /* Avoid conditionals by using array */
146 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
147 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
148 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
150 static void sky2_set_multicast(struct net_device *dev);
152 /* Access to PHY via serial interconnect */
153 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
157 gma_write16(hw, port, GM_SMI_DATA, val);
158 gma_write16(hw, port, GM_SMI_CTRL,
159 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
161 for (i = 0; i < PHY_RETRIES; i++) {
162 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
166 if (!(ctrl & GM_SMI_CT_BUSY))
172 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
176 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
180 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
184 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
185 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
187 for (i = 0; i < PHY_RETRIES; i++) {
188 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
192 if (ctrl & GM_SMI_CT_RD_VAL) {
193 *val = gma_read16(hw, port, GM_SMI_DATA);
200 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
203 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
207 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
210 __gm_phy_read(hw, port, reg, &v);
215 static void sky2_power_on(struct sky2_hw *hw)
217 /* switch power to VCC (WA for VAUX problem) */
218 sky2_write8(hw, B0_POWER_CTRL,
219 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
221 /* disable Core Clock Division, */
222 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
224 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
225 /* enable bits are inverted */
226 sky2_write8(hw, B2_Y2_CLK_GATE,
227 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
228 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
229 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
231 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
233 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
236 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
238 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
239 /* set all bits to 0 except bits 15..12 and 8 */
240 reg &= P_ASPM_CONTROL_MSK;
241 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
243 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
244 /* set all bits to 0 except bits 28 & 27 */
245 reg &= P_CTL_TIM_VMAIN_AV_MSK;
246 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
248 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
250 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
251 reg = sky2_read32(hw, B2_GP_IO);
252 reg |= GLB_GPIO_STAT_RACE_DIS;
253 sky2_write32(hw, B2_GP_IO, reg);
255 sky2_read32(hw, B2_GP_IO);
259 static void sky2_power_aux(struct sky2_hw *hw)
261 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
262 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
264 /* enable bits are inverted */
265 sky2_write8(hw, B2_Y2_CLK_GATE,
266 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
267 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
268 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
270 /* switch power to VAUX */
271 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
272 sky2_write8(hw, B0_POWER_CTRL,
273 (PC_VAUX_ENA | PC_VCC_ENA |
274 PC_VAUX_ON | PC_VCC_OFF));
277 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
281 /* disable all GMAC IRQ's */
282 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
284 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
285 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
286 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
287 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
289 reg = gma_read16(hw, port, GM_RX_CTRL);
290 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
291 gma_write16(hw, port, GM_RX_CTRL, reg);
294 /* flow control to advertise bits */
295 static const u16 copper_fc_adv[] = {
297 [FC_TX] = PHY_M_AN_ASP,
298 [FC_RX] = PHY_M_AN_PC,
299 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
302 /* flow control to advertise bits when using 1000BaseX */
303 static const u16 fiber_fc_adv[] = {
304 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
305 [FC_TX] = PHY_M_P_ASYM_MD_X,
306 [FC_RX] = PHY_M_P_SYM_MD_X,
307 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
310 /* flow control to GMA disable bits */
311 static const u16 gm_fc_disable[] = {
312 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
313 [FC_TX] = GM_GPCR_FC_RX_DIS,
314 [FC_RX] = GM_GPCR_FC_TX_DIS,
319 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
321 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
322 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
324 if (sky2->autoneg == AUTONEG_ENABLE &&
325 !(hw->flags & SKY2_HW_NEWER_PHY)) {
326 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
328 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
330 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
332 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
333 if (hw->chip_id == CHIP_ID_YUKON_EC)
334 /* set downshift counter to 3x and enable downshift */
335 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
337 /* set master & slave downshift counter to 1x */
338 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
340 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
343 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
344 if (sky2_is_copper(hw)) {
345 if (!(hw->flags & SKY2_HW_GIGABIT)) {
346 /* enable automatic crossover */
347 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
349 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
350 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
353 /* Enable Class A driver for FE+ A0 */
354 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
355 spec |= PHY_M_FESC_SEL_CL_A;
356 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
359 /* disable energy detect */
360 ctrl &= ~PHY_M_PC_EN_DET_MSK;
362 /* enable automatic crossover */
363 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
365 /* downshift on PHY 88E1112 and 88E1149 is changed */
366 if (sky2->autoneg == AUTONEG_ENABLE
367 && (hw->flags & SKY2_HW_NEWER_PHY)) {
368 /* set downshift counter to 3x and enable downshift */
369 ctrl &= ~PHY_M_PC_DSC_MSK;
370 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
374 /* workaround for deviation #4.88 (CRC errors) */
375 /* disable Automatic Crossover */
377 ctrl &= ~PHY_M_PC_MDIX_MSK;
380 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
382 /* special setup for PHY 88E1112 Fiber */
383 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
384 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
386 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
387 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
388 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
389 ctrl &= ~PHY_M_MAC_MD_MSK;
390 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
391 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
393 if (hw->pmd_type == 'P') {
394 /* select page 1 to access Fiber registers */
395 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
397 /* for SFP-module set SIGDET polarity to low */
398 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
399 ctrl |= PHY_M_FIB_SIGD_POL;
400 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
403 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
411 if (sky2->autoneg == AUTONEG_ENABLE) {
412 if (sky2_is_copper(hw)) {
413 if (sky2->advertising & ADVERTISED_1000baseT_Full)
414 ct1000 |= PHY_M_1000C_AFD;
415 if (sky2->advertising & ADVERTISED_1000baseT_Half)
416 ct1000 |= PHY_M_1000C_AHD;
417 if (sky2->advertising & ADVERTISED_100baseT_Full)
418 adv |= PHY_M_AN_100_FD;
419 if (sky2->advertising & ADVERTISED_100baseT_Half)
420 adv |= PHY_M_AN_100_HD;
421 if (sky2->advertising & ADVERTISED_10baseT_Full)
422 adv |= PHY_M_AN_10_FD;
423 if (sky2->advertising & ADVERTISED_10baseT_Half)
424 adv |= PHY_M_AN_10_HD;
426 adv |= copper_fc_adv[sky2->flow_mode];
427 } else { /* special defines for FIBER (88E1040S only) */
428 if (sky2->advertising & ADVERTISED_1000baseT_Full)
429 adv |= PHY_M_AN_1000X_AFD;
430 if (sky2->advertising & ADVERTISED_1000baseT_Half)
431 adv |= PHY_M_AN_1000X_AHD;
433 adv |= fiber_fc_adv[sky2->flow_mode];
436 /* Restart Auto-negotiation */
437 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
439 /* forced speed/duplex settings */
440 ct1000 = PHY_M_1000C_MSE;
442 /* Disable auto update for duplex flow control and speed */
443 reg |= GM_GPCR_AU_ALL_DIS;
445 switch (sky2->speed) {
447 ctrl |= PHY_CT_SP1000;
448 reg |= GM_GPCR_SPEED_1000;
451 ctrl |= PHY_CT_SP100;
452 reg |= GM_GPCR_SPEED_100;
456 if (sky2->duplex == DUPLEX_FULL) {
457 reg |= GM_GPCR_DUP_FULL;
458 ctrl |= PHY_CT_DUP_MD;
459 } else if (sky2->speed < SPEED_1000)
460 sky2->flow_mode = FC_NONE;
463 reg |= gm_fc_disable[sky2->flow_mode];
465 /* Forward pause packets to GMAC? */
466 if (sky2->flow_mode & FC_RX)
467 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
469 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
472 gma_write16(hw, port, GM_GP_CTRL, reg);
474 if (hw->flags & SKY2_HW_GIGABIT)
475 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
477 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
478 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
480 /* Setup Phy LED's */
481 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
484 switch (hw->chip_id) {
485 case CHIP_ID_YUKON_FE:
486 /* on 88E3082 these bits are at 11..9 (shifted left) */
487 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
489 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
491 /* delete ACT LED control bits */
492 ctrl &= ~PHY_M_FELP_LED1_MSK;
493 /* change ACT LED control to blink mode */
494 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
495 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
498 case CHIP_ID_YUKON_FE_P:
499 /* Enable Link Partner Next Page */
500 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
501 ctrl |= PHY_M_PC_ENA_LIP_NP;
503 /* disable Energy Detect and enable scrambler */
504 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
505 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
507 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
508 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
509 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
510 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
512 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
515 case CHIP_ID_YUKON_XL:
516 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
518 /* select page 3 to access LED control register */
519 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
521 /* set LED Function Control register */
522 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
523 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
524 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
525 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
526 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
528 /* set Polarity Control register */
529 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
530 (PHY_M_POLC_LS1_P_MIX(4) |
531 PHY_M_POLC_IS0_P_MIX(4) |
532 PHY_M_POLC_LOS_CTRL(2) |
533 PHY_M_POLC_INIT_CTRL(2) |
534 PHY_M_POLC_STA1_CTRL(2) |
535 PHY_M_POLC_STA0_CTRL(2)));
537 /* restore page register */
538 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
541 case CHIP_ID_YUKON_EC_U:
542 case CHIP_ID_YUKON_EX:
543 case CHIP_ID_YUKON_SUPR:
544 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
546 /* select page 3 to access LED control register */
547 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
549 /* set LED Function Control register */
550 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
551 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
552 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
553 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
554 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
556 /* set Blink Rate in LED Timer Control Register */
557 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
558 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
559 /* restore page register */
560 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
564 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
565 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
567 /* turn off the Rx LED (LED_RX) */
568 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
571 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
572 /* apply fixes in PHY AFE */
573 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
575 /* increase differential signal amplitude in 10BASE-T */
576 gm_phy_write(hw, port, 0x18, 0xaa99);
577 gm_phy_write(hw, port, 0x17, 0x2011);
579 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
580 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
581 gm_phy_write(hw, port, 0x18, 0xa204);
582 gm_phy_write(hw, port, 0x17, 0x2002);
585 /* set page register to 0 */
586 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
587 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
588 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
589 /* apply workaround for integrated resistors calibration */
590 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
591 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
592 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
593 hw->chip_id < CHIP_ID_YUKON_SUPR) {
594 /* no effect on Yukon-XL */
595 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
597 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
598 /* turn on 100 Mbps LED (LED_LINK100) */
599 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
603 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
607 /* Enable phy interrupt on auto-negotiation complete (or link up) */
608 if (sky2->autoneg == AUTONEG_ENABLE)
609 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
611 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
614 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
615 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
617 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
621 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
622 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
623 reg1 &= ~phy_power[port];
625 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
626 reg1 |= coma_mode[port];
628 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
629 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
630 sky2_pci_read32(hw, PCI_DEV_REG1);
632 if (hw->chip_id == CHIP_ID_YUKON_FE)
633 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
634 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
635 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
638 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
643 /* release GPHY Control reset */
644 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
646 /* release GMAC reset */
647 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
649 if (hw->flags & SKY2_HW_NEWER_PHY) {
650 /* select page 2 to access MAC control register */
651 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
653 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
654 /* allow GMII Power Down */
655 ctrl &= ~PHY_M_MAC_GMIF_PUP;
656 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
658 /* set page register back to 0 */
659 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
662 /* setup General Purpose Control Register */
663 gma_write16(hw, port, GM_GP_CTRL,
664 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
666 if (hw->chip_id != CHIP_ID_YUKON_EC) {
667 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
668 /* select page 2 to access MAC control register */
669 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
671 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
672 /* enable Power Down */
673 ctrl |= PHY_M_PC_POW_D_ENA;
674 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
676 /* set page register back to 0 */
677 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
680 /* set IEEE compatible Power Down Mode (dev. #4.99) */
681 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
684 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
685 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
686 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
687 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
688 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
691 /* Force a renegotiation */
692 static void sky2_phy_reinit(struct sky2_port *sky2)
694 spin_lock_bh(&sky2->phy_lock);
695 sky2_phy_init(sky2->hw, sky2->port);
696 spin_unlock_bh(&sky2->phy_lock);
699 /* Put device in state to listen for Wake On Lan */
700 static void sky2_wol_init(struct sky2_port *sky2)
702 struct sky2_hw *hw = sky2->hw;
703 unsigned port = sky2->port;
704 enum flow_control save_mode;
708 /* Bring hardware out of reset */
709 sky2_write16(hw, B0_CTST, CS_RST_CLR);
710 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
712 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
713 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
716 * sky2_reset will re-enable on resume
718 save_mode = sky2->flow_mode;
719 ctrl = sky2->advertising;
721 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
722 sky2->flow_mode = FC_NONE;
724 spin_lock_bh(&sky2->phy_lock);
725 sky2_phy_power_up(hw, port);
726 sky2_phy_init(hw, port);
727 spin_unlock_bh(&sky2->phy_lock);
729 sky2->flow_mode = save_mode;
730 sky2->advertising = ctrl;
732 /* Set GMAC to no flow control and auto update for speed/duplex */
733 gma_write16(hw, port, GM_GP_CTRL,
734 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
735 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
737 /* Set WOL address */
738 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
739 sky2->netdev->dev_addr, ETH_ALEN);
741 /* Turn on appropriate WOL control bits */
742 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
744 if (sky2->wol & WAKE_PHY)
745 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
747 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
749 if (sky2->wol & WAKE_MAGIC)
750 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
752 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
754 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
755 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
757 /* Turn on legacy PCI-Express PME mode */
758 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
759 reg1 |= PCI_Y2_PME_LEGACY;
760 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
763 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
767 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
769 struct net_device *dev = hw->dev[port];
771 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
772 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
773 hw->chip_id == CHIP_ID_YUKON_FE_P ||
774 hw->chip_id == CHIP_ID_YUKON_SUPR) {
775 /* Yukon-Extreme B0 and further Extreme devices */
776 /* enable Store & Forward mode for TX */
778 if (dev->mtu <= ETH_DATA_LEN)
779 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
780 TX_JUMBO_DIS | TX_STFW_ENA);
783 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
784 TX_JUMBO_ENA| TX_STFW_ENA);
786 if (dev->mtu <= ETH_DATA_LEN)
787 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
789 /* set Tx GMAC FIFO Almost Empty Threshold */
790 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
791 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
793 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
795 /* Can't do offload because of lack of store/forward */
796 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
801 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
803 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
807 const u8 *addr = hw->dev[port]->dev_addr;
809 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
810 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
812 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
814 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
815 /* WA DEV_472 -- looks like crossed wires on port 2 */
816 /* clear GMAC 1 Control reset */
817 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
819 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
820 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
821 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
822 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
823 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
826 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
828 /* Enable Transmit FIFO Underrun */
829 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
831 spin_lock_bh(&sky2->phy_lock);
832 sky2_phy_power_up(hw, port);
833 sky2_phy_init(hw, port);
834 spin_unlock_bh(&sky2->phy_lock);
837 reg = gma_read16(hw, port, GM_PHY_ADDR);
838 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
840 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
841 gma_read16(hw, port, i);
842 gma_write16(hw, port, GM_PHY_ADDR, reg);
844 /* transmit control */
845 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
847 /* receive control reg: unicast + multicast + no FCS */
848 gma_write16(hw, port, GM_RX_CTRL,
849 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
851 /* transmit flow control */
852 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
854 /* transmit parameter */
855 gma_write16(hw, port, GM_TX_PARAM,
856 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
857 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
858 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
859 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
861 /* serial mode register */
862 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
863 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
865 if (hw->dev[port]->mtu > ETH_DATA_LEN)
866 reg |= GM_SMOD_JUMBO_ENA;
868 gma_write16(hw, port, GM_SERIAL_MODE, reg);
870 /* virtual address for data */
871 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
873 /* physical address: used for pause frames */
874 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
876 /* ignore counter overflows */
877 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
878 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
879 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
881 /* Configure Rx MAC FIFO */
882 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
883 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
884 if (hw->chip_id == CHIP_ID_YUKON_EX ||
885 hw->chip_id == CHIP_ID_YUKON_FE_P)
886 rx_reg |= GMF_RX_OVER_ON;
888 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
890 if (hw->chip_id == CHIP_ID_YUKON_XL) {
891 /* Hardware errata - clear flush mask */
892 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
894 /* Flush Rx MAC FIFO on any flow control or error */
895 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
898 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
899 reg = RX_GMF_FL_THR_DEF + 1;
900 /* Another magic mystery workaround from sk98lin */
901 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
902 hw->chip_rev == CHIP_REV_YU_FE2_A0)
904 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
906 /* Configure Tx MAC FIFO */
907 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
908 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
910 /* On chips without ram buffer, pause is controled by MAC level */
911 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
912 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
913 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
915 sky2_set_tx_stfwd(hw, port);
918 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
919 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
920 /* disable dynamic watermark */
921 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
922 reg &= ~TX_DYN_WM_ENA;
923 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
927 /* Assign Ram Buffer allocation to queue */
928 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
932 /* convert from K bytes to qwords used for hw register */
935 end = start + space - 1;
937 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
938 sky2_write32(hw, RB_ADDR(q, RB_START), start);
939 sky2_write32(hw, RB_ADDR(q, RB_END), end);
940 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
941 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
943 if (q == Q_R1 || q == Q_R2) {
944 u32 tp = space - space/4;
946 /* On receive queue's set the thresholds
947 * give receiver priority when > 3/4 full
948 * send pause when down to 2K
950 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
951 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
954 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
955 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
957 /* Enable store & forward on Tx queue's because
958 * Tx FIFO is only 1K on Yukon
960 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
963 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
964 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
967 /* Setup Bus Memory Interface */
968 static void sky2_qset(struct sky2_hw *hw, u16 q)
970 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
971 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
972 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
973 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
976 /* Setup prefetch unit registers. This is the interface between
977 * hardware and driver list elements
979 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
982 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
983 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
984 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
985 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
986 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
987 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
989 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
992 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
994 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
996 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
1001 static void tx_init(struct sky2_port *sky2)
1003 struct sky2_tx_le *le;
1005 sky2->tx_prod = sky2->tx_cons = 0;
1006 sky2->tx_tcpsum = 0;
1007 sky2->tx_last_mss = 0;
1009 le = get_tx_le(sky2);
1011 le->opcode = OP_ADDR64 | HW_OWNER;
1014 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
1015 struct sky2_tx_le *le)
1017 return sky2->tx_ring + (le - sky2->tx_le);
1020 /* Update chip's next pointer */
1021 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1023 /* Make sure write' to descriptors are complete before we tell hardware */
1025 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1027 /* Synchronize I/O on since next processor may write to tail */
1032 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1034 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1035 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1040 /* Build description to hardware for one receive segment */
1041 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1042 dma_addr_t map, unsigned len)
1044 struct sky2_rx_le *le;
1046 if (sizeof(dma_addr_t) > sizeof(u32)) {
1047 le = sky2_next_rx(sky2);
1048 le->addr = cpu_to_le32(upper_32_bits(map));
1049 le->opcode = OP_ADDR64 | HW_OWNER;
1052 le = sky2_next_rx(sky2);
1053 le->addr = cpu_to_le32((u32) map);
1054 le->length = cpu_to_le16(len);
1055 le->opcode = op | HW_OWNER;
1058 /* Build description to hardware for one possibly fragmented skb */
1059 static void sky2_rx_submit(struct sky2_port *sky2,
1060 const struct rx_ring_info *re)
1064 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1066 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1067 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1071 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1074 struct sk_buff *skb = re->skb;
1077 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1078 if (unlikely(pci_dma_mapping_error(pdev, re->data_addr)))
1081 pci_unmap_len_set(re, data_size, size);
1083 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1084 re->frag_addr[i] = pci_map_page(pdev,
1085 skb_shinfo(skb)->frags[i].page,
1086 skb_shinfo(skb)->frags[i].page_offset,
1087 skb_shinfo(skb)->frags[i].size,
1088 PCI_DMA_FROMDEVICE);
1092 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1094 struct sk_buff *skb = re->skb;
1097 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1098 PCI_DMA_FROMDEVICE);
1100 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1101 pci_unmap_page(pdev, re->frag_addr[i],
1102 skb_shinfo(skb)->frags[i].size,
1103 PCI_DMA_FROMDEVICE);
1106 /* Tell chip where to start receive checksum.
1107 * Actually has two checksums, but set both same to avoid possible byte
1110 static void rx_set_checksum(struct sky2_port *sky2)
1112 struct sky2_rx_le *le = sky2_next_rx(sky2);
1114 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1116 le->opcode = OP_TCPSTART | HW_OWNER;
1118 sky2_write32(sky2->hw,
1119 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1120 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1124 * The RX Stop command will not work for Yukon-2 if the BMU does not
1125 * reach the end of packet and since we can't make sure that we have
1126 * incoming data, we must reset the BMU while it is not doing a DMA
1127 * transfer. Since it is possible that the RX path is still active,
1128 * the RX RAM buffer will be stopped first, so any possible incoming
1129 * data will not trigger a DMA. After the RAM buffer is stopped, the
1130 * BMU is polled until any DMA in progress is ended and only then it
1133 static void sky2_rx_stop(struct sky2_port *sky2)
1135 struct sky2_hw *hw = sky2->hw;
1136 unsigned rxq = rxqaddr[sky2->port];
1139 /* disable the RAM Buffer receive queue */
1140 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1142 for (i = 0; i < 0xffff; i++)
1143 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1144 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1147 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1148 sky2->netdev->name);
1150 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1152 /* reset the Rx prefetch unit */
1153 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1155 /* Reset the RAM Buffer receive queue */
1156 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_RST_SET);
1158 /* Reset Rx MAC FIFO */
1159 sky2_write8(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), GMF_RST_SET);
1161 sky2_read8(hw, B0_CTST);
1164 /* Clean out receive buffer area, assumes receiver hardware stopped */
1165 static void sky2_rx_clean(struct sky2_port *sky2)
1169 memset(sky2->rx_le, 0, RX_LE_BYTES);
1170 for (i = 0; i < sky2->rx_pending; i++) {
1171 struct rx_ring_info *re = sky2->rx_ring + i;
1174 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1181 /* Basic MII support */
1182 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1184 struct mii_ioctl_data *data = if_mii(ifr);
1185 struct sky2_port *sky2 = netdev_priv(dev);
1186 struct sky2_hw *hw = sky2->hw;
1187 int err = -EOPNOTSUPP;
1189 if (!netif_running(dev))
1190 return -ENODEV; /* Phy still in reset */
1194 data->phy_id = PHY_ADDR_MARV;
1200 spin_lock_bh(&sky2->phy_lock);
1201 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1202 spin_unlock_bh(&sky2->phy_lock);
1204 data->val_out = val;
1209 if (!capable(CAP_NET_ADMIN))
1212 spin_lock_bh(&sky2->phy_lock);
1213 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1215 spin_unlock_bh(&sky2->phy_lock);
1221 #ifdef SKY2_VLAN_TAG_USED
1222 static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
1225 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1227 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1230 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1232 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1237 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1239 struct sky2_port *sky2 = netdev_priv(dev);
1240 struct sky2_hw *hw = sky2->hw;
1241 u16 port = sky2->port;
1243 netif_tx_lock_bh(dev);
1244 napi_disable(&hw->napi);
1247 sky2_set_vlan_mode(hw, port, grp != NULL);
1249 sky2_read32(hw, B0_Y2_SP_LISR);
1250 napi_enable(&hw->napi);
1251 netif_tx_unlock_bh(dev);
1256 * Allocate an skb for receiving. If the MTU is large enough
1257 * make the skb non-linear with a fragment list of pages.
1259 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1261 struct sk_buff *skb;
1264 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1265 unsigned char *start;
1267 * Workaround for a bug in FIFO that cause hang
1268 * if the FIFO if the receive buffer is not 64 byte aligned.
1269 * The buffer returned from netdev_alloc_skb is
1270 * aligned except if slab debugging is enabled.
1272 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + 8);
1275 start = PTR_ALIGN(skb->data, 8);
1276 skb_reserve(skb, start - skb->data);
1278 skb = netdev_alloc_skb(sky2->netdev,
1279 sky2->rx_data_size + NET_IP_ALIGN);
1282 skb_reserve(skb, NET_IP_ALIGN);
1285 for (i = 0; i < sky2->rx_nfrags; i++) {
1286 struct page *page = alloc_page(GFP_ATOMIC);
1290 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1300 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1302 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1306 * Allocate and setup receiver buffer pool.
1307 * Normal case this ends up creating one list element for skb
1308 * in the receive ring. Worst case if using large MTU and each
1309 * allocation falls on a different 64 bit region, that results
1310 * in 6 list elements per ring entry.
1311 * One element is used for checksum enable/disable, and one
1312 * extra to avoid wrap.
1314 static int sky2_rx_start(struct sky2_port *sky2)
1316 struct sky2_hw *hw = sky2->hw;
1317 struct rx_ring_info *re;
1318 unsigned rxq = rxqaddr[sky2->port];
1319 unsigned i, size, thresh;
1321 sky2->rx_put = sky2->rx_next = 0;
1324 /* On PCI express lowering the watermark gives better performance */
1325 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1326 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1328 /* These chips have no ram buffer?
1329 * MAC Rx RAM Read is controlled by hardware */
1330 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1331 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1332 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1333 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1335 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1337 if (!(hw->flags & SKY2_HW_NEW_LE))
1338 rx_set_checksum(sky2);
1340 /* Space needed for frame data + headers rounded up */
1341 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1343 /* Stopping point for hardware truncation */
1344 thresh = (size - 8) / sizeof(u32);
1346 sky2->rx_nfrags = size >> PAGE_SHIFT;
1347 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1349 /* Compute residue after pages */
1350 size -= sky2->rx_nfrags << PAGE_SHIFT;
1352 /* Optimize to handle small packets and headers */
1353 if (size < copybreak)
1355 if (size < ETH_HLEN)
1358 sky2->rx_data_size = size;
1361 for (i = 0; i < sky2->rx_pending; i++) {
1362 re = sky2->rx_ring + i;
1364 re->skb = sky2_rx_alloc(sky2);
1368 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1369 dev_kfree_skb(re->skb);
1374 sky2_rx_submit(sky2, re);
1378 * The receiver hangs if it receives frames larger than the
1379 * packet buffer. As a workaround, truncate oversize frames, but
1380 * the register is limited to 9 bits, so if you do frames > 2052
1381 * you better get the MTU right!
1384 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1386 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1387 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1390 /* Tell chip about available buffers */
1391 sky2_rx_update(sky2, rxq);
1394 sky2_rx_clean(sky2);
1398 /* Bring up network interface. */
1399 static int sky2_up(struct net_device *dev)
1401 struct sky2_port *sky2 = netdev_priv(dev);
1402 struct sky2_hw *hw = sky2->hw;
1403 unsigned port = sky2->port;
1405 int cap, err = -ENOMEM;
1406 struct net_device *otherdev = hw->dev[sky2->port^1];
1409 * On dual port PCI-X card, there is an problem where status
1410 * can be received out of order due to split transactions
1412 if (otherdev && netif_running(otherdev) &&
1413 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1416 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1417 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1418 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1422 netif_carrier_off(dev);
1424 /* must be power of 2 */
1425 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1427 sizeof(struct sky2_tx_le),
1432 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1439 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1443 memset(sky2->rx_le, 0, RX_LE_BYTES);
1445 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1450 sky2_mac_init(hw, port);
1452 /* Register is number of 4K blocks on internal RAM buffer. */
1453 ramsize = sky2_read8(hw, B2_E_0) * 4;
1457 hw->flags |= SKY2_HW_RAM_BUFFER;
1458 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1460 rxspace = ramsize / 2;
1462 rxspace = 8 + (2*(ramsize - 16))/3;
1464 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1465 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1467 /* Make sure SyncQ is disabled */
1468 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1472 sky2_qset(hw, txqaddr[port]);
1474 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1475 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1476 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1478 /* Set almost empty threshold */
1479 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1480 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1481 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1483 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1486 #ifdef SKY2_VLAN_TAG_USED
1487 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1490 err = sky2_rx_start(sky2);
1494 /* Enable interrupts from phy/mac for port */
1495 imask = sky2_read32(hw, B0_IMSK);
1496 imask |= portirq_msk[port];
1497 sky2_write32(hw, B0_IMSK, imask);
1498 sky2_read32(hw, B0_IMSK);
1500 sky2_set_multicast(dev);
1502 if (netif_msg_ifup(sky2))
1503 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1508 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1509 sky2->rx_le, sky2->rx_le_map);
1513 pci_free_consistent(hw->pdev,
1514 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1515 sky2->tx_le, sky2->tx_le_map);
1518 kfree(sky2->tx_ring);
1519 kfree(sky2->rx_ring);
1521 sky2->tx_ring = NULL;
1522 sky2->rx_ring = NULL;
1526 /* Modular subtraction in ring */
1527 static inline int tx_dist(unsigned tail, unsigned head)
1529 return (head - tail) & (TX_RING_SIZE - 1);
1532 /* Number of list elements available for next tx */
1533 static inline int tx_avail(const struct sky2_port *sky2)
1535 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1538 /* Estimate of number of transmit list elements required */
1539 static unsigned tx_le_req(const struct sk_buff *skb)
1543 count = sizeof(dma_addr_t) / sizeof(u32);
1544 count += skb_shinfo(skb)->nr_frags * count;
1546 if (skb_is_gso(skb))
1549 if (skb->ip_summed == CHECKSUM_PARTIAL)
1556 * Put one packet in ring for transmit.
1557 * A single packet can generate multiple list elements, and
1558 * the number of ring elements will probably be less than the number
1559 * of list elements used.
1561 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1563 struct sky2_port *sky2 = netdev_priv(dev);
1564 struct sky2_hw *hw = sky2->hw;
1565 struct sky2_tx_le *le = NULL;
1566 struct tx_ring_info *re;
1567 unsigned i, len, first_slot;
1572 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1573 return NETDEV_TX_BUSY;
1575 len = skb_headlen(skb);
1576 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1578 if (pci_dma_mapping_error(hw->pdev, mapping))
1581 first_slot = sky2->tx_prod;
1582 if (unlikely(netif_msg_tx_queued(sky2)))
1583 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1584 dev->name, first_slot, skb->len);
1586 /* Send high bits if needed */
1587 if (sizeof(dma_addr_t) > sizeof(u32)) {
1588 le = get_tx_le(sky2);
1589 le->addr = cpu_to_le32(upper_32_bits(mapping));
1590 le->opcode = OP_ADDR64 | HW_OWNER;
1593 /* Check for TCP Segmentation Offload */
1594 mss = skb_shinfo(skb)->gso_size;
1597 if (!(hw->flags & SKY2_HW_NEW_LE))
1598 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1600 if (mss != sky2->tx_last_mss) {
1601 le = get_tx_le(sky2);
1602 le->addr = cpu_to_le32(mss);
1604 if (hw->flags & SKY2_HW_NEW_LE)
1605 le->opcode = OP_MSS | HW_OWNER;
1607 le->opcode = OP_LRGLEN | HW_OWNER;
1608 sky2->tx_last_mss = mss;
1613 #ifdef SKY2_VLAN_TAG_USED
1614 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1615 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1617 le = get_tx_le(sky2);
1619 le->opcode = OP_VLAN|HW_OWNER;
1621 le->opcode |= OP_VLAN;
1622 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1627 /* Handle TCP checksum offload */
1628 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1629 /* On Yukon EX (some versions) encoding change. */
1630 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1631 ctrl |= CALSUM; /* auto checksum */
1633 const unsigned offset = skb_transport_offset(skb);
1636 tcpsum = offset << 16; /* sum start */
1637 tcpsum |= offset + skb->csum_offset; /* sum write */
1639 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1640 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1643 if (tcpsum != sky2->tx_tcpsum) {
1644 sky2->tx_tcpsum = tcpsum;
1646 le = get_tx_le(sky2);
1647 le->addr = cpu_to_le32(tcpsum);
1648 le->length = 0; /* initial checksum value */
1649 le->ctrl = 1; /* one packet */
1650 le->opcode = OP_TCPLISW | HW_OWNER;
1655 le = get_tx_le(sky2);
1656 le->addr = cpu_to_le32((u32) mapping);
1657 le->length = cpu_to_le16(len);
1659 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1661 re = tx_le_re(sky2, le);
1663 pci_unmap_addr_set(re, mapaddr, mapping);
1664 pci_unmap_len_set(re, maplen, len);
1666 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1667 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1669 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1670 frag->size, PCI_DMA_TODEVICE);
1672 if (pci_dma_mapping_error(hw->pdev, mapping))
1673 goto mapping_unwind;
1675 if (sizeof(dma_addr_t) > sizeof(u32)) {
1676 le = get_tx_le(sky2);
1677 le->addr = cpu_to_le32(upper_32_bits(mapping));
1679 le->opcode = OP_ADDR64 | HW_OWNER;
1682 le = get_tx_le(sky2);
1683 le->addr = cpu_to_le32((u32) mapping);
1684 le->length = cpu_to_le16(frag->size);
1686 le->opcode = OP_BUFFER | HW_OWNER;
1688 re = tx_le_re(sky2, le);
1690 pci_unmap_addr_set(re, mapaddr, mapping);
1691 pci_unmap_len_set(re, maplen, frag->size);
1696 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1697 netif_stop_queue(dev);
1699 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1701 return NETDEV_TX_OK;
1704 for (i = first_slot; i != sky2->tx_prod; i = RING_NEXT(i, TX_RING_SIZE)) {
1705 le = sky2->tx_le + i;
1706 re = sky2->tx_ring + i;
1708 switch(le->opcode & ~HW_OWNER) {
1711 pci_unmap_single(hw->pdev,
1712 pci_unmap_addr(re, mapaddr),
1713 pci_unmap_len(re, maplen),
1717 pci_unmap_page(hw->pdev, pci_unmap_addr(re, mapaddr),
1718 pci_unmap_len(re, maplen),
1724 sky2->tx_prod = first_slot;
1726 if (net_ratelimit())
1727 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1729 return NETDEV_TX_OK;
1733 * Free ring elements from starting at tx_cons until "done"
1735 * NB: the hardware will tell us about partial completion of multi-part
1736 * buffers so make sure not to free skb to early.
1738 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1740 struct net_device *dev = sky2->netdev;
1741 struct pci_dev *pdev = sky2->hw->pdev;
1744 BUG_ON(done >= TX_RING_SIZE);
1746 for (idx = sky2->tx_cons; idx != done;
1747 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1748 struct sky2_tx_le *le = sky2->tx_le + idx;
1749 struct tx_ring_info *re = sky2->tx_ring + idx;
1751 switch(le->opcode & ~HW_OWNER) {
1754 pci_unmap_single(pdev,
1755 pci_unmap_addr(re, mapaddr),
1756 pci_unmap_len(re, maplen),
1760 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1761 pci_unmap_len(re, maplen),
1766 if (le->ctrl & EOP) {
1767 if (unlikely(netif_msg_tx_done(sky2)))
1768 printk(KERN_DEBUG "%s: tx done %u\n",
1771 dev->stats.tx_packets++;
1772 dev->stats.tx_bytes += re->skb->len;
1774 dev_kfree_skb_any(re->skb);
1775 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
1779 sky2->tx_cons = idx;
1782 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1783 netif_wake_queue(dev);
1786 /* Cleanup all untransmitted buffers, assume transmitter not running */
1787 static void sky2_tx_clean(struct net_device *dev)
1789 struct sky2_port *sky2 = netdev_priv(dev);
1791 netif_tx_lock_bh(dev);
1792 sky2_tx_complete(sky2, sky2->tx_prod);
1793 netif_tx_unlock_bh(dev);
1796 /* Network shutdown */
1797 static int sky2_down(struct net_device *dev)
1799 struct sky2_port *sky2 = netdev_priv(dev);
1800 struct sky2_hw *hw = sky2->hw;
1801 unsigned port = sky2->port;
1805 /* Never really got started! */
1809 if (netif_msg_ifdown(sky2))
1810 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1812 /* Disable port IRQ */
1813 imask = sky2_read32(hw, B0_IMSK);
1814 imask &= ~portirq_msk[port];
1815 sky2_write32(hw, B0_IMSK, imask);
1816 sky2_read32(hw, B0_IMSK);
1818 /* Force flow control off */
1819 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1821 /* Stop transmitter */
1822 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1823 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1825 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1826 RB_RST_SET | RB_DIS_OP_MD);
1828 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1829 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1830 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1832 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1834 /* Workaround shared GMAC reset */
1835 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1836 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1837 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1839 /* Disable Force Sync bit and Enable Alloc bit */
1840 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1841 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1843 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1844 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1845 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1847 /* Reset the PCI FIFO of the async Tx queue */
1848 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1849 BMU_RST_SET | BMU_FIFO_RST);
1851 /* Reset the Tx prefetch units */
1852 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1855 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1859 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1860 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1862 /* Force any delayed status interrrupt and NAPI */
1863 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1864 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1865 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1866 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1868 synchronize_irq(hw->pdev->irq);
1869 napi_synchronize(&hw->napi);
1871 sky2_phy_power_down(hw, port);
1873 /* turn off LED's */
1874 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1877 sky2_rx_clean(sky2);
1879 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1880 sky2->rx_le, sky2->rx_le_map);
1881 kfree(sky2->rx_ring);
1883 pci_free_consistent(hw->pdev,
1884 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1885 sky2->tx_le, sky2->tx_le_map);
1886 kfree(sky2->tx_ring);
1891 sky2->rx_ring = NULL;
1892 sky2->tx_ring = NULL;
1897 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1899 if (hw->flags & SKY2_HW_FIBRE_PHY)
1902 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1903 if (aux & PHY_M_PS_SPEED_100)
1909 switch (aux & PHY_M_PS_SPEED_MSK) {
1910 case PHY_M_PS_SPEED_1000:
1912 case PHY_M_PS_SPEED_100:
1919 static void sky2_link_up(struct sky2_port *sky2)
1921 struct sky2_hw *hw = sky2->hw;
1922 unsigned port = sky2->port;
1924 static const char *fc_name[] = {
1932 reg = gma_read16(hw, port, GM_GP_CTRL);
1933 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1934 gma_write16(hw, port, GM_GP_CTRL, reg);
1936 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1938 netif_carrier_on(sky2->netdev);
1940 mod_timer(&hw->watchdog_timer, jiffies + 1);
1942 /* Turn on link LED */
1943 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1944 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1946 if (netif_msg_link(sky2))
1947 printk(KERN_INFO PFX
1948 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1949 sky2->netdev->name, sky2->speed,
1950 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1951 fc_name[sky2->flow_status]);
1954 static void sky2_link_down(struct sky2_port *sky2)
1956 struct sky2_hw *hw = sky2->hw;
1957 unsigned port = sky2->port;
1960 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1962 reg = gma_read16(hw, port, GM_GP_CTRL);
1963 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1964 gma_write16(hw, port, GM_GP_CTRL, reg);
1966 netif_carrier_off(sky2->netdev);
1968 /* Turn on link LED */
1969 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1971 if (netif_msg_link(sky2))
1972 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1974 sky2_phy_init(hw, port);
1977 static enum flow_control sky2_flow(int rx, int tx)
1980 return tx ? FC_BOTH : FC_RX;
1982 return tx ? FC_TX : FC_NONE;
1985 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1987 struct sky2_hw *hw = sky2->hw;
1988 unsigned port = sky2->port;
1991 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1992 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1993 if (lpa & PHY_M_AN_RF) {
1994 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1998 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1999 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2000 sky2->netdev->name);
2004 sky2->speed = sky2_phy_speed(hw, aux);
2005 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2007 /* Since the pause result bits seem to in different positions on
2008 * different chips. look at registers.
2010 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2011 /* Shift for bits in fiber PHY */
2012 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2013 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2015 if (advert & ADVERTISE_1000XPAUSE)
2016 advert |= ADVERTISE_PAUSE_CAP;
2017 if (advert & ADVERTISE_1000XPSE_ASYM)
2018 advert |= ADVERTISE_PAUSE_ASYM;
2019 if (lpa & LPA_1000XPAUSE)
2020 lpa |= LPA_PAUSE_CAP;
2021 if (lpa & LPA_1000XPAUSE_ASYM)
2022 lpa |= LPA_PAUSE_ASYM;
2025 sky2->flow_status = FC_NONE;
2026 if (advert & ADVERTISE_PAUSE_CAP) {
2027 if (lpa & LPA_PAUSE_CAP)
2028 sky2->flow_status = FC_BOTH;
2029 else if (advert & ADVERTISE_PAUSE_ASYM)
2030 sky2->flow_status = FC_RX;
2031 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2032 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2033 sky2->flow_status = FC_TX;
2036 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
2037 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2038 sky2->flow_status = FC_NONE;
2040 if (sky2->flow_status & FC_TX)
2041 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2043 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2048 /* Interrupt from PHY */
2049 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2051 struct net_device *dev = hw->dev[port];
2052 struct sky2_port *sky2 = netdev_priv(dev);
2053 u16 istatus, phystat;
2055 if (!netif_running(dev))
2058 spin_lock(&sky2->phy_lock);
2059 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2060 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2062 if (netif_msg_intr(sky2))
2063 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2064 sky2->netdev->name, istatus, phystat);
2066 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
2067 if (sky2_autoneg_done(sky2, phystat) == 0)
2072 if (istatus & PHY_M_IS_LSP_CHANGE)
2073 sky2->speed = sky2_phy_speed(hw, phystat);
2075 if (istatus & PHY_M_IS_DUP_CHANGE)
2077 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2079 if (istatus & PHY_M_IS_LST_CHANGE) {
2080 if (phystat & PHY_M_PS_LINK_UP)
2083 sky2_link_down(sky2);
2086 spin_unlock(&sky2->phy_lock);
2089 /* Transmit timeout is only called if we are running, carrier is up
2090 * and tx queue is full (stopped).
2092 static void sky2_tx_timeout(struct net_device *dev)
2094 struct sky2_port *sky2 = netdev_priv(dev);
2095 struct sky2_hw *hw = sky2->hw;
2097 if (netif_msg_timer(sky2))
2098 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2100 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
2101 dev->name, sky2->tx_cons, sky2->tx_prod,
2102 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2103 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2105 /* can't restart safely under softirq */
2106 schedule_work(&hw->restart_work);
2109 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2111 struct sky2_port *sky2 = netdev_priv(dev);
2112 struct sky2_hw *hw = sky2->hw;
2113 unsigned port = sky2->port;
2118 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2121 if (new_mtu > ETH_DATA_LEN &&
2122 (hw->chip_id == CHIP_ID_YUKON_FE ||
2123 hw->chip_id == CHIP_ID_YUKON_FE_P))
2126 if (!netif_running(dev)) {
2131 imask = sky2_read32(hw, B0_IMSK);
2132 sky2_write32(hw, B0_IMSK, 0);
2134 dev->trans_start = jiffies; /* prevent tx timeout */
2135 netif_stop_queue(dev);
2136 napi_disable(&hw->napi);
2138 synchronize_irq(hw->pdev->irq);
2140 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2141 sky2_set_tx_stfwd(hw, port);
2143 ctl = gma_read16(hw, port, GM_GP_CTRL);
2144 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2146 sky2_rx_clean(sky2);
2150 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2151 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2153 if (dev->mtu > ETH_DATA_LEN)
2154 mode |= GM_SMOD_JUMBO_ENA;
2156 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2158 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2160 err = sky2_rx_start(sky2);
2161 sky2_write32(hw, B0_IMSK, imask);
2163 sky2_read32(hw, B0_Y2_SP_LISR);
2164 napi_enable(&hw->napi);
2169 gma_write16(hw, port, GM_GP_CTRL, ctl);
2171 netif_wake_queue(dev);
2177 /* For small just reuse existing skb for next receive */
2178 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2179 const struct rx_ring_info *re,
2182 struct sk_buff *skb;
2184 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2186 skb_reserve(skb, 2);
2187 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2188 length, PCI_DMA_FROMDEVICE);
2189 skb_copy_from_linear_data(re->skb, skb->data, length);
2190 skb->ip_summed = re->skb->ip_summed;
2191 skb->csum = re->skb->csum;
2192 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2193 length, PCI_DMA_FROMDEVICE);
2194 re->skb->ip_summed = CHECKSUM_NONE;
2195 skb_put(skb, length);
2200 /* Adjust length of skb with fragments to match received data */
2201 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2202 unsigned int length)
2207 /* put header into skb */
2208 size = min(length, hdr_space);
2213 num_frags = skb_shinfo(skb)->nr_frags;
2214 for (i = 0; i < num_frags; i++) {
2215 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2218 /* don't need this page */
2219 __free_page(frag->page);
2220 --skb_shinfo(skb)->nr_frags;
2222 size = min(length, (unsigned) PAGE_SIZE);
2225 skb->data_len += size;
2226 skb->truesize += size;
2233 /* Normal packet - take skb from ring element and put in a new one */
2234 static struct sk_buff *receive_new(struct sky2_port *sky2,
2235 struct rx_ring_info *re,
2236 unsigned int length)
2238 struct sk_buff *skb, *nskb;
2239 unsigned hdr_space = sky2->rx_data_size;
2241 /* Don't be tricky about reusing pages (yet) */
2242 nskb = sky2_rx_alloc(sky2);
2243 if (unlikely(!nskb))
2247 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2249 prefetch(skb->data);
2251 if (sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space)) {
2252 dev_kfree_skb(nskb);
2257 if (skb_shinfo(skb)->nr_frags)
2258 skb_put_frags(skb, hdr_space, length);
2260 skb_put(skb, length);
2265 * Receive one packet.
2266 * For larger packets, get new buffer.
2268 static struct sk_buff *sky2_receive(struct net_device *dev,
2269 u16 length, u32 status)
2271 struct sky2_port *sky2 = netdev_priv(dev);
2272 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2273 struct sk_buff *skb = NULL;
2274 u16 count = (status & GMR_FS_LEN) >> 16;
2276 #ifdef SKY2_VLAN_TAG_USED
2277 /* Account for vlan tag */
2278 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2282 if (unlikely(netif_msg_rx_status(sky2)))
2283 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2284 dev->name, sky2->rx_next, status, length);
2286 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2287 prefetch(sky2->rx_ring + sky2->rx_next);
2289 /* This chip has hardware problems that generates bogus status.
2290 * So do only marginal checking and expect higher level protocols
2291 * to handle crap frames.
2293 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2294 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2298 if (status & GMR_FS_ANY_ERR)
2301 if (!(status & GMR_FS_RX_OK))
2304 /* if length reported by DMA does not match PHY, packet was truncated */
2305 if (length != count)
2309 if (length < copybreak)
2310 skb = receive_copy(sky2, re, length);
2312 skb = receive_new(sky2, re, length);
2314 sky2_rx_submit(sky2, re);
2319 /* Truncation of overlength packets
2320 causes PHY length to not match MAC length */
2321 ++dev->stats.rx_length_errors;
2322 if (netif_msg_rx_err(sky2) && net_ratelimit())
2323 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2324 dev->name, status, length);
2328 ++dev->stats.rx_errors;
2329 if (status & GMR_FS_RX_FF_OV) {
2330 dev->stats.rx_over_errors++;
2334 if (netif_msg_rx_err(sky2) && net_ratelimit())
2335 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2336 dev->name, status, length);
2338 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2339 dev->stats.rx_length_errors++;
2340 if (status & GMR_FS_FRAGMENT)
2341 dev->stats.rx_frame_errors++;
2342 if (status & GMR_FS_CRC_ERR)
2343 dev->stats.rx_crc_errors++;
2348 /* Transmit complete */
2349 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2351 struct sky2_port *sky2 = netdev_priv(dev);
2353 if (netif_running(dev)) {
2355 sky2_tx_complete(sky2, last);
2356 netif_tx_unlock(dev);
2360 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2361 unsigned packets, unsigned bytes)
2364 struct net_device *dev = hw->dev[port];
2366 dev->stats.rx_packets += packets;
2367 dev->stats.rx_bytes += bytes;
2368 dev->last_rx = jiffies;
2369 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2373 /* Process status response ring */
2374 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2377 unsigned int total_bytes[2] = { 0 };
2378 unsigned int total_packets[2] = { 0 };
2382 struct sky2_port *sky2;
2383 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2385 struct net_device *dev;
2386 struct sk_buff *skb;
2389 u8 opcode = le->opcode;
2391 if (!(opcode & HW_OWNER))
2394 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2396 port = le->css & CSS_LINK_BIT;
2397 dev = hw->dev[port];
2398 sky2 = netdev_priv(dev);
2399 length = le16_to_cpu(le->length);
2400 status = le32_to_cpu(le->status);
2403 switch (opcode & ~HW_OWNER) {
2405 total_packets[port]++;
2406 total_bytes[port] += length;
2407 skb = sky2_receive(dev, length, status);
2408 if (unlikely(!skb)) {
2409 dev->stats.rx_dropped++;
2413 /* This chip reports checksum status differently */
2414 if (hw->flags & SKY2_HW_NEW_LE) {
2415 if (sky2->rx_csum &&
2416 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2417 (le->css & CSS_TCPUDPCSOK))
2418 skb->ip_summed = CHECKSUM_UNNECESSARY;
2420 skb->ip_summed = CHECKSUM_NONE;
2423 skb->protocol = eth_type_trans(skb, dev);
2425 #ifdef SKY2_VLAN_TAG_USED
2426 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2427 vlan_hwaccel_receive_skb(skb,
2429 be16_to_cpu(sky2->rx_tag));
2432 netif_receive_skb(skb);
2434 /* Stop after net poll weight */
2435 if (++work_done >= to_do)
2439 #ifdef SKY2_VLAN_TAG_USED
2441 sky2->rx_tag = length;
2445 sky2->rx_tag = length;
2452 /* If this happens then driver assuming wrong format */
2453 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2454 if (net_ratelimit())
2455 printk(KERN_NOTICE "%s: unexpected"
2456 " checksum status\n",
2461 /* Both checksum counters are programmed to start at
2462 * the same offset, so unless there is a problem they
2463 * should match. This failure is an early indication that
2464 * hardware receive checksumming won't work.
2466 if (likely(status >> 16 == (status & 0xffff))) {
2467 skb = sky2->rx_ring[sky2->rx_next].skb;
2468 skb->ip_summed = CHECKSUM_COMPLETE;
2469 skb->csum = status & 0xffff;
2471 printk(KERN_NOTICE PFX "%s: hardware receive "
2472 "checksum problem (status = %#x)\n",
2475 sky2_write32(sky2->hw,
2476 Q_ADDR(rxqaddr[port], Q_CSR),
2482 /* TX index reports status for both ports */
2483 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2484 sky2_tx_done(hw->dev[0], status & 0xfff);
2486 sky2_tx_done(hw->dev[1],
2487 ((status >> 24) & 0xff)
2488 | (u16)(length & 0xf) << 8);
2492 if (net_ratelimit())
2493 printk(KERN_WARNING PFX
2494 "unknown status opcode 0x%x\n", opcode);
2496 } while (hw->st_idx != idx);
2498 /* Fully processed status ring so clear irq */
2499 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2502 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2503 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2508 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2510 struct net_device *dev = hw->dev[port];
2512 if (net_ratelimit())
2513 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2516 if (status & Y2_IS_PAR_RD1) {
2517 if (net_ratelimit())
2518 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2521 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2524 if (status & Y2_IS_PAR_WR1) {
2525 if (net_ratelimit())
2526 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2529 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2532 if (status & Y2_IS_PAR_MAC1) {
2533 if (net_ratelimit())
2534 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2535 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2538 if (status & Y2_IS_PAR_RX1) {
2539 if (net_ratelimit())
2540 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2541 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2544 if (status & Y2_IS_TCP_TXA1) {
2545 if (net_ratelimit())
2546 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2548 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2552 static void sky2_hw_intr(struct sky2_hw *hw)
2554 struct pci_dev *pdev = hw->pdev;
2555 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2556 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2560 if (status & Y2_IS_TIST_OV)
2561 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2563 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2566 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2567 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2568 if (net_ratelimit())
2569 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2572 sky2_pci_write16(hw, PCI_STATUS,
2573 pci_err | PCI_STATUS_ERROR_BITS);
2574 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2577 if (status & Y2_IS_PCI_EXP) {
2578 /* PCI-Express uncorrectable Error occurred */
2581 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2582 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2583 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2585 if (net_ratelimit())
2586 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2588 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2589 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2592 if (status & Y2_HWE_L1_MASK)
2593 sky2_hw_error(hw, 0, status);
2595 if (status & Y2_HWE_L1_MASK)
2596 sky2_hw_error(hw, 1, status);
2599 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2601 struct net_device *dev = hw->dev[port];
2602 struct sky2_port *sky2 = netdev_priv(dev);
2603 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2605 if (netif_msg_intr(sky2))
2606 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2609 if (status & GM_IS_RX_CO_OV)
2610 gma_read16(hw, port, GM_RX_IRQ_SRC);
2612 if (status & GM_IS_TX_CO_OV)
2613 gma_read16(hw, port, GM_TX_IRQ_SRC);
2615 if (status & GM_IS_RX_FF_OR) {
2616 ++dev->stats.rx_fifo_errors;
2617 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2620 if (status & GM_IS_TX_FF_UR) {
2621 ++dev->stats.tx_fifo_errors;
2622 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2626 /* This should never happen it is a bug. */
2627 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2628 u16 q, unsigned ring_size)
2630 struct net_device *dev = hw->dev[port];
2631 struct sky2_port *sky2 = netdev_priv(dev);
2633 const u64 *le = (q == Q_R1 || q == Q_R2)
2634 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2636 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2637 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2638 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2639 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2641 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2644 static int sky2_rx_hung(struct net_device *dev)
2646 struct sky2_port *sky2 = netdev_priv(dev);
2647 struct sky2_hw *hw = sky2->hw;
2648 unsigned port = sky2->port;
2649 unsigned rxq = rxqaddr[port];
2650 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2651 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2652 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2653 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2655 /* If idle and MAC or PCI is stuck */
2656 if (sky2->check.last == dev->last_rx &&
2657 ((mac_rp == sky2->check.mac_rp &&
2658 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2659 /* Check if the PCI RX hang */
2660 (fifo_rp == sky2->check.fifo_rp &&
2661 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2662 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2663 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2664 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2667 sky2->check.last = dev->last_rx;
2668 sky2->check.mac_rp = mac_rp;
2669 sky2->check.mac_lev = mac_lev;
2670 sky2->check.fifo_rp = fifo_rp;
2671 sky2->check.fifo_lev = fifo_lev;
2676 static void sky2_watchdog(unsigned long arg)
2678 struct sky2_hw *hw = (struct sky2_hw *) arg;
2680 /* Check for lost IRQ once a second */
2681 if (sky2_read32(hw, B0_ISRC)) {
2682 napi_schedule(&hw->napi);
2686 for (i = 0; i < hw->ports; i++) {
2687 struct net_device *dev = hw->dev[i];
2688 if (!netif_running(dev))
2692 /* For chips with Rx FIFO, check if stuck */
2693 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2694 sky2_rx_hung(dev)) {
2695 pr_info(PFX "%s: receiver hang detected\n",
2697 schedule_work(&hw->restart_work);
2706 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2709 /* Hardware/software error handling */
2710 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2712 if (net_ratelimit())
2713 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2715 if (status & Y2_IS_HW_ERR)
2718 if (status & Y2_IS_IRQ_MAC1)
2719 sky2_mac_intr(hw, 0);
2721 if (status & Y2_IS_IRQ_MAC2)
2722 sky2_mac_intr(hw, 1);
2724 if (status & Y2_IS_CHK_RX1)
2725 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2727 if (status & Y2_IS_CHK_RX2)
2728 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2730 if (status & Y2_IS_CHK_TXA1)
2731 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2733 if (status & Y2_IS_CHK_TXA2)
2734 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2737 static int sky2_poll(struct napi_struct *napi, int work_limit)
2739 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2740 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2744 if (unlikely(status & Y2_IS_ERROR))
2745 sky2_err_intr(hw, status);
2747 if (status & Y2_IS_IRQ_PHY1)
2748 sky2_phy_intr(hw, 0);
2750 if (status & Y2_IS_IRQ_PHY2)
2751 sky2_phy_intr(hw, 1);
2753 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2754 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2756 if (work_done >= work_limit)
2760 napi_complete(napi);
2761 sky2_read32(hw, B0_Y2_SP_LISR);
2767 static irqreturn_t sky2_intr(int irq, void *dev_id)
2769 struct sky2_hw *hw = dev_id;
2772 /* Reading this mask interrupts as side effect */
2773 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2774 if (status == 0 || status == ~0)
2777 prefetch(&hw->st_le[hw->st_idx]);
2779 napi_schedule(&hw->napi);
2784 #ifdef CONFIG_NET_POLL_CONTROLLER
2785 static void sky2_netpoll(struct net_device *dev)
2787 struct sky2_port *sky2 = netdev_priv(dev);
2789 napi_schedule(&sky2->hw->napi);
2793 /* Chip internal frequency for clock calculations */
2794 static u32 sky2_mhz(const struct sky2_hw *hw)
2796 switch (hw->chip_id) {
2797 case CHIP_ID_YUKON_EC:
2798 case CHIP_ID_YUKON_EC_U:
2799 case CHIP_ID_YUKON_EX:
2800 case CHIP_ID_YUKON_SUPR:
2801 case CHIP_ID_YUKON_UL_2:
2804 case CHIP_ID_YUKON_FE:
2807 case CHIP_ID_YUKON_FE_P:
2810 case CHIP_ID_YUKON_XL:
2818 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2820 return sky2_mhz(hw) * us;
2823 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2825 return clk / sky2_mhz(hw);
2829 static int __devinit sky2_init(struct sky2_hw *hw)
2833 /* Enable all clocks and check for bad PCI access */
2834 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2836 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2838 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2839 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2841 switch(hw->chip_id) {
2842 case CHIP_ID_YUKON_XL:
2843 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
2846 case CHIP_ID_YUKON_EC_U:
2847 hw->flags = SKY2_HW_GIGABIT
2849 | SKY2_HW_ADV_POWER_CTL;
2852 case CHIP_ID_YUKON_EX:
2853 hw->flags = SKY2_HW_GIGABIT
2856 | SKY2_HW_ADV_POWER_CTL;
2858 /* New transmit checksum */
2859 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2860 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2863 case CHIP_ID_YUKON_EC:
2864 /* This rev is really old, and requires untested workarounds */
2865 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2866 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2869 hw->flags = SKY2_HW_GIGABIT;
2872 case CHIP_ID_YUKON_FE:
2875 case CHIP_ID_YUKON_FE_P:
2876 hw->flags = SKY2_HW_NEWER_PHY
2878 | SKY2_HW_AUTO_TX_SUM
2879 | SKY2_HW_ADV_POWER_CTL;
2882 case CHIP_ID_YUKON_SUPR:
2883 hw->flags = SKY2_HW_GIGABIT
2886 | SKY2_HW_AUTO_TX_SUM
2887 | SKY2_HW_ADV_POWER_CTL;
2890 case CHIP_ID_YUKON_UL_2:
2891 hw->flags = SKY2_HW_GIGABIT
2892 | SKY2_HW_ADV_POWER_CTL;
2896 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2901 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2902 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2903 hw->flags |= SKY2_HW_FIBRE_PHY;
2906 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2907 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2908 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2915 static void sky2_reset(struct sky2_hw *hw)
2917 struct pci_dev *pdev = hw->pdev;
2920 u32 hwe_mask = Y2_HWE_ALL_MASK;
2923 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2924 status = sky2_read16(hw, HCU_CCSR);
2925 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2926 HCU_CCSR_UC_STATE_MSK);
2927 sky2_write16(hw, HCU_CCSR, status);
2929 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2930 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2933 sky2_write8(hw, B0_CTST, CS_RST_SET);
2934 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2936 /* allow writes to PCI config */
2937 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2939 /* clear PCI errors, if any */
2940 status = sky2_pci_read16(hw, PCI_STATUS);
2941 status |= PCI_STATUS_ERROR_BITS;
2942 sky2_pci_write16(hw, PCI_STATUS, status);
2944 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2946 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2948 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2951 /* If error bit is stuck on ignore it */
2952 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2953 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
2955 hwe_mask |= Y2_IS_PCI_EXP;
2959 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2961 for (i = 0; i < hw->ports; i++) {
2962 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2963 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2965 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2966 hw->chip_id == CHIP_ID_YUKON_SUPR)
2967 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2968 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2972 /* Clear I2C IRQ noise */
2973 sky2_write32(hw, B2_I2C_IRQ, 1);
2975 /* turn off hardware timer (unused) */
2976 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2977 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2979 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2981 /* Turn off descriptor polling */
2982 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2984 /* Turn off receive timestamp */
2985 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2986 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2988 /* enable the Tx Arbiters */
2989 for (i = 0; i < hw->ports; i++)
2990 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2992 /* Initialize ram interface */
2993 for (i = 0; i < hw->ports; i++) {
2994 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2996 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2997 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2998 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2999 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3000 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3001 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3002 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3003 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3004 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3005 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3006 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3007 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3010 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3012 for (i = 0; i < hw->ports; i++)
3013 sky2_gmac_reset(hw, i);
3015 memset(hw->st_le, 0, STATUS_LE_BYTES);
3018 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3019 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3021 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3022 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3024 /* Set the list last index */
3025 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
3027 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3028 sky2_write8(hw, STAT_FIFO_WM, 16);
3030 /* set Status-FIFO ISR watermark */
3031 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3032 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3034 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3036 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3037 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3038 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3040 /* enable status unit */
3041 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3043 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3044 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3045 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3048 static void sky2_restart(struct work_struct *work)
3050 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3051 struct net_device *dev;
3055 for (i = 0; i < hw->ports; i++) {
3057 if (netif_running(dev))
3061 napi_disable(&hw->napi);
3062 sky2_write32(hw, B0_IMSK, 0);
3064 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3065 napi_enable(&hw->napi);
3067 for (i = 0; i < hw->ports; i++) {
3069 if (netif_running(dev)) {
3072 printk(KERN_INFO PFX "%s: could not restart %d\n",
3082 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3084 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3087 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3089 const struct sky2_port *sky2 = netdev_priv(dev);
3091 wol->supported = sky2_wol_supported(sky2->hw);
3092 wol->wolopts = sky2->wol;
3095 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3097 struct sky2_port *sky2 = netdev_priv(dev);
3098 struct sky2_hw *hw = sky2->hw;
3100 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw))
3101 || !device_can_wakeup(&hw->pdev->dev))
3104 sky2->wol = wol->wolopts;
3106 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3107 hw->chip_id == CHIP_ID_YUKON_EX ||
3108 hw->chip_id == CHIP_ID_YUKON_FE_P)
3109 sky2_write32(hw, B0_CTST, sky2->wol
3110 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3112 device_set_wakeup_enable(&hw->pdev->dev, sky2->wol);
3114 if (!netif_running(dev))
3115 sky2_wol_init(sky2);
3119 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3121 if (sky2_is_copper(hw)) {
3122 u32 modes = SUPPORTED_10baseT_Half
3123 | SUPPORTED_10baseT_Full
3124 | SUPPORTED_100baseT_Half
3125 | SUPPORTED_100baseT_Full
3126 | SUPPORTED_Autoneg | SUPPORTED_TP;
3128 if (hw->flags & SKY2_HW_GIGABIT)
3129 modes |= SUPPORTED_1000baseT_Half
3130 | SUPPORTED_1000baseT_Full;
3133 return SUPPORTED_1000baseT_Half
3134 | SUPPORTED_1000baseT_Full
3139 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3141 struct sky2_port *sky2 = netdev_priv(dev);
3142 struct sky2_hw *hw = sky2->hw;
3144 ecmd->transceiver = XCVR_INTERNAL;
3145 ecmd->supported = sky2_supported_modes(hw);
3146 ecmd->phy_address = PHY_ADDR_MARV;
3147 if (sky2_is_copper(hw)) {
3148 ecmd->port = PORT_TP;
3149 ecmd->speed = sky2->speed;
3151 ecmd->speed = SPEED_1000;
3152 ecmd->port = PORT_FIBRE;
3155 ecmd->advertising = sky2->advertising;
3156 ecmd->autoneg = sky2->autoneg;
3157 ecmd->duplex = sky2->duplex;
3161 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3163 struct sky2_port *sky2 = netdev_priv(dev);
3164 const struct sky2_hw *hw = sky2->hw;
3165 u32 supported = sky2_supported_modes(hw);
3167 if (ecmd->autoneg == AUTONEG_ENABLE) {
3168 ecmd->advertising = supported;
3174 switch (ecmd->speed) {
3176 if (ecmd->duplex == DUPLEX_FULL)
3177 setting = SUPPORTED_1000baseT_Full;
3178 else if (ecmd->duplex == DUPLEX_HALF)
3179 setting = SUPPORTED_1000baseT_Half;
3184 if (ecmd->duplex == DUPLEX_FULL)
3185 setting = SUPPORTED_100baseT_Full;
3186 else if (ecmd->duplex == DUPLEX_HALF)
3187 setting = SUPPORTED_100baseT_Half;
3193 if (ecmd->duplex == DUPLEX_FULL)
3194 setting = SUPPORTED_10baseT_Full;
3195 else if (ecmd->duplex == DUPLEX_HALF)
3196 setting = SUPPORTED_10baseT_Half;
3204 if ((setting & supported) == 0)
3207 sky2->speed = ecmd->speed;
3208 sky2->duplex = ecmd->duplex;
3211 sky2->autoneg = ecmd->autoneg;
3212 sky2->advertising = ecmd->advertising;
3214 if (netif_running(dev)) {
3215 sky2_phy_reinit(sky2);
3216 sky2_set_multicast(dev);
3222 static void sky2_get_drvinfo(struct net_device *dev,
3223 struct ethtool_drvinfo *info)
3225 struct sky2_port *sky2 = netdev_priv(dev);
3227 strcpy(info->driver, DRV_NAME);
3228 strcpy(info->version, DRV_VERSION);
3229 strcpy(info->fw_version, "N/A");
3230 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3233 static const struct sky2_stat {
3234 char name[ETH_GSTRING_LEN];
3237 { "tx_bytes", GM_TXO_OK_HI },
3238 { "rx_bytes", GM_RXO_OK_HI },
3239 { "tx_broadcast", GM_TXF_BC_OK },
3240 { "rx_broadcast", GM_RXF_BC_OK },
3241 { "tx_multicast", GM_TXF_MC_OK },
3242 { "rx_multicast", GM_RXF_MC_OK },
3243 { "tx_unicast", GM_TXF_UC_OK },
3244 { "rx_unicast", GM_RXF_UC_OK },
3245 { "tx_mac_pause", GM_TXF_MPAUSE },
3246 { "rx_mac_pause", GM_RXF_MPAUSE },
3247 { "collisions", GM_TXF_COL },
3248 { "late_collision",GM_TXF_LAT_COL },
3249 { "aborted", GM_TXF_ABO_COL },
3250 { "single_collisions", GM_TXF_SNG_COL },
3251 { "multi_collisions", GM_TXF_MUL_COL },
3253 { "rx_short", GM_RXF_SHT },
3254 { "rx_runt", GM_RXE_FRAG },
3255 { "rx_64_byte_packets", GM_RXF_64B },
3256 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3257 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3258 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3259 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3260 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3261 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3262 { "rx_too_long", GM_RXF_LNG_ERR },
3263 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3264 { "rx_jabber", GM_RXF_JAB_PKT },
3265 { "rx_fcs_error", GM_RXF_FCS_ERR },
3267 { "tx_64_byte_packets", GM_TXF_64B },
3268 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3269 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3270 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3271 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3272 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3273 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3274 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3277 static u32 sky2_get_rx_csum(struct net_device *dev)
3279 struct sky2_port *sky2 = netdev_priv(dev);
3281 return sky2->rx_csum;
3284 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3286 struct sky2_port *sky2 = netdev_priv(dev);
3288 sky2->rx_csum = data;
3290 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3291 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3296 static u32 sky2_get_msglevel(struct net_device *netdev)
3298 struct sky2_port *sky2 = netdev_priv(netdev);
3299 return sky2->msg_enable;
3302 static int sky2_nway_reset(struct net_device *dev)
3304 struct sky2_port *sky2 = netdev_priv(dev);
3306 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
3309 sky2_phy_reinit(sky2);
3310 sky2_set_multicast(dev);
3315 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3317 struct sky2_hw *hw = sky2->hw;
3318 unsigned port = sky2->port;
3321 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3322 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3323 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3324 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3326 for (i = 2; i < count; i++)
3327 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3330 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3332 struct sky2_port *sky2 = netdev_priv(netdev);
3333 sky2->msg_enable = value;
3336 static int sky2_get_sset_count(struct net_device *dev, int sset)
3340 return ARRAY_SIZE(sky2_stats);
3346 static void sky2_get_ethtool_stats(struct net_device *dev,
3347 struct ethtool_stats *stats, u64 * data)
3349 struct sky2_port *sky2 = netdev_priv(dev);
3351 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3354 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3358 switch (stringset) {
3360 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3361 memcpy(data + i * ETH_GSTRING_LEN,
3362 sky2_stats[i].name, ETH_GSTRING_LEN);
3367 static int sky2_set_mac_address(struct net_device *dev, void *p)
3369 struct sky2_port *sky2 = netdev_priv(dev);
3370 struct sky2_hw *hw = sky2->hw;
3371 unsigned port = sky2->port;
3372 const struct sockaddr *addr = p;
3374 if (!is_valid_ether_addr(addr->sa_data))
3375 return -EADDRNOTAVAIL;
3377 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3378 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3379 dev->dev_addr, ETH_ALEN);
3380 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3381 dev->dev_addr, ETH_ALEN);
3383 /* virtual address for data */
3384 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3386 /* physical address: used for pause frames */
3387 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3392 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3396 bit = ether_crc(ETH_ALEN, addr) & 63;
3397 filter[bit >> 3] |= 1 << (bit & 7);
3400 static void sky2_set_multicast(struct net_device *dev)
3402 struct sky2_port *sky2 = netdev_priv(dev);
3403 struct sky2_hw *hw = sky2->hw;
3404 unsigned port = sky2->port;
3405 struct dev_mc_list *list = dev->mc_list;
3409 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3411 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3412 memset(filter, 0, sizeof(filter));
3414 reg = gma_read16(hw, port, GM_RX_CTRL);
3415 reg |= GM_RXCR_UCF_ENA;
3417 if (dev->flags & IFF_PROMISC) /* promiscuous */
3418 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3419 else if (dev->flags & IFF_ALLMULTI)
3420 memset(filter, 0xff, sizeof(filter));
3421 else if (dev->mc_count == 0 && !rx_pause)
3422 reg &= ~GM_RXCR_MCF_ENA;
3425 reg |= GM_RXCR_MCF_ENA;
3428 sky2_add_filter(filter, pause_mc_addr);
3430 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3431 sky2_add_filter(filter, list->dmi_addr);
3434 gma_write16(hw, port, GM_MC_ADDR_H1,
3435 (u16) filter[0] | ((u16) filter[1] << 8));
3436 gma_write16(hw, port, GM_MC_ADDR_H2,
3437 (u16) filter[2] | ((u16) filter[3] << 8));
3438 gma_write16(hw, port, GM_MC_ADDR_H3,
3439 (u16) filter[4] | ((u16) filter[5] << 8));
3440 gma_write16(hw, port, GM_MC_ADDR_H4,
3441 (u16) filter[6] | ((u16) filter[7] << 8));
3443 gma_write16(hw, port, GM_RX_CTRL, reg);
3446 /* Can have one global because blinking is controlled by
3447 * ethtool and that is always under RTNL mutex
3449 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3451 struct sky2_hw *hw = sky2->hw;
3452 unsigned port = sky2->port;
3454 spin_lock_bh(&sky2->phy_lock);
3455 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3456 hw->chip_id == CHIP_ID_YUKON_EX ||
3457 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3459 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3460 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3464 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3465 PHY_M_LEDC_LOS_CTRL(8) |
3466 PHY_M_LEDC_INIT_CTRL(8) |
3467 PHY_M_LEDC_STA1_CTRL(8) |
3468 PHY_M_LEDC_STA0_CTRL(8));
3471 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3472 PHY_M_LEDC_LOS_CTRL(9) |
3473 PHY_M_LEDC_INIT_CTRL(9) |
3474 PHY_M_LEDC_STA1_CTRL(9) |
3475 PHY_M_LEDC_STA0_CTRL(9));
3478 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3479 PHY_M_LEDC_LOS_CTRL(0xa) |
3480 PHY_M_LEDC_INIT_CTRL(0xa) |
3481 PHY_M_LEDC_STA1_CTRL(0xa) |
3482 PHY_M_LEDC_STA0_CTRL(0xa));
3485 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3486 PHY_M_LEDC_LOS_CTRL(1) |
3487 PHY_M_LEDC_INIT_CTRL(8) |
3488 PHY_M_LEDC_STA1_CTRL(7) |
3489 PHY_M_LEDC_STA0_CTRL(7));
3492 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3494 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3495 PHY_M_LED_MO_DUP(mode) |
3496 PHY_M_LED_MO_10(mode) |
3497 PHY_M_LED_MO_100(mode) |
3498 PHY_M_LED_MO_1000(mode) |
3499 PHY_M_LED_MO_RX(mode) |
3500 PHY_M_LED_MO_TX(mode));
3502 spin_unlock_bh(&sky2->phy_lock);
3505 /* blink LED's for finding board */
3506 static int sky2_phys_id(struct net_device *dev, u32 data)
3508 struct sky2_port *sky2 = netdev_priv(dev);
3514 for (i = 0; i < data; i++) {
3515 sky2_led(sky2, MO_LED_ON);
3516 if (msleep_interruptible(500))
3518 sky2_led(sky2, MO_LED_OFF);
3519 if (msleep_interruptible(500))
3522 sky2_led(sky2, MO_LED_NORM);
3527 static void sky2_get_pauseparam(struct net_device *dev,
3528 struct ethtool_pauseparam *ecmd)
3530 struct sky2_port *sky2 = netdev_priv(dev);
3532 switch (sky2->flow_mode) {
3534 ecmd->tx_pause = ecmd->rx_pause = 0;
3537 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3540 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3543 ecmd->tx_pause = ecmd->rx_pause = 1;
3546 ecmd->autoneg = sky2->autoneg;
3549 static int sky2_set_pauseparam(struct net_device *dev,
3550 struct ethtool_pauseparam *ecmd)
3552 struct sky2_port *sky2 = netdev_priv(dev);
3554 sky2->autoneg = ecmd->autoneg;
3555 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3557 if (netif_running(dev))
3558 sky2_phy_reinit(sky2);
3563 static int sky2_get_coalesce(struct net_device *dev,
3564 struct ethtool_coalesce *ecmd)
3566 struct sky2_port *sky2 = netdev_priv(dev);
3567 struct sky2_hw *hw = sky2->hw;
3569 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3570 ecmd->tx_coalesce_usecs = 0;
3572 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3573 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3575 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3577 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3578 ecmd->rx_coalesce_usecs = 0;
3580 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3581 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3583 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3585 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3586 ecmd->rx_coalesce_usecs_irq = 0;
3588 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3589 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3592 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3597 /* Note: this affect both ports */
3598 static int sky2_set_coalesce(struct net_device *dev,
3599 struct ethtool_coalesce *ecmd)
3601 struct sky2_port *sky2 = netdev_priv(dev);
3602 struct sky2_hw *hw = sky2->hw;
3603 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3605 if (ecmd->tx_coalesce_usecs > tmax ||
3606 ecmd->rx_coalesce_usecs > tmax ||
3607 ecmd->rx_coalesce_usecs_irq > tmax)
3610 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3612 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3614 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3617 if (ecmd->tx_coalesce_usecs == 0)
3618 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3620 sky2_write32(hw, STAT_TX_TIMER_INI,
3621 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3622 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3624 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3626 if (ecmd->rx_coalesce_usecs == 0)
3627 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3629 sky2_write32(hw, STAT_LEV_TIMER_INI,
3630 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3631 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3633 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3635 if (ecmd->rx_coalesce_usecs_irq == 0)
3636 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3638 sky2_write32(hw, STAT_ISR_TIMER_INI,
3639 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3640 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3642 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3646 static void sky2_get_ringparam(struct net_device *dev,
3647 struct ethtool_ringparam *ering)
3649 struct sky2_port *sky2 = netdev_priv(dev);
3651 ering->rx_max_pending = RX_MAX_PENDING;
3652 ering->rx_mini_max_pending = 0;
3653 ering->rx_jumbo_max_pending = 0;
3654 ering->tx_max_pending = TX_RING_SIZE - 1;
3656 ering->rx_pending = sky2->rx_pending;
3657 ering->rx_mini_pending = 0;
3658 ering->rx_jumbo_pending = 0;
3659 ering->tx_pending = sky2->tx_pending;
3662 static int sky2_set_ringparam(struct net_device *dev,
3663 struct ethtool_ringparam *ering)
3665 struct sky2_port *sky2 = netdev_priv(dev);
3668 if (ering->rx_pending > RX_MAX_PENDING ||
3669 ering->rx_pending < 8 ||
3670 ering->tx_pending < MAX_SKB_TX_LE ||
3671 ering->tx_pending > TX_RING_SIZE - 1)
3674 if (netif_running(dev))
3677 sky2->rx_pending = ering->rx_pending;
3678 sky2->tx_pending = ering->tx_pending;
3680 if (netif_running(dev)) {
3689 static int sky2_get_regs_len(struct net_device *dev)
3695 * Returns copy of control register region
3696 * Note: ethtool_get_regs always provides full size (16k) buffer
3698 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3701 const struct sky2_port *sky2 = netdev_priv(dev);
3702 const void __iomem *io = sky2->hw->regs;
3707 for (b = 0; b < 128; b++) {
3708 /* This complicated switch statement is to make sure and
3709 * only access regions that are unreserved.
3710 * Some blocks are only valid on dual port cards.
3711 * and block 3 has some special diagnostic registers that
3716 /* skip diagnostic ram region */
3717 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3720 /* dual port cards only */
3721 case 5: /* Tx Arbiter 2 */
3723 case 14 ... 15: /* TX2 */
3724 case 17: case 19: /* Ram Buffer 2 */
3725 case 22 ... 23: /* Tx Ram Buffer 2 */
3726 case 25: /* Rx MAC Fifo 1 */
3727 case 27: /* Tx MAC Fifo 2 */
3728 case 31: /* GPHY 2 */
3729 case 40 ... 47: /* Pattern Ram 2 */
3730 case 52: case 54: /* TCP Segmentation 2 */
3731 case 112 ... 116: /* GMAC 2 */
3732 if (sky2->hw->ports == 1)
3735 case 0: /* Control */
3736 case 2: /* Mac address */
3737 case 4: /* Tx Arbiter 1 */
3738 case 7: /* PCI express reg */
3740 case 12 ... 13: /* TX1 */
3741 case 16: case 18:/* Rx Ram Buffer 1 */
3742 case 20 ... 21: /* Tx Ram Buffer 1 */
3743 case 24: /* Rx MAC Fifo 1 */
3744 case 26: /* Tx MAC Fifo 1 */
3745 case 28 ... 29: /* Descriptor and status unit */
3746 case 30: /* GPHY 1*/
3747 case 32 ... 39: /* Pattern Ram 1 */
3748 case 48: case 50: /* TCP Segmentation 1 */
3749 case 56 ... 60: /* PCI space */
3750 case 80 ... 84: /* GMAC 1 */
3751 memcpy_fromio(p, io, 128);
3763 /* In order to do Jumbo packets on these chips, need to turn off the
3764 * transmit store/forward. Therefore checksum offload won't work.
3766 static int no_tx_offload(struct net_device *dev)
3768 const struct sky2_port *sky2 = netdev_priv(dev);
3769 const struct sky2_hw *hw = sky2->hw;
3771 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3774 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3776 if (data && no_tx_offload(dev))
3779 return ethtool_op_set_tx_csum(dev, data);
3783 static int sky2_set_tso(struct net_device *dev, u32 data)
3785 if (data && no_tx_offload(dev))
3788 return ethtool_op_set_tso(dev, data);
3791 static int sky2_get_eeprom_len(struct net_device *dev)
3793 struct sky2_port *sky2 = netdev_priv(dev);
3794 struct sky2_hw *hw = sky2->hw;
3797 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3798 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3801 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
3803 unsigned long start = jiffies;
3805 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3806 /* Can take up to 10.6 ms for write */
3807 if (time_after(jiffies, start + HZ/4)) {
3808 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3817 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
3818 u16 offset, size_t length)
3822 while (length > 0) {
3825 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3826 rc = sky2_vpd_wait(hw, cap, 0);
3830 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3832 memcpy(data, &val, min(sizeof(val), length));
3833 offset += sizeof(u32);
3834 data += sizeof(u32);
3835 length -= sizeof(u32);
3841 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
3842 u16 offset, unsigned int length)
3847 for (i = 0; i < length; i += sizeof(u32)) {
3848 u32 val = *(u32 *)(data + i);
3850 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3851 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3853 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
3860 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3863 struct sky2_port *sky2 = netdev_priv(dev);
3864 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3869 eeprom->magic = SKY2_EEPROM_MAGIC;
3871 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
3874 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3877 struct sky2_port *sky2 = netdev_priv(dev);
3878 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3883 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3886 /* Partial writes not supported */
3887 if ((eeprom->offset & 3) || (eeprom->len & 3))
3890 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
3894 static const struct ethtool_ops sky2_ethtool_ops = {
3895 .get_settings = sky2_get_settings,
3896 .set_settings = sky2_set_settings,
3897 .get_drvinfo = sky2_get_drvinfo,
3898 .get_wol = sky2_get_wol,
3899 .set_wol = sky2_set_wol,
3900 .get_msglevel = sky2_get_msglevel,
3901 .set_msglevel = sky2_set_msglevel,
3902 .nway_reset = sky2_nway_reset,
3903 .get_regs_len = sky2_get_regs_len,
3904 .get_regs = sky2_get_regs,
3905 .get_link = ethtool_op_get_link,
3906 .get_eeprom_len = sky2_get_eeprom_len,
3907 .get_eeprom = sky2_get_eeprom,
3908 .set_eeprom = sky2_set_eeprom,
3909 .set_sg = ethtool_op_set_sg,
3910 .set_tx_csum = sky2_set_tx_csum,
3911 .set_tso = sky2_set_tso,
3912 .get_rx_csum = sky2_get_rx_csum,
3913 .set_rx_csum = sky2_set_rx_csum,
3914 .get_strings = sky2_get_strings,
3915 .get_coalesce = sky2_get_coalesce,
3916 .set_coalesce = sky2_set_coalesce,
3917 .get_ringparam = sky2_get_ringparam,
3918 .set_ringparam = sky2_set_ringparam,
3919 .get_pauseparam = sky2_get_pauseparam,
3920 .set_pauseparam = sky2_set_pauseparam,
3921 .phys_id = sky2_phys_id,
3922 .get_sset_count = sky2_get_sset_count,
3923 .get_ethtool_stats = sky2_get_ethtool_stats,
3926 #ifdef CONFIG_SKY2_DEBUG
3928 static struct dentry *sky2_debug;
3932 * Read and parse the first part of Vital Product Data
3934 #define VPD_SIZE 128
3935 #define VPD_MAGIC 0x82
3937 static const struct vpd_tag {
3941 { "PN", "Part Number" },
3942 { "EC", "Engineering Level" },
3943 { "MN", "Manufacturer" },
3944 { "SN", "Serial Number" },
3945 { "YA", "Asset Tag" },
3946 { "VL", "First Error Log Message" },
3947 { "VF", "Second Error Log Message" },
3948 { "VB", "Boot Agent ROM Configuration" },
3949 { "VE", "EFI UNDI Configuration" },
3952 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
3960 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3961 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3963 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
3964 buf = kmalloc(vpd_size, GFP_KERNEL);
3966 seq_puts(seq, "no memory!\n");
3970 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
3971 seq_puts(seq, "VPD read failed\n");
3975 if (buf[0] != VPD_MAGIC) {
3976 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
3980 if (len == 0 || len > vpd_size - 4) {
3981 seq_printf(seq, "Invalid id length: %d\n", len);
3985 seq_printf(seq, "%.*s\n", len, buf + 3);
3988 while (offs < vpd_size - 4) {
3991 if (!memcmp("RW", buf + offs, 2)) /* end marker */
3993 len = buf[offs + 2];
3994 if (offs + len + 3 >= vpd_size)
3997 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
3998 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
3999 seq_printf(seq, " %s: %.*s\n",
4000 vpd_tags[i].label, len, buf + offs + 3);
4010 static int sky2_debug_show(struct seq_file *seq, void *v)
4012 struct net_device *dev = seq->private;
4013 const struct sky2_port *sky2 = netdev_priv(dev);
4014 struct sky2_hw *hw = sky2->hw;
4015 unsigned port = sky2->port;
4019 sky2_show_vpd(seq, hw);
4021 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4022 sky2_read32(hw, B0_ISRC),
4023 sky2_read32(hw, B0_IMSK),
4024 sky2_read32(hw, B0_Y2_SP_ICR));
4026 if (!netif_running(dev)) {
4027 seq_printf(seq, "network not running\n");
4031 napi_disable(&hw->napi);
4032 last = sky2_read16(hw, STAT_PUT_IDX);
4034 if (hw->st_idx == last)
4035 seq_puts(seq, "Status ring (empty)\n");
4037 seq_puts(seq, "Status ring\n");
4038 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4039 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4040 const struct sky2_status_le *le = hw->st_le + idx;
4041 seq_printf(seq, "[%d] %#x %d %#x\n",
4042 idx, le->opcode, le->length, le->status);
4044 seq_puts(seq, "\n");
4047 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4048 sky2->tx_cons, sky2->tx_prod,
4049 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4050 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4052 /* Dump contents of tx ring */
4054 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
4055 idx = RING_NEXT(idx, TX_RING_SIZE)) {
4056 const struct sky2_tx_le *le = sky2->tx_le + idx;
4057 u32 a = le32_to_cpu(le->addr);
4060 seq_printf(seq, "%u:", idx);
4063 switch(le->opcode & ~HW_OWNER) {
4065 seq_printf(seq, " %#x:", a);
4068 seq_printf(seq, " mtu=%d", a);
4071 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4074 seq_printf(seq, " csum=%#x", a);
4077 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4080 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4083 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4086 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4087 a, le16_to_cpu(le->length));
4090 if (le->ctrl & EOP) {
4091 seq_putc(seq, '\n');
4096 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4097 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4098 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4099 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4101 sky2_read32(hw, B0_Y2_SP_LISR);
4102 napi_enable(&hw->napi);
4106 static int sky2_debug_open(struct inode *inode, struct file *file)
4108 return single_open(file, sky2_debug_show, inode->i_private);
4111 static const struct file_operations sky2_debug_fops = {
4112 .owner = THIS_MODULE,
4113 .open = sky2_debug_open,
4115 .llseek = seq_lseek,
4116 .release = single_release,
4120 * Use network device events to create/remove/rename
4121 * debugfs file entries
4123 static int sky2_device_event(struct notifier_block *unused,
4124 unsigned long event, void *ptr)
4126 struct net_device *dev = ptr;
4127 struct sky2_port *sky2 = netdev_priv(dev);
4129 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
4133 case NETDEV_CHANGENAME:
4134 if (sky2->debugfs) {
4135 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4136 sky2_debug, dev->name);
4140 case NETDEV_GOING_DOWN:
4141 if (sky2->debugfs) {
4142 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4144 debugfs_remove(sky2->debugfs);
4145 sky2->debugfs = NULL;
4150 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4153 if (IS_ERR(sky2->debugfs))
4154 sky2->debugfs = NULL;
4160 static struct notifier_block sky2_notifier = {
4161 .notifier_call = sky2_device_event,
4165 static __init void sky2_debug_init(void)
4169 ent = debugfs_create_dir("sky2", NULL);
4170 if (!ent || IS_ERR(ent))
4174 register_netdevice_notifier(&sky2_notifier);
4177 static __exit void sky2_debug_cleanup(void)
4180 unregister_netdevice_notifier(&sky2_notifier);
4181 debugfs_remove(sky2_debug);
4187 #define sky2_debug_init()
4188 #define sky2_debug_cleanup()
4191 /* Two copies of network device operations to handle special case of
4192 not allowing netpoll on second port */
4193 static const struct net_device_ops sky2_netdev_ops[2] = {
4195 .ndo_open = sky2_up,
4196 .ndo_stop = sky2_down,
4197 .ndo_start_xmit = sky2_xmit_frame,
4198 .ndo_do_ioctl = sky2_ioctl,
4199 .ndo_validate_addr = eth_validate_addr,
4200 .ndo_set_mac_address = sky2_set_mac_address,
4201 .ndo_set_multicast_list = sky2_set_multicast,
4202 .ndo_change_mtu = sky2_change_mtu,
4203 .ndo_tx_timeout = sky2_tx_timeout,
4204 #ifdef SKY2_VLAN_TAG_USED
4205 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4207 #ifdef CONFIG_NET_POLL_CONTROLLER
4208 .ndo_poll_controller = sky2_netpoll,
4212 .ndo_open = sky2_up,
4213 .ndo_stop = sky2_down,
4214 .ndo_start_xmit = sky2_xmit_frame,
4215 .ndo_do_ioctl = sky2_ioctl,
4216 .ndo_validate_addr = eth_validate_addr,
4217 .ndo_set_mac_address = sky2_set_mac_address,
4218 .ndo_set_multicast_list = sky2_set_multicast,
4219 .ndo_change_mtu = sky2_change_mtu,
4220 .ndo_tx_timeout = sky2_tx_timeout,
4221 #ifdef SKY2_VLAN_TAG_USED
4222 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4227 /* Initialize network device */
4228 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
4230 int highmem, int wol)
4232 struct sky2_port *sky2;
4233 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4236 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
4240 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4241 dev->irq = hw->pdev->irq;
4242 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4243 dev->watchdog_timeo = TX_WATCHDOG;
4244 dev->netdev_ops = &sky2_netdev_ops[port];
4246 sky2 = netdev_priv(dev);
4249 sky2->msg_enable = netif_msg_init(debug, default_msg);
4251 /* Auto speed and flow control */
4252 sky2->autoneg = AUTONEG_ENABLE;
4253 sky2->flow_mode = FC_BOTH;
4257 sky2->advertising = sky2_supported_modes(hw);
4258 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
4261 spin_lock_init(&sky2->phy_lock);
4262 sky2->tx_pending = TX_DEF_PENDING;
4263 sky2->rx_pending = RX_DEF_PENDING;
4265 hw->dev[port] = dev;
4269 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4271 dev->features |= NETIF_F_HIGHDMA;
4273 #ifdef SKY2_VLAN_TAG_USED
4274 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4275 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4276 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4277 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4281 /* read the mac address */
4282 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4283 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4288 static void __devinit sky2_show_addr(struct net_device *dev)
4290 const struct sky2_port *sky2 = netdev_priv(dev);
4292 if (netif_msg_probe(sky2))
4293 printk(KERN_INFO PFX "%s: addr %pM\n",
4294 dev->name, dev->dev_addr);
4297 /* Handle software interrupt used during MSI test */
4298 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4300 struct sky2_hw *hw = dev_id;
4301 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4306 if (status & Y2_IS_IRQ_SW) {
4307 hw->flags |= SKY2_HW_USE_MSI;
4308 wake_up(&hw->msi_wait);
4309 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4311 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4316 /* Test interrupt path by forcing a a software IRQ */
4317 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4319 struct pci_dev *pdev = hw->pdev;
4322 init_waitqueue_head (&hw->msi_wait);
4324 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4326 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4328 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4332 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4333 sky2_read8(hw, B0_CTST);
4335 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4337 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4338 /* MSI test failed, go back to INTx mode */
4339 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4340 "switching to INTx mode.\n");
4343 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4346 sky2_write32(hw, B0_IMSK, 0);
4347 sky2_read32(hw, B0_IMSK);
4349 free_irq(pdev->irq, hw);
4354 /* This driver supports yukon2 chipset only */
4355 static const char *sky2_name(u8 chipid, char *buf, int sz)
4357 const char *name[] = {
4359 "EC Ultra", /* 0xb4 */
4360 "Extreme", /* 0xb5 */
4364 "Supreme", /* 0xb9 */
4368 if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
4369 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4371 snprintf(buf, sz, "(chip %#x)", chipid);
4375 static int __devinit sky2_probe(struct pci_dev *pdev,
4376 const struct pci_device_id *ent)
4378 struct net_device *dev;
4380 int err, using_dac = 0, wol_default;
4384 err = pci_enable_device(pdev);
4386 dev_err(&pdev->dev, "cannot enable PCI device\n");
4390 /* Get configuration information
4391 * Note: only regular PCI config access once to test for HW issues
4392 * other PCI access through shared memory for speed and to
4393 * avoid MMCONFIG problems.
4395 err = pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
4397 dev_err(&pdev->dev, "PCI read config failed\n");
4402 dev_err(&pdev->dev, "PCI configuration read error\n");
4406 err = pci_request_regions(pdev, DRV_NAME);
4408 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4409 goto err_out_disable;
4412 pci_set_master(pdev);
4414 if (sizeof(dma_addr_t) > sizeof(u32) &&
4415 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
4417 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4419 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4420 "for consistent allocations\n");
4421 goto err_out_free_regions;
4424 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4426 dev_err(&pdev->dev, "no usable DMA configuration\n");
4427 goto err_out_free_regions;
4433 /* The sk98lin vendor driver uses hardware byte swapping but
4434 * this driver uses software swapping.
4436 reg &= ~PCI_REV_DESC;
4437 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4439 dev_err(&pdev->dev, "PCI write config failed\n");
4440 goto err_out_free_regions;
4444 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
4447 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
4449 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4450 goto err_out_free_regions;
4455 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4457 dev_err(&pdev->dev, "cannot map device registers\n");
4458 goto err_out_free_hw;
4461 /* ring for status responses */
4462 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4464 goto err_out_iounmap;
4466 err = sky2_init(hw);
4468 goto err_out_iounmap;
4470 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4471 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
4475 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4478 goto err_out_free_pci;
4481 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4482 err = sky2_test_msi(hw);
4483 if (err == -EOPNOTSUPP)
4484 pci_disable_msi(pdev);
4486 goto err_out_free_netdev;
4489 err = register_netdev(dev);
4491 dev_err(&pdev->dev, "cannot register net device\n");
4492 goto err_out_free_netdev;
4495 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4497 err = request_irq(pdev->irq, sky2_intr,
4498 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4501 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4502 goto err_out_unregister;
4504 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4505 napi_enable(&hw->napi);
4507 sky2_show_addr(dev);
4509 if (hw->ports > 1) {
4510 struct net_device *dev1;
4512 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4514 dev_warn(&pdev->dev, "allocation for second device failed\n");
4515 else if ((err = register_netdev(dev1))) {
4516 dev_warn(&pdev->dev,
4517 "register of second port failed (%d)\n", err);
4521 sky2_show_addr(dev1);
4524 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4525 INIT_WORK(&hw->restart_work, sky2_restart);
4527 pci_set_drvdata(pdev, hw);
4532 if (hw->flags & SKY2_HW_USE_MSI)
4533 pci_disable_msi(pdev);
4534 unregister_netdev(dev);
4535 err_out_free_netdev:
4538 sky2_write8(hw, B0_CTST, CS_RST_SET);
4539 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4544 err_out_free_regions:
4545 pci_release_regions(pdev);
4547 pci_disable_device(pdev);
4549 pci_set_drvdata(pdev, NULL);
4553 static void __devexit sky2_remove(struct pci_dev *pdev)
4555 struct sky2_hw *hw = pci_get_drvdata(pdev);
4561 del_timer_sync(&hw->watchdog_timer);
4562 cancel_work_sync(&hw->restart_work);
4564 for (i = hw->ports-1; i >= 0; --i)
4565 unregister_netdev(hw->dev[i]);
4567 sky2_write32(hw, B0_IMSK, 0);
4571 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
4572 sky2_write8(hw, B0_CTST, CS_RST_SET);
4573 sky2_read8(hw, B0_CTST);
4575 free_irq(pdev->irq, hw);
4576 if (hw->flags & SKY2_HW_USE_MSI)
4577 pci_disable_msi(pdev);
4578 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4579 pci_release_regions(pdev);
4580 pci_disable_device(pdev);
4582 for (i = hw->ports-1; i >= 0; --i)
4583 free_netdev(hw->dev[i]);
4588 pci_set_drvdata(pdev, NULL);
4592 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4594 struct sky2_hw *hw = pci_get_drvdata(pdev);
4600 del_timer_sync(&hw->watchdog_timer);
4601 cancel_work_sync(&hw->restart_work);
4603 for (i = 0; i < hw->ports; i++) {
4604 struct net_device *dev = hw->dev[i];
4605 struct sky2_port *sky2 = netdev_priv(dev);
4607 netif_device_detach(dev);
4608 if (netif_running(dev))
4612 sky2_wol_init(sky2);
4617 sky2_write32(hw, B0_IMSK, 0);
4618 napi_disable(&hw->napi);
4621 pci_save_state(pdev);
4622 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4623 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4628 static int sky2_resume(struct pci_dev *pdev)
4630 struct sky2_hw *hw = pci_get_drvdata(pdev);
4636 err = pci_set_power_state(pdev, PCI_D0);
4640 err = pci_restore_state(pdev);
4644 pci_enable_wake(pdev, PCI_D0, 0);
4646 /* Re-enable all clocks */
4647 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4648 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4649 hw->chip_id == CHIP_ID_YUKON_FE_P)
4650 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4653 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4654 napi_enable(&hw->napi);
4656 for (i = 0; i < hw->ports; i++) {
4657 struct net_device *dev = hw->dev[i];
4659 netif_device_attach(dev);
4660 if (netif_running(dev)) {
4663 printk(KERN_ERR PFX "%s: could not up: %d\n",
4675 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4676 pci_disable_device(pdev);
4681 static void sky2_shutdown(struct pci_dev *pdev)
4683 struct sky2_hw *hw = pci_get_drvdata(pdev);
4689 del_timer_sync(&hw->watchdog_timer);
4691 for (i = 0; i < hw->ports; i++) {
4692 struct net_device *dev = hw->dev[i];
4693 struct sky2_port *sky2 = netdev_priv(dev);
4697 sky2_wol_init(sky2);
4704 pci_enable_wake(pdev, PCI_D3hot, wol);
4705 pci_enable_wake(pdev, PCI_D3cold, wol);
4707 pci_disable_device(pdev);
4708 pci_set_power_state(pdev, PCI_D3hot);
4711 static struct pci_driver sky2_driver = {
4713 .id_table = sky2_id_table,
4714 .probe = sky2_probe,
4715 .remove = __devexit_p(sky2_remove),
4717 .suspend = sky2_suspend,
4718 .resume = sky2_resume,
4720 .shutdown = sky2_shutdown,
4723 static int __init sky2_init_module(void)
4725 pr_info(PFX "driver version " DRV_VERSION "\n");
4728 return pci_register_driver(&sky2_driver);
4731 static void __exit sky2_cleanup_module(void)
4733 pci_unregister_driver(&sky2_driver);
4734 sky2_debug_cleanup();
4737 module_init(sky2_init_module);
4738 module_exit(sky2_cleanup_module);
4740 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4741 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4742 MODULE_LICENSE("GPL");
4743 MODULE_VERSION(DRV_VERSION);