2 * pata_atiixp.c - ATI PATA for new ATA layer
4 * Alan Cox <alan@redhat.com>
8 * linux/drivers/ide/pci/atiixp.c Version 0.01-bart2 Feb. 26, 2004
10 * Copyright (C) 2003 ATI Inc. <hyu@ati.com>
11 * Copyright (C) 2004 Bartlomiej Zolnierkiewicz
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/blkdev.h>
20 #include <linux/delay.h>
21 #include <scsi/scsi_host.h>
22 #include <linux/libata.h>
24 #define DRV_NAME "pata_atiixp"
25 #define DRV_VERSION "0.4.4"
28 ATIIXP_IDE_PIO_TIMING = 0x40,
29 ATIIXP_IDE_MWDMA_TIMING = 0x44,
30 ATIIXP_IDE_PIO_CONTROL = 0x48,
31 ATIIXP_IDE_PIO_MODE = 0x4a,
32 ATIIXP_IDE_UDMA_CONTROL = 0x54,
33 ATIIXP_IDE_UDMA_MODE = 0x56
36 static int atiixp_pre_reset(struct ata_port *ap)
38 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
39 static struct pci_bits atiixp_enable_bits[] = {
40 { 0x48, 1, 0x01, 0x00 },
41 { 0x48, 1, 0x08, 0x00 }
44 if (!pci_test_config_bits(pdev, &atiixp_enable_bits[ap->port_no]))
47 ap->cbl = ATA_CBL_PATA80;
48 return ata_std_prereset(ap);
51 static void atiixp_error_handler(struct ata_port *ap)
53 ata_bmdma_drive_eh(ap, atiixp_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
57 * atiixp_set_pio_timing - set initial PIO mode data
61 * Called by both the pio and dma setup functions to set the controller
62 * timings for PIO transfers. We must load both the mode number and
63 * timing values into the controller.
66 static void atiixp_set_pio_timing(struct ata_port *ap, struct ata_device *adev, int pio)
68 static u8 pio_timings[5] = { 0x5D, 0x47, 0x34, 0x22, 0x20 };
70 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
71 int dn = 2 * ap->port_no + adev->devno;
73 /* Check this is correct - the order is odd in both drivers */
74 int timing_shift = (16 * ap->port_no) + 8 * (adev->devno ^ 1);
75 u16 pio_mode_data, pio_timing_data;
77 pci_read_config_word(pdev, ATIIXP_IDE_PIO_MODE, &pio_mode_data);
78 pio_mode_data &= ~(0x7 << (4 * dn));
79 pio_mode_data |= pio << (4 * dn);
80 pci_write_config_word(pdev, ATIIXP_IDE_PIO_MODE, pio_mode_data);
82 pci_read_config_word(pdev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data);
83 pio_mode_data &= ~(0xFF << timing_shift);
84 pio_mode_data |= (pio_timings[pio] << timing_shift);
85 pci_write_config_word(pdev, ATIIXP_IDE_PIO_TIMING, pio_timing_data);
89 * atiixp_set_piomode - set initial PIO mode data
93 * Called to do the PIO mode setup. We use a shared helper for this
94 * as the DMA setup must also adjust the PIO timing information.
97 static void atiixp_set_piomode(struct ata_port *ap, struct ata_device *adev)
99 atiixp_set_pio_timing(ap, adev, adev->pio_mode - XFER_PIO_0);
103 * atiixp_set_dmamode - set initial DMA mode data
107 * Called to do the DMA mode setup. We use timing tables for most
108 * modes but must tune an appropriate PIO mode to match.
111 static void atiixp_set_dmamode(struct ata_port *ap, struct ata_device *adev)
113 static u8 mwdma_timings[5] = { 0x77, 0x21, 0x20 };
115 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
116 int dma = adev->dma_mode;
117 int dn = 2 * ap->port_no + adev->devno;
120 if (adev->dma_mode >= XFER_UDMA_0) {
125 pci_read_config_word(pdev, ATIIXP_IDE_UDMA_MODE, &udma_mode_data);
126 udma_mode_data &= ~(0x7 << (4 * dn));
127 udma_mode_data |= dma << (4 * dn);
128 pci_write_config_word(pdev, ATIIXP_IDE_UDMA_MODE, udma_mode_data);
130 u16 mwdma_timing_data;
131 /* Check this is correct - the order is odd in both drivers */
132 int timing_shift = (16 * ap->port_no) + 8 * (adev->devno ^ 1);
134 dma -= XFER_MW_DMA_0;
136 pci_read_config_word(pdev, ATIIXP_IDE_MWDMA_TIMING, &mwdma_timing_data);
137 mwdma_timing_data &= ~(0xFF << timing_shift);
138 mwdma_timing_data |= (mwdma_timings[dma] << timing_shift);
139 pci_write_config_word(pdev, ATIIXP_IDE_MWDMA_TIMING, mwdma_timing_data);
142 * We must now look at the PIO mode situation. We may need to
143 * adjust the PIO mode to keep the timings acceptable
145 if (adev->dma_mode >= XFER_MW_DMA_2)
147 else if (adev->dma_mode == XFER_MW_DMA_1)
149 else if (adev->dma_mode == XFER_MW_DMA_0)
153 if (adev->pio_mode != wanted_pio)
154 atiixp_set_pio_timing(ap, adev, wanted_pio);
158 * atiixp_bmdma_start - DMA start callback
159 * @qc: Command in progress
161 * When DMA begins we need to ensure that the UDMA control
162 * register for the channel is correctly set.
165 static void atiixp_bmdma_start(struct ata_queued_cmd *qc)
167 struct ata_port *ap = qc->ap;
168 struct ata_device *adev = qc->dev;
170 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
171 int dn = (2 * ap->port_no) + adev->devno;
174 pci_read_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
175 if (adev->dma_mode >= XFER_UDMA_0)
179 pci_write_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, tmp16);
184 * atiixp_dma_stop - DMA stop callback
185 * @qc: Command in progress
187 * DMA has completed. Clear the UDMA flag as the next operations will
188 * be PIO ones not UDMA data transfer.
191 static void atiixp_bmdma_stop(struct ata_queued_cmd *qc)
193 struct ata_port *ap = qc->ap;
194 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
195 int dn = (2 * ap->port_no) + qc->dev->devno;
198 pci_read_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
200 pci_write_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, tmp16);
204 static struct scsi_host_template atiixp_sht = {
205 .module = THIS_MODULE,
207 .ioctl = ata_scsi_ioctl,
208 .queuecommand = ata_scsi_queuecmd,
209 .can_queue = ATA_DEF_QUEUE,
210 .this_id = ATA_SHT_THIS_ID,
211 .sg_tablesize = LIBATA_MAX_PRD,
212 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
213 .emulated = ATA_SHT_EMULATED,
214 .use_clustering = ATA_SHT_USE_CLUSTERING,
215 .proc_name = DRV_NAME,
216 .dma_boundary = ATA_DMA_BOUNDARY,
217 .slave_configure = ata_scsi_slave_config,
218 .slave_destroy = ata_scsi_slave_destroy,
219 .bios_param = ata_std_bios_param,
220 .resume = ata_scsi_device_resume,
221 .suspend = ata_scsi_device_suspend,
224 static struct ata_port_operations atiixp_port_ops = {
225 .port_disable = ata_port_disable,
226 .set_piomode = atiixp_set_piomode,
227 .set_dmamode = atiixp_set_dmamode,
228 .mode_filter = ata_pci_default_filter,
229 .tf_load = ata_tf_load,
230 .tf_read = ata_tf_read,
231 .check_status = ata_check_status,
232 .exec_command = ata_exec_command,
233 .dev_select = ata_std_dev_select,
235 .freeze = ata_bmdma_freeze,
236 .thaw = ata_bmdma_thaw,
237 .error_handler = atiixp_error_handler,
238 .post_internal_cmd = ata_bmdma_post_internal_cmd,
240 .bmdma_setup = ata_bmdma_setup,
241 .bmdma_start = atiixp_bmdma_start,
242 .bmdma_stop = atiixp_bmdma_stop,
243 .bmdma_status = ata_bmdma_status,
245 .qc_prep = ata_qc_prep,
246 .qc_issue = ata_qc_issue_prot,
248 .data_xfer = ata_pio_data_xfer,
250 .irq_handler = ata_interrupt,
251 .irq_clear = ata_bmdma_irq_clear,
253 .port_start = ata_port_start,
254 .port_stop = ata_port_stop,
255 .host_stop = ata_host_stop
258 static int atiixp_init_one(struct pci_dev *dev, const struct pci_device_id *id)
260 static struct ata_port_info info = {
262 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
264 .mwdma_mask = 0x06, /* No MWDMA0 support */
266 .port_ops = &atiixp_port_ops
268 static struct ata_port_info *port_info[2] = { &info, &info };
269 return ata_pci_init_one(dev, port_info, 2);
272 static const struct pci_device_id atiixp[] = {
273 { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP200_IDE), },
274 { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP300_IDE), },
275 { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP400_IDE), },
276 { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP600_IDE), },
281 static struct pci_driver atiixp_pci_driver = {
284 .probe = atiixp_init_one,
285 .remove = ata_pci_remove_one,
286 .resume = ata_pci_device_resume,
287 .suspend = ata_pci_device_suspend,
290 static int __init atiixp_init(void)
292 return pci_register_driver(&atiixp_pci_driver);
296 static void __exit atiixp_exit(void)
298 pci_unregister_driver(&atiixp_pci_driver);
301 MODULE_AUTHOR("Alan Cox");
302 MODULE_DESCRIPTION("low-level driver for ATI IXP200/300/400");
303 MODULE_LICENSE("GPL");
304 MODULE_DEVICE_TABLE(pci, atiixp);
305 MODULE_VERSION(DRV_VERSION);
307 module_init(atiixp_init);
308 module_exit(atiixp_exit);