3 * device driver for Conexant 2388x based TV cards
4 * MPEG Transport Stream (DVB) routines
6 * (c) 2004, 2005 Chris Pascoe <c.pascoe@itee.uq.edu.au>
7 * (c) 2004 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/module.h>
25 #include <linux/init.h>
26 #include <linux/device.h>
28 #include <linux/kthread.h>
29 #include <linux/file.h>
30 #include <linux/suspend.h>
34 #include <media/v4l2-common.h>
38 # include "mt352_priv.h"
39 # ifdef HAVE_VP3054_I2C
40 # include "cx88-vp3054-i2c.h"
50 # include "lgdt330x.h"
59 MODULE_DESCRIPTION("driver for cx2388x based DVB cards");
60 MODULE_AUTHOR("Chris Pascoe <c.pascoe@itee.uq.edu.au>");
61 MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
62 MODULE_LICENSE("GPL");
64 static unsigned int debug = 0;
65 module_param(debug, int, 0644);
66 MODULE_PARM_DESC(debug,"enable debug messages [dvb]");
68 #define dprintk(level,fmt, arg...) if (debug >= level) \
69 printk(KERN_DEBUG "%s/2-dvb: " fmt, dev->core->name , ## arg)
71 /* ------------------------------------------------------------------ */
73 static int dvb_buf_setup(struct videobuf_queue *q,
74 unsigned int *count, unsigned int *size)
76 struct cx8802_dev *dev = q->priv_data;
78 dev->ts_packet_size = 188 * 4;
79 dev->ts_packet_count = 32;
81 *size = dev->ts_packet_size * dev->ts_packet_count;
86 static int dvb_buf_prepare(struct videobuf_queue *q, struct videobuf_buffer *vb,
87 enum v4l2_field field)
89 struct cx8802_dev *dev = q->priv_data;
90 return cx8802_buf_prepare(dev, (struct cx88_buffer*)vb,field);
93 static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
95 struct cx8802_dev *dev = q->priv_data;
96 cx8802_buf_queue(dev, (struct cx88_buffer*)vb);
99 static void dvb_buf_release(struct videobuf_queue *q, struct videobuf_buffer *vb)
101 struct cx8802_dev *dev = q->priv_data;
102 cx88_free_buffer(dev->pci, (struct cx88_buffer*)vb);
105 static struct videobuf_queue_ops dvb_qops = {
106 .buf_setup = dvb_buf_setup,
107 .buf_prepare = dvb_buf_prepare,
108 .buf_queue = dvb_buf_queue,
109 .buf_release = dvb_buf_release,
112 /* ------------------------------------------------------------------ */
115 static int dvico_fusionhdtv_demod_init(struct dvb_frontend* fe)
117 static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x39 };
118 static u8 reset [] = { RESET, 0x80 };
119 static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 };
120 static u8 agc_cfg [] = { AGC_TARGET, 0x24, 0x20 };
121 static u8 gpp_ctl_cfg [] = { GPP_CTL, 0x33 };
122 static u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 };
124 mt352_write(fe, clock_config, sizeof(clock_config));
126 mt352_write(fe, reset, sizeof(reset));
127 mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
129 mt352_write(fe, agc_cfg, sizeof(agc_cfg));
130 mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg));
131 mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
135 static int dvico_dual_demod_init(struct dvb_frontend *fe)
137 static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x38 };
138 static u8 reset [] = { RESET, 0x80 };
139 static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 };
140 static u8 agc_cfg [] = { AGC_TARGET, 0x28, 0x20 };
141 static u8 gpp_ctl_cfg [] = { GPP_CTL, 0x33 };
142 static u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 };
144 mt352_write(fe, clock_config, sizeof(clock_config));
146 mt352_write(fe, reset, sizeof(reset));
147 mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
149 mt352_write(fe, agc_cfg, sizeof(agc_cfg));
150 mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg));
151 mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
156 static int dntv_live_dvbt_demod_init(struct dvb_frontend* fe)
158 static u8 clock_config [] = { 0x89, 0x38, 0x39 };
159 static u8 reset [] = { 0x50, 0x80 };
160 static u8 adc_ctl_1_cfg [] = { 0x8E, 0x40 };
161 static u8 agc_cfg [] = { 0x67, 0x10, 0x23, 0x00, 0xFF, 0xFF,
162 0x00, 0xFF, 0x00, 0x40, 0x40 };
163 static u8 dntv_extra[] = { 0xB5, 0x7A };
164 static u8 capt_range_cfg[] = { 0x75, 0x32 };
166 mt352_write(fe, clock_config, sizeof(clock_config));
168 mt352_write(fe, reset, sizeof(reset));
169 mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
171 mt352_write(fe, agc_cfg, sizeof(agc_cfg));
173 mt352_write(fe, dntv_extra, sizeof(dntv_extra));
174 mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
179 static int mt352_pll_set(struct dvb_frontend* fe,
180 struct dvb_frontend_parameters* params,
183 struct cx8802_dev *dev= fe->dvb->priv;
185 pllbuf[0] = dev->core->pll_addr << 1;
186 dvb_pll_configure(dev->core->pll_desc, pllbuf+1,
188 params->u.ofdm.bandwidth);
192 static struct mt352_config dvico_fusionhdtv = {
193 .demod_address = 0x0F,
194 .demod_init = dvico_fusionhdtv_demod_init,
195 .pll_set = mt352_pll_set,
198 static struct mt352_config dntv_live_dvbt_config = {
199 .demod_address = 0x0f,
200 .demod_init = dntv_live_dvbt_demod_init,
201 .pll_set = mt352_pll_set,
204 static struct mt352_config dvico_fusionhdtv_dual = {
205 .demod_address = 0x0F,
206 .demod_init = dvico_dual_demod_init,
207 .pll_set = mt352_pll_set,
210 #ifdef HAVE_VP3054_I2C
211 static int dntv_live_dvbt_pro_demod_init(struct dvb_frontend* fe)
213 static u8 clock_config [] = { 0x89, 0x38, 0x38 };
214 static u8 reset [] = { 0x50, 0x80 };
215 static u8 adc_ctl_1_cfg [] = { 0x8E, 0x40 };
216 static u8 agc_cfg [] = { 0x67, 0x10, 0x20, 0x00, 0xFF, 0xFF,
217 0x00, 0xFF, 0x00, 0x40, 0x40 };
218 static u8 dntv_extra[] = { 0xB5, 0x7A };
219 static u8 capt_range_cfg[] = { 0x75, 0x32 };
221 mt352_write(fe, clock_config, sizeof(clock_config));
223 mt352_write(fe, reset, sizeof(reset));
224 mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
226 mt352_write(fe, agc_cfg, sizeof(agc_cfg));
228 mt352_write(fe, dntv_extra, sizeof(dntv_extra));
229 mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
234 static int philips_fmd1216_pll_init(struct dvb_frontend *fe)
236 struct cx8802_dev *dev= fe->dvb->priv;
238 /* this message is to set up ATC and ALC */
239 static u8 fmd1216_init[] = { 0x0b, 0xdc, 0x9c, 0xa0 };
241 { .addr = dev->core->pll_addr, .flags = 0,
242 .buf = fmd1216_init, .len = sizeof(fmd1216_init) };
245 if ((err = i2c_transfer(&dev->core->i2c_adap, &msg, 1)) != 1) {
255 static int dntv_live_dvbt_pro_pll_set(struct dvb_frontend* fe,
256 struct dvb_frontend_parameters* params,
259 struct cx8802_dev *dev= fe->dvb->priv;
261 { .addr = dev->core->pll_addr, .flags = 0,
262 .buf = pllbuf+1, .len = 4 };
265 /* Switch PLL to DVB mode */
266 err = philips_fmd1216_pll_init(fe);
271 pllbuf[0] = dev->core->pll_addr << 1;
272 dvb_pll_configure(dev->core->pll_desc, pllbuf+1,
274 params->u.ofdm.bandwidth);
275 if ((err = i2c_transfer(&dev->core->i2c_adap, &msg, 1)) != 1) {
276 printk(KERN_WARNING "cx88-dvb: %s error "
277 "(addr %02x <- %02x, err = %i)\n",
278 __FUNCTION__, pllbuf[0], pllbuf[1], err);
288 static struct mt352_config dntv_live_dvbt_pro_config = {
289 .demod_address = 0x0f,
291 .demod_init = dntv_live_dvbt_pro_demod_init,
292 .pll_set = dntv_live_dvbt_pro_pll_set,
298 static struct cx22702_config connexant_refboard_config = {
299 .demod_address = 0x43,
300 .output_mode = CX22702_SERIAL_OUTPUT,
302 .pll_desc = &dvb_pll_thomson_dtt7579,
305 static struct cx22702_config hauppauge_novat_config = {
306 .demod_address = 0x43,
307 .output_mode = CX22702_SERIAL_OUTPUT,
309 .pll_desc = &dvb_pll_thomson_dtt759x,
311 static struct cx22702_config hauppauge_hvr1100_config = {
312 .demod_address = 0x63,
313 .output_mode = CX22702_SERIAL_OUTPUT,
315 .pll_desc = &dvb_pll_fmd1216me,
320 static int or51132_set_ts_param(struct dvb_frontend* fe,
323 struct cx8802_dev *dev= fe->dvb->priv;
324 dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00;
328 static struct or51132_config pchdtv_hd3000 = {
329 .demod_address = 0x15,
331 .pll_desc = &dvb_pll_thomson_dtt7610,
332 .set_ts_params = or51132_set_ts_param,
337 static int lgdt330x_pll_set(struct dvb_frontend* fe,
338 struct dvb_frontend_parameters* params)
340 /* FIXME make this routine use the tuner-simple code.
341 * It could probably be shared with a number of ATSC
342 * frontends. Many share the same tuner with analog TV. */
344 struct cx8802_dev *dev= fe->dvb->priv;
345 struct cx88_core *core = dev->core;
348 { .addr = dev->core->pll_addr, .flags = 0, .buf = buf, .len = 4 };
351 /* Put the analog decoder in standby to keep it quiet */
352 cx88_call_i2c_clients (dev->core, TUNER_SET_STANDBY, NULL);
354 dvb_pll_configure(core->pll_desc, buf, params->frequency, 0);
355 dprintk(1, "%s: tuner at 0x%02x bytes: 0x%02x 0x%02x 0x%02x 0x%02x\n",
356 __FUNCTION__, msg.addr, buf[0],buf[1],buf[2],buf[3]);
357 if ((err = i2c_transfer(&core->i2c_adap, &msg, 1)) != 1) {
358 printk(KERN_WARNING "cx88-dvb: %s error "
359 "(addr %02x <- %02x, err = %i)\n",
360 __FUNCTION__, buf[0], buf[1], err);
366 if (core->tuner_type == TUNER_LG_TDVS_H062F) {
367 /* Set the Auxiliary Byte. */
371 i2c_transfer(&core->i2c_adap, &msg, 1);
376 static int lgdt330x_pll_rf_set(struct dvb_frontend* fe, int index)
378 struct cx8802_dev *dev= fe->dvb->priv;
379 struct cx88_core *core = dev->core;
381 dprintk(1, "%s: index = %d\n", __FUNCTION__, index);
383 cx_clear(MO_GP0_IO, 8);
385 cx_set(MO_GP0_IO, 8);
389 static int lgdt330x_set_ts_param(struct dvb_frontend* fe, int is_punctured)
391 struct cx8802_dev *dev= fe->dvb->priv;
393 dev->ts_gen_cntrl |= 0x04;
395 dev->ts_gen_cntrl &= ~0x04;
399 static struct lgdt330x_config fusionhdtv_3_gold = {
400 .demod_address = 0x0e,
401 .demod_chip = LGDT3302,
402 .serial_mpeg = 0x04, /* TPSERIAL for 3302 in TOP_CONTROL */
403 .pll_set = lgdt330x_pll_set,
404 .set_ts_params = lgdt330x_set_ts_param,
407 static struct lgdt330x_config fusionhdtv_5_gold = {
408 .demod_address = 0x0e,
409 .demod_chip = LGDT3303,
410 .serial_mpeg = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */
411 .pll_set = lgdt330x_pll_set,
412 .set_ts_params = lgdt330x_set_ts_param,
417 static int nxt200x_set_ts_param(struct dvb_frontend* fe,
420 struct cx8802_dev *dev= fe->dvb->priv;
421 dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00;
425 static int nxt200x_set_pll_input(u8* buf, int input)
434 static struct nxt200x_config ati_hdtvwonder = {
435 .demod_address = 0x0a,
437 .pll_desc = &dvb_pll_tuv1236d,
438 .set_pll_input = nxt200x_set_pll_input,
439 .set_ts_params = nxt200x_set_ts_param,
444 static int cx24123_set_ts_param(struct dvb_frontend* fe,
447 struct cx8802_dev *dev= fe->dvb->priv;
448 dev->ts_gen_cntrl = 0x2;
452 static void cx24123_enable_lnb_voltage(struct dvb_frontend* fe, int on)
454 struct cx8802_dev *dev= fe->dvb->priv;
455 struct cx88_core *core = dev->core;
458 cx_write(MO_GP0_IO, 0x000006f9);
460 cx_write(MO_GP0_IO, 0x000006fB);
463 static struct cx24123_config hauppauge_novas_config = {
464 .demod_address = 0x55,
466 .set_ts_params = cx24123_set_ts_param,
469 static struct cx24123_config kworld_dvbs_100_config = {
470 .demod_address = 0x15,
472 .set_ts_params = cx24123_set_ts_param,
473 .enable_lnb_voltage = cx24123_enable_lnb_voltage,
477 static int dvb_register(struct cx8802_dev *dev)
479 /* init struct videobuf_dvb */
480 dev->dvb.name = dev->core->name;
481 dev->ts_gen_cntrl = 0x0c;
484 switch (dev->core->board) {
486 case CX88_BOARD_HAUPPAUGE_DVB_T1:
487 dev->dvb.frontend = cx22702_attach(&hauppauge_novat_config,
488 &dev->core->i2c_adap);
490 case CX88_BOARD_TERRATEC_CINERGY_1400_DVB_T1:
491 case CX88_BOARD_CONEXANT_DVB_T1:
492 case CX88_BOARD_KWORLD_DVB_T_CX22702:
493 case CX88_BOARD_WINFAST_DTV1000:
494 dev->dvb.frontend = cx22702_attach(&connexant_refboard_config,
495 &dev->core->i2c_adap);
497 case CX88_BOARD_HAUPPAUGE_HVR1100:
498 case CX88_BOARD_HAUPPAUGE_HVR1100LP:
499 dev->dvb.frontend = cx22702_attach(&hauppauge_hvr1100_config,
500 &dev->core->i2c_adap);
504 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T1:
505 dev->core->pll_addr = 0x61;
506 dev->core->pll_desc = &dvb_pll_lg_z201;
507 dev->dvb.frontend = mt352_attach(&dvico_fusionhdtv,
508 &dev->core->i2c_adap);
510 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PLUS:
511 dev->core->pll_addr = 0x60;
512 dev->core->pll_desc = &dvb_pll_thomson_dtt7579;
513 dev->dvb.frontend = mt352_attach(&dvico_fusionhdtv,
514 &dev->core->i2c_adap);
516 case CX88_BOARD_KWORLD_DVB_T:
517 case CX88_BOARD_DNTV_LIVE_DVB_T:
518 case CX88_BOARD_ADSTECH_DVB_T_PCI:
519 dev->core->pll_addr = 0x61;
520 dev->core->pll_desc = &dvb_pll_unknown_1;
521 dev->dvb.frontend = mt352_attach(&dntv_live_dvbt_config,
522 &dev->core->i2c_adap);
524 case CX88_BOARD_DNTV_LIVE_DVB_T_PRO:
525 #ifdef HAVE_VP3054_I2C
526 dev->core->pll_addr = 0x61;
527 dev->core->pll_desc = &dvb_pll_fmd1216me;
528 dev->dvb.frontend = mt352_attach(&dntv_live_dvbt_pro_config,
529 &((struct vp3054_i2c_state *)dev->card_priv)->adap);
531 printk("%s: built without vp3054 support\n", dev->core->name);
534 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL:
535 /* The tin box says DEE1601, but it seems to be DTT7579
536 * compatible, with a slightly different MT352 AGC gain. */
537 dev->core->pll_addr = 0x61;
538 dev->core->pll_desc = &dvb_pll_thomson_dtt7579;
539 dev->dvb.frontend = mt352_attach(&dvico_fusionhdtv_dual,
540 &dev->core->i2c_adap);
544 case CX88_BOARD_PCHDTV_HD3000:
545 dev->dvb.frontend = or51132_attach(&pchdtv_hd3000,
546 &dev->core->i2c_adap);
550 case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q:
551 dev->ts_gen_cntrl = 0x08;
553 /* Do a hardware reset of chip before using it. */
554 struct cx88_core *core = dev->core;
556 cx_clear(MO_GP0_IO, 1);
558 cx_set(MO_GP0_IO, 1);
561 /* Select RF connector callback */
562 fusionhdtv_3_gold.pll_rf_set = lgdt330x_pll_rf_set;
563 dev->core->pll_addr = 0x61;
564 dev->core->pll_desc = &dvb_pll_microtune_4042;
565 dev->dvb.frontend = lgdt330x_attach(&fusionhdtv_3_gold,
566 &dev->core->i2c_adap);
569 case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_T:
570 dev->ts_gen_cntrl = 0x08;
572 /* Do a hardware reset of chip before using it. */
573 struct cx88_core *core = dev->core;
575 cx_clear(MO_GP0_IO, 1);
577 cx_set(MO_GP0_IO, 9);
579 dev->core->pll_addr = 0x61;
580 dev->core->pll_desc = &dvb_pll_thomson_dtt761x;
581 dev->dvb.frontend = lgdt330x_attach(&fusionhdtv_3_gold,
582 &dev->core->i2c_adap);
585 case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD:
586 dev->ts_gen_cntrl = 0x08;
588 /* Do a hardware reset of chip before using it. */
589 struct cx88_core *core = dev->core;
591 cx_clear(MO_GP0_IO, 1);
593 cx_set(MO_GP0_IO, 1);
595 dev->core->pll_addr = 0x61;
596 dev->core->pll_desc = &dvb_pll_tdvs_tua6034;
597 dev->dvb.frontend = lgdt330x_attach(&fusionhdtv_5_gold,
598 &dev->core->i2c_adap);
603 case CX88_BOARD_ATI_HDTVWONDER:
604 dev->dvb.frontend = nxt200x_attach(&ati_hdtvwonder,
605 &dev->core->i2c_adap);
609 case CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1:
610 case CX88_BOARD_HAUPPAUGE_NOVASE2_S1:
611 dev->dvb.frontend = cx24123_attach(&hauppauge_novas_config,
612 &dev->core->i2c_adap);
614 case CX88_BOARD_KWORLD_DVBS_100:
615 dev->dvb.frontend = cx24123_attach(&kworld_dvbs_100_config,
616 &dev->core->i2c_adap);
620 printk("%s: The frontend of your DVB/ATSC card isn't supported yet\n",
624 if (NULL == dev->dvb.frontend) {
625 printk("%s: frontend initialization failed\n",dev->core->name);
629 if (dev->core->pll_desc) {
630 dev->dvb.frontend->ops->info.frequency_min = dev->core->pll_desc->min;
631 dev->dvb.frontend->ops->info.frequency_max = dev->core->pll_desc->max;
634 /* Put the analog decoder in standby to keep it quiet */
635 cx88_call_i2c_clients (dev->core, TUNER_SET_STANDBY, NULL);
637 /* register everything */
638 return videobuf_dvb_register(&dev->dvb, THIS_MODULE, dev);
641 /* ----------------------------------------------------------- */
643 static int __devinit dvb_probe(struct pci_dev *pci_dev,
644 const struct pci_device_id *pci_id)
646 struct cx8802_dev *dev;
647 struct cx88_core *core;
651 core = cx88_core_get(pci_dev);
656 if (!cx88_boards[core->board].dvb)
660 dev = kzalloc(sizeof(*dev),GFP_KERNEL);
666 err = cx8802_init_common(dev);
670 #ifdef HAVE_VP3054_I2C
671 err = vp3054_i2c_probe(dev);
677 printk("%s/2: cx2388x based dvb card\n", core->name);
678 videobuf_queue_init(&dev->dvb.dvbq, &dvb_qops,
679 dev->pci, &dev->slock,
680 V4L2_BUF_TYPE_VIDEO_CAPTURE,
682 sizeof(struct cx88_buffer),
684 err = dvb_register(dev);
688 /* Maintain a reference to cx88-video can query the 8802 device. */
693 cx8802_fini_common(dev);
697 cx88_core_put(core,pci_dev);
701 static void __devexit dvb_remove(struct pci_dev *pci_dev)
703 struct cx8802_dev *dev = pci_get_drvdata(pci_dev);
705 /* Destroy any 8802 reference. */
706 dev->core->dvbdev = NULL;
709 videobuf_dvb_unregister(&dev->dvb);
711 #ifdef HAVE_VP3054_I2C
712 vp3054_i2c_remove(dev);
716 cx8802_fini_common(dev);
717 cx88_core_put(dev->core,dev->pci);
721 static struct pci_device_id cx8802_pci_tbl[] = {
725 .subvendor = PCI_ANY_ID,
726 .subdevice = PCI_ANY_ID,
728 /* --- end of list --- */
731 MODULE_DEVICE_TABLE(pci, cx8802_pci_tbl);
733 static struct pci_driver dvb_pci_driver = {
735 .id_table = cx8802_pci_tbl,
737 .remove = __devexit_p(dvb_remove),
738 .suspend = cx8802_suspend_common,
739 .resume = cx8802_resume_common,
742 static int dvb_init(void)
744 printk(KERN_INFO "cx2388x dvb driver version %d.%d.%d loaded\n",
745 (CX88_VERSION_CODE >> 16) & 0xff,
746 (CX88_VERSION_CODE >> 8) & 0xff,
747 CX88_VERSION_CODE & 0xff);
749 printk(KERN_INFO "cx2388x: snapshot date %04d-%02d-%02d\n",
750 SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
752 return pci_register_driver(&dvb_pci_driver);
755 static void dvb_fini(void)
757 pci_unregister_driver(&dvb_pci_driver);
760 module_init(dvb_init);
761 module_exit(dvb_fini);
766 * compile-command: "make DVB=1"