2 * MPC8541 CDS Device Tree Source
4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
16 compatible = "MPC8541CDS", "MPC85xxCDS";
36 d-cache-line-size = <32>; // 32 bytes
37 i-cache-line-size = <32>; // 32 bytes
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
40 timebase-frequency = <0>; // 33 MHz, from uboot
41 bus-frequency = <0>; // 166 MHz
42 clock-frequency = <0>; // 825 MHz, from uboot
43 next-level-cache = <&L2>;
48 device_type = "memory";
49 reg = <0x0 0x8000000>; // 128M at 0x0
56 ranges = <0x0 0xe0000000 0x100000>;
57 reg = <0xe0000000 0x1000>; // CCSRBAR 1M
60 memory-controller@2000 {
61 compatible = "fsl,8541-memory-controller";
62 reg = <0x2000 0x1000>;
63 interrupt-parent = <&mpic>;
67 L2: l2-cache-controller@20000 {
68 compatible = "fsl,8541-l2-cache-controller";
69 reg = <0x20000 0x1000>;
70 cache-line-size = <32>; // 32 bytes
71 cache-size = <0x40000>; // L2, 256K
72 interrupt-parent = <&mpic>;
80 compatible = "fsl-i2c";
83 interrupt-parent = <&mpic>;
90 compatible = "fsl,gianfar-mdio";
93 phy0: ethernet-phy@0 {
94 interrupt-parent = <&mpic>;
97 device_type = "ethernet-phy";
99 phy1: ethernet-phy@1 {
100 interrupt-parent = <&mpic>;
103 device_type = "ethernet-phy";
107 enet0: ethernet@24000 {
109 device_type = "network";
111 compatible = "gianfar";
112 reg = <0x24000 0x1000>;
113 local-mac-address = [ 00 00 00 00 00 00 ];
114 interrupts = <29 2 30 2 34 2>;
115 interrupt-parent = <&mpic>;
116 phy-handle = <&phy0>;
119 enet1: ethernet@25000 {
121 device_type = "network";
123 compatible = "gianfar";
124 reg = <0x25000 0x1000>;
125 local-mac-address = [ 00 00 00 00 00 00 ];
126 interrupts = <35 2 36 2 40 2>;
127 interrupt-parent = <&mpic>;
128 phy-handle = <&phy1>;
131 serial0: serial@4500 {
133 device_type = "serial";
134 compatible = "ns16550";
135 reg = <0x4500 0x100>; // reg base, size
136 clock-frequency = <0>; // should we fill in in uboot?
138 interrupt-parent = <&mpic>;
141 serial1: serial@4600 {
143 device_type = "serial";
144 compatible = "ns16550";
145 reg = <0x4600 0x100>; // reg base, size
146 clock-frequency = <0>; // should we fill in in uboot?
148 interrupt-parent = <&mpic>;
152 interrupt-controller;
153 #address-cells = <0>;
154 #interrupt-cells = <2>;
155 reg = <0x40000 0x40000>;
156 compatible = "chrp,open-pic";
157 device_type = "open-pic";
161 #address-cells = <1>;
163 compatible = "fsl,mpc8541-cpm", "fsl,cpm2";
164 reg = <0x919c0 0x30>;
168 #address-cells = <1>;
170 ranges = <0x0 0x80000 0x10000>;
173 compatible = "fsl,cpm-muram-data";
174 reg = <0x0 0x2000 0x9000 0x1000>;
179 compatible = "fsl,mpc8541-brg",
182 reg = <0x919f0 0x10 0x915f0 0x10>;
186 interrupt-controller;
187 #address-cells = <0>;
188 #interrupt-cells = <2>;
190 interrupt-parent = <&mpic>;
191 reg = <0x90c00 0x80>;
192 compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic";
199 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
203 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
204 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
205 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
206 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
209 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
210 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
211 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
212 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
214 /* IDSEL 0x12 (Slot 1) */
215 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
216 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
217 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
218 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
220 /* IDSEL 0x13 (Slot 2) */
221 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
222 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
223 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
224 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
226 /* IDSEL 0x14 (Slot 3) */
227 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
228 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
229 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
230 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
232 /* IDSEL 0x15 (Slot 4) */
233 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
234 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
235 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
236 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
238 /* Bus 1 (Tundra Bridge) */
239 /* IDSEL 0x12 (ISA bridge) */
240 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
241 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
242 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
243 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
244 interrupt-parent = <&mpic>;
247 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
248 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
249 clock-frequency = <66666666>;
250 #interrupt-cells = <1>;
252 #address-cells = <3>;
253 reg = <0xe0008000 0x1000>;
254 compatible = "fsl,mpc8540-pci";
258 interrupt-controller;
259 device_type = "interrupt-controller";
260 reg = <0x19000 0x0 0x0 0x0 0x1>;
261 #address-cells = <0>;
262 #interrupt-cells = <2>;
263 compatible = "chrp,iic";
265 interrupt-parent = <&pci0>;
271 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
275 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
276 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
277 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
278 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
279 interrupt-parent = <&mpic>;
282 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
283 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
284 clock-frequency = <66666666>;
285 #interrupt-cells = <1>;
287 #address-cells = <3>;
288 reg = <0xe0009000 0x1000>;
289 compatible = "fsl,mpc8540-pci";