git.oblomov.eu Git - linux-2.6/blob - arch/powerpc/boot/dts/mpc8568mds.dts

   1 /*
   2  * MPC8568E MDS Device Tree Source
   3  *
   4  * Copyright 2007, 2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 / {
  15         model = "MPC8568EMDS";
  16         compatible = "MPC8568EMDS", "MPC85xxMDS";
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         aliases {
  21                 ethernet0 = &enet0;
  22                 ethernet1 = &enet1;
  23                 ethernet2 = &enet2;
  24                 ethernet3 = &enet3;
  25                 serial0 = &serial0;
  26                 serial1 = &serial1;
  27                 pci0 = &pci0;
  28                 pci1 = &pci1;
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 PowerPC,8568@0 {
  36                         device_type = "cpu";
  37                         reg = <0x0>;
  38                         d-cache-line-size = <32>;       // 32 bytes
  39                         i-cache-line-size = <32>;       // 32 bytes
  40                         d-cache-size = <0x8000>;                // L1, 32K
  41                         i-cache-size = <0x8000>;                // L1, 32K
  42                         timebase-frequency = <0>;
  43                         bus-frequency = <0>;
  44                         clock-frequency = <0>;
  45                         next-level-cache = <&L2>;
  46                 };
  47         };
  48
  49         memory {
  50                 device_type = "memory";
  51                 reg = <0x0 0x10000000>;
  52         };
  53
  54         bcsr@f8000000 {
  55                 device_type = "board-control";
  56                 reg = <0xf8000000 0x8000>;
  57         };
  58
  59         soc8568@e0000000 {
  60                 #address-cells = <1>;
  61                 #size-cells = <1>;
  62                 device_type = "soc";
  63                 ranges = <0x0 0xe0000000 0x100000>;
  64                 reg = <0xe0000000 0x1000>;
  65                 bus-frequency = <0>;
  66
  67                 memory-controller@2000 {
  68                         compatible = "fsl,8568-memory-controller";
  69                         reg = <0x2000 0x1000>;
  70                         interrupt-parent = <&mpic>;
  71                         interrupts = <18 2>;
  72                 };
  73
  74                 L2: l2-cache-controller@20000 {
  75                         compatible = "fsl,8568-l2-cache-controller";
  76                         reg = <0x20000 0x1000>;
  77                         cache-line-size = <32>; // 32 bytes
  78                         cache-size = <0x80000>; // L2, 512K
  79                         interrupt-parent = <&mpic>;
  80                         interrupts = <16 2>;
  81                 };
  82
  83                 i2c@3000 {
  84                         #address-cells = <1>;
  85                         #size-cells = <0>;
  86                         cell-index = <0>;
  87                         compatible = "fsl-i2c";
  88                         reg = <0x3000 0x100>;
  89                         interrupts = <43 2>;
  90                         interrupt-parent = <&mpic>;
  91                         dfsrr;
  92
  93                         rtc@68 {
  94                                 compatible = "dallas,ds1374";
  95                                 reg = <0x68>;
  96                         };
  97                 };
  98
  99                 i2c@3100 {
 100                         #address-cells = <1>;
 101                         #size-cells = <0>;
 102                         cell-index = <1>;
 103                         compatible = "fsl-i2c";
 104                         reg = <0x3100 0x100>;
 105                         interrupts = <43 2>;
 106                         interrupt-parent = <&mpic>;
 107                         dfsrr;
 108                 };
 109
 110                 mdio@24520 {
 111                         #address-cells = <1>;
 112                         #size-cells = <0>;
 113                         compatible = "fsl,gianfar-mdio";
 114                         reg = <0x24520 0x20>;
 115
 116                         phy0: ethernet-phy@7 {
 117                                 interrupt-parent = <&mpic>;
 118                                 interrupts = <1 1>;
 119                                 reg = <0x7>;
 120                                 device_type = "ethernet-phy";
 121                         };
 122                         phy1: ethernet-phy@1 {
 123                                 interrupt-parent = <&mpic>;
 124                                 interrupts = <2 1>;
 125                                 reg = <0x1>;
 126                                 device_type = "ethernet-phy";
 127                         };
 128                         phy2: ethernet-phy@2 {
 129                                 interrupt-parent = <&mpic>;
 130                                 interrupts = <1 1>;
 131                                 reg = <0x2>;
 132                                 device_type = "ethernet-phy";
 133                         };
 134                         phy3: ethernet-phy@3 {
 135                                 interrupt-parent = <&mpic>;
 136                                 interrupts = <2 1>;
 137                                 reg = <0x3>;
 138                                 device_type = "ethernet-phy";
 139                         };
 140                 };
 141
 142                 enet0: ethernet@24000 {
 143                         cell-index = <0>;
 144                         device_type = "network";
 145                         model = "eTSEC";
 146                         compatible = "gianfar";
 147                         reg = <0x24000 0x1000>;
 148                         local-mac-address = [ 00 00 00 00 00 00 ];
 149                         interrupts = <29 2 30 2 34 2>;
 150                         interrupt-parent = <&mpic>;
 151                         phy-handle = <&phy2>;
 152                 };
 153
 154                 enet1: ethernet@25000 {
 155                         cell-index = <1>;
 156                         device_type = "network";
 157                         model = "eTSEC";
 158                         compatible = "gianfar";
 159                         reg = <0x25000 0x1000>;
 160                         local-mac-address = [ 00 00 00 00 00 00 ];
 161                         interrupts = <35 2 36 2 40 2>;
 162                         interrupt-parent = <&mpic>;
 163                         phy-handle = <&phy3>;
 164                 };
 165
 166                 serial0: serial@4500 {
 167                         cell-index = <0>;
 168                         device_type = "serial";
 169                         compatible = "ns16550";
 170                         reg = <0x4500 0x100>;
 171                         clock-frequency = <0>;
 172                         interrupts = <42 2>;
 173                         interrupt-parent = <&mpic>;
 174                 };
 175
 176                 global-utilities@e0000 {        //global utilities block
 177                         compatible = "fsl,mpc8548-guts";
 178                         reg = <0xe0000 0x1000>;
 179                         fsl,has-rstcr;
 180                 };
 181
 182                 serial1: serial@4600 {
 183                         cell-index = <1>;
 184                         device_type = "serial";
 185                         compatible = "ns16550";
 186                         reg = <0x4600 0x100>;
 187                         clock-frequency = <0>;
 188                         interrupts = <42 2>;
 189                         interrupt-parent = <&mpic>;
 190                 };
 191
 192                 crypto@30000 {
 193                         device_type = "crypto";
 194                         model = "SEC2";
 195                         compatible = "talitos";
 196                         reg = <0x30000 0xf000>;
 197                         interrupts = <45 2>;
 198                         interrupt-parent = <&mpic>;
 199                         num-channels = <4>;
 200                         channel-fifo-len = <24>;
 201                         exec-units-mask = <0xfe>;
 202                         descriptor-types-mask = <0x12b0ebf>;
 203                 };
 204
 205                 mpic: pic@40000 {
 206                         interrupt-controller;
 207                         #address-cells = <0>;
 208                         #interrupt-cells = <2>;
 209                         reg = <0x40000 0x40000>;
 210                         compatible = "chrp,open-pic";
 211                         device_type = "open-pic";
 212                 };
 213
 214                 par_io@e0100 {
 215                         reg = <0xe0100 0x100>;
 216                         device_type = "par_io";
 217                         num-ports = <7>;
 218
 219                         pio1: ucc_pin@01 {
 220                                 pio-map = <
 221                         /* port  pin  dir  open_drain  assignment  has_irq */
 222                                         0x4  0xa  0x1  0x0  0x2  0x0    /* TxD0 */
 223                                         0x4  0x9  0x1  0x0  0x2  0x0    /* TxD1 */
 224                                         0x4  0x8  0x1  0x0  0x2  0x0    /* TxD2 */
 225                                         0x4  0x7  0x1  0x0  0x2  0x0    /* TxD3 */
 226                                         0x4  0x17  0x1  0x0  0x2  0x0   /* TxD4 */
 227                                         0x4  0x16  0x1  0x0  0x2  0x0   /* TxD5 */
 228                                         0x4  0x15  0x1  0x0  0x2  0x0   /* TxD6 */
 229                                         0x4  0x14  0x1  0x0  0x2  0x0   /* TxD7 */
 230                                         0x4  0xf  0x2  0x0  0x2  0x0    /* RxD0 */
 231                                         0x4  0xe  0x2  0x0  0x2  0x0    /* RxD1 */
 232                                         0x4  0xd  0x2  0x0  0x2  0x0    /* RxD2 */
 233                                         0x4  0xc  0x2  0x0  0x2  0x0    /* RxD3 */
 234                                         0x4  0x1d  0x2  0x0  0x2  0x0   /* RxD4 */
 235                                         0x4  0x1c  0x2  0x0  0x2  0x0   /* RxD5 */
 236                                         0x4  0x1b  0x2  0x0  0x2  0x0   /* RxD6 */
 237                                         0x4  0x1a  0x2  0x0  0x2  0x0   /* RxD7 */
 238                                         0x4  0xb  0x1  0x0  0x2  0x0    /* TX_EN */
 239                                         0x4  0x18  0x1  0x0  0x2  0x0   /* TX_ER */
 240                                         0x4  0x10  0x2  0x0  0x2  0x0   /* RX_DV */
 241                                         0x4  0x1e  0x2  0x0  0x2  0x0   /* RX_ER */
 242                                         0x4  0x11  0x2  0x0  0x2  0x0   /* RX_CLK */
 243                                         0x4  0x13  0x1  0x0  0x2  0x0   /* GTX_CLK */
 244                                         0x1  0x1f  0x2  0x0  0x3  0x0>; /* GTX125 */
 245                         };
 246
 247                         pio2: ucc_pin@02 {
 248                                 pio-map = <
 249                         /* port  pin  dir  open_drain  assignment  has_irq */
 250                                         0x5  0xa 0x1  0x0  0x2  0x0   /* TxD0 */
 251                                         0x5  0x9 0x1  0x0  0x2  0x0   /* TxD1 */
 252                                         0x5  0x8 0x1  0x0  0x2  0x0   /* TxD2 */
 253                                         0x5  0x7 0x1  0x0  0x2  0x0   /* TxD3 */
 254                                         0x5  0x17 0x1  0x0  0x2  0x0   /* TxD4 */
 255                                         0x5  0x16 0x1  0x0  0x2  0x0   /* TxD5 */
 256                                         0x5  0x15 0x1  0x0  0x2  0x0   /* TxD6 */
 257                                         0x5  0x14 0x1  0x0  0x2  0x0   /* TxD7 */
 258                                         0x5  0xf 0x2  0x0  0x2  0x0   /* RxD0 */
 259                                         0x5  0xe 0x2  0x0  0x2  0x0   /* RxD1 */
 260                                         0x5  0xd 0x2  0x0  0x2  0x0   /* RxD2 */
 261                                         0x5  0xc 0x2  0x0  0x2  0x0   /* RxD3 */
 262                                         0x5  0x1d 0x2  0x0  0x2  0x0   /* RxD4 */
 263                                         0x5  0x1c 0x2  0x0  0x2  0x0   /* RxD5 */
 264                                         0x5  0x1b 0x2  0x0  0x2  0x0   /* RxD6 */
 265                                         0x5  0x1a 0x2  0x0  0x2  0x0   /* RxD7 */
 266                                         0x5  0xb 0x1  0x0  0x2  0x0   /* TX_EN */
 267                                         0x5  0x18 0x1  0x0  0x2  0x0   /* TX_ER */
 268                                         0x5  0x10 0x2  0x0  0x2  0x0   /* RX_DV */
 269                                         0x5  0x1e 0x2  0x0  0x2  0x0   /* RX_ER */
 270                                         0x5  0x11 0x2  0x0  0x2  0x0   /* RX_CLK */
 271                                         0x5  0x13 0x1  0x0  0x2  0x0   /* GTX_CLK */
 272                                         0x1  0x1f 0x2  0x0  0x3  0x0   /* GTX125 */
 273                                         0x4  0x6 0x3  0x0  0x2  0x0   /* MDIO */
 274                                         0x4  0x5 0x1  0x0  0x2  0x0>; /* MDC */
 275                         };
 276                 };
 277         };
 278
 279         qe@e0080000 {
 280                 #address-cells = <1>;
 281                 #size-cells = <1>;
 282                 device_type = "qe";
 283                 compatible = "fsl,qe";
 284                 ranges = <0x0 0xe0080000 0x40000>;
 285                 reg = <0xe0080000 0x480>;
 286                 brg-frequency = <0>;
 287                 bus-frequency = <396000000>;
 288
 289                 muram@10000 {
 290                         #address-cells = <1>;
 291                         #size-cells = <1>;
 292                         compatible = "fsl,qe-muram", "fsl,cpm-muram";
 293                         ranges = <0x0 0x10000 0x10000>;
 294
 295                         data-only@0 {
 296                                 compatible = "fsl,qe-muram-data",
 297                                              "fsl,cpm-muram-data";
 298                                 reg = <0x0 0x10000>;
 299                         };
 300                 };
 301
 302                 spi@4c0 {
 303                         cell-index = <0>;
 304                         compatible = "fsl,spi";
 305                         reg = <0x4c0 0x40>;
 306                         interrupts = <2>;
 307                         interrupt-parent = <&qeic>;
 308                         mode = "cpu";
 309                 };
 310
 311                 spi@500 {
 312                         cell-index = <1>;
 313                         compatible = "fsl,spi";
 314                         reg = <0x500 0x40>;
 315                         interrupts = <1>;
 316                         interrupt-parent = <&qeic>;
 317                         mode = "cpu";
 318                 };
 319
 320                 enet2: ucc@2000 {
 321                         device_type = "network";
 322                         compatible = "ucc_geth";
 323                         cell-index = <1>;
 324                         reg = <0x2000 0x200>;
 325                         interrupts = <32>;
 326                         interrupt-parent = <&qeic>;
 327                         local-mac-address = [ 00 00 00 00 00 00 ];
 328                         rx-clock-name = "none";
 329                         tx-clock-name = "clk16";
 330                         pio-handle = <&pio1>;
 331                         phy-handle = <&phy0>;
 332                         phy-connection-type = "rgmii-id";
 333                 };
 334
 335                 enet3: ucc@3000 {
 336                         device_type = "network";
 337                         compatible = "ucc_geth";
 338                         cell-index = <2>;
 339                         reg = <0x3000 0x200>;
 340                         interrupts = <33>;
 341                         interrupt-parent = <&qeic>;
 342                         local-mac-address = [ 00 00 00 00 00 00 ];
 343                         rx-clock-name = "none";
 344                         tx-clock-name = "clk16";
 345                         pio-handle = <&pio2>;
 346                         phy-handle = <&phy1>;
 347                         phy-connection-type = "rgmii-id";
 348                 };
 349
 350                 mdio@2120 {
 351                         #address-cells = <1>;
 352                         #size-cells = <0>;
 353                         reg = <0x2120 0x18>;
 354                         compatible = "fsl,ucc-mdio";
 355
 356                         /* These are the same PHYs as on
 357                          * gianfar's MDIO bus */
 358                         qe_phy0: ethernet-phy@07 {
 359                                 interrupt-parent = <&mpic>;
 360                                 interrupts = <1 1>;
 361                                 reg = <0x7>;
 362                                 device_type = "ethernet-phy";
 363                         };
 364                         qe_phy1: ethernet-phy@01 {
 365                                 interrupt-parent = <&mpic>;
 366                                 interrupts = <2 1>;
 367                                 reg = <0x1>;
 368                                 device_type = "ethernet-phy";
 369                         };
 370                         qe_phy2: ethernet-phy@02 {
 371                                 interrupt-parent = <&mpic>;
 372                                 interrupts = <1 1>;
 373                                 reg = <0x2>;
 374                                 device_type = "ethernet-phy";
 375                         };
 376                         qe_phy3: ethernet-phy@03 {
 377                                 interrupt-parent = <&mpic>;
 378                                 interrupts = <2 1>;
 379                                 reg = <0x3>;
 380                                 device_type = "ethernet-phy";
 381                         };
 382                 };
 383
 384                 qeic: interrupt-controller@80 {
 385                         interrupt-controller;
 386                         compatible = "fsl,qe-ic";
 387                         #address-cells = <0>;
 388                         #interrupt-cells = <1>;
 389                         reg = <0x80 0x80>;
 390                         big-endian;
 391                         interrupts = <46 2 46 2>; //high:30 low:30
 392                         interrupt-parent = <&mpic>;
 393                 };
 394
 395         };
 396
 397         pci0: pci@e0008000 {
 398                 cell-index = <0>;
 399                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 400                 interrupt-map = <
 401                         /* IDSEL 0x12 AD18 */
 402                         0x9000 0x0 0x0 0x1 &mpic 0x5 0x1
 403                         0x9000 0x0 0x0 0x2 &mpic 0x6 0x1
 404                         0x9000 0x0 0x0 0x3 &mpic 0x7 0x1
 405                         0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
 406
 407                         /* IDSEL 0x13 AD19 */
 408                         0x9800 0x0 0x0 0x1 &mpic 0x6 0x1
 409                         0x9800 0x0 0x0 0x2 &mpic 0x7 0x1
 410                         0x9800 0x0 0x0 0x3 &mpic 0x4 0x1
 411                         0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>;
 412
 413                 interrupt-parent = <&mpic>;
 414                 interrupts = <24 2>;
 415                 bus-range = <0 255>;
 416                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
 417                           0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
 418                 clock-frequency = <66666666>;
 419                 #interrupt-cells = <1>;
 420                 #size-cells = <2>;
 421                 #address-cells = <3>;
 422                 reg = <0xe0008000 0x1000>;
 423                 compatible = "fsl,mpc8540-pci";
 424                 device_type = "pci";
 425         };
 426
 427         /* PCI Express */
 428         pci1: pcie@e000a000 {
 429                 cell-index = <2>;
 430                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 431                 interrupt-map = <
 432
 433                         /* IDSEL 0x0 (PEX) */
 434                         00000 0x0 0x0 0x1 &mpic 0x0 0x1
 435                         00000 0x0 0x0 0x2 &mpic 0x1 0x1
 436                         00000 0x0 0x0 0x3 &mpic 0x2 0x1
 437                         00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 438
 439                 interrupt-parent = <&mpic>;
 440                 interrupts = <26 2>;
 441                 bus-range = <0 255>;
 442                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
 443                           0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
 444                 clock-frequency = <33333333>;
 445                 #interrupt-cells = <1>;
 446                 #size-cells = <2>;
 447                 #address-cells = <3>;
 448                 reg = <0xe000a000 0x1000>;
 449                 compatible = "fsl,mpc8548-pcie";
 450                 device_type = "pci";
 451                 pcie@0 {
 452                         reg = <0x0 0x0 0x0 0x0 0x0>;
 453                         #size-cells = <2>;
 454                         #address-cells = <3>;
 455                         device_type = "pci";
 456                         ranges = <0x2000000 0x0 0xa0000000
 457                                   0x2000000 0x0 0xa0000000
 458                                   0x0 0x10000000
 459
 460                                   0x1000000 0x0 0x0
 461                                   0x1000000 0x0 0x0
 462                                   0x0 0x800000>;
 463                 };
 464         };
 465 };