1 /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
31 #ifndef __RADEON_DRV_H__
32 #define __RADEON_DRV_H__
34 /* General customization:
37 #define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
39 #define DRIVER_NAME "radeon"
40 #define DRIVER_DESC "ATI Radeon"
41 #define DRIVER_DATE "20080528"
46 * 1.2 - Add vertex2 ioctl (keith)
47 * - Add stencil capability to clear ioctl (gareth, keith)
48 * - Increase MAX_TEXTURE_LEVELS (brian)
49 * 1.3 - Add cmdbuf ioctl (keith)
50 * - Add support for new radeon packets (keith)
51 * - Add getparam ioctl (keith)
52 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
53 * 1.4 - Add scratch registers to get_param ioctl.
54 * 1.5 - Add r200 packets to cmdbuf ioctl
55 * - Add r200 function to init ioctl
56 * - Add 'scalar2' instruction to cmdbuf
57 * 1.6 - Add static GART memory manager
58 * Add irq handler (won't be turned on unless X server knows to)
59 * Add irq ioctls and irq_active getparam.
60 * Add wait command for cmdbuf ioctl
61 * Add GART offset query for getparam
62 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
63 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
64 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
65 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
66 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
67 * Add 'GET' queries for starting additional clients on different VT's.
68 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
69 * Add texture rectangle support for r100.
70 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
71 * clients use to tell the DRM where they think the framebuffer is
72 * located in the card's address space
73 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
74 * and GL_EXT_blend_[func|equation]_separate on r200
75 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
76 * (No 3D support yet - just microcode loading).
77 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
78 * - Add hyperz support, add hyperz flags to clear ioctl.
79 * 1.14- Add support for color tiling
80 * - Add R100/R200 surface allocation/free support
81 * 1.15- Add support for texture micro tiling
82 * - Add support for r100 cube maps
83 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
84 * texture filtering on r200
85 * 1.17- Add initial support for R300 (3D).
86 * 1.18- Add support for GL_ATI_fragment_shader, new packets
87 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
88 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
89 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
90 * 1.19- Add support for gart table in FB memory and PCIE r300
91 * 1.20- Add support for r300 texrect
92 * 1.21- Add support for card type getparam
93 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
94 * 1.23- Add new radeon memory map work from benh
95 * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
96 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
98 * 1.26- Add support for variable size PCI(E) gart aperture
99 * 1.27- Add support for IGP GART
100 * 1.28- Add support for VBL on CRTC2
101 * 1.29- R500 3D cmd buffer support
103 #define DRIVER_MAJOR 1
104 #define DRIVER_MINOR 29
105 #define DRIVER_PATCHLEVEL 0
108 * Radeon chip families
150 enum radeon_cp_microcode_version {
159 enum radeon_chip_flags {
160 RADEON_FAMILY_MASK = 0x0000ffffUL,
161 RADEON_FLAGS_MASK = 0xffff0000UL,
162 RADEON_IS_MOBILITY = 0x00010000UL,
163 RADEON_IS_IGP = 0x00020000UL,
164 RADEON_SINGLE_CRTC = 0x00040000UL,
165 RADEON_IS_AGP = 0x00080000UL,
166 RADEON_HAS_HIERZ = 0x00100000UL,
167 RADEON_IS_PCIE = 0x00200000UL,
168 RADEON_NEW_MEMMAP = 0x00400000UL,
169 RADEON_IS_PCI = 0x00800000UL,
170 RADEON_IS_IGPGART = 0x01000000UL,
173 typedef struct drm_radeon_freelist {
176 struct drm_radeon_freelist *next;
177 struct drm_radeon_freelist *prev;
178 } drm_radeon_freelist_t;
180 typedef struct drm_radeon_ring_buffer {
186 int rptr_update; /* Double Words */
187 int rptr_update_l2qw; /* log2 Quad Words */
189 int fetch_size; /* Double Words */
190 int fetch_size_l2ow; /* log2 Oct Words */
197 } drm_radeon_ring_buffer_t;
199 typedef struct drm_radeon_depth_clear_t {
201 u32 rb3d_zstencilcntl;
203 } drm_radeon_depth_clear_t;
205 struct drm_radeon_driver_file_fields {
206 int64_t radeon_fb_delta;
210 struct mem_block *next;
211 struct mem_block *prev;
214 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
217 struct radeon_surface {
224 struct radeon_virt_surface {
229 struct drm_file *file_priv;
230 #define PCIGART_FILE_PRIV ((void *) -1L)
233 #define RADEON_FLUSH_EMITED (1 << 0)
234 #define RADEON_PURGE_EMITED (1 << 1)
236 struct drm_radeon_master_private {
237 drm_local_map_t *sarea;
238 drm_radeon_sarea_t *sarea_priv;
241 typedef struct drm_radeon_private {
242 drm_radeon_ring_buffer_t ring;
250 unsigned long gart_buffers_offset;
255 drm_radeon_freelist_t *head;
256 drm_radeon_freelist_t *tail;
262 int microcode_version;
266 int freelist_timeouts;
269 int last_frame_reads;
270 int last_clear_reads;
279 unsigned int front_offset;
280 unsigned int front_pitch;
281 unsigned int back_offset;
282 unsigned int back_pitch;
285 unsigned int depth_offset;
286 unsigned int depth_pitch;
288 u32 front_pitch_offset;
289 u32 back_pitch_offset;
290 u32 depth_pitch_offset;
292 drm_radeon_depth_clear_t depth_clear;
294 unsigned long ring_offset;
295 unsigned long ring_rptr_offset;
296 unsigned long buffers_offset;
297 unsigned long gart_textures_offset;
299 drm_local_map_t *sarea;
300 drm_local_map_t *cp_ring;
301 drm_local_map_t *ring_rptr;
302 drm_local_map_t *gart_textures;
304 struct mem_block *gart_heap;
305 struct mem_block *fb_heap;
308 wait_queue_head_t swi_queue;
309 atomic_t swi_emitted;
311 uint32_t irq_enable_reg;
312 uint32_t r500_disp_irq_reg;
314 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
315 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
317 unsigned long pcigart_offset;
318 unsigned int pcigart_offset_set;
319 struct drm_ati_pcigart_info gart_info;
323 /* starting from here on, data is preserved accross an open */
324 uint32_t flags; /* see radeon_chip_flags */
325 resource_size_t fb_aper_offset;
329 drm_local_map_t *mmio;
331 /* r6xx/r7xx pipe/shader config */
333 int r600_max_tile_pipes;
335 int r600_max_backends;
337 int r600_max_threads;
338 int r600_max_stack_entries;
339 int r600_max_hw_contexts;
340 int r600_max_gs_threads;
341 int r600_sx_max_export_size;
342 int r600_sx_max_export_pos_size;
343 int r600_sx_max_export_smx_size;
344 int r600_sq_num_cf_insts;
345 int r700_sx_num_of_sets;
346 int r700_sc_prim_fifo_size;
347 int r700_sc_hiz_tile_fifo_size;
348 int r700_sc_earlyz_tile_fifo_fize;
350 } drm_radeon_private_t;
352 typedef struct drm_radeon_buf_priv {
354 } drm_radeon_buf_priv_t;
356 typedef struct drm_radeon_kcmd_buffer {
360 struct drm_clip_rect __user *boxes;
361 } drm_radeon_kcmd_buffer_t;
363 extern int radeon_no_wb;
364 extern struct drm_ioctl_desc radeon_ioctls[];
365 extern int radeon_max_ioctl;
367 extern u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv);
368 extern void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val);
370 #define GET_RING_HEAD(dev_priv) radeon_get_ring_head(dev_priv)
371 #define SET_RING_HEAD(dev_priv, val) radeon_set_ring_head(dev_priv, val)
373 /* Check whether the given hardware address is inside the framebuffer or the
376 static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,
379 u32 fb_start = dev_priv->fb_location;
380 u32 fb_end = fb_start + dev_priv->fb_size - 1;
381 u32 gart_start = dev_priv->gart_vm_start;
382 u32 gart_end = gart_start + dev_priv->gart_size - 1;
384 return ((off >= fb_start && off <= fb_end) ||
385 (off >= gart_start && off <= gart_end));
389 extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
390 extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv);
391 extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv);
392 extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
393 extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv);
394 extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv);
395 extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
396 extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
397 extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
398 extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv);
399 extern void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc);
400 extern void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base);
401 extern u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr);
403 extern void radeon_freelist_reset(struct drm_device * dev);
404 extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
406 extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
408 extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
410 extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
411 extern int radeon_presetup(struct drm_device *dev);
412 extern int radeon_driver_postcleanup(struct drm_device *dev);
414 extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
415 extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv);
416 extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv);
417 extern void radeon_mem_takedown(struct mem_block **heap);
418 extern void radeon_mem_release(struct drm_file *file_priv,
419 struct mem_block *heap);
421 extern void radeon_enable_bm(struct drm_radeon_private *dev_priv);
422 extern u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off);
423 extern void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val);
426 extern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state);
427 extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv);
428 extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv);
430 extern void radeon_do_release(struct drm_device * dev);
431 extern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc);
432 extern int radeon_enable_vblank(struct drm_device *dev, int crtc);
433 extern void radeon_disable_vblank(struct drm_device *dev, int crtc);
434 extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
435 extern void radeon_driver_irq_preinstall(struct drm_device * dev);
436 extern int radeon_driver_irq_postinstall(struct drm_device *dev);
437 extern void radeon_driver_irq_uninstall(struct drm_device * dev);
438 extern void radeon_enable_interrupt(struct drm_device *dev);
439 extern int radeon_vblank_crtc_get(struct drm_device *dev);
440 extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
442 extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
443 extern int radeon_driver_unload(struct drm_device *dev);
444 extern int radeon_driver_firstopen(struct drm_device *dev);
445 extern void radeon_driver_preclose(struct drm_device *dev,
446 struct drm_file *file_priv);
447 extern void radeon_driver_postclose(struct drm_device *dev,
448 struct drm_file *file_priv);
449 extern void radeon_driver_lastclose(struct drm_device * dev);
450 extern int radeon_driver_open(struct drm_device *dev,
451 struct drm_file *file_priv);
452 extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
455 extern int radeon_master_create(struct drm_device *dev, struct drm_master *master);
456 extern void radeon_master_destroy(struct drm_device *dev, struct drm_master *master);
457 extern void radeon_cp_dispatch_flip(struct drm_device *dev, struct drm_master *master);
459 extern void r300_init_reg_flags(struct drm_device *dev);
461 extern int r300_do_cp_cmdbuf(struct drm_device *dev,
462 struct drm_file *file_priv,
463 drm_radeon_kcmd_buffer_t *cmdbuf);
466 extern int r600_do_engine_reset(struct drm_device *dev);
467 extern int r600_do_cleanup_cp(struct drm_device *dev);
468 extern int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
469 struct drm_file *file_priv);
470 extern int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv);
471 extern int r600_do_cp_idle(drm_radeon_private_t *dev_priv);
472 extern void r600_do_cp_start(drm_radeon_private_t *dev_priv);
473 extern void r600_do_cp_reset(drm_radeon_private_t *dev_priv);
474 extern void r600_do_cp_stop(drm_radeon_private_t *dev_priv);
475 extern int r600_cp_dispatch_indirect(struct drm_device *dev,
476 struct drm_buf *buf, int start, int end);
478 /* Flags for stats.boxes
480 #define RADEON_BOX_DMA_IDLE 0x1
481 #define RADEON_BOX_RING_FULL 0x2
482 #define RADEON_BOX_FLIP 0x4
483 #define RADEON_BOX_WAIT_IDLE 0x8
484 #define RADEON_BOX_TEXTURE_LOAD 0x10
486 /* Register definitions, register access macros and drmAddMap constants
487 * for Radeon kernel driver.
489 #define RADEON_MM_INDEX 0x0000
490 #define RADEON_MM_DATA 0x0004
492 #define RADEON_AGP_COMMAND 0x0f60
493 #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
494 # define RADEON_AGP_ENABLE (1<<8)
495 #define RADEON_AUX_SCISSOR_CNTL 0x26f0
496 # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
497 # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
498 # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
499 # define RADEON_SCISSOR_0_ENABLE (1 << 28)
500 # define RADEON_SCISSOR_1_ENABLE (1 << 29)
501 # define RADEON_SCISSOR_2_ENABLE (1 << 30)
504 * PCIE radeons (rv370/rv380, rv410, r423/r430/r480, r5xx)
505 * don't have an explicit bus mastering disable bit. It's handled
506 * by the PCI D-states. PMI_BM_DIS disables D-state bus master
507 * handling, not bus mastering itself.
509 #define RADEON_BUS_CNTL 0x0030
510 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
511 # define RADEON_BUS_MASTER_DIS (1 << 6)
512 /* rs600/rs690/rs740 */
513 # define RS600_BUS_MASTER_DIS (1 << 14)
514 # define RS600_MSI_REARM (1 << 20)
515 /* see RS400_MSI_REARM in AIC_CNTL for rs480 */
517 #define RADEON_BUS_CNTL1 0x0034
518 # define RADEON_PMI_BM_DIS (1 << 2)
519 # define RADEON_PMI_INT_DIS (1 << 3)
521 #define RV370_BUS_CNTL 0x004c
522 # define RV370_PMI_BM_DIS (1 << 5)
523 # define RV370_PMI_INT_DIS (1 << 6)
525 #define RADEON_MSI_REARM_EN 0x0160
526 /* rv370/rv380, rv410, r423/r430/r480, r5xx */
527 # define RV370_MSI_REARM_EN (1 << 0)
529 #define RADEON_CLOCK_CNTL_DATA 0x000c
530 # define RADEON_PLL_WR_EN (1 << 7)
531 #define RADEON_CLOCK_CNTL_INDEX 0x0008
532 #define RADEON_CONFIG_APER_SIZE 0x0108
533 #define RADEON_CONFIG_MEMSIZE 0x00f8
534 #define RADEON_CRTC_OFFSET 0x0224
535 #define RADEON_CRTC_OFFSET_CNTL 0x0228
536 # define RADEON_CRTC_TILE_EN (1 << 15)
537 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
538 #define RADEON_CRTC2_OFFSET 0x0324
539 #define RADEON_CRTC2_OFFSET_CNTL 0x0328
541 #define RADEON_PCIE_INDEX 0x0030
542 #define RADEON_PCIE_DATA 0x0034
543 #define RADEON_PCIE_TX_GART_CNTL 0x10
544 # define RADEON_PCIE_TX_GART_EN (1 << 0)
545 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)
546 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1)
547 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1)
548 # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3)
549 # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3)
550 # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5)
551 # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8)
552 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
553 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
554 #define RADEON_PCIE_TX_GART_BASE 0x13
555 #define RADEON_PCIE_TX_GART_START_LO 0x14
556 #define RADEON_PCIE_TX_GART_START_HI 0x15
557 #define RADEON_PCIE_TX_GART_END_LO 0x16
558 #define RADEON_PCIE_TX_GART_END_HI 0x17
560 #define RS480_NB_MC_INDEX 0x168
561 # define RS480_NB_MC_IND_WR_EN (1 << 8)
562 #define RS480_NB_MC_DATA 0x16c
564 #define RS690_MC_INDEX 0x78
565 # define RS690_MC_INDEX_MASK 0x1ff
566 # define RS690_MC_INDEX_WR_EN (1 << 9)
567 # define RS690_MC_INDEX_WR_ACK 0x7f
568 #define RS690_MC_DATA 0x7c
570 /* MC indirect registers */
571 #define RS480_MC_MISC_CNTL 0x18
572 # define RS480_DISABLE_GTW (1 << 1)
573 /* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */
574 # define RS480_GART_INDEX_REG_EN (1 << 12)
575 # define RS690_BLOCK_GFX_D3_EN (1 << 14)
576 #define RS480_K8_FB_LOCATION 0x1e
577 #define RS480_GART_FEATURE_ID 0x2b
578 # define RS480_HANG_EN (1 << 11)
579 # define RS480_TLB_ENABLE (1 << 18)
580 # define RS480_P2P_ENABLE (1 << 19)
581 # define RS480_GTW_LAC_EN (1 << 25)
582 # define RS480_2LEVEL_GART (0 << 30)
583 # define RS480_1LEVEL_GART (1 << 30)
584 # define RS480_PDC_EN (1 << 31)
585 #define RS480_GART_BASE 0x2c
586 #define RS480_GART_CACHE_CNTRL 0x2e
587 # define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
588 #define RS480_AGP_ADDRESS_SPACE_SIZE 0x38
589 # define RS480_GART_EN (1 << 0)
590 # define RS480_VA_SIZE_32MB (0 << 1)
591 # define RS480_VA_SIZE_64MB (1 << 1)
592 # define RS480_VA_SIZE_128MB (2 << 1)
593 # define RS480_VA_SIZE_256MB (3 << 1)
594 # define RS480_VA_SIZE_512MB (4 << 1)
595 # define RS480_VA_SIZE_1GB (5 << 1)
596 # define RS480_VA_SIZE_2GB (6 << 1)
597 #define RS480_AGP_MODE_CNTL 0x39
598 # define RS480_POST_GART_Q_SIZE (1 << 18)
599 # define RS480_NONGART_SNOOP (1 << 19)
600 # define RS480_AGP_RD_BUF_SIZE (1 << 20)
601 # define RS480_REQ_TYPE_SNOOP_SHIFT 22
602 # define RS480_REQ_TYPE_SNOOP_MASK 0x3
603 # define RS480_REQ_TYPE_SNOOP_DIS (1 << 24)
604 #define RS480_MC_MISC_UMA_CNTL 0x5f
605 #define RS480_MC_MCLK_CNTL 0x7a
606 #define RS480_MC_UMA_DUALCH_CNTL 0x86
608 #define RS690_MC_FB_LOCATION 0x100
609 #define RS690_MC_AGP_LOCATION 0x101
610 #define RS690_MC_AGP_BASE 0x102
611 #define RS690_MC_AGP_BASE_2 0x103
613 #define R520_MC_IND_INDEX 0x70
614 #define R520_MC_IND_WR_EN (1 << 24)
615 #define R520_MC_IND_DATA 0x74
617 #define RV515_MC_FB_LOCATION 0x01
618 #define RV515_MC_AGP_LOCATION 0x02
619 #define RV515_MC_AGP_BASE 0x03
620 #define RV515_MC_AGP_BASE_2 0x04
622 #define R520_MC_FB_LOCATION 0x04
623 #define R520_MC_AGP_LOCATION 0x05
624 #define R520_MC_AGP_BASE 0x06
625 #define R520_MC_AGP_BASE_2 0x07
627 #define RADEON_MPP_TB_CONFIG 0x01c0
628 #define RADEON_MEM_CNTL 0x0140
629 #define RADEON_MEM_SDRAM_MODE_REG 0x0158
630 #define RADEON_AGP_BASE_2 0x015c /* r200+ only */
631 #define RS480_AGP_BASE_2 0x0164
632 #define RADEON_AGP_BASE 0x0170
634 /* pipe config regs */
635 #define R400_GB_PIPE_SELECT 0x402c
636 #define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */
637 #define R500_SU_REG_DEST 0x42c8
638 #define R300_GB_TILE_CONFIG 0x4018
639 # define R300_ENABLE_TILING (1 << 0)
640 # define R300_PIPE_COUNT_RV350 (0 << 1)
641 # define R300_PIPE_COUNT_R300 (3 << 1)
642 # define R300_PIPE_COUNT_R420_3P (6 << 1)
643 # define R300_PIPE_COUNT_R420 (7 << 1)
644 # define R300_TILE_SIZE_8 (0 << 4)
645 # define R300_TILE_SIZE_16 (1 << 4)
646 # define R300_TILE_SIZE_32 (2 << 4)
647 # define R300_SUBPIXEL_1_12 (0 << 16)
648 # define R300_SUBPIXEL_1_16 (1 << 16)
649 #define R300_DST_PIPE_CONFIG 0x170c
650 # define R300_PIPE_AUTO_CONFIG (1 << 31)
651 #define R300_RB2D_DSTCACHE_MODE 0x3428
652 # define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
653 # define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
655 #define RADEON_RB3D_COLOROFFSET 0x1c40
656 #define RADEON_RB3D_COLORPITCH 0x1c48
658 #define RADEON_SRC_X_Y 0x1590
660 #define RADEON_DP_GUI_MASTER_CNTL 0x146c
661 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
662 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
663 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
664 # define RADEON_GMC_BRUSH_NONE (15 << 4)
665 # define RADEON_GMC_DST_16BPP (4 << 8)
666 # define RADEON_GMC_DST_24BPP (5 << 8)
667 # define RADEON_GMC_DST_32BPP (6 << 8)
668 # define RADEON_GMC_DST_DATATYPE_SHIFT 8
669 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
670 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
671 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
672 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
673 # define RADEON_GMC_WR_MSK_DIS (1 << 30)
674 # define RADEON_ROP3_S 0x00cc0000
675 # define RADEON_ROP3_P 0x00f00000
676 #define RADEON_DP_WRITE_MASK 0x16cc
677 #define RADEON_SRC_PITCH_OFFSET 0x1428
678 #define RADEON_DST_PITCH_OFFSET 0x142c
679 #define RADEON_DST_PITCH_OFFSET_C 0x1c80
680 # define RADEON_DST_TILE_LINEAR (0 << 30)
681 # define RADEON_DST_TILE_MACRO (1 << 30)
682 # define RADEON_DST_TILE_MICRO (2 << 30)
683 # define RADEON_DST_TILE_BOTH (3 << 30)
685 #define RADEON_SCRATCH_REG0 0x15e0
686 #define RADEON_SCRATCH_REG1 0x15e4
687 #define RADEON_SCRATCH_REG2 0x15e8
688 #define RADEON_SCRATCH_REG3 0x15ec
689 #define RADEON_SCRATCH_REG4 0x15f0
690 #define RADEON_SCRATCH_REG5 0x15f4
691 #define RADEON_SCRATCH_UMSK 0x0770
692 #define RADEON_SCRATCH_ADDR 0x0774
694 #define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
696 extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
698 #define GET_SCRATCH(dev_priv, x) radeon_get_scratch(dev_priv, x)
700 #define R600_SCRATCH_REG0 0x8500
701 #define R600_SCRATCH_REG1 0x8504
702 #define R600_SCRATCH_REG2 0x8508
703 #define R600_SCRATCH_REG3 0x850c
704 #define R600_SCRATCH_REG4 0x8510
705 #define R600_SCRATCH_REG5 0x8514
706 #define R600_SCRATCH_REG6 0x8518
707 #define R600_SCRATCH_REG7 0x851c
708 #define R600_SCRATCH_UMSK 0x8540
709 #define R600_SCRATCH_ADDR 0x8544
711 #define R600_SCRATCHOFF(x) (R600_SCRATCH_REG_OFFSET + 4*(x))
713 #define RADEON_GEN_INT_CNTL 0x0040
714 # define RADEON_CRTC_VBLANK_MASK (1 << 0)
715 # define RADEON_CRTC2_VBLANK_MASK (1 << 9)
716 # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
717 # define RADEON_SW_INT_ENABLE (1 << 25)
719 #define RADEON_GEN_INT_STATUS 0x0044
720 # define RADEON_CRTC_VBLANK_STAT (1 << 0)
721 # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
722 # define RADEON_CRTC2_VBLANK_STAT (1 << 9)
723 # define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
724 # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
725 # define RADEON_SW_INT_TEST (1 << 25)
726 # define RADEON_SW_INT_TEST_ACK (1 << 25)
727 # define RADEON_SW_INT_FIRE (1 << 26)
728 # define R500_DISPLAY_INT_STATUS (1 << 0)
730 #define RADEON_HOST_PATH_CNTL 0x0130
731 # define RADEON_HDP_SOFT_RESET (1 << 26)
732 # define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
733 # define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
735 #define RADEON_ISYNC_CNTL 0x1724
736 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
737 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
738 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
739 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
740 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
741 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
743 #define RADEON_RBBM_GUICNTL 0x172c
744 # define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
745 # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
746 # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
747 # define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
749 #define RADEON_MC_AGP_LOCATION 0x014c
750 #define RADEON_MC_FB_LOCATION 0x0148
751 #define RADEON_MCLK_CNTL 0x0012
752 # define RADEON_FORCEON_MCLKA (1 << 16)
753 # define RADEON_FORCEON_MCLKB (1 << 17)
754 # define RADEON_FORCEON_YCLKA (1 << 18)
755 # define RADEON_FORCEON_YCLKB (1 << 19)
756 # define RADEON_FORCEON_MC (1 << 20)
757 # define RADEON_FORCEON_AIC (1 << 21)
759 #define RADEON_PP_BORDER_COLOR_0 0x1d40
760 #define RADEON_PP_BORDER_COLOR_1 0x1d44
761 #define RADEON_PP_BORDER_COLOR_2 0x1d48
762 #define RADEON_PP_CNTL 0x1c38
763 # define RADEON_SCISSOR_ENABLE (1 << 1)
764 #define RADEON_PP_LUM_MATRIX 0x1d00
765 #define RADEON_PP_MISC 0x1c14
766 #define RADEON_PP_ROT_MATRIX_0 0x1d58
767 #define RADEON_PP_TXFILTER_0 0x1c54
768 #define RADEON_PP_TXOFFSET_0 0x1c5c
769 #define RADEON_PP_TXFILTER_1 0x1c6c
770 #define RADEON_PP_TXFILTER_2 0x1c84
772 #define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */
773 #define R300_DSTCACHE_CTLSTAT 0x1714
774 # define R300_RB2D_DC_FLUSH (3 << 0)
775 # define R300_RB2D_DC_FREE (3 << 2)
776 # define R300_RB2D_DC_FLUSH_ALL 0xf
777 # define R300_RB2D_DC_BUSY (1 << 31)
778 #define RADEON_RB3D_CNTL 0x1c3c
779 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
780 # define RADEON_PLANE_MASK_ENABLE (1 << 1)
781 # define RADEON_DITHER_ENABLE (1 << 2)
782 # define RADEON_ROUND_ENABLE (1 << 3)
783 # define RADEON_SCALE_DITHER_ENABLE (1 << 4)
784 # define RADEON_DITHER_INIT (1 << 5)
785 # define RADEON_ROP_ENABLE (1 << 6)
786 # define RADEON_STENCIL_ENABLE (1 << 7)
787 # define RADEON_Z_ENABLE (1 << 8)
788 # define RADEON_ZBLOCK16 (1 << 15)
789 #define RADEON_RB3D_DEPTHOFFSET 0x1c24
790 #define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
791 #define RADEON_RB3D_DEPTHPITCH 0x1c28
792 #define RADEON_RB3D_PLANEMASK 0x1d84
793 #define RADEON_RB3D_STENCILREFMASK 0x1d7c
794 #define RADEON_RB3D_ZCACHE_MODE 0x3250
795 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
796 # define RADEON_RB3D_ZC_FLUSH (1 << 0)
797 # define RADEON_RB3D_ZC_FREE (1 << 2)
798 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5
799 # define RADEON_RB3D_ZC_BUSY (1 << 31)
800 #define R300_ZB_ZCACHE_CTLSTAT 0x4f18
801 # define R300_ZC_FLUSH (1 << 0)
802 # define R300_ZC_FREE (1 << 1)
803 # define R300_ZC_BUSY (1 << 31)
804 #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
805 # define RADEON_RB3D_DC_FLUSH (3 << 0)
806 # define RADEON_RB3D_DC_FREE (3 << 2)
807 # define RADEON_RB3D_DC_FLUSH_ALL 0xf
808 # define RADEON_RB3D_DC_BUSY (1 << 31)
809 #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
810 # define R300_RB3D_DC_FLUSH (2 << 0)
811 # define R300_RB3D_DC_FREE (2 << 2)
812 # define R300_RB3D_DC_FINISH (1 << 4)
813 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
814 # define RADEON_Z_TEST_MASK (7 << 4)
815 # define RADEON_Z_TEST_ALWAYS (7 << 4)
816 # define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
817 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
818 # define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
819 # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
820 # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
821 # define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
822 # define RADEON_FORCE_Z_DIRTY (1 << 29)
823 # define RADEON_Z_WRITE_ENABLE (1 << 30)
824 # define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
825 #define RADEON_RBBM_SOFT_RESET 0x00f0
826 # define RADEON_SOFT_RESET_CP (1 << 0)
827 # define RADEON_SOFT_RESET_HI (1 << 1)
828 # define RADEON_SOFT_RESET_SE (1 << 2)
829 # define RADEON_SOFT_RESET_RE (1 << 3)
830 # define RADEON_SOFT_RESET_PP (1 << 4)
831 # define RADEON_SOFT_RESET_E2 (1 << 5)
832 # define RADEON_SOFT_RESET_RB (1 << 6)
833 # define RADEON_SOFT_RESET_HDP (1 << 7)
835 * 6:0 Available slots in the FIFO
836 * 8 Host Interface active
837 * 9 CP request active
838 * 10 FIFO request active
839 * 11 Host Interface retry active
841 * 13 FIFO retry active
842 * 14 FIFO pipeline busy
843 * 15 Event engine busy
844 * 16 CP command stream busy
846 * 18 2D portion of render backend busy
847 * 20 3D setup engine busy
849 * 27 CBA 2D engine busy
850 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or
851 * command stream queue not empty or Ring Buffer not empty
853 #define RADEON_RBBM_STATUS 0x0e40
854 /* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */
855 /* #define RADEON_RBBM_STATUS 0x1740 */
856 /* bits 6:0 are dword slots available in the cmd fifo */
857 # define RADEON_RBBM_FIFOCNT_MASK 0x007f
858 # define RADEON_HIRQ_ON_RBB (1 << 8)
859 # define RADEON_CPRQ_ON_RBB (1 << 9)
860 # define RADEON_CFRQ_ON_RBB (1 << 10)
861 # define RADEON_HIRQ_IN_RTBUF (1 << 11)
862 # define RADEON_CPRQ_IN_RTBUF (1 << 12)
863 # define RADEON_CFRQ_IN_RTBUF (1 << 13)
864 # define RADEON_PIPE_BUSY (1 << 14)
865 # define RADEON_ENG_EV_BUSY (1 << 15)
866 # define RADEON_CP_CMDSTRM_BUSY (1 << 16)
867 # define RADEON_E2_BUSY (1 << 17)
868 # define RADEON_RB2D_BUSY (1 << 18)
869 # define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */
870 # define RADEON_VAP_BUSY (1 << 20)
871 # define RADEON_RE_BUSY (1 << 21) /* not used on r300 */
872 # define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */
873 # define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */
874 # define RADEON_PB_BUSY (1 << 24) /* not used on r300 */
875 # define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */
876 # define RADEON_GA_BUSY (1 << 26)
877 # define RADEON_CBA2D_BUSY (1 << 27)
878 # define RADEON_RBBM_ACTIVE (1 << 31)
879 #define RADEON_RE_LINE_PATTERN 0x1cd0
880 #define RADEON_RE_MISC 0x26c4
881 #define RADEON_RE_TOP_LEFT 0x26c0
882 #define RADEON_RE_WIDTH_HEIGHT 0x1c44
883 #define RADEON_RE_STIPPLE_ADDR 0x1cc8
884 #define RADEON_RE_STIPPLE_DATA 0x1ccc
886 #define RADEON_SCISSOR_TL_0 0x1cd8
887 #define RADEON_SCISSOR_BR_0 0x1cdc
888 #define RADEON_SCISSOR_TL_1 0x1ce0
889 #define RADEON_SCISSOR_BR_1 0x1ce4
890 #define RADEON_SCISSOR_TL_2 0x1ce8
891 #define RADEON_SCISSOR_BR_2 0x1cec
892 #define RADEON_SE_COORD_FMT 0x1c50
893 #define RADEON_SE_CNTL 0x1c4c
894 # define RADEON_FFACE_CULL_CW (0 << 0)
895 # define RADEON_BFACE_SOLID (3 << 1)
896 # define RADEON_FFACE_SOLID (3 << 3)
897 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
898 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
899 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
900 # define RADEON_ALPHA_SHADE_FLAT (1 << 10)
901 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
902 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
903 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
904 # define RADEON_FOG_SHADE_FLAT (1 << 14)
905 # define RADEON_FOG_SHADE_GOURAUD (2 << 14)
906 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
907 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
908 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
909 # define RADEON_ROUND_MODE_TRUNC (0 << 28)
910 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
911 #define RADEON_SE_CNTL_STATUS 0x2140
912 #define RADEON_SE_LINE_WIDTH 0x1db8
913 #define RADEON_SE_VPORT_XSCALE 0x1d98
914 #define RADEON_SE_ZBIAS_FACTOR 0x1db0
915 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
916 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
917 #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
918 # define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
919 # define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
920 #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
921 #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
922 # define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
923 #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
924 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
925 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc
926 #define RADEON_SURFACE_CNTL 0x0b00
927 # define RADEON_SURF_TRANSLATION_DIS (1 << 8)
928 # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
929 # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
930 # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
931 # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
932 # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
933 # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
934 # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
935 # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
936 #define RADEON_SURFACE0_INFO 0x0b0c
937 # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
938 # define RADEON_SURF_TILE_MODE_MASK (3 << 16)
939 # define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
940 # define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
941 # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
942 # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
943 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04
944 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08
945 # define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
946 #define RADEON_SURFACE1_INFO 0x0b1c
947 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14
948 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18
949 #define RADEON_SURFACE2_INFO 0x0b2c
950 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24
951 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28
952 #define RADEON_SURFACE3_INFO 0x0b3c
953 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34
954 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38
955 #define RADEON_SURFACE4_INFO 0x0b4c
956 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44
957 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48
958 #define RADEON_SURFACE5_INFO 0x0b5c
959 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54
960 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58
961 #define RADEON_SURFACE6_INFO 0x0b6c
962 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64
963 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68
964 #define RADEON_SURFACE7_INFO 0x0b7c
965 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74
966 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78
967 #define RADEON_SW_SEMAPHORE 0x013c
969 #define RADEON_WAIT_UNTIL 0x1720
970 # define RADEON_WAIT_CRTC_PFLIP (1 << 0)
971 # define RADEON_WAIT_2D_IDLE (1 << 14)
972 # define RADEON_WAIT_3D_IDLE (1 << 15)
973 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
974 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
975 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
977 #define RADEON_RB3D_ZMASKOFFSET 0x3234
978 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
979 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
980 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
983 #define RADEON_CP_ME_RAM_ADDR 0x07d4
984 #define RADEON_CP_ME_RAM_RADDR 0x07d8
985 #define RADEON_CP_ME_RAM_DATAH 0x07dc
986 #define RADEON_CP_ME_RAM_DATAL 0x07e0
988 #define RADEON_CP_RB_BASE 0x0700
989 #define RADEON_CP_RB_CNTL 0x0704
990 # define RADEON_BUF_SWAP_32BIT (2 << 16)
991 # define RADEON_RB_NO_UPDATE (1 << 27)
992 # define RADEON_RB_RPTR_WR_ENA (1 << 31)
993 #define RADEON_CP_RB_RPTR_ADDR 0x070c
994 #define RADEON_CP_RB_RPTR 0x0710
995 #define RADEON_CP_RB_WPTR 0x0714
997 #define RADEON_CP_RB_WPTR_DELAY 0x0718
998 # define RADEON_PRE_WRITE_TIMER_SHIFT 0
999 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23
1001 #define RADEON_CP_IB_BASE 0x0738
1003 #define RADEON_CP_CSQ_CNTL 0x0740
1004 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
1005 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
1006 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
1007 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
1008 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
1009 # define RADEON_CSQ_PRIBM_INDBM (4 << 28)
1010 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
1012 #define RADEON_AIC_CNTL 0x01d0
1013 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
1014 # define RS400_MSI_REARM (1 << 3)
1015 #define RADEON_AIC_STAT 0x01d4
1016 #define RADEON_AIC_PT_BASE 0x01d8
1017 #define RADEON_AIC_LO_ADDR 0x01dc
1018 #define RADEON_AIC_HI_ADDR 0x01e0
1019 #define RADEON_AIC_TLB_ADDR 0x01e4
1020 #define RADEON_AIC_TLB_DATA 0x01e8
1022 /* CP command packets */
1023 #define RADEON_CP_PACKET0 0x00000000
1024 # define RADEON_ONE_REG_WR (1 << 15)
1025 #define RADEON_CP_PACKET1 0x40000000
1026 #define RADEON_CP_PACKET2 0x80000000
1027 #define RADEON_CP_PACKET3 0xC0000000
1028 # define RADEON_CP_NOP 0x00001000
1029 # define RADEON_CP_NEXT_CHAR 0x00001900
1030 # define RADEON_CP_PLY_NEXTSCAN 0x00001D00
1031 # define RADEON_CP_SET_SCISSORS 0x00001E00
1032 /* GEN_INDX_PRIM is unsupported starting with R300 */
1033 # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
1034 # define RADEON_WAIT_FOR_IDLE 0x00002600
1035 # define RADEON_3D_DRAW_VBUF 0x00002800
1036 # define RADEON_3D_DRAW_IMMD 0x00002900
1037 # define RADEON_3D_DRAW_INDX 0x00002A00
1038 # define RADEON_CP_LOAD_PALETTE 0x00002C00
1039 # define RADEON_3D_LOAD_VBPNTR 0x00002F00
1040 # define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
1041 # define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
1042 # define RADEON_3D_CLEAR_ZMASK 0x00003200
1043 # define RADEON_CP_INDX_BUFFER 0x00003300
1044 # define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
1045 # define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
1046 # define RADEON_CP_3D_DRAW_INDX_2 0x00003600
1047 # define RADEON_3D_CLEAR_HIZ 0x00003700
1048 # define RADEON_CP_3D_CLEAR_CMASK 0x00003802
1049 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400
1050 # define RADEON_CNTL_PAINT_MULTI 0x00009A00
1051 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00
1052 # define RADEON_CNTL_SET_SCISSORS 0xC0001E00
1054 # define R600_IT_INDIRECT_BUFFER 0x00003200
1055 # define R600_IT_ME_INITIALIZE 0x00004400
1056 # define R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
1057 # define R600_IT_EVENT_WRITE 0x00004600
1058 # define R600_IT_SET_CONFIG_REG 0x00006800
1059 # define R600_SET_CONFIG_REG_OFFSET 0x00008000
1060 # define R600_SET_CONFIG_REG_END 0x0000ac00
1062 #define RADEON_CP_PACKET_MASK 0xC0000000
1063 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
1064 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff
1065 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
1066 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
1068 #define RADEON_VTX_Z_PRESENT (1 << 31)
1069 #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
1071 #define RADEON_PRIM_TYPE_NONE (0 << 0)
1072 #define RADEON_PRIM_TYPE_POINT (1 << 0)
1073 #define RADEON_PRIM_TYPE_LINE (2 << 0)
1074 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
1075 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
1076 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
1077 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
1078 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
1079 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
1080 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
1081 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
1082 #define RADEON_PRIM_TYPE_MASK 0xf
1083 #define RADEON_PRIM_WALK_IND (1 << 4)
1084 #define RADEON_PRIM_WALK_LIST (2 << 4)
1085 #define RADEON_PRIM_WALK_RING (3 << 4)
1086 #define RADEON_COLOR_ORDER_BGRA (0 << 6)
1087 #define RADEON_COLOR_ORDER_RGBA (1 << 6)
1088 #define RADEON_MAOS_ENABLE (1 << 7)
1089 #define RADEON_VTX_FMT_R128_MODE (0 << 8)
1090 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
1091 #define RADEON_NUM_VERTICES_SHIFT 16
1093 #define RADEON_COLOR_FORMAT_CI8 2
1094 #define RADEON_COLOR_FORMAT_ARGB1555 3
1095 #define RADEON_COLOR_FORMAT_RGB565 4
1096 #define RADEON_COLOR_FORMAT_ARGB8888 6
1097 #define RADEON_COLOR_FORMAT_RGB332 7
1098 #define RADEON_COLOR_FORMAT_RGB8 9
1099 #define RADEON_COLOR_FORMAT_ARGB4444 15
1101 #define RADEON_TXFORMAT_I8 0
1102 #define RADEON_TXFORMAT_AI88 1
1103 #define RADEON_TXFORMAT_RGB332 2
1104 #define RADEON_TXFORMAT_ARGB1555 3
1105 #define RADEON_TXFORMAT_RGB565 4
1106 #define RADEON_TXFORMAT_ARGB4444 5
1107 #define RADEON_TXFORMAT_ARGB8888 6
1108 #define RADEON_TXFORMAT_RGBA8888 7
1109 #define RADEON_TXFORMAT_Y8 8
1110 #define RADEON_TXFORMAT_VYUY422 10
1111 #define RADEON_TXFORMAT_YVYU422 11
1112 #define RADEON_TXFORMAT_DXT1 12
1113 #define RADEON_TXFORMAT_DXT23 14
1114 #define RADEON_TXFORMAT_DXT45 15
1116 #define R200_PP_TXCBLEND_0 0x2f00
1117 #define R200_PP_TXCBLEND_1 0x2f10
1118 #define R200_PP_TXCBLEND_2 0x2f20
1119 #define R200_PP_TXCBLEND_3 0x2f30
1120 #define R200_PP_TXCBLEND_4 0x2f40
1121 #define R200_PP_TXCBLEND_5 0x2f50
1122 #define R200_PP_TXCBLEND_6 0x2f60
1123 #define R200_PP_TXCBLEND_7 0x2f70
1124 #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
1125 #define R200_PP_TFACTOR_0 0x2ee0
1126 #define R200_SE_VTX_FMT_0 0x2088
1127 #define R200_SE_VAP_CNTL 0x2080
1128 #define R200_SE_TCL_MATRIX_SEL_0 0x2230
1129 #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
1130 #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
1131 #define R200_PP_TXFILTER_5 0x2ca0
1132 #define R200_PP_TXFILTER_4 0x2c80
1133 #define R200_PP_TXFILTER_3 0x2c60
1134 #define R200_PP_TXFILTER_2 0x2c40
1135 #define R200_PP_TXFILTER_1 0x2c20
1136 #define R200_PP_TXFILTER_0 0x2c00
1137 #define R200_PP_TXOFFSET_5 0x2d78
1138 #define R200_PP_TXOFFSET_4 0x2d60
1139 #define R200_PP_TXOFFSET_3 0x2d48
1140 #define R200_PP_TXOFFSET_2 0x2d30
1141 #define R200_PP_TXOFFSET_1 0x2d18
1142 #define R200_PP_TXOFFSET_0 0x2d00
1144 #define R200_PP_CUBIC_FACES_0 0x2c18
1145 #define R200_PP_CUBIC_FACES_1 0x2c38
1146 #define R200_PP_CUBIC_FACES_2 0x2c58
1147 #define R200_PP_CUBIC_FACES_3 0x2c78
1148 #define R200_PP_CUBIC_FACES_4 0x2c98
1149 #define R200_PP_CUBIC_FACES_5 0x2cb8
1150 #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
1151 #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
1152 #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
1153 #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
1154 #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
1155 #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
1156 #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
1157 #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
1158 #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
1159 #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
1160 #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
1161 #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
1162 #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
1163 #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
1164 #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
1165 #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
1166 #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
1167 #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
1168 #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
1169 #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
1170 #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
1171 #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
1172 #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
1173 #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
1174 #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
1175 #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
1176 #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
1177 #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
1178 #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
1179 #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
1181 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1182 #define R200_SE_VTE_CNTL 0x20b0
1183 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
1184 #define R200_PP_TAM_DEBUG3 0x2d9c
1185 #define R200_PP_CNTL_X 0x2cc4
1186 #define R200_SE_VAP_CNTL_STATUS 0x2140
1187 #define R200_RE_SCISSOR_TL_0 0x1cd8
1188 #define R200_RE_SCISSOR_TL_1 0x1ce0
1189 #define R200_RE_SCISSOR_TL_2 0x1ce8
1190 #define R200_RB3D_DEPTHXY_OFFSET 0x1d60
1191 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1192 #define R200_SE_VTX_STATE_CNTL 0x2180
1193 #define R200_RE_POINTSIZE 0x2648
1194 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
1196 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
1197 #define RADEON_PP_TEX_SIZE_1 0x1d0c
1198 #define RADEON_PP_TEX_SIZE_2 0x1d14
1200 #define RADEON_PP_CUBIC_FACES_0 0x1d24
1201 #define RADEON_PP_CUBIC_FACES_1 0x1d28
1202 #define RADEON_PP_CUBIC_FACES_2 0x1d2c
1203 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
1204 #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
1205 #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
1207 #define RADEON_SE_TCL_STATE_FLUSH 0x2284
1209 #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
1210 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
1211 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
1212 #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
1213 #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
1214 #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
1215 #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
1216 #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
1217 #define R200_3D_DRAW_IMMD_2 0xC0003500
1218 #define R200_SE_VTX_FMT_1 0x208c
1219 #define R200_RE_CNTL 0x1c50
1221 #define R200_RB3D_BLENDCOLOR 0x3218
1223 #define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
1225 #define R200_PP_TRI_PERF 0x2cf8
1227 #define R200_PP_AFS_0 0x2f80
1228 #define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
1230 #define R200_VAP_PVS_CNTL_1 0x22D0
1232 #define RADEON_CRTC_CRNT_FRAME 0x0214
1233 #define RADEON_CRTC2_CRNT_FRAME 0x0314
1235 #define R500_D1CRTC_STATUS 0x609c
1236 #define R500_D2CRTC_STATUS 0x689c
1237 #define R500_CRTC_V_BLANK (1<<0)
1239 #define R500_D1CRTC_FRAME_COUNT 0x60a4
1240 #define R500_D2CRTC_FRAME_COUNT 0x68a4
1242 #define R500_D1MODE_V_COUNTER 0x6530
1243 #define R500_D2MODE_V_COUNTER 0x6d30
1245 #define R500_D1MODE_VBLANK_STATUS 0x6534
1246 #define R500_D2MODE_VBLANK_STATUS 0x6d34
1247 #define R500_VBLANK_OCCURED (1<<0)
1248 #define R500_VBLANK_ACK (1<<4)
1249 #define R500_VBLANK_STAT (1<<12)
1250 #define R500_VBLANK_INT (1<<16)
1252 #define R500_DxMODE_INT_MASK 0x6540
1253 #define R500_D1MODE_INT_MASK (1<<0)
1254 #define R500_D2MODE_INT_MASK (1<<8)
1256 #define R500_DISP_INTERRUPT_STATUS 0x7edc
1257 #define R500_D1_VBLANK_INTERRUPT (1 << 4)
1258 #define R500_D2_VBLANK_INTERRUPT (1 << 5)
1260 /* R6xx/R7xx registers */
1261 #define R600_MC_VM_FB_LOCATION 0x2180
1262 #define R600_MC_VM_AGP_TOP 0x2184
1263 #define R600_MC_VM_AGP_BOT 0x2188
1264 #define R600_MC_VM_AGP_BASE 0x218c
1265 #define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
1266 #define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
1267 #define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
1269 #define R700_MC_VM_FB_LOCATION 0x2024
1270 #define R700_MC_VM_AGP_TOP 0x2028
1271 #define R700_MC_VM_AGP_BOT 0x202c
1272 #define R700_MC_VM_AGP_BASE 0x2030
1273 #define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
1274 #define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
1275 #define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c
1277 #define R600_MCD_RD_A_CNTL 0x219c
1278 #define R600_MCD_RD_B_CNTL 0x21a0
1280 #define R600_MCD_WR_A_CNTL 0x21a4
1281 #define R600_MCD_WR_B_CNTL 0x21a8
1283 #define R600_MCD_RD_SYS_CNTL 0x2200
1284 #define R600_MCD_WR_SYS_CNTL 0x2214
1286 #define R600_MCD_RD_GFX_CNTL 0x21fc
1287 #define R600_MCD_RD_HDP_CNTL 0x2204
1288 #define R600_MCD_RD_PDMA_CNTL 0x2208
1289 #define R600_MCD_RD_SEM_CNTL 0x220c
1290 #define R600_MCD_WR_GFX_CNTL 0x2210
1291 #define R600_MCD_WR_HDP_CNTL 0x2218
1292 #define R600_MCD_WR_PDMA_CNTL 0x221c
1293 #define R600_MCD_WR_SEM_CNTL 0x2220
1295 # define R600_MCD_L1_TLB (1 << 0)
1296 # define R600_MCD_L1_FRAG_PROC (1 << 1)
1297 # define R600_MCD_L1_STRICT_ORDERING (1 << 2)
1299 # define R600_MCD_SYSTEM_ACCESS_MODE_MASK (3 << 6)
1300 # define R600_MCD_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6)
1301 # define R600_MCD_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6)
1302 # define R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS (2 << 6)
1303 # define R600_MCD_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6)
1305 # define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8)
1306 # define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8)
1308 # define R600_MCD_SEMAPHORE_MODE (1 << 10)
1309 # define R600_MCD_WAIT_L2_QUERY (1 << 11)
1310 # define R600_MCD_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 12)
1311 # define R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15)
1313 #define R700_MC_VM_MD_L1_TLB0_CNTL 0x2654
1314 #define R700_MC_VM_MD_L1_TLB1_CNTL 0x2658
1315 #define R700_MC_VM_MD_L1_TLB2_CNTL 0x265c
1317 #define R700_MC_VM_MB_L1_TLB0_CNTL 0x2234
1318 #define R700_MC_VM_MB_L1_TLB1_CNTL 0x2238
1319 #define R700_MC_VM_MB_L1_TLB2_CNTL 0x223c
1320 #define R700_MC_VM_MB_L1_TLB3_CNTL 0x2240
1322 # define R700_ENABLE_L1_TLB (1 << 0)
1323 # define R700_ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
1324 # define R700_SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
1325 # define R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
1326 # define R700_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 15)
1327 # define R700_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 18)
1329 #define R700_MC_ARB_RAMCFG 0x2760
1330 # define R700_NOOFBANK_SHIFT 0
1331 # define R700_NOOFBANK_MASK 0x3
1332 # define R700_NOOFRANK_SHIFT 2
1333 # define R700_NOOFRANK_MASK 0x1
1334 # define R700_NOOFROWS_SHIFT 3
1335 # define R700_NOOFROWS_MASK 0x7
1336 # define R700_NOOFCOLS_SHIFT 6
1337 # define R700_NOOFCOLS_MASK 0x3
1338 # define R700_CHANSIZE_SHIFT 8
1339 # define R700_CHANSIZE_MASK 0x1
1340 # define R700_BURSTLENGTH_SHIFT 9
1341 # define R700_BURSTLENGTH_MASK 0x1
1342 #define R600_RAMCFG 0x2408
1343 # define R600_NOOFBANK_SHIFT 0
1344 # define R600_NOOFBANK_MASK 0x1
1345 # define R600_NOOFRANK_SHIFT 1
1346 # define R600_NOOFRANK_MASK 0x1
1347 # define R600_NOOFROWS_SHIFT 2
1348 # define R600_NOOFROWS_MASK 0x7
1349 # define R600_NOOFCOLS_SHIFT 5
1350 # define R600_NOOFCOLS_MASK 0x3
1351 # define R600_CHANSIZE_SHIFT 7
1352 # define R600_CHANSIZE_MASK 0x1
1353 # define R600_BURSTLENGTH_SHIFT 8
1354 # define R600_BURSTLENGTH_MASK 0x1
1356 #define R600_VM_L2_CNTL 0x1400
1357 # define R600_VM_L2_CACHE_EN (1 << 0)
1358 # define R600_VM_L2_FRAG_PROC (1 << 1)
1359 # define R600_VM_ENABLE_PTE_CACHE_LRU_W (1 << 9)
1360 # define R600_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 13)
1361 # define R700_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 14)
1363 #define R600_VM_L2_CNTL2 0x1404
1364 # define R600_VM_L2_CNTL2_INVALIDATE_ALL_L1_TLBS (1 << 0)
1365 # define R600_VM_L2_CNTL2_INVALIDATE_L2_CACHE (1 << 1)
1366 #define R600_VM_L2_CNTL3 0x1408
1367 # define R600_VM_L2_CNTL3_BANK_SELECT_0(x) ((x) << 0)
1368 # define R600_VM_L2_CNTL3_BANK_SELECT_1(x) ((x) << 5)
1369 # define R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 10)
1370 # define R700_VM_L2_CNTL3_BANK_SELECT(x) ((x) << 0)
1371 # define R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 6)
1373 #define R600_VM_L2_STATUS 0x140c
1375 #define R600_VM_CONTEXT0_CNTL 0x1410
1376 # define R600_VM_ENABLE_CONTEXT (1 << 0)
1377 # define R600_VM_PAGE_TABLE_DEPTH_FLAT (0 << 1)
1379 #define R600_VM_CONTEXT0_CNTL2 0x1430
1380 #define R600_VM_CONTEXT0_REQUEST_RESPONSE 0x1470
1381 #define R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490
1382 #define R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14b0
1383 #define R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574
1384 #define R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594
1385 #define R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15b4
1387 #define R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c
1388 #define R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c
1389 #define R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157c
1391 #define R600_HDP_HOST_PATH_CNTL 0x2c00
1393 #define R600_GRBM_CNTL 0x8000
1394 # define R600_GRBM_READ_TIMEOUT(x) ((x) << 0)
1396 #define R600_GRBM_STATUS 0x8010
1397 # define R600_CMDFIFO_AVAIL_MASK 0x1f
1398 # define R700_CMDFIFO_AVAIL_MASK 0xf
1399 # define R600_GUI_ACTIVE (1 << 31)
1400 #define R600_GRBM_STATUS2 0x8014
1401 #define R600_GRBM_SOFT_RESET 0x8020
1402 # define R600_SOFT_RESET_CP (1 << 0)
1403 #define R600_WAIT_UNTIL 0x8040
1405 #define R600_CP_SEM_WAIT_TIMER 0x85bc
1406 #define R600_CP_ME_CNTL 0x86d8
1407 # define R600_CP_ME_HALT (1 << 28)
1408 #define R600_CP_QUEUE_THRESHOLDS 0x8760
1409 # define R600_ROQ_IB1_START(x) ((x) << 0)
1410 # define R600_ROQ_IB2_START(x) ((x) << 8)
1411 #define R600_CP_MEQ_THRESHOLDS 0x8764
1412 # define R700_STQ_SPLIT(x) ((x) << 0)
1413 # define R600_MEQ_END(x) ((x) << 16)
1414 # define R600_ROQ_END(x) ((x) << 24)
1415 #define R600_CP_PERFMON_CNTL 0x87fc
1416 #define R600_CP_RB_BASE 0xc100
1417 #define R600_CP_RB_CNTL 0xc104
1418 # define R600_RB_BUFSZ(x) ((x) << 0)
1419 # define R600_RB_BLKSZ(x) ((x) << 8)
1420 # define R600_RB_NO_UPDATE (1 << 27)
1421 # define R600_RB_RPTR_WR_ENA (1 << 31)
1422 #define R600_CP_RB_RPTR_WR 0xc108
1423 #define R600_CP_RB_RPTR_ADDR 0xc10c
1424 #define R600_CP_RB_RPTR_ADDR_HI 0xc110
1425 #define R600_CP_RB_WPTR 0xc114
1426 #define R600_CP_RB_WPTR_ADDR 0xc118
1427 #define R600_CP_RB_WPTR_ADDR_HI 0xc11c
1428 #define R600_CP_RB_RPTR 0x8700
1429 #define R600_CP_RB_WPTR_DELAY 0x8704
1430 #define R600_CP_PFP_UCODE_ADDR 0xc150
1431 #define R600_CP_PFP_UCODE_DATA 0xc154
1432 #define R600_CP_ME_RAM_RADDR 0xc158
1433 #define R600_CP_ME_RAM_WADDR 0xc15c
1434 #define R600_CP_ME_RAM_DATA 0xc160
1435 #define R600_CP_DEBUG 0xc1fc
1437 #define R600_PA_CL_ENHANCE 0x8a14
1438 # define R600_CLIP_VTX_REORDER_ENA (1 << 0)
1439 # define R600_NUM_CLIP_SEQ(x) ((x) << 1)
1440 #define R600_PA_SC_LINE_STIPPLE_STATE 0x8b10
1441 #define R600_PA_SC_MULTI_CHIP_CNTL 0x8b20
1442 #define R700_PA_SC_FORCE_EOV_MAX_CNTS 0x8b24
1443 # define R700_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
1444 # define R700_FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
1445 #define R600_PA_SC_AA_SAMPLE_LOCS_2S 0x8b40
1446 #define R600_PA_SC_AA_SAMPLE_LOCS_4S 0x8b44
1447 #define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8b48
1448 #define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8b4c
1449 # define R600_S0_X(x) ((x) << 0)
1450 # define R600_S0_Y(x) ((x) << 4)
1451 # define R600_S1_X(x) ((x) << 8)
1452 # define R600_S1_Y(x) ((x) << 12)
1453 # define R600_S2_X(x) ((x) << 16)
1454 # define R600_S2_Y(x) ((x) << 20)
1455 # define R600_S3_X(x) ((x) << 24)
1456 # define R600_S3_Y(x) ((x) << 28)
1457 # define R600_S4_X(x) ((x) << 0)
1458 # define R600_S4_Y(x) ((x) << 4)
1459 # define R600_S5_X(x) ((x) << 8)
1460 # define R600_S5_Y(x) ((x) << 12)
1461 # define R600_S6_X(x) ((x) << 16)
1462 # define R600_S6_Y(x) ((x) << 20)
1463 # define R600_S7_X(x) ((x) << 24)
1464 # define R600_S7_Y(x) ((x) << 28)
1465 #define R600_PA_SC_FIFO_SIZE 0x8bd0
1466 # define R600_SC_PRIM_FIFO_SIZE(x) ((x) << 0)
1467 # define R600_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 8)
1468 # define R600_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 16)
1469 #define R700_PA_SC_FIFO_SIZE_R7XX 0x8bcc
1470 # define R700_SC_PRIM_FIFO_SIZE(x) ((x) << 0)
1471 # define R700_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
1472 # define R700_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
1473 #define R600_PA_SC_ENHANCE 0x8bf0
1474 # define R600_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
1475 # define R600_FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12)
1476 #define R600_PA_SC_CLIPRECT_RULE 0x2820c
1477 #define R700_PA_SC_EDGERULE 0x28230
1478 #define R600_PA_SC_LINE_STIPPLE 0x28a0c
1479 #define R600_PA_SC_MODE_CNTL 0x28a4c
1480 #define R600_PA_SC_AA_CONFIG 0x28c04
1482 #define R600_SX_EXPORT_BUFFER_SIZES 0x900c
1483 # define R600_COLOR_BUFFER_SIZE(x) ((x) << 0)
1484 # define R600_POSITION_BUFFER_SIZE(x) ((x) << 8)
1485 # define R600_SMX_BUFFER_SIZE(x) ((x) << 16)
1486 #define R600_SX_DEBUG_1 0x9054
1487 # define R600_SMX_EVENT_RELEASE (1 << 0)
1488 # define R600_ENABLE_NEW_SMX_ADDRESS (1 << 16)
1489 #define R700_SX_DEBUG_1 0x9058
1490 # define R700_ENABLE_NEW_SMX_ADDRESS (1 << 16)
1491 #define R600_SX_MISC 0x28350
1493 #define R600_DB_DEBUG 0x9830
1494 # define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31)
1495 #define R600_DB_WATERMARKS 0x9838
1496 # define R600_DEPTH_FREE(x) ((x) << 0)
1497 # define R600_DEPTH_FLUSH(x) ((x) << 5)
1498 # define R600_DEPTH_PENDING_FREE(x) ((x) << 15)
1499 # define R600_DEPTH_CACHELINE_FREE(x) ((x) << 20)
1500 #define R700_DB_DEBUG3 0x98b0
1501 # define R700_DB_CLK_OFF_DELAY(x) ((x) << 11)
1502 #define RV700_DB_DEBUG4 0x9b8c
1503 # define RV700_DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6)
1505 #define R600_VGT_CACHE_INVALIDATION 0x88c4
1506 # define R600_CACHE_INVALIDATION(x) ((x) << 0)
1507 # define R600_VC_ONLY 0
1508 # define R600_TC_ONLY 1
1509 # define R600_VC_AND_TC 2
1510 # define R700_AUTO_INVLD_EN(x) ((x) << 6)
1511 # define R700_NO_AUTO 0
1512 # define R700_ES_AUTO 1
1513 # define R700_GS_AUTO 2
1514 # define R700_ES_AND_GS_AUTO 3
1515 #define R600_VGT_GS_PER_ES 0x88c8
1516 #define R600_VGT_ES_PER_GS 0x88cc
1517 #define R600_VGT_GS_PER_VS 0x88e8
1518 #define R600_VGT_GS_VERTEX_REUSE 0x88d4
1519 #define R600_VGT_NUM_INSTANCES 0x8974
1520 #define R600_VGT_STRMOUT_EN 0x28ab0
1521 #define R600_VGT_EVENT_INITIATOR 0x28a90
1522 # define R600_CACHE_FLUSH_AND_INV_EVENT (0x16 << 0)
1523 #define R600_VGT_VERTEX_REUSE_BLOCK_CNTL 0x28c58
1524 # define R600_VTX_REUSE_DEPTH_MASK 0xff
1525 #define R600_VGT_OUT_DEALLOC_CNTL 0x28c5c
1526 # define R600_DEALLOC_DIST_MASK 0x7f
1528 #define R600_CB_COLOR0_BASE 0x28040
1529 #define R600_CB_COLOR1_BASE 0x28044
1530 #define R600_CB_COLOR2_BASE 0x28048
1531 #define R600_CB_COLOR3_BASE 0x2804c
1532 #define R600_CB_COLOR4_BASE 0x28050
1533 #define R600_CB_COLOR5_BASE 0x28054
1534 #define R600_CB_COLOR6_BASE 0x28058
1535 #define R600_CB_COLOR7_BASE 0x2805c
1536 #define R600_CB_COLOR7_FRAG 0x280fc
1538 #define R600_TC_CNTL 0x9608
1539 # define R600_TC_L2_SIZE(x) ((x) << 5)
1540 # define R600_L2_DISABLE_LATE_HIT (1 << 9)
1542 #define R600_ARB_POP 0x2418
1543 # define R600_ENABLE_TC128 (1 << 30)
1544 #define R600_ARB_GDEC_RD_CNTL 0x246c
1546 #define R600_TA_CNTL_AUX 0x9508
1547 # define R600_DISABLE_CUBE_WRAP (1 << 0)
1548 # define R600_DISABLE_CUBE_ANISO (1 << 1)
1549 # define R700_GETLOD_SELECT(x) ((x) << 2)
1550 # define R600_SYNC_GRADIENT (1 << 24)
1551 # define R600_SYNC_WALKER (1 << 25)
1552 # define R600_SYNC_ALIGNER (1 << 26)
1553 # define R600_BILINEAR_PRECISION_6_BIT (0 << 31)
1554 # define R600_BILINEAR_PRECISION_8_BIT (1 << 31)
1556 #define R700_TCP_CNTL 0x9610
1558 #define R600_SMX_DC_CTL0 0xa020
1559 # define R700_USE_HASH_FUNCTION (1 << 0)
1560 # define R700_CACHE_DEPTH(x) ((x) << 1)
1561 # define R700_FLUSH_ALL_ON_EVENT (1 << 10)
1562 # define R700_STALL_ON_EVENT (1 << 11)
1563 #define R700_SMX_EVENT_CTL 0xa02c
1564 # define R700_ES_FLUSH_CTL(x) ((x) << 0)
1565 # define R700_GS_FLUSH_CTL(x) ((x) << 3)
1566 # define R700_ACK_FLUSH_CTL(x) ((x) << 6)
1567 # define R700_SYNC_FLUSH_CTL (1 << 8)
1569 #define R600_SQ_CONFIG 0x8c00
1570 # define R600_VC_ENABLE (1 << 0)
1571 # define R600_EXPORT_SRC_C (1 << 1)
1572 # define R600_DX9_CONSTS (1 << 2)
1573 # define R600_ALU_INST_PREFER_VECTOR (1 << 3)
1574 # define R600_DX10_CLAMP (1 << 4)
1575 # define R600_CLAUSE_SEQ_PRIO(x) ((x) << 8)
1576 # define R600_PS_PRIO(x) ((x) << 24)
1577 # define R600_VS_PRIO(x) ((x) << 26)
1578 # define R600_GS_PRIO(x) ((x) << 28)
1579 # define R600_ES_PRIO(x) ((x) << 30)
1580 #define R600_SQ_GPR_RESOURCE_MGMT_1 0x8c04
1581 # define R600_NUM_PS_GPRS(x) ((x) << 0)
1582 # define R600_NUM_VS_GPRS(x) ((x) << 16)
1583 # define R700_DYN_GPR_ENABLE (1 << 27)
1584 # define R600_NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
1585 #define R600_SQ_GPR_RESOURCE_MGMT_2 0x8c08
1586 # define R600_NUM_GS_GPRS(x) ((x) << 0)
1587 # define R600_NUM_ES_GPRS(x) ((x) << 16)
1588 #define R600_SQ_THREAD_RESOURCE_MGMT 0x8c0c
1589 # define R600_NUM_PS_THREADS(x) ((x) << 0)
1590 # define R600_NUM_VS_THREADS(x) ((x) << 8)
1591 # define R600_NUM_GS_THREADS(x) ((x) << 16)
1592 # define R600_NUM_ES_THREADS(x) ((x) << 24)
1593 #define R600_SQ_STACK_RESOURCE_MGMT_1 0x8c10
1594 # define R600_NUM_PS_STACK_ENTRIES(x) ((x) << 0)
1595 # define R600_NUM_VS_STACK_ENTRIES(x) ((x) << 16)
1596 #define R600_SQ_STACK_RESOURCE_MGMT_2 0x8c14
1597 # define R600_NUM_GS_STACK_ENTRIES(x) ((x) << 0)
1598 # define R600_NUM_ES_STACK_ENTRIES(x) ((x) << 16)
1599 #define R600_SQ_MS_FIFO_SIZES 0x8cf0
1600 # define R600_CACHE_FIFO_SIZE(x) ((x) << 0)
1601 # define R600_FETCH_FIFO_HIWATER(x) ((x) << 8)
1602 # define R600_DONE_FIFO_HIWATER(x) ((x) << 16)
1603 # define R600_ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
1604 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8db0
1605 # define R700_SIMDA_RING0(x) ((x) << 0)
1606 # define R700_SIMDA_RING1(x) ((x) << 8)
1607 # define R700_SIMDB_RING0(x) ((x) << 16)
1608 # define R700_SIMDB_RING1(x) ((x) << 24)
1609 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8db4
1610 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8db8
1611 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8dbc
1612 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8dc0
1613 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8dc4
1614 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8dc8
1615 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8dcc
1617 #define R600_SPI_PS_IN_CONTROL_0 0x286cc
1618 # define R600_NUM_INTERP(x) ((x) << 0)
1619 # define R600_POSITION_ENA (1 << 8)
1620 # define R600_POSITION_CENTROID (1 << 9)
1621 # define R600_POSITION_ADDR(x) ((x) << 10)
1622 # define R600_PARAM_GEN(x) ((x) << 15)
1623 # define R600_PARAM_GEN_ADDR(x) ((x) << 19)
1624 # define R600_BARYC_SAMPLE_CNTL(x) ((x) << 26)
1625 # define R600_PERSP_GRADIENT_ENA (1 << 28)
1626 # define R600_LINEAR_GRADIENT_ENA (1 << 29)
1627 # define R600_POSITION_SAMPLE (1 << 30)
1628 # define R600_BARYC_AT_SAMPLE_ENA (1 << 31)
1629 #define R600_SPI_PS_IN_CONTROL_1 0x286d0
1630 # define R600_GEN_INDEX_PIX (1 << 0)
1631 # define R600_GEN_INDEX_PIX_ADDR(x) ((x) << 1)
1632 # define R600_FRONT_FACE_ENA (1 << 8)
1633 # define R600_FRONT_FACE_CHAN(x) ((x) << 9)
1634 # define R600_FRONT_FACE_ALL_BITS (1 << 11)
1635 # define R600_FRONT_FACE_ADDR(x) ((x) << 12)
1636 # define R600_FOG_ADDR(x) ((x) << 17)
1637 # define R600_FIXED_PT_POSITION_ENA (1 << 24)
1638 # define R600_FIXED_PT_POSITION_ADDR(x) ((x) << 25)
1639 # define R700_POSITION_ULC (1 << 30)
1640 #define R600_SPI_INPUT_Z 0x286d8
1642 #define R600_SPI_CONFIG_CNTL 0x9100
1643 # define R600_GPR_WRITE_PRIORITY(x) ((x) << 0)
1644 # define R600_DISABLE_INTERP_1 (1 << 5)
1645 #define R600_SPI_CONFIG_CNTL_1 0x913c
1646 # define R600_VTX_DONE_DELAY(x) ((x) << 0)
1647 # define R600_INTERP_ONE_PRIM_PER_ROW (1 << 4)
1649 #define R600_GB_TILING_CONFIG 0x98f0
1650 # define R600_PIPE_TILING(x) ((x) << 1)
1651 # define R600_BANK_TILING(x) ((x) << 4)
1652 # define R600_GROUP_SIZE(x) ((x) << 6)
1653 # define R600_ROW_TILING(x) ((x) << 8)
1654 # define R600_BANK_SWAPS(x) ((x) << 11)
1655 # define R600_SAMPLE_SPLIT(x) ((x) << 14)
1656 # define R600_BACKEND_MAP(x) ((x) << 16)
1657 #define R600_DCP_TILING_CONFIG 0x6ca0
1658 #define R600_HDP_TILING_CONFIG 0x2f3c
1660 #define R600_CC_RB_BACKEND_DISABLE 0x98f4
1661 #define R700_CC_SYS_RB_BACKEND_DISABLE 0x3f88
1662 # define R600_BACKEND_DISABLE(x) ((x) << 16)
1664 #define R600_CC_GC_SHADER_PIPE_CONFIG 0x8950
1665 #define R600_GC_USER_SHADER_PIPE_CONFIG 0x8954
1666 # define R600_INACTIVE_QD_PIPES(x) ((x) << 8)
1667 # define R600_INACTIVE_QD_PIPES_MASK (0xff << 8)
1668 # define R600_INACTIVE_SIMDS(x) ((x) << 16)
1669 # define R600_INACTIVE_SIMDS_MASK (0xff << 16)
1671 #define R700_CGTS_SYS_TCC_DISABLE 0x3f90
1672 #define R700_CGTS_USER_SYS_TCC_DISABLE 0x3f94
1673 #define R700_CGTS_TCC_DISABLE 0x9148
1674 #define R700_CGTS_USER_TCC_DISABLE 0x914c
1677 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
1679 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
1680 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
1681 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
1682 #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
1683 #define RADEON_LAST_DISPATCH 1
1685 #define R600_LAST_FRAME_REG R600_SCRATCH_REG0
1686 #define R600_LAST_DISPATCH_REG R600_SCRATCH_REG1
1687 #define R600_LAST_CLEAR_REG R600_SCRATCH_REG2
1688 #define R600_LAST_SWI_REG R600_SCRATCH_REG3
1690 #define RADEON_MAX_VB_AGE 0x7fffffff
1691 #define RADEON_MAX_VB_VERTS (0xffff)
1693 #define RADEON_RING_HIGH_MARK 128
1695 #define RADEON_PCIGART_TABLE_SIZE (32*1024)
1697 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
1698 #define RADEON_WRITE(reg, val) \
1700 if (reg < 0x10000) { \
1701 DRM_WRITE32(dev_priv->mmio, (reg), (val)); \
1703 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, (reg)); \
1704 DRM_WRITE32(dev_priv->mmio, RADEON_MM_DATA, (val)); \
1707 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
1708 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
1710 #define RADEON_WRITE_PLL(addr, val) \
1712 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \
1713 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
1714 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \
1717 #define RADEON_WRITE_PCIE(addr, val) \
1719 RADEON_WRITE8(RADEON_PCIE_INDEX, \
1721 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \
1724 #define R500_WRITE_MCIND(addr, val) \
1726 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
1727 RADEON_WRITE(R520_MC_IND_DATA, (val)); \
1728 RADEON_WRITE(R520_MC_IND_INDEX, 0); \
1731 #define RS480_WRITE_MCIND(addr, val) \
1733 RADEON_WRITE(RS480_NB_MC_INDEX, \
1734 ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \
1735 RADEON_WRITE(RS480_NB_MC_DATA, (val)); \
1736 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \
1739 #define RS690_WRITE_MCIND(addr, val) \
1741 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \
1742 RADEON_WRITE(RS690_MC_DATA, val); \
1743 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \
1746 #define IGP_WRITE_MCIND(addr, val) \
1748 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \
1749 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \
1750 RS690_WRITE_MCIND(addr, val); \
1752 RS480_WRITE_MCIND(addr, val); \
1755 #define CP_PACKET0( reg, n ) \
1756 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
1757 #define CP_PACKET0_TABLE( reg, n ) \
1758 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
1759 #define CP_PACKET1( reg0, reg1 ) \
1760 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
1761 #define CP_PACKET2() \
1763 #define CP_PACKET3( pkt, n ) \
1764 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
1766 /* ================================================================
1767 * Engine control helper macros
1770 #define RADEON_WAIT_UNTIL_2D_IDLE() do { \
1771 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1772 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1773 RADEON_WAIT_HOST_IDLECLEAN) ); \
1776 #define RADEON_WAIT_UNTIL_3D_IDLE() do { \
1777 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1778 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
1779 RADEON_WAIT_HOST_IDLECLEAN) ); \
1782 #define RADEON_WAIT_UNTIL_IDLE() do { \
1783 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1784 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1785 RADEON_WAIT_3D_IDLECLEAN | \
1786 RADEON_WAIT_HOST_IDLECLEAN) ); \
1789 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
1790 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1791 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
1794 #define RADEON_FLUSH_CACHE() do { \
1795 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1796 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1797 OUT_RING(RADEON_RB3D_DC_FLUSH); \
1799 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1800 OUT_RING(R300_RB3D_DC_FLUSH); \
1804 #define RADEON_PURGE_CACHE() do { \
1805 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1806 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1807 OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \
1809 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1810 OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); \
1814 #define RADEON_FLUSH_ZCACHE() do { \
1815 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1816 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1817 OUT_RING(RADEON_RB3D_ZC_FLUSH); \
1819 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1820 OUT_RING(R300_ZC_FLUSH); \
1824 #define RADEON_PURGE_ZCACHE() do { \
1825 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1826 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1827 OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \
1829 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1830 OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \
1834 /* ================================================================
1835 * Misc helper macros
1838 /* Perfbox functionality only.
1840 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
1842 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
1843 u32 head = GET_RING_HEAD( dev_priv ); \
1844 if (head == dev_priv->ring.tail) \
1845 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
1849 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
1851 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv; \
1852 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; \
1853 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
1855 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \
1856 __ret = r600_do_cp_idle(dev_priv); \
1858 __ret = radeon_do_cp_idle(dev_priv); \
1859 if ( __ret ) return __ret; \
1860 sarea_priv->last_dispatch = 0; \
1861 radeon_freelist_reset( dev ); \
1865 #define RADEON_DISPATCH_AGE( age ) do { \
1866 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
1870 #define RADEON_FRAME_AGE( age ) do { \
1871 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
1875 #define RADEON_CLEAR_AGE( age ) do { \
1876 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
1880 #define R600_DISPATCH_AGE(age) do { \
1881 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
1882 OUT_RING((R600_LAST_DISPATCH_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \
1886 #define R600_FRAME_AGE(age) do { \
1887 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
1888 OUT_RING((R600_LAST_FRAME_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \
1892 #define R600_CLEAR_AGE(age) do { \
1893 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
1894 OUT_RING((R600_LAST_CLEAR_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \
1898 /* ================================================================
1902 #define RADEON_VERBOSE 0
1904 #define RING_LOCALS int write, _nr, _align_nr; unsigned int mask; u32 *ring;
1906 #define BEGIN_RING( n ) do { \
1907 if ( RADEON_VERBOSE ) { \
1908 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \
1910 _align_nr = (n + 0xf) & ~0xf; \
1911 if (dev_priv->ring.space <= (_align_nr * sizeof(u32))) { \
1913 radeon_wait_ring( dev_priv, _align_nr * sizeof(u32)); \
1915 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
1916 ring = dev_priv->ring.start; \
1917 write = dev_priv->ring.tail; \
1918 mask = dev_priv->ring.tail_mask; \
1921 #define ADVANCE_RING() do { \
1922 if ( RADEON_VERBOSE ) { \
1923 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
1924 write, dev_priv->ring.tail ); \
1926 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
1928 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
1929 ((dev_priv->ring.tail + _nr) & mask), \
1932 dev_priv->ring.tail = write; \
1935 extern void radeon_commit_ring(drm_radeon_private_t *dev_priv);
1937 #define COMMIT_RING() do { \
1938 radeon_commit_ring(dev_priv); \
1941 #define OUT_RING( x ) do { \
1942 if ( RADEON_VERBOSE ) { \
1943 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
1944 (unsigned int)(x), write ); \
1946 ring[write++] = (x); \
1950 #define OUT_RING_REG( reg, val ) do { \
1951 OUT_RING( CP_PACKET0( reg, 0 ) ); \
1955 #define OUT_RING_TABLE( tab, sz ) do { \
1957 int *_tab = (int *)(tab); \
1959 if (write + _size > mask) { \
1960 int _i = (mask+1) - write; \
1963 *(int *)(ring + write) = *_tab++; \
1970 while (_size > 0) { \
1971 *(ring + write) = *_tab++; \
1978 #endif /* __RADEON_DRV_H__ */