git.oblomov.eu Git - linux-2.6/blob - arch/mips/include/asm/mach-pnx8550/nand.h

   1 #ifndef __PNX8550_NAND_H
   2 #define __PNX8550_NAND_H
   3
   4 #define PNX8550_NAND_BASE_ADDR   0x10000000
   5 #define PNX8550_PCIXIO_BASE      0xBBE40000
   6
   7 #define PNX8550_DMA_EXT_ADDR     *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x800)
   8 #define PNX8550_DMA_INT_ADDR     *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x804)
   9 #define PNX8550_DMA_TRANS_SIZE   *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x808)
  10 #define PNX8550_DMA_CTRL         *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x80c)
  11 #define PNX8550_XIO_SEL0         *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x814)
  12 #define PNX8550_GPXIO_ADDR       *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x820)
  13 #define PNX8550_GPXIO_WR         *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x824)
  14 #define PNX8550_GPXIO_RD         *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x828)
  15 #define PNX8550_GPXIO_CTRL       *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x82C)
  16 #define PNX8550_XIO_FLASH_CTRL   *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x830)
  17 #define PNX8550_GPXIO_INT_STATUS *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb0)
  18 #define PNX8550_GPXIO_INT_ENABLE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb4)
  19 #define PNX8550_GPXIO_INT_CLEAR  *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb8)
  20 #define PNX8550_DMA_INT_STATUS   *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd0)
  21 #define PNX8550_DMA_INT_ENABLE   *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd4)
  22 #define PNX8550_DMA_INT_CLEAR    *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd8)
  23
  24 #define PNX8550_XIO_SEL0_EN_16BIT    0x00800000
  25 #define PNX8550_XIO_SEL0_USE_ACK     0x00400000
  26 #define PNX8550_XIO_SEL0_REN_HIGH    0x00100000
  27 #define PNX8550_XIO_SEL0_REN_LOW     0x00040000
  28 #define PNX8550_XIO_SEL0_WEN_HIGH    0x00010000
  29 #define PNX8550_XIO_SEL0_WEN_LOW     0x00004000
  30 #define PNX8550_XIO_SEL0_WAIT        0x00000200
  31 #define PNX8550_XIO_SEL0_OFFSET      0x00000020
  32 #define PNX8550_XIO_SEL0_TYPE_68360  0x00000000
  33 #define PNX8550_XIO_SEL0_TYPE_NOR    0x00000008
  34 #define PNX8550_XIO_SEL0_TYPE_NAND   0x00000010
  35 #define PNX8550_XIO_SEL0_TYPE_IDE    0x00000018
  36 #define PNX8550_XIO_SEL0_SIZE_8MB    0x00000000
  37 #define PNX8550_XIO_SEL0_SIZE_16MB   0x00000002
  38 #define PNX8550_XIO_SEL0_SIZE_32MB   0x00000004
  39 #define PNX8550_XIO_SEL0_SIZE_64MB   0x00000006
  40 #define PNX8550_XIO_SEL0_ENAB        0x00000001
  41
  42 #define PNX8550_SEL0_DEFAULT ((PNX8550_XIO_SEL0_EN_16BIT)  | \
  43                               (PNX8550_XIO_SEL0_REN_HIGH*0)| \
  44                               (PNX8550_XIO_SEL0_REN_LOW*2) | \
  45                               (PNX8550_XIO_SEL0_WEN_HIGH*0)| \
  46                               (PNX8550_XIO_SEL0_WEN_LOW*2) | \
  47                               (PNX8550_XIO_SEL0_WAIT*4)    | \
  48                               (PNX8550_XIO_SEL0_OFFSET*0)  | \
  49                               (PNX8550_XIO_SEL0_TYPE_NAND) | \
  50                               (PNX8550_XIO_SEL0_SIZE_32MB) | \
  51                               (PNX8550_XIO_SEL0_ENAB))
  52
  53 #define PNX8550_GPXIO_PENDING        0x00000200
  54 #define PNX8550_GPXIO_DONE           0x00000100
  55 #define PNX8550_GPXIO_CLR_DONE       0x00000080
  56 #define PNX8550_GPXIO_INIT           0x00000040
  57 #define PNX8550_GPXIO_READ_CMD       0x00000010
  58 #define PNX8550_GPXIO_BEN            0x0000000F
  59
  60 #define PNX8550_XIO_FLASH_64MB       0x00200000
  61 #define PNX8550_XIO_FLASH_INC_DATA   0x00100000
  62 #define PNX8550_XIO_FLASH_CMD_PH     0x000C0000
  63 #define PNX8550_XIO_FLASH_CMD_PH2    0x00080000
  64 #define PNX8550_XIO_FLASH_CMD_PH1    0x00040000
  65 #define PNX8550_XIO_FLASH_CMD_PH0    0x00000000
  66 #define PNX8550_XIO_FLASH_ADR_PH     0x00030000
  67 #define PNX8550_XIO_FLASH_ADR_PH3    0x00030000
  68 #define PNX8550_XIO_FLASH_ADR_PH2    0x00020000
  69 #define PNX8550_XIO_FLASH_ADR_PH1    0x00010000
  70 #define PNX8550_XIO_FLASH_ADR_PH0    0x00000000
  71 #define PNX8550_XIO_FLASH_CMD_B(x)   ((x<<8) & 0x0000FF00)
  72 #define PNX8550_XIO_FLASH_CMD_A(x)   (x & 0x000000FF)
  73
  74 #define PNX8550_XIO_INT_ACK          0x00004000
  75 #define PNX8550_XIO_INT_COMPL        0x00002000
  76 #define PNX8550_XIO_INT_NONSUP       0x00000200
  77 #define PNX8550_XIO_INT_ABORT        0x00000004
  78
  79 #define PNX8550_DMA_CTRL_SINGLE_DATA 0x00000400
  80 #define PNX8550_DMA_CTRL_SND2XIO     0x00000200
  81 #define PNX8550_DMA_CTRL_FIX_ADDR    0x00000100
  82 #define PNX8550_DMA_CTRL_BURST_8     0x00000000
  83 #define PNX8550_DMA_CTRL_BURST_16    0x00000020
  84 #define PNX8550_DMA_CTRL_BURST_32    0x00000040
  85 #define PNX8550_DMA_CTRL_BURST_64    0x00000060
  86 #define PNX8550_DMA_CTRL_BURST_128   0x00000080
  87 #define PNX8550_DMA_CTRL_BURST_256   0x000000A0
  88 #define PNX8550_DMA_CTRL_BURST_512   0x000000C0
  89 #define PNX8550_DMA_CTRL_BURST_NORES 0x000000E0
  90 #define PNX8550_DMA_CTRL_INIT_DMA    0x00000010
  91 #define PNX8550_DMA_CTRL_CMD_TYPE    0x0000000F
  92
  93 /* see PCI system arch, page 100 for the full list: */
  94 #define PNX8550_DMA_CTRL_PCI_CMD_READ    0x00000006
  95 #define PNX8550_DMA_CTRL_PCI_CMD_WRITE   0x00000007
  96
  97 #define PNX8550_DMA_INT_STAT_ACK_DONE   (1<<14)
  98 #define PNX8550_DMA_INT_STAT_DMA_DONE   (1<<12)
  99 #define PNX8550_DMA_INT_STAT_DMA_ERR    (1<<9)
 100 #define PNX8550_DMA_INT_STAT_PERR5      (1<<5)
 101 #define PNX8550_DMA_INT_STAT_PERR4      (1<<4)
 102 #define PNX8550_DMA_INT_STAT_M_ABORT    (1<<2)
 103 #define PNX8550_DMA_INT_STAT_T_ABORT    (1<<1)
 104
 105 #define PNX8550_DMA_INT_EN_ACK_DONE     (1<<14)
 106 #define PNX8550_DMA_INT_EN_DMA_DONE     (1<<12)
 107 #define PNX8550_DMA_INT_EN_DMA_ERR      (1<<9)
 108 #define PNX8550_DMA_INT_EN_PERR5        (1<<5)
 109 #define PNX8550_DMA_INT_EN_PERR4        (1<<4)
 110 #define PNX8550_DMA_INT_EN_M_ABORT      (1<<2)
 111 #define PNX8550_DMA_INT_EN_T_ABORT      (1<<1)
 112
 113 #define PNX8550_DMA_INT_CLR_ACK_DONE    (1<<14)
 114 #define PNX8550_DMA_INT_CLR_DMA_DONE    (1<<12)
 115 #define PNX8550_DMA_INT_CLR_DMA_ERR     (1<<9)
 116 #define PNX8550_DMA_INT_CLR_PERR5       (1<<5)
 117 #define PNX8550_DMA_INT_CLR_PERR4       (1<<4)
 118 #define PNX8550_DMA_INT_CLR_M_ABORT     (1<<2)
 119 #define PNX8550_DMA_INT_CLR_T_ABORT     (1<<1)
 120
 121 #endif