Merge branch 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik...
[linux-2.6] / arch / x86 / kernel / quirks.c
1 /*
2  * This file contains work-arounds for x86 and x86_64 platform bugs.
3  */
4 #include <linux/pci.h>
5 #include <linux/irq.h>
6
7 #include <asm/hpet.h>
8
9 #if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI)
10
11 static void __devinit quirk_intel_irqbalance(struct pci_dev *dev)
12 {
13         u8 config, rev;
14         u32 word;
15
16         /* BIOS may enable hardware IRQ balancing for
17          * E7520/E7320/E7525(revision ID 0x9 and below)
18          * based platforms.
19          * Disable SW irqbalance/affinity on those platforms.
20          */
21         pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
22         if (rev > 0x9)
23                 return;
24
25         /* enable access to config space*/
26         pci_read_config_byte(dev, 0xf4, &config);
27         pci_write_config_byte(dev, 0xf4, config|0x2);
28
29         /* read xTPR register */
30         raw_pci_ops->read(0, 0, 0x40, 0x4c, 2, &word);
31
32         if (!(word & (1 << 13))) {
33                 printk(KERN_INFO "Intel E7520/7320/7525 detected. "
34                         "Disabling irq balancing and affinity\n");
35 #ifdef CONFIG_IRQBALANCE
36                 irqbalance_disable("");
37 #endif
38                 noirqdebug_setup("");
39 #ifdef CONFIG_PROC_FS
40                 no_irq_affinity = 1;
41 #endif
42         }
43
44         /* put back the original value for config space*/
45         if (!(config & 0x2))
46                 pci_write_config_byte(dev, 0xf4, config);
47 }
48 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH,
49                         quirk_intel_irqbalance);
50 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH,
51                         quirk_intel_irqbalance);
52 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH,
53                         quirk_intel_irqbalance);
54 #endif
55
56 #if defined(CONFIG_HPET_TIMER)
57 unsigned long force_hpet_address;
58
59 static enum {
60         NONE_FORCE_HPET_RESUME,
61         OLD_ICH_FORCE_HPET_RESUME,
62         ICH_FORCE_HPET_RESUME,
63         VT8237_FORCE_HPET_RESUME,
64         NVIDIA_FORCE_HPET_RESUME,
65 } force_hpet_resume_type;
66
67 static void __iomem *rcba_base;
68
69 static void ich_force_hpet_resume(void)
70 {
71         u32 val;
72
73         if (!force_hpet_address)
74                 return;
75
76         if (rcba_base == NULL)
77                 BUG();
78
79         /* read the Function Disable register, dword mode only */
80         val = readl(rcba_base + 0x3404);
81         if (!(val & 0x80)) {
82                 /* HPET disabled in HPTC. Trying to enable */
83                 writel(val | 0x80, rcba_base + 0x3404);
84         }
85
86         val = readl(rcba_base + 0x3404);
87         if (!(val & 0x80))
88                 BUG();
89         else
90                 printk(KERN_DEBUG "Force enabled HPET at resume\n");
91
92         return;
93 }
94
95 static void ich_force_enable_hpet(struct pci_dev *dev)
96 {
97         u32 val;
98         u32 uninitialized_var(rcba);
99         int err = 0;
100
101         if (hpet_address || force_hpet_address)
102                 return;
103
104         pci_read_config_dword(dev, 0xF0, &rcba);
105         rcba &= 0xFFFFC000;
106         if (rcba == 0) {
107                 printk(KERN_DEBUG "RCBA disabled. Cannot force enable HPET\n");
108                 return;
109         }
110
111         /* use bits 31:14, 16 kB aligned */
112         rcba_base = ioremap_nocache(rcba, 0x4000);
113         if (rcba_base == NULL) {
114                 printk(KERN_DEBUG "ioremap failed. Cannot force enable HPET\n");
115                 return;
116         }
117
118         /* read the Function Disable register, dword mode only */
119         val = readl(rcba_base + 0x3404);
120
121         if (val & 0x80) {
122                 /* HPET is enabled in HPTC. Just not reported by BIOS */
123                 val = val & 0x3;
124                 force_hpet_address = 0xFED00000 | (val << 12);
125                 printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
126                                force_hpet_address);
127                 iounmap(rcba_base);
128                 return;
129         }
130
131         /* HPET disabled in HPTC. Trying to enable */
132         writel(val | 0x80, rcba_base + 0x3404);
133
134         val = readl(rcba_base + 0x3404);
135         if (!(val & 0x80)) {
136                 err = 1;
137         } else {
138                 val = val & 0x3;
139                 force_hpet_address = 0xFED00000 | (val << 12);
140         }
141
142         if (err) {
143                 force_hpet_address = 0;
144                 iounmap(rcba_base);
145                 printk(KERN_DEBUG "Failed to force enable HPET\n");
146         } else {
147                 force_hpet_resume_type = ICH_FORCE_HPET_RESUME;
148                 printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
149                                force_hpet_address);
150         }
151 }
152
153 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0,
154                          ich_force_enable_hpet);
155 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1,
156                          ich_force_enable_hpet);
157 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0,
158                          ich_force_enable_hpet);
159 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1,
160                          ich_force_enable_hpet);
161 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31,
162                          ich_force_enable_hpet);
163 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1,
164                          ich_force_enable_hpet);
165
166
167 static struct pci_dev *cached_dev;
168
169 static void old_ich_force_hpet_resume(void)
170 {
171         u32 val;
172         u32 uninitialized_var(gen_cntl);
173
174         if (!force_hpet_address || !cached_dev)
175                 return;
176
177         pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
178         gen_cntl &= (~(0x7 << 15));
179         gen_cntl |= (0x4 << 15);
180
181         pci_write_config_dword(cached_dev, 0xD0, gen_cntl);
182         pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
183         val = gen_cntl >> 15;
184         val &= 0x7;
185         if (val == 0x4)
186                 printk(KERN_DEBUG "Force enabled HPET at resume\n");
187         else
188                 BUG();
189 }
190
191 static void old_ich_force_enable_hpet(struct pci_dev *dev)
192 {
193         u32 val;
194         u32 uninitialized_var(gen_cntl);
195
196         if (hpet_address || force_hpet_address)
197                 return;
198
199         pci_read_config_dword(dev, 0xD0, &gen_cntl);
200         /*
201          * Bit 17 is HPET enable bit.
202          * Bit 16:15 control the HPET base address.
203          */
204         val = gen_cntl >> 15;
205         val &= 0x7;
206         if (val & 0x4) {
207                 val &= 0x3;
208                 force_hpet_address = 0xFED00000 | (val << 12);
209                 printk(KERN_DEBUG "HPET at base address 0x%lx\n",
210                                force_hpet_address);
211                 return;
212         }
213
214         /*
215          * HPET is disabled. Trying enabling at FED00000 and check
216          * whether it sticks
217          */
218         gen_cntl &= (~(0x7 << 15));
219         gen_cntl |= (0x4 << 15);
220         pci_write_config_dword(dev, 0xD0, gen_cntl);
221
222         pci_read_config_dword(dev, 0xD0, &gen_cntl);
223
224         val = gen_cntl >> 15;
225         val &= 0x7;
226         if (val & 0x4) {
227                 /* HPET is enabled in HPTC. Just not reported by BIOS */
228                 val &= 0x3;
229                 force_hpet_address = 0xFED00000 | (val << 12);
230                 printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
231                                force_hpet_address);
232                 cached_dev = dev;
233                 force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME;
234                 return;
235         }
236
237         printk(KERN_DEBUG "Failed to force enable HPET\n");
238 }
239
240 /*
241  * Undocumented chipset features. Make sure that the user enforced
242  * this.
243  */
244 static void old_ich_force_enable_hpet_user(struct pci_dev *dev)
245 {
246         if (hpet_force_user)
247                 old_ich_force_enable_hpet(dev);
248 }
249
250 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
251                          old_ich_force_enable_hpet_user);
252 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12,
253                          old_ich_force_enable_hpet_user);
254 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
255                          old_ich_force_enable_hpet_user);
256 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12,
257                          old_ich_force_enable_hpet_user);
258 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
259                          old_ich_force_enable_hpet);
260 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_12,
261                          old_ich_force_enable_hpet);
262
263
264 static void vt8237_force_hpet_resume(void)
265 {
266         u32 val;
267
268         if (!force_hpet_address || !cached_dev)
269                 return;
270
271         val = 0xfed00000 | 0x80;
272         pci_write_config_dword(cached_dev, 0x68, val);
273
274         pci_read_config_dword(cached_dev, 0x68, &val);
275         if (val & 0x80)
276                 printk(KERN_DEBUG "Force enabled HPET at resume\n");
277         else
278                 BUG();
279 }
280
281 static void vt8237_force_enable_hpet(struct pci_dev *dev)
282 {
283         u32 uninitialized_var(val);
284
285         if (!hpet_force_user || hpet_address || force_hpet_address)
286                 return;
287
288         pci_read_config_dword(dev, 0x68, &val);
289         /*
290          * Bit 7 is HPET enable bit.
291          * Bit 31:10 is HPET base address (contrary to what datasheet claims)
292          */
293         if (val & 0x80) {
294                 force_hpet_address = (val & ~0x3ff);
295                 printk(KERN_DEBUG "HPET at base address 0x%lx\n",
296                                force_hpet_address);
297                 return;
298         }
299
300         /*
301          * HPET is disabled. Trying enabling at FED00000 and check
302          * whether it sticks
303          */
304         val = 0xfed00000 | 0x80;
305         pci_write_config_dword(dev, 0x68, val);
306
307         pci_read_config_dword(dev, 0x68, &val);
308         if (val & 0x80) {
309                 force_hpet_address = (val & ~0x3ff);
310                 printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
311                                force_hpet_address);
312                 cached_dev = dev;
313                 force_hpet_resume_type = VT8237_FORCE_HPET_RESUME;
314                 return;
315         }
316
317         printk(KERN_DEBUG "Failed to force enable HPET\n");
318 }
319
320 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235,
321                          vt8237_force_enable_hpet);
322 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
323                          vt8237_force_enable_hpet);
324
325 /*
326  * Undocumented chipset feature taken from LinuxBIOS.
327  */
328 static void nvidia_force_hpet_resume(void)
329 {
330         pci_write_config_dword(cached_dev, 0x44, 0xfed00001);
331         printk(KERN_DEBUG "Force enabled HPET at resume\n");
332 }
333
334 static void nvidia_force_enable_hpet(struct pci_dev *dev)
335 {
336         u32 uninitialized_var(val);
337
338         if (!hpet_force_user || hpet_address || force_hpet_address)
339                 return;
340
341         pci_write_config_dword(dev, 0x44, 0xfed00001);
342         pci_read_config_dword(dev, 0x44, &val);
343         force_hpet_address = val & 0xfffffffe;
344         force_hpet_resume_type = NVIDIA_FORCE_HPET_RESUME;
345         printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
346                 force_hpet_address);
347         cached_dev = dev;
348         return;
349 }
350
351 /* ISA Bridges */
352 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0050,
353                         nvidia_force_enable_hpet);
354 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0051,
355                         nvidia_force_enable_hpet);
356
357 /* LPC bridges */
358 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0360,
359                         nvidia_force_enable_hpet);
360 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0361,
361                         nvidia_force_enable_hpet);
362 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0362,
363                         nvidia_force_enable_hpet);
364 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0363,
365                         nvidia_force_enable_hpet);
366 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0364,
367                         nvidia_force_enable_hpet);
368 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0365,
369                         nvidia_force_enable_hpet);
370 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0366,
371                         nvidia_force_enable_hpet);
372 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0367,
373                         nvidia_force_enable_hpet);
374
375 void force_hpet_resume(void)
376 {
377         switch (force_hpet_resume_type) {
378             case ICH_FORCE_HPET_RESUME:
379                 return ich_force_hpet_resume();
380
381             case OLD_ICH_FORCE_HPET_RESUME:
382                 return old_ich_force_hpet_resume();
383
384             case VT8237_FORCE_HPET_RESUME:
385                 return vt8237_force_hpet_resume();
386
387             case NVIDIA_FORCE_HPET_RESUME:
388                 return nvidia_force_hpet_resume();
389
390             default:
391                 break;
392         }
393 }
394
395 #endif