git.oblomov.eu Git - linux-2.6/blob - arch/x86/kernel/genx2apic_uv_x.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV APIC functions (note: not an Intel compatible APIC)
   7  *
   8  * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/threads.h>
  13 #include <linux/cpu.h>
  14 #include <linux/cpumask.h>
  15 #include <linux/string.h>
  16 #include <linux/ctype.h>
  17 #include <linux/init.h>
  18 #include <linux/sched.h>
  19 #include <linux/module.h>
  20 #include <linux/hardirq.h>
  21 #include <linux/timer.h>
  22 #include <linux/proc_fs.h>
  23 #include <asm/current.h>
  24 #include <asm/smp.h>
  25 #include <asm/ipi.h>
  26 #include <asm/genapic.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/uv/uv.h>
  29 #include <asm/uv/uv_mmrs.h>
  30 #include <asm/uv/uv_hub.h>
  31 #include <asm/uv/bios.h>
  32
  33 DEFINE_PER_CPU(int, x2apic_extra_bits);
  34
  35 static enum uv_system_type uv_system_type;
  36
  37 static int uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
  38 {
  39         if (!strcmp(oem_id, "SGI")) {
  40                 if (!strcmp(oem_table_id, "UVL"))
  41                         uv_system_type = UV_LEGACY_APIC;
  42                 else if (!strcmp(oem_table_id, "UVX"))
  43                         uv_system_type = UV_X2APIC;
  44                 else if (!strcmp(oem_table_id, "UVH")) {
  45                         uv_system_type = UV_NON_UNIQUE_APIC;
  46                         return 1;
  47                 }
  48         }
  49         return 0;
  50 }
  51
  52 enum uv_system_type get_uv_system_type(void)
  53 {
  54         return uv_system_type;
  55 }
  56
  57 int is_uv_system(void)
  58 {
  59         return uv_system_type != UV_NONE;
  60 }
  61 EXPORT_SYMBOL_GPL(is_uv_system);
  62
  63 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
  64 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
  65
  66 struct uv_blade_info *uv_blade_info;
  67 EXPORT_SYMBOL_GPL(uv_blade_info);
  68
  69 short *uv_node_to_blade;
  70 EXPORT_SYMBOL_GPL(uv_node_to_blade);
  71
  72 short *uv_cpu_to_blade;
  73 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
  74
  75 short uv_possible_blades;
  76 EXPORT_SYMBOL_GPL(uv_possible_blades);
  77
  78 unsigned long sn_rtc_cycles_per_second;
  79 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
  80
  81 /* Start with all IRQs pointing to boot CPU.  IRQ balancing will shift them. */
  82
  83 static const struct cpumask *uv_target_cpus(void)
  84 {
  85         return cpumask_of(0);
  86 }
  87
  88 static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask)
  89 {
  90         cpumask_clear(retmask);
  91         cpumask_set_cpu(cpu, retmask);
  92 }
  93
  94 int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
  95 {
  96         unsigned long val;
  97         int pnode;
  98
  99         pnode = uv_apicid_to_pnode(phys_apicid);
 100         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 101             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 102             (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 103             APIC_DM_INIT;
 104         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 105         mdelay(10);
 106
 107         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 108             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 109             (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 110             APIC_DM_STARTUP;
 111         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 112         return 0;
 113 }
 114
 115 static void uv_send_IPI_one(int cpu, int vector)
 116 {
 117         unsigned long val, apicid, lapicid;
 118         int pnode;
 119
 120         apicid = per_cpu(x86_cpu_to_apicid, cpu);
 121         lapicid = apicid & 0x3f; /* ZZZ macro needed */
 122         pnode = uv_apicid_to_pnode(apicid);
 123
 124         val = (     1UL << UVH_IPI_INT_SEND_SHFT    ) |
 125               ( lapicid << UVH_IPI_INT_APIC_ID_SHFT ) |
 126               (  vector << UVH_IPI_INT_VECTOR_SHFT  );
 127
 128         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 129 }
 130
 131 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
 132 {
 133         unsigned int cpu;
 134
 135         for_each_cpu(cpu, mask)
 136                 uv_send_IPI_one(cpu, vector);
 137 }
 138
 139 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
 140 {
 141         unsigned int this_cpu = smp_processor_id();
 142         unsigned int cpu;
 143
 144         for_each_cpu(cpu, mask) {
 145                 if (cpu != this_cpu)
 146                         uv_send_IPI_one(cpu, vector);
 147         }
 148 }
 149
 150 static void uv_send_IPI_allbutself(int vector)
 151 {
 152         unsigned int this_cpu = smp_processor_id();
 153         unsigned int cpu;
 154
 155         for_each_online_cpu(cpu) {
 156                 if (cpu != this_cpu)
 157                         uv_send_IPI_one(cpu, vector);
 158         }
 159 }
 160
 161 static void uv_send_IPI_all(int vector)
 162 {
 163         uv_send_IPI_mask(cpu_online_mask, vector);
 164 }
 165
 166 static int uv_apic_id_registered(void)
 167 {
 168         return 1;
 169 }
 170
 171 static void uv_init_apic_ldr(void)
 172 {
 173 }
 174
 175 static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask)
 176 {
 177         /*
 178          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 179          * May as well be the first.
 180          */
 181         int cpu = cpumask_first(cpumask);
 182
 183         if ((unsigned)cpu < nr_cpu_ids)
 184                 return per_cpu(x86_cpu_to_apicid, cpu);
 185         else
 186                 return BAD_APICID;
 187 }
 188
 189 static unsigned int
 190 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
 191                           const struct cpumask *andmask)
 192 {
 193         int cpu;
 194
 195         /*
 196          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 197          * May as well be the first.
 198          */
 199         for_each_cpu_and(cpu, cpumask, andmask) {
 200                 if (cpumask_test_cpu(cpu, cpu_online_mask))
 201                         break;
 202         }
 203         if (cpu < nr_cpu_ids)
 204                 return per_cpu(x86_cpu_to_apicid, cpu);
 205
 206         return BAD_APICID;
 207 }
 208
 209 static unsigned int x2apic_get_apic_id(unsigned long x)
 210 {
 211         unsigned int id;
 212
 213         WARN_ON(preemptible() && num_online_cpus() > 1);
 214         id = x | __get_cpu_var(x2apic_extra_bits);
 215
 216         return id;
 217 }
 218
 219 static unsigned long set_apic_id(unsigned int id)
 220 {
 221         unsigned long x;
 222
 223         /* maskout x2apic_extra_bits ? */
 224         x = id;
 225         return x;
 226 }
 227
 228 static unsigned int uv_read_apic_id(void)
 229 {
 230
 231         return x2apic_get_apic_id(apic_read(APIC_ID));
 232 }
 233
 234 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
 235 {
 236         return uv_read_apic_id() >> index_msb;
 237 }
 238
 239 static void uv_send_IPI_self(int vector)
 240 {
 241         apic_write(APIC_SELF_IPI, vector);
 242 }
 243
 244 struct genapic apic_x2apic_uv_x = {
 245
 246         .name                           = "UV large system",
 247         .probe                          = NULL,
 248         .acpi_madt_oem_check            = uv_acpi_madt_oem_check,
 249         .apic_id_registered             = uv_apic_id_registered,
 250
 251         .irq_delivery_mode              = dest_Fixed,
 252         .irq_dest_mode                  = 1, /* logical */
 253
 254         .target_cpus                    = uv_target_cpus,
 255         .disable_esr                    = 0,
 256         .dest_logical                   = APIC_DEST_LOGICAL,
 257         .check_apicid_used              = NULL,
 258         .check_apicid_present           = NULL,
 259
 260         .vector_allocation_domain       = uv_vector_allocation_domain,
 261         .init_apic_ldr                  = uv_init_apic_ldr,
 262
 263         .ioapic_phys_id_map             = NULL,
 264         .setup_apic_routing             = NULL,
 265         .multi_timer_check              = NULL,
 266         .apicid_to_node                 = NULL,
 267         .cpu_to_logical_apicid          = NULL,
 268         .cpu_present_to_apicid          = default_cpu_present_to_apicid,
 269         .apicid_to_cpu_present          = NULL,
 270         .setup_portio_remap             = NULL,
 271         .check_phys_apicid_present      = default_check_phys_apicid_present,
 272         .enable_apic_mode               = NULL,
 273         .phys_pkg_id                    = uv_phys_pkg_id,
 274         .mps_oem_check                  = NULL,
 275
 276         .get_apic_id                    = x2apic_get_apic_id,
 277         .set_apic_id                    = set_apic_id,
 278         .apic_id_mask                   = 0xFFFFFFFFu,
 279
 280         .cpu_mask_to_apicid             = uv_cpu_mask_to_apicid,
 281         .cpu_mask_to_apicid_and         = uv_cpu_mask_to_apicid_and,
 282
 283         .send_IPI_mask                  = uv_send_IPI_mask,
 284         .send_IPI_mask_allbutself       = uv_send_IPI_mask_allbutself,
 285         .send_IPI_allbutself            = uv_send_IPI_allbutself,
 286         .send_IPI_all                   = uv_send_IPI_all,
 287         .send_IPI_self                  = uv_send_IPI_self,
 288
 289         .wakeup_cpu                     = NULL,
 290         .trampoline_phys_low            = DEFAULT_TRAMPOLINE_PHYS_LOW,
 291         .trampoline_phys_high           = DEFAULT_TRAMPOLINE_PHYS_HIGH,
 292         .wait_for_init_deassert         = NULL,
 293         .smp_callin_clear_local_apic    = NULL,
 294         .store_NMI_vector               = NULL,
 295         .inquire_remote_apic            = NULL,
 296 };
 297
 298 static __cpuinit void set_x2apic_extra_bits(int pnode)
 299 {
 300         __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
 301 }
 302
 303 /*
 304  * Called on boot cpu.
 305  */
 306 static __init int boot_pnode_to_blade(int pnode)
 307 {
 308         int blade;
 309
 310         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 311                 if (pnode == uv_blade_info[blade].pnode)
 312                         return blade;
 313         BUG();
 314 }
 315
 316 struct redir_addr {
 317         unsigned long redirect;
 318         unsigned long alias;
 319 };
 320
 321 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 322
 323 static __initdata struct redir_addr redir_addrs[] = {
 324         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
 325         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
 326         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
 327 };
 328
 329 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 330 {
 331         union uvh_si_alias0_overlay_config_u alias;
 332         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
 333         int i;
 334
 335         for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
 336                 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
 337                 if (alias.s.base == 0) {
 338                         *size = (1UL << alias.s.m_alias);
 339                         redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
 340                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
 341                         return;
 342                 }
 343         }
 344         BUG();
 345 }
 346
 347 static __init void map_low_mmrs(void)
 348 {
 349         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
 350         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
 351 }
 352
 353 enum map_type {map_wb, map_uc};
 354
 355 static __init void map_high(char *id, unsigned long base, int shift,
 356                             int max_pnode, enum map_type map_type)
 357 {
 358         unsigned long bytes, paddr;
 359
 360         paddr = base << shift;
 361         bytes = (1UL << shift) * (max_pnode + 1);
 362         printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
 363                                                 paddr + bytes);
 364         if (map_type == map_uc)
 365                 init_extra_mapping_uc(paddr, bytes);
 366         else
 367                 init_extra_mapping_wb(paddr, bytes);
 368
 369 }
 370 static __init void map_gru_high(int max_pnode)
 371 {
 372         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 373         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 374
 375         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
 376         if (gru.s.enable)
 377                 map_high("GRU", gru.s.base, shift, max_pnode, map_wb);
 378 }
 379
 380 static __init void map_config_high(int max_pnode)
 381 {
 382         union uvh_rh_gam_cfg_overlay_config_mmr_u cfg;
 383         int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT;
 384
 385         cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR);
 386         if (cfg.s.enable)
 387                 map_high("CONFIG", cfg.s.base, shift, max_pnode, map_uc);
 388 }
 389
 390 static __init void map_mmr_high(int max_pnode)
 391 {
 392         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
 393         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
 394
 395         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
 396         if (mmr.s.enable)
 397                 map_high("MMR", mmr.s.base, shift, max_pnode, map_uc);
 398 }
 399
 400 static __init void map_mmioh_high(int max_pnode)
 401 {
 402         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
 403         int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 404
 405         mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
 406         if (mmioh.s.enable)
 407                 map_high("MMIOH", mmioh.s.base, shift, max_pnode, map_uc);
 408 }
 409
 410 static __init void uv_rtc_init(void)
 411 {
 412         long status;
 413         u64 ticks_per_sec;
 414
 415         status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
 416                                         &ticks_per_sec);
 417         if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
 418                 printk(KERN_WARNING
 419                         "unable to determine platform RTC clock frequency, "
 420                         "guessing.\n");
 421                 /* BIOS gives wrong value for clock freq. so guess */
 422                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
 423         } else
 424                 sn_rtc_cycles_per_second = ticks_per_sec;
 425 }
 426
 427 /*
 428  * percpu heartbeat timer
 429  */
 430 static void uv_heartbeat(unsigned long ignored)
 431 {
 432         struct timer_list *timer = &uv_hub_info->scir.timer;
 433         unsigned char bits = uv_hub_info->scir.state;
 434
 435         /* flip heartbeat bit */
 436         bits ^= SCIR_CPU_HEARTBEAT;
 437
 438         /* is this cpu idle? */
 439         if (idle_cpu(raw_smp_processor_id()))
 440                 bits &= ~SCIR_CPU_ACTIVITY;
 441         else
 442                 bits |= SCIR_CPU_ACTIVITY;
 443
 444         /* update system controller interface reg */
 445         uv_set_scir_bits(bits);
 446
 447         /* enable next timer period */
 448         mod_timer(timer, jiffies + SCIR_CPU_HB_INTERVAL);
 449 }
 450
 451 static void __cpuinit uv_heartbeat_enable(int cpu)
 452 {
 453         if (!uv_cpu_hub_info(cpu)->scir.enabled) {
 454                 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
 455
 456                 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
 457                 setup_timer(timer, uv_heartbeat, cpu);
 458                 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
 459                 add_timer_on(timer, cpu);
 460                 uv_cpu_hub_info(cpu)->scir.enabled = 1;
 461         }
 462
 463         /* check boot cpu */
 464         if (!uv_cpu_hub_info(0)->scir.enabled)
 465                 uv_heartbeat_enable(0);
 466 }
 467
 468 #ifdef CONFIG_HOTPLUG_CPU
 469 static void __cpuinit uv_heartbeat_disable(int cpu)
 470 {
 471         if (uv_cpu_hub_info(cpu)->scir.enabled) {
 472                 uv_cpu_hub_info(cpu)->scir.enabled = 0;
 473                 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
 474         }
 475         uv_set_cpu_scir_bits(cpu, 0xff);
 476 }
 477
 478 /*
 479  * cpu hotplug notifier
 480  */
 481 static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self,
 482                                        unsigned long action, void *hcpu)
 483 {
 484         long cpu = (long)hcpu;
 485
 486         switch (action) {
 487         case CPU_ONLINE:
 488                 uv_heartbeat_enable(cpu);
 489                 break;
 490         case CPU_DOWN_PREPARE:
 491                 uv_heartbeat_disable(cpu);
 492                 break;
 493         default:
 494                 break;
 495         }
 496         return NOTIFY_OK;
 497 }
 498
 499 static __init void uv_scir_register_cpu_notifier(void)
 500 {
 501         hotcpu_notifier(uv_scir_cpu_notify, 0);
 502 }
 503
 504 #else /* !CONFIG_HOTPLUG_CPU */
 505
 506 static __init void uv_scir_register_cpu_notifier(void)
 507 {
 508 }
 509
 510 static __init int uv_init_heartbeat(void)
 511 {
 512         int cpu;
 513
 514         if (is_uv_system())
 515                 for_each_online_cpu(cpu)
 516                         uv_heartbeat_enable(cpu);
 517         return 0;
 518 }
 519
 520 late_initcall(uv_init_heartbeat);
 521
 522 #endif /* !CONFIG_HOTPLUG_CPU */
 523
 524 /*
 525  * Called on each cpu to initialize the per_cpu UV data area.
 526  *      ZZZ hotplug not supported yet
 527  */
 528 void __cpuinit uv_cpu_init(void)
 529 {
 530         /* CPU 0 initilization will be done via uv_system_init. */
 531         if (!uv_blade_info)
 532                 return;
 533
 534         uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
 535
 536         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
 537                 set_x2apic_extra_bits(uv_hub_info->pnode);
 538 }
 539
 540
 541 void __init uv_system_init(void)
 542 {
 543         union uvh_si_addr_map_config_u m_n_config;
 544         union uvh_node_id_u node_id;
 545         unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
 546         int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
 547         int max_pnode = 0;
 548         unsigned long mmr_base, present;
 549
 550         map_low_mmrs();
 551
 552         m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
 553         m_val = m_n_config.s.m_skt;
 554         n_val = m_n_config.s.n_skt;
 555         mmr_base =
 556             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
 557             ~UV_MMR_ENABLE;
 558         printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
 559
 560         for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
 561                 uv_possible_blades +=
 562                   hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
 563         printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
 564
 565         bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
 566         uv_blade_info = kmalloc(bytes, GFP_KERNEL);
 567
 568         get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
 569
 570         bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
 571         uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
 572         memset(uv_node_to_blade, 255, bytes);
 573
 574         bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
 575         uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
 576         memset(uv_cpu_to_blade, 255, bytes);
 577
 578         blade = 0;
 579         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
 580                 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
 581                 for (j = 0; j < 64; j++) {
 582                         if (!test_bit(j, &present))
 583                                 continue;
 584                         uv_blade_info[blade].pnode = (i * 64 + j);
 585                         uv_blade_info[blade].nr_possible_cpus = 0;
 586                         uv_blade_info[blade].nr_online_cpus = 0;
 587                         blade++;
 588                 }
 589         }
 590
 591         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
 592         gnode_upper = (((unsigned long)node_id.s.node_id) &
 593                        ~((1 << n_val) - 1)) << m_val;
 594
 595         uv_bios_init();
 596         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id,
 597                             &sn_coherency_id, &sn_region_size);
 598         uv_rtc_init();
 599
 600         for_each_present_cpu(cpu) {
 601                 nid = cpu_to_node(cpu);
 602                 pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
 603                 blade = boot_pnode_to_blade(pnode);
 604                 lcpu = uv_blade_info[blade].nr_possible_cpus;
 605                 uv_blade_info[blade].nr_possible_cpus++;
 606
 607                 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
 608                 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
 609                 uv_cpu_hub_info(cpu)->m_val = m_val;
 610                 uv_cpu_hub_info(cpu)->n_val = m_val;
 611                 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
 612                 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
 613                 uv_cpu_hub_info(cpu)->pnode = pnode;
 614                 uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
 615                 uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
 616                 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
 617                 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
 618                 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
 619                 uv_cpu_hub_info(cpu)->scir.offset = SCIR_LOCAL_MMR_BASE + lcpu;
 620                 uv_node_to_blade[nid] = blade;
 621                 uv_cpu_to_blade[cpu] = blade;
 622                 max_pnode = max(pnode, max_pnode);
 623
 624                 printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
 625                         "lcpu %d, blade %d\n",
 626                         cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
 627                         lcpu, blade);
 628         }
 629
 630         map_gru_high(max_pnode);
 631         map_mmr_high(max_pnode);
 632         map_config_high(max_pnode);
 633         map_mmioh_high(max_pnode);
 634
 635         uv_cpu_init();
 636         uv_scir_register_cpu_notifier();
 637         proc_mkdir("sgi_uv", NULL);
 638 }