Merge branch 'upstream' of git://lost.foo-projects.org/~ahkok/git/netdev-2.6 into...
[linux-2.6] / arch / ppc / platforms / 4xx / bamboo.c
1 /*
2  * Bamboo board specific routines
3  *
4  * Wade Farnsworth <wfarnsworth@mvista.com>
5  * Copyright 2004 MontaVista Software Inc.
6  *
7  * This program is free software; you can redistribute  it and/or modify it
8  * under  the terms of  the GNU General  Public License as published by the
9  * Free Software Foundation;  either version 2 of the  License, or (at your
10  * option) any later version.
11  */
12
13 #include <linux/stddef.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/errno.h>
17 #include <linux/reboot.h>
18 #include <linux/pci.h>
19 #include <linux/kdev_t.h>
20 #include <linux/types.h>
21 #include <linux/major.h>
22 #include <linux/blkdev.h>
23 #include <linux/console.h>
24 #include <linux/delay.h>
25 #include <linux/ide.h>
26 #include <linux/initrd.h>
27 #include <linux/seq_file.h>
28 #include <linux/root_dev.h>
29 #include <linux/tty.h>
30 #include <linux/serial.h>
31 #include <linux/serial_core.h>
32 #include <linux/ethtool.h>
33
34 #include <asm/system.h>
35 #include <asm/pgtable.h>
36 #include <asm/page.h>
37 #include <asm/dma.h>
38 #include <asm/io.h>
39 #include <asm/machdep.h>
40 #include <asm/ocp.h>
41 #include <asm/pci-bridge.h>
42 #include <asm/time.h>
43 #include <asm/todc.h>
44 #include <asm/bootinfo.h>
45 #include <asm/ppc4xx_pic.h>
46 #include <asm/ppcboot.h>
47
48 #include <syslib/gen550.h>
49 #include <syslib/ibm440gx_common.h>
50
51 extern bd_t __res;
52
53 static struct ibm44x_clocks clocks __initdata;
54
55 /*
56  * Bamboo external IRQ triggering/polarity settings
57  */
58 unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
59         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ0: Ethernet transceiver */
60         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ1: Expansion connector */
61         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ2: PCI slot 0 */
62         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ3: PCI slot 1 */
63         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ4: PCI slot 2 */
64         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ5: PCI slot 3 */
65         (IRQ_SENSE_EDGE  | IRQ_POLARITY_NEGATIVE), /* IRQ6: SMI pushbutton */
66         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ7: EXT */
67         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ8: EXT */
68         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ9: EXT */
69 };
70
71 static void __init
72 bamboo_calibrate_decr(void)
73 {
74         unsigned int freq;
75
76         if (mfspr(SPRN_CCR1) & CCR1_TCS)
77                 freq = BAMBOO_TMRCLK;
78         else
79                 freq = clocks.cpu;
80
81         ibm44x_calibrate_decr(freq);
82
83 }
84
85 static int
86 bamboo_show_cpuinfo(struct seq_file *m)
87 {
88         seq_printf(m, "vendor\t\t: IBM\n");
89         seq_printf(m, "machine\t\t: PPC440EP EVB (Bamboo)\n");
90
91         return 0;
92 }
93
94 static inline int
95 bamboo_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
96 {
97         static char pci_irq_table[][4] =
98         /*
99          *      PCI IDSEL/INTPIN->INTLINE
100          *         A   B   C   D
101          */
102         {
103                 { 28, 28, 28, 28 },     /* IDSEL 1 - PCI Slot 0 */
104                 { 27, 27, 27, 27 },     /* IDSEL 2 - PCI Slot 1 */
105                 { 26, 26, 26, 26 },     /* IDSEL 3 - PCI Slot 2 */
106                 { 25, 25, 25, 25 },     /* IDSEL 4 - PCI Slot 3 */
107         };
108
109         const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
110         return PCI_IRQ_TABLE_LOOKUP;
111 }
112
113 static void __init bamboo_set_emacdata(void)
114 {
115         u8 * base_addr;
116         struct ocp_def *def;
117         struct ocp_func_emac_data *emacdata;
118         u8 val;
119         int mode;
120         u32 excluded = 0;
121
122         base_addr = ioremap64(BAMBOO_FPGA_SELECTION1_REG_ADDR, 16);
123         val = readb(base_addr);
124         iounmap((void *) base_addr);
125         if (BAMBOO_SEL_MII(val))
126                 mode = PHY_MODE_MII;
127         else if (BAMBOO_SEL_RMII(val))
128                 mode = PHY_MODE_RMII;
129         else
130                 mode = PHY_MODE_SMII;
131
132         /*
133          * SW2 on the Bamboo is used for ethernet configuration and is accessed
134          * via the CONFIG2 register in the FPGA.  If the ANEG pin is set,
135          * overwrite the supported features with the settings in SW2.
136          *
137          * This is used as a workaround for the improperly biased RJ-45 sockets
138          * on the Rev. 0 Bamboo.  By default only 10baseT is functional.
139          * Removing inductors L17 and L18 from the board allows 100baseT, but
140          * disables 10baseT.  The Rev. 1 has no such limitations.
141          */
142
143         base_addr = ioremap64(BAMBOO_FPGA_CONFIG2_REG_ADDR, 8);
144         val = readb(base_addr);
145         iounmap((void *) base_addr);
146         if (!BAMBOO_AUTONEGOTIATE(val)) {
147                 excluded |= SUPPORTED_Autoneg;
148                 if (BAMBOO_FORCE_100Mbps(val)) {
149                         excluded |= SUPPORTED_10baseT_Full;
150                         excluded |= SUPPORTED_10baseT_Half;
151                         if (BAMBOO_FULL_DUPLEX_EN(val))
152                                 excluded |= SUPPORTED_100baseT_Half;
153                         else
154                                 excluded |= SUPPORTED_100baseT_Full;
155                 } else {
156                         excluded |= SUPPORTED_100baseT_Full;
157                         excluded |= SUPPORTED_100baseT_Half;
158                         if (BAMBOO_FULL_DUPLEX_EN(val))
159                                 excluded |= SUPPORTED_10baseT_Half;
160                         else
161                                 excluded |= SUPPORTED_10baseT_Full;
162                 }
163         }
164
165         /* Set mac_addr, phy mode and unsupported phy features for each EMAC */
166
167         def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
168         emacdata = def->additions;
169         memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
170         emacdata->phy_mode = mode;
171         emacdata->phy_feat_exc = excluded;
172
173         def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
174         emacdata = def->additions;
175         memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
176         emacdata->phy_mode = mode;
177         emacdata->phy_feat_exc = excluded;
178 }
179
180 static int
181 bamboo_exclude_device(unsigned char bus, unsigned char devfn)
182 {
183         return (bus == 0 && devfn == 0);
184 }
185
186 #define PCI_READW(offset) \
187         (readw((void *)((u32)pci_reg_base+offset)))
188
189 #define PCI_WRITEW(value, offset) \
190         (writew(value, (void *)((u32)pci_reg_base+offset)))
191
192 #define PCI_WRITEL(value, offset) \
193         (writel(value, (void *)((u32)pci_reg_base+offset)))
194
195 static void __init
196 bamboo_setup_pci(void)
197 {
198         void *pci_reg_base;
199         unsigned long memory_size;
200         memory_size = ppc_md.find_end_of_memory();
201
202         pci_reg_base = ioremap64(BAMBOO_PCIL0_BASE, BAMBOO_PCIL0_SIZE);
203
204         /* Enable PCI I/O, Mem, and Busmaster cycles */
205         PCI_WRITEW(PCI_READW(PCI_COMMAND) |
206                    PCI_COMMAND_MEMORY |
207                    PCI_COMMAND_MASTER, PCI_COMMAND);
208
209         /* Disable region first */
210         PCI_WRITEL(0, BAMBOO_PCIL0_PMM0MA);
211
212         /* PLB starting addr: 0x00000000A0000000 */
213         PCI_WRITEL(BAMBOO_PCI_PHY_MEM_BASE, BAMBOO_PCIL0_PMM0LA);
214
215         /* PCI start addr, 0xA0000000 (PCI Address) */
216         PCI_WRITEL(BAMBOO_PCI_MEM_BASE, BAMBOO_PCIL0_PMM0PCILA);
217         PCI_WRITEL(0, BAMBOO_PCIL0_PMM0PCIHA);
218
219         /* Enable no pre-fetch, enable region */
220         PCI_WRITEL(((0xffffffff -
221                      (BAMBOO_PCI_UPPER_MEM - BAMBOO_PCI_MEM_BASE)) | 0x01),
222                       BAMBOO_PCIL0_PMM0MA);
223
224         /* Disable region one */
225         PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
226         PCI_WRITEL(0, BAMBOO_PCIL0_PMM1LA);
227         PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCILA);
228         PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCIHA);
229         PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
230
231         /* Disable region two */
232         PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
233         PCI_WRITEL(0, BAMBOO_PCIL0_PMM2LA);
234         PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCILA);
235         PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCIHA);
236         PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
237
238         /* Now configure the PCI->PLB windows, we only use PTM1
239          *
240          * For Inbound flow, set the window size to all available memory
241          * This is required because if size is smaller,
242          * then Eth/PCI DD would fail as PCI card not able to access
243          * the memory allocated by DD.
244          */
245
246         PCI_WRITEL(0, BAMBOO_PCIL0_PTM1MS);     /* disabled region 1 */
247         PCI_WRITEL(0, BAMBOO_PCIL0_PTM1LA);     /* begin of address map */
248
249         memory_size = 1 << fls(memory_size - 1);
250
251         /* Size low + Enabled */
252         PCI_WRITEL((0xffffffff - (memory_size - 1)) | 0x1, BAMBOO_PCIL0_PTM1MS);
253
254         eieio();
255         iounmap(pci_reg_base);
256 }
257
258 static void __init
259 bamboo_setup_hose(void)
260 {
261         unsigned int bar_response, bar;
262         struct pci_controller *hose;
263
264         bamboo_setup_pci();
265
266         hose = pcibios_alloc_controller();
267
268         if (!hose)
269                 return;
270
271         hose->first_busno = 0;
272         hose->last_busno = 0xff;
273
274         hose->pci_mem_offset = BAMBOO_PCI_MEM_OFFSET;
275
276         pci_init_resource(&hose->io_resource,
277                         BAMBOO_PCI_LOWER_IO,
278                         BAMBOO_PCI_UPPER_IO,
279                         IORESOURCE_IO,
280                         "PCI host bridge");
281
282         pci_init_resource(&hose->mem_resources[0],
283                         BAMBOO_PCI_LOWER_MEM,
284                         BAMBOO_PCI_UPPER_MEM,
285                         IORESOURCE_MEM,
286                         "PCI host bridge");
287
288         ppc_md.pci_exclude_device = bamboo_exclude_device;
289
290         hose->io_space.start = BAMBOO_PCI_LOWER_IO;
291         hose->io_space.end = BAMBOO_PCI_UPPER_IO;
292         hose->mem_space.start = BAMBOO_PCI_LOWER_MEM;
293         hose->mem_space.end = BAMBOO_PCI_UPPER_MEM;
294         isa_io_base =
295                 (unsigned long)ioremap64(BAMBOO_PCI_IO_BASE, BAMBOO_PCI_IO_SIZE);
296         hose->io_base_virt = (void *)isa_io_base;
297
298         setup_indirect_pci(hose,
299                         BAMBOO_PCI_CFGA_PLB32,
300                         BAMBOO_PCI_CFGD_PLB32);
301         hose->set_cfg_type = 1;
302
303         /* Zero config bars */
304         for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
305                 early_write_config_dword(hose, hose->first_busno,
306                                          PCI_FUNC(hose->first_busno), bar,
307                                          0x00000000);
308                 early_read_config_dword(hose, hose->first_busno,
309                                         PCI_FUNC(hose->first_busno), bar,
310                                         &bar_response);
311         }
312
313         hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
314
315         ppc_md.pci_swizzle = common_swizzle;
316         ppc_md.pci_map_irq = bamboo_map_irq;
317 }
318
319 TODC_ALLOC();
320
321 static void __init
322 bamboo_early_serial_map(void)
323 {
324         struct uart_port port;
325
326         /* Setup ioremapped serial port access */
327         memset(&port, 0, sizeof(port));
328         port.membase = ioremap64(PPC440EP_UART0_ADDR, 8);
329         port.irq = 0;
330         port.uartclk = clocks.uart0;
331         port.regshift = 0;
332         port.iotype = UPIO_MEM;
333         port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
334         port.line = 0;
335
336         if (early_serial_setup(&port) != 0) {
337                 printk("Early serial init of port 0 failed\n");
338         }
339
340 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
341         /* Configure debug serial access */
342         gen550_init(0, &port);
343 #endif
344
345         port.membase = ioremap64(PPC440EP_UART1_ADDR, 8);
346         port.irq = 1;
347         port.uartclk = clocks.uart1;
348         port.line = 1;
349
350         if (early_serial_setup(&port) != 0) {
351                 printk("Early serial init of port 1 failed\n");
352         }
353
354 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
355         /* Configure debug serial access */
356         gen550_init(1, &port);
357 #endif
358
359         port.membase = ioremap64(PPC440EP_UART2_ADDR, 8);
360         port.irq = 3;
361         port.uartclk = clocks.uart2;
362         port.line = 2;
363
364         if (early_serial_setup(&port) != 0) {
365                 printk("Early serial init of port 2 failed\n");
366         }
367
368 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
369         /* Configure debug serial access */
370         gen550_init(2, &port);
371 #endif
372
373         port.membase = ioremap64(PPC440EP_UART3_ADDR, 8);
374         port.irq = 4;
375         port.uartclk = clocks.uart3;
376         port.line = 3;
377
378         if (early_serial_setup(&port) != 0) {
379                 printk("Early serial init of port 3 failed\n");
380         }
381 }
382
383 static void __init
384 bamboo_setup_arch(void)
385 {
386
387         bamboo_set_emacdata();
388
389         ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
390         ocp_sys_info.opb_bus_freq = clocks.opb;
391
392         /* Setup TODC access */
393         TODC_INIT(TODC_TYPE_DS1743,
394                         0,
395                         0,
396                         ioremap64(BAMBOO_RTC_ADDR, BAMBOO_RTC_SIZE),
397                         8);
398
399         /* init to some ~sane value until calibrate_delay() runs */
400         loops_per_jiffy = 50000000/HZ;
401
402         /* Setup PCI host bridge */
403         bamboo_setup_hose();
404
405 #ifdef CONFIG_BLK_DEV_INITRD
406         if (initrd_start)
407                 ROOT_DEV = Root_RAM0;
408         else
409 #endif
410 #ifdef CONFIG_ROOT_NFS
411                 ROOT_DEV = Root_NFS;
412 #else
413                 ROOT_DEV = Root_HDA1;
414 #endif
415
416         bamboo_early_serial_map();
417
418         /* Identify the system */
419         printk("IBM Bamboo port (MontaVista Software, Inc. (source@mvista.com))\n");
420 }
421
422 void __init platform_init(unsigned long r3, unsigned long r4,
423                 unsigned long r5, unsigned long r6, unsigned long r7)
424 {
425         ibm44x_platform_init(r3, r4, r5, r6, r7);
426
427         ppc_md.setup_arch = bamboo_setup_arch;
428         ppc_md.show_cpuinfo = bamboo_show_cpuinfo;
429         ppc_md.get_irq = NULL;          /* Set in ppc4xx_pic_init() */
430
431         ppc_md.calibrate_decr = bamboo_calibrate_decr;
432         ppc_md.time_init = todc_time_init;
433         ppc_md.set_rtc_time = todc_set_rtc_time;
434         ppc_md.get_rtc_time = todc_get_rtc_time;
435
436         ppc_md.nvram_read_val = todc_direct_read_val;
437         ppc_md.nvram_write_val = todc_direct_write_val;
438 #ifdef CONFIG_KGDB
439         ppc_md.early_serial_map = bamboo_early_serial_map;
440 #endif
441 }
442