Merge master.kernel.org:/home/rmk/linux-2.6-i2c manually
[linux-2.6] / arch / arm / plat-omap / mux.c
1 /*
2  * linux/arch/arm/plat-omap/mux.c
3  *
4  * Utility to set the Omap MUX and PULL_DWN registers from a table in mux.h
5  *
6  * Copyright (C) 2003 Nokia Corporation
7  *
8  * Written by Tony Lindgren <tony.lindgren@nokia.com>
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License, or
13  * (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23  *
24  */
25 #include <linux/config.h>
26 #include <linux/module.h>
27 #include <linux/init.h>
28 #include <asm/system.h>
29 #include <asm/io.h>
30 #include <linux/spinlock.h>
31
32 #define __MUX_C__
33 #include <asm/arch/mux.h>
34
35 #ifdef CONFIG_OMAP_MUX
36
37 /*
38  * Sets the Omap MUX and PULL_DWN registers based on the table
39  */
40 int __init_or_module
41 omap_cfg_reg(const reg_cfg_t reg_cfg)
42 {
43         static DEFINE_SPINLOCK(mux_spin_lock);
44
45         unsigned long flags;
46         reg_cfg_set *cfg;
47         unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
48                 pull_orig = 0, pull = 0;
49         unsigned int mask, warn = 0;
50
51         if (cpu_is_omap7xx())
52                 return 0;
53
54         if (reg_cfg > ARRAY_SIZE(reg_cfg_table)) {
55                 printk(KERN_ERR "MUX: reg_cfg %d\n", reg_cfg);
56                 return -EINVAL;
57         }
58
59         cfg = (reg_cfg_set *)&reg_cfg_table[reg_cfg];
60
61         /* Check the mux register in question */
62         if (cfg->mux_reg) {
63                 unsigned        tmp1, tmp2;
64
65                 spin_lock_irqsave(&mux_spin_lock, flags);
66                 reg_orig = omap_readl(cfg->mux_reg);
67
68                 /* The mux registers always seem to be 3 bits long */
69                 mask = (0x7 << cfg->mask_offset);
70                 tmp1 = reg_orig & mask;
71                 reg = reg_orig & ~mask;
72
73                 tmp2 = (cfg->mask << cfg->mask_offset);
74                 reg |= tmp2;
75
76                 if (tmp1 != tmp2)
77                         warn = 1;
78
79                 omap_writel(reg, cfg->mux_reg);
80                 spin_unlock_irqrestore(&mux_spin_lock, flags);
81         }
82
83         /* Check for pull up or pull down selection on 1610 */
84         if (!cpu_is_omap1510()) {
85                 if (cfg->pu_pd_reg && cfg->pull_val) {
86                         spin_lock_irqsave(&mux_spin_lock, flags);
87                         pu_pd_orig = omap_readl(cfg->pu_pd_reg);
88                         mask = 1 << cfg->pull_bit;
89
90                         if (cfg->pu_pd_val) {
91                                 if (!(pu_pd_orig & mask))
92                                         warn = 1;
93                                 /* Use pull up */
94                                 pu_pd = pu_pd_orig | mask;
95                         } else {
96                                 if (pu_pd_orig & mask)
97                                         warn = 1;
98                                 /* Use pull down */
99                                 pu_pd = pu_pd_orig & ~mask;
100                         }
101                         omap_writel(pu_pd, cfg->pu_pd_reg);
102                         spin_unlock_irqrestore(&mux_spin_lock, flags);
103                 }
104         }
105
106         /* Check for an associated pull down register */
107         if (cfg->pull_reg) {
108                 spin_lock_irqsave(&mux_spin_lock, flags);
109                 pull_orig = omap_readl(cfg->pull_reg);
110                 mask = 1 << cfg->pull_bit;
111
112                 if (cfg->pull_val) {
113                         if (pull_orig & mask)
114                                 warn = 1;
115                         /* Low bit = pull enabled */
116                         pull = pull_orig & ~mask;
117                 } else {
118                         if (!(pull_orig & mask))
119                                 warn = 1;
120                         /* High bit = pull disabled */
121                         pull = pull_orig | mask;
122                 }
123
124                 omap_writel(pull, cfg->pull_reg);
125                 spin_unlock_irqrestore(&mux_spin_lock, flags);
126         }
127
128         if (warn) {
129 #ifdef CONFIG_OMAP_MUX_WARNINGS
130                 printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
131 #endif
132         }
133
134 #ifdef CONFIG_OMAP_MUX_DEBUG
135         if (cfg->debug || warn) {
136                 printk("MUX: Setting register %s\n", cfg->name);
137                 printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
138                        cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
139
140                 if (!cpu_is_omap1510()) {
141                         if (cfg->pu_pd_reg && cfg->pull_val) {
142                                 printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
143                                        cfg->pu_pd_name, cfg->pu_pd_reg,
144                                        pu_pd_orig, pu_pd);
145                         }
146                 }
147
148                 if (cfg->pull_reg)
149                         printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
150                                cfg->pull_name, cfg->pull_reg, pull_orig, pull);
151         }
152 #endif
153
154 #ifdef CONFIG_OMAP_MUX_ERRORS
155         return warn ? -ETXTBSY : 0;
156 #else
157         return 0;
158 #endif
159 }
160
161 EXPORT_SYMBOL(omap_cfg_reg);
162
163 #endif  /* CONFIG_OMAP_MUX */