2 * pdc_adma.c - Pacific Digital Corporation ADMA
4 * Maintained by: Mark Lord <mlord@pobox.com>
6 * Copyright 2005 Mark Lord
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
27 * Supports ATA disks in single-packet ADMA mode.
28 * Uses PIO for everything else.
30 * TODO: Use ADMA transfers for ATAPI devices, when possible.
31 * This requires careful attention to a number of quirks of the chip.
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/device.h>
43 #include <scsi/scsi_host.h>
44 #include <linux/libata.h>
46 #define DRV_NAME "pdc_adma"
47 #define DRV_VERSION "1.0"
49 /* macro to calculate base address for ATA regs */
50 #define ADMA_ATA_REGS(base, port_no) ((base) + ((port_no) * 0x40))
52 /* macro to calculate base address for ADMA regs */
53 #define ADMA_REGS(base, port_no) ((base) + 0x80 + ((port_no) * 0x20))
55 /* macro to obtain addresses from ata_port */
56 #define ADMA_PORT_REGS(ap) \
57 ADMA_REGS((ap)->host->iomap[ADMA_MMIO_BAR], ap->port_no)
64 ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16,
65 ADMA_PKT_BYTES = ADMA_CPB_BYTES + ADMA_PRD_BYTES,
67 ADMA_DMA_BOUNDARY = 0xffffffff,
69 /* global register offsets */
70 ADMA_MODE_LOCK = 0x00c7,
72 /* per-channel register offsets */
73 ADMA_CONTROL = 0x0000, /* ADMA control */
74 ADMA_STATUS = 0x0002, /* ADMA status */
75 ADMA_CPB_COUNT = 0x0004, /* CPB count */
76 ADMA_CPB_CURRENT = 0x000c, /* current CPB address */
77 ADMA_CPB_NEXT = 0x000c, /* next CPB address */
78 ADMA_CPB_LOOKUP = 0x0010, /* CPB lookup table */
79 ADMA_FIFO_IN = 0x0014, /* input FIFO threshold */
80 ADMA_FIFO_OUT = 0x0016, /* output FIFO threshold */
82 /* ADMA_CONTROL register bits */
83 aNIEN = (1 << 8), /* irq mask: 1==masked */
84 aGO = (1 << 7), /* packet trigger ("Go!") */
85 aRSTADM = (1 << 5), /* ADMA logic reset */
86 aPIOMD4 = 0x0003, /* PIO mode 4 */
88 /* ADMA_STATUS register bits */
106 /* ATA register flags */
110 /* ATA register addresses */
111 ADMA_REGS_CONTROL = 0x0e,
112 ADMA_REGS_SECTOR_COUNT = 0x12,
113 ADMA_REGS_LBA_LOW = 0x13,
114 ADMA_REGS_LBA_MID = 0x14,
115 ADMA_REGS_LBA_HIGH = 0x15,
116 ADMA_REGS_DEVICE = 0x16,
117 ADMA_REGS_COMMAND = 0x17,
120 board_1841_idx = 0, /* ADMA 2-port controller */
123 typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t;
125 struct adma_port_priv {
131 static int adma_ata_init_one(struct pci_dev *pdev,
132 const struct pci_device_id *ent);
133 static int adma_port_start(struct ata_port *ap);
134 static void adma_host_stop(struct ata_host *host);
135 static void adma_port_stop(struct ata_port *ap);
136 static void adma_qc_prep(struct ata_queued_cmd *qc);
137 static unsigned int adma_qc_issue(struct ata_queued_cmd *qc);
138 static int adma_check_atapi_dma(struct ata_queued_cmd *qc);
139 static void adma_bmdma_stop(struct ata_queued_cmd *qc);
140 static u8 adma_bmdma_status(struct ata_port *ap);
141 static void adma_freeze(struct ata_port *ap);
142 static void adma_thaw(struct ata_port *ap);
143 static int adma_prereset(struct ata_link *link, unsigned long deadline);
145 static struct scsi_host_template adma_ata_sht = {
146 ATA_BASE_SHT(DRV_NAME),
147 .sg_tablesize = LIBATA_MAX_PRD,
148 .dma_boundary = ADMA_DMA_BOUNDARY,
151 static struct ata_port_operations adma_ata_ops = {
152 .inherits = &ata_base_port_ops,
154 .dev_select = ata_std_dev_select,
155 .tf_load = ata_tf_load,
156 .tf_read = ata_tf_read,
157 .check_status = ata_check_status,
158 .exec_command = ata_exec_command,
159 .data_xfer = ata_data_xfer,
160 .check_atapi_dma = adma_check_atapi_dma,
161 .bmdma_stop = adma_bmdma_stop,
162 .bmdma_status = adma_bmdma_status,
163 .qc_prep = adma_qc_prep,
164 .qc_issue = adma_qc_issue,
165 .irq_on = ata_irq_on,
167 .freeze = adma_freeze,
169 .prereset = adma_prereset,
170 .softreset = ata_std_softreset,
172 .port_start = adma_port_start,
173 .port_stop = adma_port_stop,
174 .host_stop = adma_host_stop,
177 static struct ata_port_info adma_port_info[] = {
180 .flags = ATA_FLAG_SLAVE_POSS |
181 ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO |
182 ATA_FLAG_PIO_POLLING,
183 .pio_mask = 0x10, /* pio4 */
184 .udma_mask = ATA_UDMA4,
185 .port_ops = &adma_ata_ops,
189 static const struct pci_device_id adma_ata_pci_tbl[] = {
190 { PCI_VDEVICE(PDC, 0x1841), board_1841_idx },
192 { } /* terminate list */
195 static struct pci_driver adma_ata_pci_driver = {
197 .id_table = adma_ata_pci_tbl,
198 .probe = adma_ata_init_one,
199 .remove = ata_pci_remove_one,
202 static int adma_check_atapi_dma(struct ata_queued_cmd *qc)
204 return 1; /* ATAPI DMA not yet supported */
207 static void adma_bmdma_stop(struct ata_queued_cmd *qc)
212 static u8 adma_bmdma_status(struct ata_port *ap)
217 static void adma_reset_engine(struct ata_port *ap)
219 void __iomem *chan = ADMA_PORT_REGS(ap);
221 /* reset ADMA to idle state */
222 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
224 writew(aPIOMD4, chan + ADMA_CONTROL);
228 static void adma_reinit_engine(struct ata_port *ap)
230 struct adma_port_priv *pp = ap->private_data;
231 void __iomem *chan = ADMA_PORT_REGS(ap);
233 /* mask/clear ATA interrupts */
234 writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
235 ata_check_status(ap);
237 /* reset the ADMA engine */
238 adma_reset_engine(ap);
240 /* set in-FIFO threshold to 0x100 */
241 writew(0x100, chan + ADMA_FIFO_IN);
243 /* set CPB pointer */
244 writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT);
246 /* set out-FIFO threshold to 0x100 */
247 writew(0x100, chan + ADMA_FIFO_OUT);
250 writew(1, chan + ADMA_CPB_COUNT);
252 /* read/discard ADMA status */
253 readb(chan + ADMA_STATUS);
256 static inline void adma_enter_reg_mode(struct ata_port *ap)
258 void __iomem *chan = ADMA_PORT_REGS(ap);
260 writew(aPIOMD4, chan + ADMA_CONTROL);
261 readb(chan + ADMA_STATUS); /* flush */
264 static void adma_freeze(struct ata_port *ap)
266 void __iomem *chan = ADMA_PORT_REGS(ap);
268 /* mask/clear ATA interrupts */
269 writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
270 ata_check_status(ap);
272 /* reset ADMA to idle state */
273 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
275 writew(aPIOMD4 | aNIEN, chan + ADMA_CONTROL);
279 static void adma_thaw(struct ata_port *ap)
281 adma_reinit_engine(ap);
284 static int adma_prereset(struct ata_link *link, unsigned long deadline)
286 struct ata_port *ap = link->ap;
287 struct adma_port_priv *pp = ap->private_data;
289 if (pp->state != adma_state_idle) /* healthy paranoia */
290 pp->state = adma_state_mmio;
291 adma_reinit_engine(ap);
293 return ata_std_prereset(link, deadline);
296 static int adma_fill_sg(struct ata_queued_cmd *qc)
298 struct scatterlist *sg;
299 struct ata_port *ap = qc->ap;
300 struct adma_port_priv *pp = ap->private_data;
301 u8 *buf = pp->pkt, *last_buf = NULL;
302 int i = (2 + buf[3]) * 8;
303 u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0);
306 for_each_sg(qc->sg, sg, qc->n_elem, si) {
310 addr = (u32)sg_dma_address(sg);
311 *(__le32 *)(buf + i) = cpu_to_le32(addr);
314 len = sg_dma_len(sg) >> 3;
315 *(__le32 *)(buf + i) = cpu_to_le32(len);
320 buf[i++] = qc->dev->dma_mode & 0xf;
321 buf[i++] = 0; /* pPKLW */
322 buf[i++] = 0; /* reserved */
324 *(__le32 *)(buf + i) =
325 (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
328 VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4,
329 (unsigned long)addr, len);
332 if (likely(last_buf))
338 static void adma_qc_prep(struct ata_queued_cmd *qc)
340 struct adma_port_priv *pp = qc->ap->private_data;
342 u32 pkt_dma = (u32)pp->pkt_dma;
347 adma_enter_reg_mode(qc->ap);
348 if (qc->tf.protocol != ATA_PROT_DMA) {
353 buf[i++] = 0; /* Response flags */
354 buf[i++] = 0; /* reserved */
355 buf[i++] = cVLD | cDAT | cIEN;
356 i++; /* cLEN, gets filled in below */
358 *(__le32 *)(buf+i) = cpu_to_le32(pkt_dma); /* cNCPB */
360 i += 4; /* cPRD, gets filled in below */
362 buf[i++] = 0; /* reserved */
363 buf[i++] = 0; /* reserved */
364 buf[i++] = 0; /* reserved */
365 buf[i++] = 0; /* reserved */
367 /* ATA registers; must be a multiple of 4 */
368 buf[i++] = qc->tf.device;
369 buf[i++] = ADMA_REGS_DEVICE;
370 if ((qc->tf.flags & ATA_TFLAG_LBA48)) {
371 buf[i++] = qc->tf.hob_nsect;
372 buf[i++] = ADMA_REGS_SECTOR_COUNT;
373 buf[i++] = qc->tf.hob_lbal;
374 buf[i++] = ADMA_REGS_LBA_LOW;
375 buf[i++] = qc->tf.hob_lbam;
376 buf[i++] = ADMA_REGS_LBA_MID;
377 buf[i++] = qc->tf.hob_lbah;
378 buf[i++] = ADMA_REGS_LBA_HIGH;
380 buf[i++] = qc->tf.nsect;
381 buf[i++] = ADMA_REGS_SECTOR_COUNT;
382 buf[i++] = qc->tf.lbal;
383 buf[i++] = ADMA_REGS_LBA_LOW;
384 buf[i++] = qc->tf.lbam;
385 buf[i++] = ADMA_REGS_LBA_MID;
386 buf[i++] = qc->tf.lbah;
387 buf[i++] = ADMA_REGS_LBA_HIGH;
389 buf[i++] = ADMA_REGS_CONTROL;
392 buf[i++] = qc->tf.command;
393 buf[i++] = ADMA_REGS_COMMAND | rEND;
395 buf[3] = (i >> 3) - 2; /* cLEN */
396 *(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i); /* cPRD */
398 i = adma_fill_sg(qc);
399 wmb(); /* flush PRDs and pkt to memory */
401 /* dump out CPB + PRDs for debug */
404 static char obuf[2048];
405 for (j = 0; j < i; ++j) {
406 len += sprintf(obuf+len, "%02x ", buf[j]);
408 printk("%s\n", obuf);
413 printk("%s\n", obuf);
418 static inline void adma_packet_start(struct ata_queued_cmd *qc)
420 struct ata_port *ap = qc->ap;
421 void __iomem *chan = ADMA_PORT_REGS(ap);
423 VPRINTK("ENTER, ap %p\n", ap);
425 /* fire up the ADMA engine */
426 writew(aPIOMD4 | aGO, chan + ADMA_CONTROL);
429 static unsigned int adma_qc_issue(struct ata_queued_cmd *qc)
431 struct adma_port_priv *pp = qc->ap->private_data;
433 switch (qc->tf.protocol) {
435 pp->state = adma_state_pkt;
436 adma_packet_start(qc);
447 pp->state = adma_state_mmio;
448 return ata_qc_issue_prot(qc);
451 static inline unsigned int adma_intr_pkt(struct ata_host *host)
453 unsigned int handled = 0, port_no;
455 for (port_no = 0; port_no < host->n_ports; ++port_no) {
456 struct ata_port *ap = host->ports[port_no];
457 struct adma_port_priv *pp;
458 struct ata_queued_cmd *qc;
459 void __iomem *chan = ADMA_PORT_REGS(ap);
460 u8 status = readb(chan + ADMA_STATUS);
465 adma_enter_reg_mode(ap);
466 if (ap->flags & ATA_FLAG_DISABLED)
468 pp = ap->private_data;
469 if (!pp || pp->state != adma_state_pkt)
471 qc = ata_qc_from_tag(ap, ap->link.active_tag);
472 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
474 qc->err_mask |= AC_ERR_HOST_BUS;
475 else if ((status & (aPSD | aUIRQ)))
476 qc->err_mask |= AC_ERR_OTHER;
478 if (pp->pkt[0] & cATERR)
479 qc->err_mask |= AC_ERR_DEV;
480 else if (pp->pkt[0] != cDONE)
481 qc->err_mask |= AC_ERR_OTHER;
486 struct ata_eh_info *ehi = &ap->link.eh_info;
487 ata_ehi_clear_desc(ehi);
488 ata_ehi_push_desc(ehi,
489 "ADMA-status 0x%02X", status);
490 ata_ehi_push_desc(ehi,
491 "pkt[0] 0x%02X", pp->pkt[0]);
493 if (qc->err_mask == AC_ERR_DEV)
503 static inline unsigned int adma_intr_mmio(struct ata_host *host)
505 unsigned int handled = 0, port_no;
507 for (port_no = 0; port_no < host->n_ports; ++port_no) {
509 ap = host->ports[port_no];
510 if (ap && (!(ap->flags & ATA_FLAG_DISABLED))) {
511 struct ata_queued_cmd *qc;
512 struct adma_port_priv *pp = ap->private_data;
513 if (!pp || pp->state != adma_state_mmio)
515 qc = ata_qc_from_tag(ap, ap->link.active_tag);
516 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
518 /* check main status, clearing INTRQ */
519 u8 status = ata_check_status(ap);
520 if ((status & ATA_BUSY))
522 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
523 ap->print_id, qc->tf.protocol, status);
525 /* complete taskfile transaction */
526 pp->state = adma_state_idle;
527 qc->err_mask |= ac_err_mask(status);
531 struct ata_eh_info *ehi =
533 ata_ehi_clear_desc(ehi);
534 ata_ehi_push_desc(ehi,
535 "status 0x%02X", status);
537 if (qc->err_mask == AC_ERR_DEV)
549 static irqreturn_t adma_intr(int irq, void *dev_instance)
551 struct ata_host *host = dev_instance;
552 unsigned int handled = 0;
556 spin_lock(&host->lock);
557 handled = adma_intr_pkt(host) | adma_intr_mmio(host);
558 spin_unlock(&host->lock);
562 return IRQ_RETVAL(handled);
565 static void adma_ata_setup_port(struct ata_ioports *port, void __iomem *base)
568 port->data_addr = base + 0x000;
570 port->feature_addr = base + 0x004;
571 port->nsect_addr = base + 0x008;
572 port->lbal_addr = base + 0x00c;
573 port->lbam_addr = base + 0x010;
574 port->lbah_addr = base + 0x014;
575 port->device_addr = base + 0x018;
577 port->command_addr = base + 0x01c;
578 port->altstatus_addr =
579 port->ctl_addr = base + 0x038;
582 static int adma_port_start(struct ata_port *ap)
584 struct device *dev = ap->host->dev;
585 struct adma_port_priv *pp;
588 rc = ata_port_start(ap);
591 adma_enter_reg_mode(ap);
592 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
595 pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma,
600 if ((pp->pkt_dma & 7) != 0) {
601 printk(KERN_ERR "bad alignment for pp->pkt_dma: %08x\n",
605 memset(pp->pkt, 0, ADMA_PKT_BYTES);
606 ap->private_data = pp;
607 adma_reinit_engine(ap);
611 static void adma_port_stop(struct ata_port *ap)
613 adma_reset_engine(ap);
616 static void adma_host_stop(struct ata_host *host)
618 unsigned int port_no;
620 for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
621 adma_reset_engine(host->ports[port_no]);
624 static void adma_host_init(struct ata_host *host, unsigned int chip_id)
626 unsigned int port_no;
628 /* enable/lock aGO operation */
629 writeb(7, host->iomap[ADMA_MMIO_BAR] + ADMA_MODE_LOCK);
631 /* reset the ADMA logic */
632 for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
633 adma_reset_engine(host->ports[port_no]);
636 static int adma_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
640 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
642 dev_printk(KERN_ERR, &pdev->dev,
643 "32-bit DMA enable failed\n");
646 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
648 dev_printk(KERN_ERR, &pdev->dev,
649 "32-bit consistent DMA enable failed\n");
655 static int adma_ata_init_one(struct pci_dev *pdev,
656 const struct pci_device_id *ent)
658 static int printed_version;
659 unsigned int board_idx = (unsigned int) ent->driver_data;
660 const struct ata_port_info *ppi[] = { &adma_port_info[board_idx], NULL };
661 struct ata_host *host;
662 void __iomem *mmio_base;
665 if (!printed_version++)
666 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
669 host = ata_host_alloc_pinfo(&pdev->dev, ppi, ADMA_PORTS);
673 /* acquire resources and fill host */
674 rc = pcim_enable_device(pdev);
678 if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0)
681 rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME);
684 host->iomap = pcim_iomap_table(pdev);
685 mmio_base = host->iomap[ADMA_MMIO_BAR];
687 rc = adma_set_dma_masks(pdev, mmio_base);
691 for (port_no = 0; port_no < ADMA_PORTS; ++port_no) {
692 struct ata_port *ap = host->ports[port_no];
693 void __iomem *port_base = ADMA_ATA_REGS(mmio_base, port_no);
694 unsigned int offset = port_base - mmio_base;
696 adma_ata_setup_port(&ap->ioaddr, port_base);
698 ata_port_pbar_desc(ap, ADMA_MMIO_BAR, -1, "mmio");
699 ata_port_pbar_desc(ap, ADMA_MMIO_BAR, offset, "port");
702 /* initialize adapter */
703 adma_host_init(host, board_idx);
705 pci_set_master(pdev);
706 return ata_host_activate(host, pdev->irq, adma_intr, IRQF_SHARED,
710 static int __init adma_ata_init(void)
712 return pci_register_driver(&adma_ata_pci_driver);
715 static void __exit adma_ata_exit(void)
717 pci_unregister_driver(&adma_ata_pci_driver);
720 MODULE_AUTHOR("Mark Lord");
721 MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
722 MODULE_LICENSE("GPL");
723 MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl);
724 MODULE_VERSION(DRV_VERSION);
726 module_init(adma_ata_init);
727 module_exit(adma_ata_exit);