4 * Prints processor specific information reported by PAL.
5 * This code is based on specification of PAL as of the
6 * Intel IA-64 Architecture Software Developer's Manual v1.0.
9 * Copyright (C) 2000-2001, 2003 Hewlett-Packard Co
10 * Stephane Eranian <eranian@hpl.hp.com>
11 * Copyright (C) 2004 Intel Corporation
12 * Ashok Raj <ashok.raj@intel.com>
14 * 05/26/2000 S.Eranian initial release
15 * 08/21/2000 S.Eranian updated to July 2000 PAL specs
16 * 02/05/2001 S.Eranian fixed module support
17 * 10/23/2001 S.Eranian updated pal_perf_mon_info bug fixes
18 * 03/24/2004 Ashok Raj updated to work with CPU Hotplug
20 #include <linux/config.h>
21 #include <linux/types.h>
22 #include <linux/errno.h>
23 #include <linux/init.h>
24 #include <linux/proc_fs.h>
26 #include <linux/module.h>
27 #include <linux/efi.h>
28 #include <linux/notifier.h>
29 #include <linux/cpu.h>
30 #include <linux/cpumask.h>
35 #include <asm/processor.h>
36 #include <linux/smp.h>
38 MODULE_AUTHOR("Stephane Eranian <eranian@hpl.hp.com>");
39 MODULE_DESCRIPTION("/proc interface to IA-64 PAL");
40 MODULE_LICENSE("GPL");
42 #define PALINFO_VERSION "0.5"
44 typedef int (*palinfo_func_t)(char*);
47 const char *name; /* name of the proc entry */
48 palinfo_func_t proc_read; /* function to call for reading */
49 struct proc_dir_entry *entry; /* registered entry (removal) */
54 * A bunch of string array to get pretty printing
57 static char *cache_types[] = {
61 "Data/Instruction" /* unified */
64 static const char *cache_mattrib[]={
71 static const char *cache_st_hints[]={
75 "Non-temporal, all levels",
82 static const char *cache_ld_hints[]={
84 "Non-temporal, level 1",
86 "Non-temporal, all levels",
93 static const char *rse_hints[]={
97 "eager loads and stores"
100 #define RSE_HINTS_COUNT ARRAY_SIZE(rse_hints)
102 static const char *mem_attrib[]={
114 * Take a 64bit vector and produces a string such that
115 * if bit n is set then 2^n in clear text is generated. The adjustment
116 * to the right unit is also done.
119 * - a pointer to a buffer to hold the string
122 * - a pointer to the end of the buffer
126 bitvector_process(char *p, u64 vector)
129 const char *units[]={ "", "K", "M", "G", "T" };
131 for (i=0, j=0; i < 64; i++ , j=i/10) {
133 p += sprintf(p, "%d%s ", 1 << (i-j*10), units[j]);
141 * Take a 64bit vector and produces a string such that
142 * if bit n is set then register n is present. The function
143 * takes into account consecutive registers and prints out ranges.
146 * - a pointer to a buffer to hold the string
149 * - a pointer to the end of the buffer
153 bitregister_process(char *p, u64 *reg_info, int max)
155 int i, begin, skip = 0;
156 u64 value = reg_info[0];
158 value >>= i = begin = ffs(value) - 1;
160 for(; i < max; i++ ) {
162 if (i != 0 && (i%64) == 0) value = *++reg_info;
164 if ((value & 0x1) == 0 && skip == 0) {
166 p += sprintf(p, "%d-%d ", begin, i-1);
168 p += sprintf(p, "%d ", i-1);
171 } else if ((value & 0x1) && skip == 1) {
179 p += sprintf(p, "%d-127", begin);
181 p += sprintf(p, "127");
188 power_info(char *page)
192 u64 halt_info_buffer[8];
193 pal_power_mgmt_info_u_t *halt_info =(pal_power_mgmt_info_u_t *)halt_info_buffer;
196 status = ia64_pal_halt_info(halt_info);
197 if (status != 0) return 0;
199 for (i=0; i < 8 ; i++ ) {
200 if (halt_info[i].pal_power_mgmt_info_s.im == 1) {
201 p += sprintf(p, "Power level %d:\n"
202 "\tentry_latency : %d cycles\n"
203 "\texit_latency : %d cycles\n"
204 "\tpower consumption : %d mW\n"
205 "\tCache+TLB coherency : %s\n", i,
206 halt_info[i].pal_power_mgmt_info_s.entry_latency,
207 halt_info[i].pal_power_mgmt_info_s.exit_latency,
208 halt_info[i].pal_power_mgmt_info_s.power_consumption,
209 halt_info[i].pal_power_mgmt_info_s.co ? "Yes" : "No");
211 p += sprintf(p,"Power level %d: not implemented\n",i);
218 cache_info(char *page)
221 u64 i, levels, unique_caches;
222 pal_cache_config_info_t cci;
226 if ((status = ia64_pal_cache_summary(&levels, &unique_caches)) != 0) {
227 printk(KERN_ERR "ia64_pal_cache_summary=%ld\n", status);
231 p += sprintf(p, "Cache levels : %ld\nUnique caches : %ld\n\n", levels, unique_caches);
233 for (i=0; i < levels; i++) {
235 for (j=2; j >0 ; j--) {
237 /* even without unification some level may not be present */
238 if ((status=ia64_pal_cache_config_info(i,j, &cci)) != 0) {
242 "%s Cache level %lu:\n"
243 "\tSize : %lu bytes\n"
245 cache_types[j+cci.pcci_unified], i+1,
246 cci.pcci_cache_size);
248 if (cci.pcci_unified) p += sprintf(p, "Unified ");
250 p += sprintf(p, "%s\n", cache_mattrib[cci.pcci_cache_attr]);
253 "\tAssociativity : %d\n"
254 "\tLine size : %d bytes\n"
255 "\tStride : %d bytes\n",
256 cci.pcci_assoc, 1<<cci.pcci_line_size, 1<<cci.pcci_stride);
258 p += sprintf(p, "\tStore latency : N/A\n");
260 p += sprintf(p, "\tStore latency : %d cycle(s)\n",
261 cci.pcci_st_latency);
264 "\tLoad latency : %d cycle(s)\n"
265 "\tStore hints : ", cci.pcci_ld_latency);
267 for(k=0; k < 8; k++ ) {
268 if ( cci.pcci_st_hints & 0x1)
269 p += sprintf(p, "[%s]", cache_st_hints[k]);
270 cci.pcci_st_hints >>=1;
272 p += sprintf(p, "\n\tLoad hints : ");
274 for(k=0; k < 8; k++ ) {
275 if (cci.pcci_ld_hints & 0x1)
276 p += sprintf(p, "[%s]", cache_ld_hints[k]);
277 cci.pcci_ld_hints >>=1;
280 "\n\tAlias boundary : %d byte(s)\n"
283 1<<cci.pcci_alias_boundary, cci.pcci_tag_lsb,
286 /* when unified, data(j=2) is enough */
287 if (cci.pcci_unified) break;
298 u64 tr_pages =0, vw_pages=0, tc_pages;
300 pal_vm_info_1_u_t vm_info_1;
301 pal_vm_info_2_u_t vm_info_2;
302 pal_tc_info_u_t tc_info;
303 ia64_ptce_info_t ptce;
308 if ((status = ia64_pal_vm_summary(&vm_info_1, &vm_info_2)) !=0) {
309 printk(KERN_ERR "ia64_pal_vm_summary=%ld\n", status);
313 "Physical Address Space : %d bits\n"
314 "Virtual Address Space : %d bits\n"
315 "Protection Key Registers(PKR) : %d\n"
316 "Implemented bits in PKR.key : %d\n"
317 "Hash Tag ID : 0x%x\n"
318 "Size of RR.rid : %d\n",
319 vm_info_1.pal_vm_info_1_s.phys_add_size,
320 vm_info_2.pal_vm_info_2_s.impl_va_msb+1,
321 vm_info_1.pal_vm_info_1_s.max_pkr+1,
322 vm_info_1.pal_vm_info_1_s.key_size,
323 vm_info_1.pal_vm_info_1_s.hash_tag_id,
324 vm_info_2.pal_vm_info_2_s.rid_size);
327 if (ia64_pal_mem_attrib(&attrib) == 0) {
328 p += sprintf(p, "Supported memory attributes : ");
330 for (i = 0; i < 8; i++) {
331 if (attrib & (1 << i)) {
332 p += sprintf(p, "%s%s", sep, mem_attrib[i]);
336 p += sprintf(p, "\n");
339 if ((status = ia64_pal_vm_page_size(&tr_pages, &vw_pages)) !=0) {
340 printk(KERN_ERR "ia64_pal_vm_page_size=%ld\n", status);
344 "\nTLB walker : %simplemented\n"
345 "Number of DTR : %d\n"
346 "Number of ITR : %d\n"
347 "TLB insertable page sizes : ",
348 vm_info_1.pal_vm_info_1_s.vw ? "" : "not ",
349 vm_info_1.pal_vm_info_1_s.max_dtr_entry+1,
350 vm_info_1.pal_vm_info_1_s.max_itr_entry+1);
353 p = bitvector_process(p, tr_pages);
355 p += sprintf(p, "\nTLB purgeable page sizes : ");
357 p = bitvector_process(p, vw_pages);
359 if ((status=ia64_get_ptce(&ptce)) != 0) {
360 printk(KERN_ERR "ia64_get_ptce=%ld\n", status);
363 "\nPurge base address : 0x%016lx\n"
364 "Purge outer loop count : %d\n"
365 "Purge inner loop count : %d\n"
366 "Purge outer loop stride : %d\n"
367 "Purge inner loop stride : %d\n",
368 ptce.base, ptce.count[0], ptce.count[1],
369 ptce.stride[0], ptce.stride[1]);
373 "Unique TC(s) : %d\n",
374 vm_info_1.pal_vm_info_1_s.num_tc_levels,
375 vm_info_1.pal_vm_info_1_s.max_unique_tcs);
377 for(i=0; i < vm_info_1.pal_vm_info_1_s.num_tc_levels; i++) {
378 for (j=2; j>0 ; j--) {
379 tc_pages = 0; /* just in case */
382 /* even without unification, some levels may not be present */
383 if ((status=ia64_pal_vm_info(i,j, &tc_info, &tc_pages)) != 0) {
388 "\n%s Translation Cache Level %d:\n"
390 "\tAssociativity : %d\n"
391 "\tNumber of entries : %d\n"
393 cache_types[j+tc_info.tc_unified], i+1,
395 tc_info.tc_associativity,
396 tc_info.tc_num_entries);
399 p += sprintf(p, "PreferredPageSizeOptimized ");
400 if (tc_info.tc_unified)
401 p += sprintf(p, "Unified ");
402 if (tc_info.tc_reduce_tr)
403 p += sprintf(p, "TCReduction");
405 p += sprintf(p, "\n\tSupported page sizes: ");
407 p = bitvector_process(p, tc_pages);
409 /* when unified date (j=2) is enough */
410 if (tc_info.tc_unified)
415 p += sprintf(p, "\n");
422 register_info(char *page)
432 "AR(s) with read side-effects",
434 "CR(s) with read side-effects",
437 for(info=0; info < 4; info++) {
439 if (ia64_pal_register_info(info, ®_info[0], ®_info[1]) != 0) return 0;
441 p += sprintf(p, "%-32s : ", info_type[info]);
443 p = bitregister_process(p, reg_info, 128);
445 p += sprintf(p, "\n");
448 if (ia64_pal_rse_info(&phys_stacked, &hints) == 0) {
451 "RSE stacked physical registers : %ld\n"
452 "RSE load/store hints : %ld (%s)\n",
453 phys_stacked, hints.ph_data,
454 hints.ph_data < RSE_HINTS_COUNT ? rse_hints[hints.ph_data]: "(??)");
456 if (ia64_pal_debug_info(&iregs, &dregs))
460 "Instruction debug register pairs : %ld\n"
461 "Data debug register pairs : %ld\n", iregs, dregs);
466 static const char *proc_features[]={
467 NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,
468 NULL,NULL,NULL,NULL,NULL,NULL,NULL, NULL,NULL,
469 NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,
470 NULL,NULL,NULL,NULL,NULL, NULL,NULL,NULL,NULL,
471 NULL,NULL,NULL,NULL,NULL,
472 "XIP,XPSR,XFS implemented",
473 "XR1-XR3 implemented",
474 "Disable dynamic predicate prediction",
475 "Disable processor physical number",
476 "Disable dynamic data cache prefetch",
477 "Disable dynamic inst cache prefetch",
478 "Disable dynamic branch prediction",
479 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
480 "Disable BINIT on processor time-out",
481 "Disable dynamic power management (DPM)",
484 "Enable CMCI promotion",
485 "Enable MCA to BINIT promotion",
486 "Enable MCA promotion",
487 "Enable BERR promotion"
492 processor_info(char *page)
495 const char **v = proc_features;
496 u64 avail=1, status=1, control=1;
500 if ((ret=ia64_pal_proc_get_features(&avail, &status, &control)) != 0) return 0;
502 for(i=0; i < 64; i++, v++,avail >>=1, status >>=1, control >>=1) {
503 if ( ! *v ) continue;
504 p += sprintf(p, "%-40s : %s%s %s\n", *v,
505 avail & 0x1 ? "" : "NotImpl",
506 avail & 0x1 ? (status & 0x1 ? "On" : "Off"): "",
507 avail & 0x1 ? (control & 0x1 ? "Ctrl" : "NoCtrl"): "");
512 static const char *bus_features[]={
513 NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,
514 NULL,NULL,NULL,NULL,NULL,NULL,NULL, NULL,NULL,
515 NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,
517 "Request Bus Parking",
519 "Enable Half Transfer",
520 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
521 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
522 NULL, NULL, NULL, NULL,
523 "Enable Cache Line Repl. Shared",
524 "Enable Cache Line Repl. Exclusive",
525 "Disable Transaction Queuing",
526 "Disable Response Error Checking",
527 "Disable Bus Error Checking",
528 "Disable Bus Requester Internal Error Signalling",
529 "Disable Bus Requester Error Signalling",
530 "Disable Bus Initialization Event Checking",
531 "Disable Bus Initialization Event Signalling",
532 "Disable Bus Address Error Checking",
533 "Disable Bus Address Error Signalling",
534 "Disable Bus Data Error Checking"
542 const char **v = bus_features;
543 pal_bus_features_u_t av, st, ct;
544 u64 avail, status, control;
548 if ((ret=ia64_pal_bus_get_features(&av, &st, &ct)) != 0) return 0;
550 avail = av.pal_bus_features_val;
551 status = st.pal_bus_features_val;
552 control = ct.pal_bus_features_val;
554 for(i=0; i < 64; i++, v++, avail >>=1, status >>=1, control >>=1) {
555 if ( ! *v ) continue;
556 p += sprintf(p, "%-48s : %s%s %s\n", *v,
557 avail & 0x1 ? "" : "NotImpl",
558 avail & 0x1 ? (status & 0x1 ? "On" : "Off"): "",
559 avail & 0x1 ? (control & 0x1 ? "Ctrl" : "NoCtrl"): "");
565 version_info(char *page)
567 pal_version_u_t min_ver, cur_ver;
570 /* The PAL_VERSION call is advertised as being able to support
571 * both physical and virtual mode calls. This seems to be a documentation
572 * bug rather than firmware bug. In fact, it does only support physical mode.
573 * So now the code reflects this fact and the pal_version() has been updated
576 if (ia64_pal_version(&min_ver, &cur_ver) != 0) return 0;
579 "PAL_vendor : 0x%02x (min=0x%02x)\n"
580 "PAL_A : %x.%x.%x (min=%x.%x.%x)\n"
581 "PAL_B : %x.%x.%x (min=%x.%x.%x)\n",
582 cur_ver.pal_version_s.pv_pal_vendor, min_ver.pal_version_s.pv_pal_vendor,
584 cur_ver.pal_version_s.pv_pal_a_model>>4,
585 cur_ver.pal_version_s.pv_pal_a_model&0xf, cur_ver.pal_version_s.pv_pal_a_rev,
586 min_ver.pal_version_s.pv_pal_a_model>>4,
587 min_ver.pal_version_s.pv_pal_a_model&0xf, min_ver.pal_version_s.pv_pal_a_rev,
589 cur_ver.pal_version_s.pv_pal_b_model>>4,
590 cur_ver.pal_version_s.pv_pal_b_model&0xf, cur_ver.pal_version_s.pv_pal_b_rev,
591 min_ver.pal_version_s.pv_pal_b_model>>4,
592 min_ver.pal_version_s.pv_pal_b_model&0xf, min_ver.pal_version_s.pv_pal_b_rev);
597 perfmon_info(char *page)
601 pal_perf_mon_info_u_t pm_info;
603 if (ia64_pal_perf_mon_info(pm_buffer, &pm_info) != 0) return 0;
606 "PMC/PMD pairs : %d\n"
607 "Counter width : %d bits\n"
608 "Cycle event number : %d\n"
609 "Retired event number : %d\n"
610 "Implemented PMC : ",
611 pm_info.pal_perf_mon_info_s.generic, pm_info.pal_perf_mon_info_s.width,
612 pm_info.pal_perf_mon_info_s.cycles, pm_info.pal_perf_mon_info_s.retired);
614 p = bitregister_process(p, pm_buffer, 256);
615 p += sprintf(p, "\nImplemented PMD : ");
616 p = bitregister_process(p, pm_buffer+4, 256);
617 p += sprintf(p, "\nCycles count capable : ");
618 p = bitregister_process(p, pm_buffer+8, 256);
619 p += sprintf(p, "\nRetired bundles count capable : ");
621 #ifdef CONFIG_ITANIUM
623 * PAL_PERF_MON_INFO reports that only PMC4 can be used to count CPU_CYCLES
624 * which is wrong, both PMC4 and PMD5 support it.
626 if (pm_buffer[12] == 0x10) pm_buffer[12]=0x30;
629 p = bitregister_process(p, pm_buffer+12, 256);
631 p += sprintf(p, "\n");
637 frequency_info(char *page)
640 struct pal_freq_ratio proc, itc, bus;
643 if (ia64_pal_freq_base(&base) == -1)
644 p += sprintf(p, "Output clock : not implemented\n");
646 p += sprintf(p, "Output clock : %ld ticks/s\n", base);
648 if (ia64_pal_freq_ratios(&proc, &bus, &itc) != 0) return 0;
651 "Processor/Clock ratio : %ld/%ld\n"
652 "Bus/Clock ratio : %ld/%ld\n"
653 "ITC/Clock ratio : %ld/%ld\n",
654 proc.num, proc.den, bus.num, bus.den, itc.num, itc.den);
664 pal_tr_valid_u_t tr_valid;
666 pal_vm_info_1_u_t vm_info_1;
667 pal_vm_info_2_u_t vm_info_2;
702 if ((status = ia64_pal_vm_summary(&vm_info_1, &vm_info_2)) !=0) {
703 printk(KERN_ERR "ia64_pal_vm_summary=%ld\n", status);
706 max[0] = vm_info_1.pal_vm_info_1_s.max_itr_entry+1;
707 max[1] = vm_info_1.pal_vm_info_1_s.max_dtr_entry+1;
709 for (i=0; i < 2; i++ ) {
710 for (j=0; j < max[i]; j++) {
712 status = ia64_pal_tr_read(j, i, tr_buffer, &tr_valid);
714 printk(KERN_ERR "palinfo: pal call failed on tr[%lu:%lu]=%ld\n",
719 ifa_reg = (struct ifa_reg *)&tr_buffer[2];
721 if (ifa_reg->valid == 0) continue;
723 gr_reg = (struct gr_reg *)tr_buffer;
724 itir_reg = (struct itir_reg *)&tr_buffer[1];
725 rid_reg = (struct rid_reg *)&tr_buffer[3];
727 pgm = -1 << (itir_reg->ps - 12);
729 "%cTR%lu: av=%d pv=%d dv=%d mv=%d\n"
734 tr_valid.pal_tr_valid_s.access_rights_valid,
735 tr_valid.pal_tr_valid_s.priv_level_valid,
736 tr_valid.pal_tr_valid_s.dirty_bit_valid,
737 tr_valid.pal_tr_valid_s.mem_attr_valid,
738 (gr_reg->ppn & pgm)<< 12, (ifa_reg->vpn & pgm)<< 12);
740 p = bitvector_process(p, 1<< itir_reg->ps);
749 gr_reg->pl, gr_reg->ar, rid_reg->rid, gr_reg->p, gr_reg->ma,
759 * List {name,function} pairs for every entry in /proc/palinfo/cpu*
761 static palinfo_entry_t palinfo_entries[]={
762 { "version_info", version_info, },
763 { "vm_info", vm_info, },
764 { "cache_info", cache_info, },
765 { "power_info", power_info, },
766 { "register_info", register_info, },
767 { "processor_info", processor_info, },
768 { "perfmon_info", perfmon_info, },
769 { "frequency_info", frequency_info, },
770 { "bus_info", bus_info },
771 { "tr_info", tr_info, }
774 #define NR_PALINFO_ENTRIES (int) ARRAY_SIZE(palinfo_entries)
777 * this array is used to keep track of the proc entries we create. This is
778 * required in the module mode when we need to remove all entries. The procfs code
779 * does not do recursion of deletion
782 * - +1 accounts for the cpuN directory entry in /proc/pal
784 #define NR_PALINFO_PROC_ENTRIES (NR_CPUS*(NR_PALINFO_ENTRIES+1))
786 static struct proc_dir_entry *palinfo_proc_entries[NR_PALINFO_PROC_ENTRIES];
787 static struct proc_dir_entry *palinfo_dir;
790 * This data structure is used to pass which cpu,function is being requested
791 * It must fit in a 64bit quantity to be passed to the proc callback routine
793 * In SMP mode, when we get a request for another CPU, we must call that
794 * other CPU using IPI and wait for the result before returning.
799 unsigned req_cpu: 32; /* for which CPU this info is */
800 unsigned func_id: 32; /* which function is requested */
804 #define req_cpu pal_func_cpu.req_cpu
805 #define func_id pal_func_cpu.func_id
810 * used to hold information about final function to call
813 palinfo_func_t func; /* pointer to function to call */
814 char *page; /* buffer to store results */
815 int ret; /* return value from call */
816 } palinfo_smp_data_t;
820 * this function does the actual final call and he called
821 * from the smp code, i.e., this is the palinfo callback routine
824 palinfo_smp_call(void *info)
826 palinfo_smp_data_t *data = (palinfo_smp_data_t *)info;
828 printk(KERN_ERR "palinfo: data pointer is NULL\n");
829 data->ret = 0; /* no output */
832 /* does this actual call */
833 data->ret = (*data->func)(data->page);
837 * function called to trigger the IPI, we need to access a remote CPU
839 * 0 : error or nothing to output
840 * otherwise how many bytes in the "page" buffer were written
843 int palinfo_handle_smp(pal_func_cpu_u_t *f, char *page)
845 palinfo_smp_data_t ptr;
848 ptr.func = palinfo_entries[f->func_id].proc_read;
850 ptr.ret = 0; /* just in case */
853 /* will send IPI to other CPU and wait for completion of remote call */
854 if ((ret=smp_call_function_single(f->req_cpu, palinfo_smp_call, &ptr, 0, 1))) {
855 printk(KERN_ERR "palinfo: remote CPU call from %d to %d on function %d: "
856 "error %d\n", smp_processor_id(), f->req_cpu, f->func_id, ret);
861 #else /* ! CONFIG_SMP */
863 int palinfo_handle_smp(pal_func_cpu_u_t *f, char *page)
865 printk(KERN_ERR "palinfo: should not be called with non SMP kernel\n");
868 #endif /* CONFIG_SMP */
871 * Entry point routine: all calls go through this function
874 palinfo_read_entry(char *page, char **start, off_t off, int count, int *eof, void *data)
877 pal_func_cpu_u_t *f = (pal_func_cpu_u_t *)&data;
880 * in SMP mode, we may need to call another CPU to get correct
881 * information. PAL, by definition, is processor specific
883 if (f->req_cpu == get_cpu())
884 len = (*palinfo_entries[f->func_id].proc_read)(page);
886 len = palinfo_handle_smp(f, page);
890 if (len <= off+count) *eof = 1;
895 if (len>count) len = count;
902 create_palinfo_proc_entries(unsigned int cpu)
904 # define CPUSTR "cpu%d"
907 struct proc_dir_entry **pdir;
908 struct proc_dir_entry *cpu_dir;
910 char cpustr[sizeof(CPUSTR)];
914 * we keep track of created entries in a depth-first order for
915 * cleanup purposes. Each entry is stored into palinfo_proc_entries
917 sprintf(cpustr,CPUSTR, cpu);
919 cpu_dir = proc_mkdir(cpustr, palinfo_dir);
924 * Compute the location to store per cpu entries
925 * We dont store the top level entry in this list, but
926 * remove it finally after removing all cpu entries.
928 pdir = &palinfo_proc_entries[cpu*(NR_PALINFO_ENTRIES+1)];
930 for (j=0; j < NR_PALINFO_ENTRIES; j++) {
932 *pdir = create_proc_read_entry(
933 palinfo_entries[j].name, 0, cpu_dir,
934 palinfo_read_entry, (void *)f.value);
936 (*pdir)->owner = THIS_MODULE;
942 remove_palinfo_proc_entries(unsigned int hcpu)
945 struct proc_dir_entry *cpu_dir, **pdir;
947 pdir = &palinfo_proc_entries[hcpu*(NR_PALINFO_ENTRIES+1)];
950 for (j=0; j < (NR_PALINFO_ENTRIES); j++) {
952 remove_proc_entry ((*pdir)->name, cpu_dir);
958 remove_proc_entry(cpu_dir->name, palinfo_dir);
962 static int __devinit palinfo_cpu_callback(struct notifier_block *nfb,
963 unsigned long action,
966 unsigned int hotcpu = (unsigned long)hcpu;
970 create_palinfo_proc_entries(hotcpu);
972 #ifdef CONFIG_HOTPLUG_CPU
974 remove_palinfo_proc_entries(hotcpu);
981 static struct notifier_block palinfo_cpu_notifier =
983 .notifier_call = palinfo_cpu_callback,
992 printk(KERN_INFO "PAL Information Facility v%s\n", PALINFO_VERSION);
993 palinfo_dir = proc_mkdir("pal", NULL);
995 /* Create palinfo dirs in /proc for all online cpus */
996 for_each_online_cpu(i) {
997 create_palinfo_proc_entries(i);
1000 /* Register for future delivery via notify registration */
1001 register_cpu_notifier(&palinfo_cpu_notifier);
1011 /* remove all nodes: depth first pass. Could optimize this */
1012 for_each_online_cpu(i) {
1013 remove_palinfo_proc_entries(i);
1017 * Remove the top level entry finally
1019 remove_proc_entry(palinfo_dir->name, NULL);
1022 * Unregister from cpu notifier callbacks
1024 unregister_cpu_notifier(&palinfo_cpu_notifier);
1027 module_init(palinfo_init);
1028 module_exit(palinfo_exit);