Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6
[linux-2.6] / drivers / video / pxafb.c
1 /*
2  *  linux/drivers/video/pxafb.c
3  *
4  *  Copyright (C) 1999 Eric A. Thomas.
5  *  Copyright (C) 2004 Jean-Frederic Clere.
6  *  Copyright (C) 2004 Ian Campbell.
7  *  Copyright (C) 2004 Jeff Lackey.
8  *   Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
9  *  which in turn is
10  *   Based on acornfb.c Copyright (C) Russell King.
11  *
12  * This file is subject to the terms and conditions of the GNU General Public
13  * License.  See the file COPYING in the main directory of this archive for
14  * more details.
15  *
16  *              Intel PXA250/210 LCD Controller Frame Buffer Driver
17  *
18  * Please direct your questions and comments on this driver to the following
19  * email address:
20  *
21  *      linux-arm-kernel@lists.arm.linux.org.uk
22  *
23  */
24
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/kernel.h>
28 #include <linux/sched.h>
29 #include <linux/errno.h>
30 #include <linux/string.h>
31 #include <linux/interrupt.h>
32 #include <linux/slab.h>
33 #include <linux/mm.h>
34 #include <linux/fb.h>
35 #include <linux/delay.h>
36 #include <linux/init.h>
37 #include <linux/ioport.h>
38 #include <linux/cpufreq.h>
39 #include <linux/platform_device.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/clk.h>
42 #include <linux/err.h>
43 #include <linux/completion.h>
44 #include <linux/mutex.h>
45 #include <linux/kthread.h>
46 #include <linux/freezer.h>
47
48 #include <mach/hardware.h>
49 #include <asm/io.h>
50 #include <asm/irq.h>
51 #include <asm/div64.h>
52 #include <mach/pxa-regs.h>
53 #include <mach/pxa2xx-gpio.h>
54 #include <mach/bitfield.h>
55 #include <mach/pxafb.h>
56
57 /*
58  * Complain if VAR is out of range.
59  */
60 #define DEBUG_VAR 1
61
62 #include "pxafb.h"
63
64 /* Bits which should not be set in machine configuration structures */
65 #define LCCR0_INVALID_CONFIG_MASK       (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
66                                          LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
67                                          LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
68
69 #define LCCR3_INVALID_CONFIG_MASK       (LCCR3_HSP | LCCR3_VSP |\
70                                          LCCR3_PCD | LCCR3_BPP)
71
72 static void (*pxafb_backlight_power)(int);
73 static void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
74
75 static int pxafb_activate_var(struct fb_var_screeninfo *var,
76                                 struct pxafb_info *);
77 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
78
79 static inline unsigned long
80 lcd_readl(struct pxafb_info *fbi, unsigned int off)
81 {
82         return __raw_readl(fbi->mmio_base + off);
83 }
84
85 static inline void
86 lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val)
87 {
88         __raw_writel(val, fbi->mmio_base + off);
89 }
90
91 static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
92 {
93         unsigned long flags;
94
95         local_irq_save(flags);
96         /*
97          * We need to handle two requests being made at the same time.
98          * There are two important cases:
99          *  1. When we are changing VT (C_REENABLE) while unblanking
100          *     (C_ENABLE) We must perform the unblanking, which will
101          *     do our REENABLE for us.
102          *  2. When we are blanking, but immediately unblank before
103          *     we have blanked.  We do the "REENABLE" thing here as
104          *     well, just to be sure.
105          */
106         if (fbi->task_state == C_ENABLE && state == C_REENABLE)
107                 state = (u_int) -1;
108         if (fbi->task_state == C_DISABLE && state == C_ENABLE)
109                 state = C_REENABLE;
110
111         if (state != (u_int)-1) {
112                 fbi->task_state = state;
113                 schedule_work(&fbi->task);
114         }
115         local_irq_restore(flags);
116 }
117
118 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
119 {
120         chan &= 0xffff;
121         chan >>= 16 - bf->length;
122         return chan << bf->offset;
123 }
124
125 static int
126 pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
127                        u_int trans, struct fb_info *info)
128 {
129         struct pxafb_info *fbi = (struct pxafb_info *)info;
130         u_int val;
131
132         if (regno >= fbi->palette_size)
133                 return 1;
134
135         if (fbi->fb.var.grayscale) {
136                 fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
137                 return 0;
138         }
139
140         switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
141         case LCCR4_PAL_FOR_0:
142                 val  = ((red   >>  0) & 0xf800);
143                 val |= ((green >>  5) & 0x07e0);
144                 val |= ((blue  >> 11) & 0x001f);
145                 fbi->palette_cpu[regno] = val;
146                 break;
147         case LCCR4_PAL_FOR_1:
148                 val  = ((red   << 8) & 0x00f80000);
149                 val |= ((green >> 0) & 0x0000fc00);
150                 val |= ((blue  >> 8) & 0x000000f8);
151                 ((u32 *)(fbi->palette_cpu))[regno] = val;
152                 break;
153         case LCCR4_PAL_FOR_2:
154                 val  = ((red   << 8) & 0x00fc0000);
155                 val |= ((green >> 0) & 0x0000fc00);
156                 val |= ((blue  >> 8) & 0x000000fc);
157                 ((u32 *)(fbi->palette_cpu))[regno] = val;
158                 break;
159         }
160
161         return 0;
162 }
163
164 static int
165 pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
166                    u_int trans, struct fb_info *info)
167 {
168         struct pxafb_info *fbi = (struct pxafb_info *)info;
169         unsigned int val;
170         int ret = 1;
171
172         /*
173          * If inverse mode was selected, invert all the colours
174          * rather than the register number.  The register number
175          * is what you poke into the framebuffer to produce the
176          * colour you requested.
177          */
178         if (fbi->cmap_inverse) {
179                 red   = 0xffff - red;
180                 green = 0xffff - green;
181                 blue  = 0xffff - blue;
182         }
183
184         /*
185          * If greyscale is true, then we convert the RGB value
186          * to greyscale no matter what visual we are using.
187          */
188         if (fbi->fb.var.grayscale)
189                 red = green = blue = (19595 * red + 38470 * green +
190                                         7471 * blue) >> 16;
191
192         switch (fbi->fb.fix.visual) {
193         case FB_VISUAL_TRUECOLOR:
194                 /*
195                  * 16-bit True Colour.  We encode the RGB value
196                  * according to the RGB bitfield information.
197                  */
198                 if (regno < 16) {
199                         u32 *pal = fbi->fb.pseudo_palette;
200
201                         val  = chan_to_field(red, &fbi->fb.var.red);
202                         val |= chan_to_field(green, &fbi->fb.var.green);
203                         val |= chan_to_field(blue, &fbi->fb.var.blue);
204
205                         pal[regno] = val;
206                         ret = 0;
207                 }
208                 break;
209
210         case FB_VISUAL_STATIC_PSEUDOCOLOR:
211         case FB_VISUAL_PSEUDOCOLOR:
212                 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
213                 break;
214         }
215
216         return ret;
217 }
218
219 /*
220  *  pxafb_bpp_to_lccr3():
221  *    Convert a bits per pixel value to the correct bit pattern for LCCR3
222  */
223 static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
224 {
225         int ret = 0;
226         switch (var->bits_per_pixel) {
227         case 1:  ret = LCCR3_1BPP; break;
228         case 2:  ret = LCCR3_2BPP; break;
229         case 4:  ret = LCCR3_4BPP; break;
230         case 8:  ret = LCCR3_8BPP; break;
231         case 16: ret = LCCR3_16BPP; break;
232         case 24:
233                 switch (var->red.length + var->green.length +
234                                 var->blue.length + var->transp.length) {
235                 case 18: ret = LCCR3_18BPP_P | LCCR3_PDFOR_3; break;
236                 case 19: ret = LCCR3_19BPP_P; break;
237                 }
238                 break;
239         case 32:
240                 switch (var->red.length + var->green.length +
241                                 var->blue.length + var->transp.length) {
242                 case 18: ret = LCCR3_18BPP | LCCR3_PDFOR_3; break;
243                 case 19: ret = LCCR3_19BPP; break;
244                 case 24: ret = LCCR3_24BPP | LCCR3_PDFOR_3; break;
245                 case 25: ret = LCCR3_25BPP; break;
246                 }
247                 break;
248         }
249         return ret;
250 }
251
252 #ifdef CONFIG_CPU_FREQ
253 /*
254  *  pxafb_display_dma_period()
255  *    Calculate the minimum period (in picoseconds) between two DMA
256  *    requests for the LCD controller.  If we hit this, it means we're
257  *    doing nothing but LCD DMA.
258  */
259 static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
260 {
261         /*
262          * Period = pixclock * bits_per_byte * bytes_per_transfer
263          *              / memory_bits_per_pixel;
264          */
265         return var->pixclock * 8 * 16 / var->bits_per_pixel;
266 }
267 #endif
268
269 /*
270  * Select the smallest mode that allows the desired resolution to be
271  * displayed. If desired parameters can be rounded up.
272  */
273 static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach,
274                                              struct fb_var_screeninfo *var)
275 {
276         struct pxafb_mode_info *mode = NULL;
277         struct pxafb_mode_info *modelist = mach->modes;
278         unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
279         unsigned int i;
280
281         for (i = 0; i < mach->num_modes; i++) {
282                 if (modelist[i].xres >= var->xres &&
283                     modelist[i].yres >= var->yres &&
284                     modelist[i].xres < best_x &&
285                     modelist[i].yres < best_y &&
286                     modelist[i].bpp >= var->bits_per_pixel) {
287                         best_x = modelist[i].xres;
288                         best_y = modelist[i].yres;
289                         mode = &modelist[i];
290                 }
291         }
292
293         return mode;
294 }
295
296 static void pxafb_setmode(struct fb_var_screeninfo *var,
297                           struct pxafb_mode_info *mode)
298 {
299         var->xres               = mode->xres;
300         var->yres               = mode->yres;
301         var->bits_per_pixel     = mode->bpp;
302         var->pixclock           = mode->pixclock;
303         var->hsync_len          = mode->hsync_len;
304         var->left_margin        = mode->left_margin;
305         var->right_margin       = mode->right_margin;
306         var->vsync_len          = mode->vsync_len;
307         var->upper_margin       = mode->upper_margin;
308         var->lower_margin       = mode->lower_margin;
309         var->sync               = mode->sync;
310         var->grayscale          = mode->cmap_greyscale;
311         var->xres_virtual       = var->xres;
312         var->yres_virtual       = var->yres;
313 }
314
315 /*
316  *  pxafb_check_var():
317  *    Get the video params out of 'var'. If a value doesn't fit, round it up,
318  *    if it's too big, return -EINVAL.
319  *
320  *    Round up in the following order: bits_per_pixel, xres,
321  *    yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
322  *    bitfields, horizontal timing, vertical timing.
323  */
324 static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
325 {
326         struct pxafb_info *fbi = (struct pxafb_info *)info;
327         struct pxafb_mach_info *inf = fbi->dev->platform_data;
328
329         if (var->xres < MIN_XRES)
330                 var->xres = MIN_XRES;
331         if (var->yres < MIN_YRES)
332                 var->yres = MIN_YRES;
333
334         if (inf->fixed_modes) {
335                 struct pxafb_mode_info *mode;
336
337                 mode = pxafb_getmode(inf, var);
338                 if (!mode)
339                         return -EINVAL;
340                 pxafb_setmode(var, mode);
341         } else {
342                 if (var->xres > inf->modes->xres)
343                         return -EINVAL;
344                 if (var->yres > inf->modes->yres)
345                         return -EINVAL;
346                 if (var->bits_per_pixel > inf->modes->bpp)
347                         return -EINVAL;
348         }
349
350         var->xres_virtual =
351                 max(var->xres_virtual, var->xres);
352         var->yres_virtual =
353                 max(var->yres_virtual, var->yres);
354
355         /*
356          * Setup the RGB parameters for this display.
357          *
358          * The pixel packing format is described on page 7-11 of the
359          * PXA2XX Developer's Manual.
360          */
361         if (var->bits_per_pixel == 16) {
362                 var->red.offset   = 11; var->red.length   = 5;
363                 var->green.offset = 5;  var->green.length = 6;
364                 var->blue.offset  = 0;  var->blue.length  = 5;
365                 var->transp.offset = var->transp.length = 0;
366         } else if (var->bits_per_pixel > 16) {
367                 struct pxafb_mode_info *mode;
368
369                 mode = pxafb_getmode(inf, var);
370                 if (!mode)
371                         return -EINVAL;
372
373                 switch (mode->depth) {
374                 case 18: /* RGB666 */
375                         var->transp.offset = var->transp.length     = 0;
376                         var->red.offset    = 12; var->red.length    = 6;
377                         var->green.offset  = 6;  var->green.length  = 6;
378                         var->blue.offset   = 0;  var->blue.length   = 6;
379                         break;
380                 case 19: /* RGBT666 */
381                         var->transp.offset = 18; var->transp.length = 1;
382                         var->red.offset    = 12; var->red.length    = 6;
383                         var->green.offset  = 6;  var->green.length  = 6;
384                         var->blue.offset   = 0;  var->blue.length   = 6;
385                         break;
386                 case 24: /* RGB888 */
387                         var->transp.offset = var->transp.length     = 0;
388                         var->red.offset    = 16; var->red.length    = 8;
389                         var->green.offset  = 8;  var->green.length  = 8;
390                         var->blue.offset   = 0;  var->blue.length   = 8;
391                         break;
392                 case 25: /* RGBT888 */
393                         var->transp.offset = 24; var->transp.length = 1;
394                         var->red.offset    = 16; var->red.length    = 8;
395                         var->green.offset  = 8;  var->green.length  = 8;
396                         var->blue.offset   = 0;  var->blue.length   = 8;
397                         break;
398                 default:
399                         return -EINVAL;
400                 }
401         } else {
402                 var->red.offset = var->green.offset = 0;
403                 var->blue.offset = var->transp.offset = 0;
404                 var->red.length   = 8;
405                 var->green.length = 8;
406                 var->blue.length  = 8;
407                 var->transp.length = 0;
408         }
409
410 #ifdef CONFIG_CPU_FREQ
411         pr_debug("pxafb: dma period = %d ps\n",
412                  pxafb_display_dma_period(var));
413 #endif
414
415         return 0;
416 }
417
418 static inline void pxafb_set_truecolor(u_int is_true_color)
419 {
420         /* do your machine-specific setup if needed */
421 }
422
423 /*
424  * pxafb_set_par():
425  *      Set the user defined part of the display for the specified console
426  */
427 static int pxafb_set_par(struct fb_info *info)
428 {
429         struct pxafb_info *fbi = (struct pxafb_info *)info;
430         struct fb_var_screeninfo *var = &info->var;
431
432         if (var->bits_per_pixel >= 16)
433                 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
434         else if (!fbi->cmap_static)
435                 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
436         else {
437                 /*
438                  * Some people have weird ideas about wanting static
439                  * pseudocolor maps.  I suspect their user space
440                  * applications are broken.
441                  */
442                 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
443         }
444
445         fbi->fb.fix.line_length = var->xres_virtual *
446                                   var->bits_per_pixel / 8;
447         if (var->bits_per_pixel >= 16)
448                 fbi->palette_size = 0;
449         else
450                 fbi->palette_size = var->bits_per_pixel == 1 ?
451                                         4 : 1 << var->bits_per_pixel;
452
453         fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
454
455         /*
456          * Set (any) board control register to handle new color depth
457          */
458         pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
459
460         if (fbi->fb.var.bits_per_pixel >= 16)
461                 fb_dealloc_cmap(&fbi->fb.cmap);
462         else
463                 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
464
465         pxafb_activate_var(var, fbi);
466
467         return 0;
468 }
469
470 /*
471  * pxafb_blank():
472  *      Blank the display by setting all palette values to zero.  Note, the
473  *      16 bpp mode does not really use the palette, so this will not
474  *      blank the display in all modes.
475  */
476 static int pxafb_blank(int blank, struct fb_info *info)
477 {
478         struct pxafb_info *fbi = (struct pxafb_info *)info;
479         int i;
480
481         switch (blank) {
482         case FB_BLANK_POWERDOWN:
483         case FB_BLANK_VSYNC_SUSPEND:
484         case FB_BLANK_HSYNC_SUSPEND:
485         case FB_BLANK_NORMAL:
486                 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
487                     fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
488                         for (i = 0; i < fbi->palette_size; i++)
489                                 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
490
491                 pxafb_schedule_work(fbi, C_DISABLE);
492                 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
493                 break;
494
495         case FB_BLANK_UNBLANK:
496                 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
497                 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
498                     fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
499                         fb_set_cmap(&fbi->fb.cmap, info);
500                 pxafb_schedule_work(fbi, C_ENABLE);
501         }
502         return 0;
503 }
504
505 static int pxafb_mmap(struct fb_info *info,
506                       struct vm_area_struct *vma)
507 {
508         struct pxafb_info *fbi = (struct pxafb_info *)info;
509         unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
510
511         if (off < info->fix.smem_len) {
512                 vma->vm_pgoff += fbi->video_offset / PAGE_SIZE;
513                 return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu,
514                                              fbi->map_dma, fbi->map_size);
515         }
516         return -EINVAL;
517 }
518
519 static struct fb_ops pxafb_ops = {
520         .owner          = THIS_MODULE,
521         .fb_check_var   = pxafb_check_var,
522         .fb_set_par     = pxafb_set_par,
523         .fb_setcolreg   = pxafb_setcolreg,
524         .fb_fillrect    = cfb_fillrect,
525         .fb_copyarea    = cfb_copyarea,
526         .fb_imageblit   = cfb_imageblit,
527         .fb_blank       = pxafb_blank,
528         .fb_mmap        = pxafb_mmap,
529 };
530
531 /*
532  * Calculate the PCD value from the clock rate (in picoseconds).
533  * We take account of the PPCR clock setting.
534  * From PXA Developer's Manual:
535  *
536  *   PixelClock =      LCLK
537  *                -------------
538  *                2 ( PCD + 1 )
539  *
540  *   PCD =      LCLK
541  *         ------------- - 1
542  *         2(PixelClock)
543  *
544  * Where:
545  *   LCLK = LCD/Memory Clock
546  *   PCD = LCCR3[7:0]
547  *
548  * PixelClock here is in Hz while the pixclock argument given is the
549  * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
550  *
551  * The function get_lclk_frequency_10khz returns LCLK in units of
552  * 10khz. Calling the result of this function lclk gives us the
553  * following
554  *
555  *    PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
556  *          -------------------------------------- - 1
557  *                          2
558  *
559  * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
560  */
561 static inline unsigned int get_pcd(struct pxafb_info *fbi,
562                                    unsigned int pixclock)
563 {
564         unsigned long long pcd;
565
566         /* FIXME: Need to take into account Double Pixel Clock mode
567          * (DPC) bit? or perhaps set it based on the various clock
568          * speeds */
569         pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
570         pcd *= pixclock;
571         do_div(pcd, 100000000 * 2);
572         /* no need for this, since we should subtract 1 anyway. they cancel */
573         /* pcd += 1; */ /* make up for integer math truncations */
574         return (unsigned int)pcd;
575 }
576
577 /*
578  * Some touchscreens need hsync information from the video driver to
579  * function correctly. We export it here.  Note that 'hsync_time' and
580  * the value returned from pxafb_get_hsync_time() is the *reciprocal*
581  * of the hsync period in seconds.
582  */
583 static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
584 {
585         unsigned long htime;
586
587         if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
588                 fbi->hsync_time = 0;
589                 return;
590         }
591
592         htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
593
594         fbi->hsync_time = htime;
595 }
596
597 unsigned long pxafb_get_hsync_time(struct device *dev)
598 {
599         struct pxafb_info *fbi = dev_get_drvdata(dev);
600
601         /* If display is blanked/suspended, hsync isn't active */
602         if (!fbi || (fbi->state != C_ENABLE))
603                 return 0;
604
605         return fbi->hsync_time;
606 }
607 EXPORT_SYMBOL(pxafb_get_hsync_time);
608
609 static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
610                 unsigned int offset, size_t size)
611 {
612         struct pxafb_dma_descriptor *dma_desc, *pal_desc;
613         unsigned int dma_desc_off, pal_desc_off;
614
615         if (dma < 0 || dma >= DMA_MAX)
616                 return -EINVAL;
617
618         dma_desc = &fbi->dma_buff->dma_desc[dma];
619         dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
620
621         dma_desc->fsadr = fbi->screen_dma + offset;
622         dma_desc->fidr  = 0;
623         dma_desc->ldcmd = size;
624
625         if (pal < 0 || pal >= PAL_MAX) {
626                 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
627                 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
628         } else {
629                 pal_desc = &fbi->dma_buff->pal_desc[pal];
630                 pal_desc_off = offsetof(struct pxafb_dma_buff, pal_desc[pal]);
631
632                 pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
633                 pal_desc->fidr  = 0;
634
635                 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
636                         pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
637                 else
638                         pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
639
640                 pal_desc->ldcmd |= LDCMD_PAL;
641
642                 /* flip back and forth between palette and frame buffer */
643                 pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
644                 dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
645                 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
646         }
647
648         return 0;
649 }
650
651 #ifdef CONFIG_FB_PXA_SMARTPANEL
652 static int setup_smart_dma(struct pxafb_info *fbi)
653 {
654         struct pxafb_dma_descriptor *dma_desc;
655         unsigned long dma_desc_off, cmd_buff_off;
656
657         dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD];
658         dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]);
659         cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff);
660
661         dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
662         dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off;
663         dma_desc->fidr  = 0;
664         dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t);
665
666         fbi->fdadr[DMA_CMD] = dma_desc->fdadr;
667         return 0;
668 }
669
670 int pxafb_smart_flush(struct fb_info *info)
671 {
672         struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
673         uint32_t prsr;
674         int ret = 0;
675
676         /* disable controller until all registers are set up */
677         lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
678
679         /* 1. make it an even number of commands to align on 32-bit boundary
680          * 2. add the interrupt command to the end of the chain so we can
681          *    keep track of the end of the transfer
682          */
683
684         while (fbi->n_smart_cmds & 1)
685                 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP;
686
687         fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT;
688         fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC;
689         setup_smart_dma(fbi);
690
691         /* continue to execute next command */
692         prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT;
693         lcd_writel(fbi, PRSR, prsr);
694
695         /* stop the processor in case it executed "wait for sync" cmd */
696         lcd_writel(fbi, CMDCR, 0x0001);
697
698         /* don't send interrupts for fifo underruns on channel 6 */
699         lcd_writel(fbi, LCCR5, LCCR5_IUM(6));
700
701         lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
702         lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
703         lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
704         lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
705         lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
706
707         /* begin sending */
708         lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
709
710         if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) {
711                 pr_warning("%s: timeout waiting for command done\n",
712                                 __func__);
713                 ret = -ETIMEDOUT;
714         }
715
716         /* quick disable */
717         prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT);
718         lcd_writel(fbi, PRSR, prsr);
719         lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
720         lcd_writel(fbi, FDADR6, 0);
721         fbi->n_smart_cmds = 0;
722         return ret;
723 }
724
725 int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
726 {
727         int i;
728         struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
729
730         /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
731         for (i = 0; i < n_cmds; i++) {
732                 if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
733                         pxafb_smart_flush(info);
734
735                 fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds++;
736         }
737
738         return 0;
739 }
740
741 static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk)
742 {
743         unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000);
744         return (t == 0) ? 1 : t;
745 }
746
747 static void setup_smart_timing(struct pxafb_info *fbi,
748                                 struct fb_var_screeninfo *var)
749 {
750         struct pxafb_mach_info *inf = fbi->dev->platform_data;
751         struct pxafb_mode_info *mode = &inf->modes[0];
752         unsigned long lclk = clk_get_rate(fbi->clk);
753         unsigned t1, t2, t3, t4;
754
755         t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld);
756         t2 = max(mode->rd_pulse_width, mode->wr_pulse_width);
757         t3 = mode->op_hold_time;
758         t4 = mode->cmd_inh_time;
759
760         fbi->reg_lccr1 =
761                 LCCR1_DisWdth(var->xres) |
762                 LCCR1_BegLnDel(__smart_timing(t1, lclk)) |
763                 LCCR1_EndLnDel(__smart_timing(t2, lclk)) |
764                 LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
765
766         fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
767         fbi->reg_lccr3 = LCCR3_PixClkDiv(__smart_timing(t4, lclk));
768
769         /* FIXME: make this configurable */
770         fbi->reg_cmdcr = 1;
771 }
772
773 static int pxafb_smart_thread(void *arg)
774 {
775         struct pxafb_info *fbi = arg;
776         struct pxafb_mach_info *inf = fbi->dev->platform_data;
777
778         if (!fbi || !inf->smart_update) {
779                 pr_err("%s: not properly initialized, thread terminated\n",
780                                 __func__);
781                 return -EINVAL;
782         }
783
784         pr_debug("%s(): task starting\n", __func__);
785
786         set_freezable();
787         while (!kthread_should_stop()) {
788
789                 if (try_to_freeze())
790                         continue;
791
792                 if (fbi->state == C_ENABLE) {
793                         inf->smart_update(&fbi->fb);
794                         complete(&fbi->refresh_done);
795                 }
796
797                 set_current_state(TASK_INTERRUPTIBLE);
798                 schedule_timeout(30 * HZ / 1000);
799         }
800
801         pr_debug("%s(): task ending\n", __func__);
802         return 0;
803 }
804
805 static int pxafb_smart_init(struct pxafb_info *fbi)
806 {
807         fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
808                                         "lcd_refresh");
809         if (IS_ERR(fbi->smart_thread)) {
810                 printk(KERN_ERR "%s: unable to create kernel thread\n",
811                                 __func__);
812                 return PTR_ERR(fbi->smart_thread);
813         }
814         return 0;
815 }
816 #else
817 int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
818 {
819         return 0;
820 }
821
822 int pxafb_smart_flush(struct fb_info *info)
823 {
824         return 0;
825 }
826 #endif /* CONFIG_FB_SMART_PANEL */
827
828 static void setup_parallel_timing(struct pxafb_info *fbi,
829                                   struct fb_var_screeninfo *var)
830 {
831         unsigned int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
832
833         fbi->reg_lccr1 =
834                 LCCR1_DisWdth(var->xres) +
835                 LCCR1_HorSnchWdth(var->hsync_len) +
836                 LCCR1_BegLnDel(var->left_margin) +
837                 LCCR1_EndLnDel(var->right_margin);
838
839         /*
840          * If we have a dual scan LCD, we need to halve
841          * the YRES parameter.
842          */
843         lines_per_panel = var->yres;
844         if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
845                 lines_per_panel /= 2;
846
847         fbi->reg_lccr2 =
848                 LCCR2_DisHght(lines_per_panel) +
849                 LCCR2_VrtSnchWdth(var->vsync_len) +
850                 LCCR2_BegFrmDel(var->upper_margin) +
851                 LCCR2_EndFrmDel(var->lower_margin);
852
853         fbi->reg_lccr3 = fbi->lccr3 |
854                 (var->sync & FB_SYNC_HOR_HIGH_ACT ?
855                  LCCR3_HorSnchH : LCCR3_HorSnchL) |
856                 (var->sync & FB_SYNC_VERT_HIGH_ACT ?
857                  LCCR3_VrtSnchH : LCCR3_VrtSnchL);
858
859         if (pcd) {
860                 fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd);
861                 set_hsync_time(fbi, pcd);
862         }
863 }
864
865 /*
866  * pxafb_activate_var():
867  *      Configures LCD Controller based on entries in var parameter.
868  *      Settings are only written to the controller if changes were made.
869  */
870 static int pxafb_activate_var(struct fb_var_screeninfo *var,
871                               struct pxafb_info *fbi)
872 {
873         u_long flags;
874         size_t nbytes;
875
876 #if DEBUG_VAR
877         if (!(fbi->lccr0 & LCCR0_LCDT)) {
878                 if (var->xres < 16 || var->xres > 1024)
879                         printk(KERN_ERR "%s: invalid xres %d\n",
880                                 fbi->fb.fix.id, var->xres);
881                 switch (var->bits_per_pixel) {
882                 case 1:
883                 case 2:
884                 case 4:
885                 case 8:
886                 case 16:
887                 case 24:
888                 case 32:
889                         break;
890                 default:
891                         printk(KERN_ERR "%s: invalid bit depth %d\n",
892                                fbi->fb.fix.id, var->bits_per_pixel);
893                         break;
894                 }
895
896                 if (var->hsync_len < 1 || var->hsync_len > 64)
897                         printk(KERN_ERR "%s: invalid hsync_len %d\n",
898                                 fbi->fb.fix.id, var->hsync_len);
899                 if (var->left_margin < 1 || var->left_margin > 255)
900                         printk(KERN_ERR "%s: invalid left_margin %d\n",
901                                 fbi->fb.fix.id, var->left_margin);
902                 if (var->right_margin < 1 || var->right_margin > 255)
903                         printk(KERN_ERR "%s: invalid right_margin %d\n",
904                                 fbi->fb.fix.id, var->right_margin);
905                 if (var->yres < 1 || var->yres > 1024)
906                         printk(KERN_ERR "%s: invalid yres %d\n",
907                                 fbi->fb.fix.id, var->yres);
908                 if (var->vsync_len < 1 || var->vsync_len > 64)
909                         printk(KERN_ERR "%s: invalid vsync_len %d\n",
910                                 fbi->fb.fix.id, var->vsync_len);
911                 if (var->upper_margin < 0 || var->upper_margin > 255)
912                         printk(KERN_ERR "%s: invalid upper_margin %d\n",
913                                 fbi->fb.fix.id, var->upper_margin);
914                 if (var->lower_margin < 0 || var->lower_margin > 255)
915                         printk(KERN_ERR "%s: invalid lower_margin %d\n",
916                                 fbi->fb.fix.id, var->lower_margin);
917         }
918 #endif
919         /* Update shadow copy atomically */
920         local_irq_save(flags);
921
922 #ifdef CONFIG_FB_PXA_SMARTPANEL
923         if (fbi->lccr0 & LCCR0_LCDT)
924                 setup_smart_timing(fbi, var);
925         else
926 #endif
927                 setup_parallel_timing(fbi, var);
928
929         fbi->reg_lccr0 = fbi->lccr0 |
930                 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
931                  LCCR0_QDM | LCCR0_BM  | LCCR0_OUM);
932
933         fbi->reg_lccr3 |= pxafb_bpp_to_lccr3(var);
934
935         nbytes = var->yres * fbi->fb.fix.line_length;
936
937         if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual) {
938                 nbytes = nbytes / 2;
939                 setup_frame_dma(fbi, DMA_LOWER, PAL_NONE, nbytes, nbytes);
940         }
941
942         if ((var->bits_per_pixel >= 16) || (fbi->lccr0 & LCCR0_LCDT))
943                 setup_frame_dma(fbi, DMA_BASE, PAL_NONE, 0, nbytes);
944         else
945                 setup_frame_dma(fbi, DMA_BASE, PAL_BASE, 0, nbytes);
946
947         fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
948         fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
949         local_irq_restore(flags);
950
951         /*
952          * Only update the registers if the controller is enabled
953          * and something has changed.
954          */
955         if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) ||
956             (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
957             (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
958             (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
959             (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
960             (lcd_readl(fbi, FDADR1) != fbi->fdadr[1]))
961                 pxafb_schedule_work(fbi, C_REENABLE);
962
963         return 0;
964 }
965
966 /*
967  * NOTE!  The following functions are purely helpers for set_ctrlr_state.
968  * Do not call them directly; set_ctrlr_state does the correct serialisation
969  * to ensure that things happen in the right way 100% of time time.
970  *      -- rmk
971  */
972 static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
973 {
974         pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
975
976         if (pxafb_backlight_power)
977                 pxafb_backlight_power(on);
978 }
979
980 static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
981 {
982         pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
983
984         if (pxafb_lcd_power)
985                 pxafb_lcd_power(on, &fbi->fb.var);
986 }
987
988 static void pxafb_setup_gpio(struct pxafb_info *fbi)
989 {
990         int gpio, ldd_bits;
991         unsigned int lccr0 = fbi->lccr0;
992
993         /*
994          * setup is based on type of panel supported
995          */
996
997         /* 4 bit interface */
998         if ((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
999             (lccr0 & LCCR0_SDS) == LCCR0_Sngl &&
1000             (lccr0 & LCCR0_DPD) == LCCR0_4PixMono)
1001                 ldd_bits = 4;
1002
1003         /* 8 bit interface */
1004         else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
1005                   ((lccr0 & LCCR0_SDS) == LCCR0_Dual ||
1006                    (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) ||
1007                  ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
1008                   (lccr0 & LCCR0_PAS) == LCCR0_Pas &&
1009                   (lccr0 & LCCR0_SDS) == LCCR0_Sngl))
1010                 ldd_bits = 8;
1011
1012         /* 16 bit interface */
1013         else if ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
1014                  ((lccr0 & LCCR0_SDS) == LCCR0_Dual ||
1015                   (lccr0 & LCCR0_PAS) == LCCR0_Act))
1016                 ldd_bits = 16;
1017
1018         else {
1019                 printk(KERN_ERR "pxafb_setup_gpio: unable to determine "
1020                                "bits per pixel\n");
1021                 return;
1022         }
1023
1024         for (gpio = 58; ldd_bits; gpio++, ldd_bits--)
1025                 pxa_gpio_mode(gpio | GPIO_ALT_FN_2_OUT);
1026         /* 18 bit interface */
1027         if (fbi->fb.var.bits_per_pixel > 16) {
1028                 pxa_gpio_mode(86 | GPIO_ALT_FN_2_OUT);
1029                 pxa_gpio_mode(87 | GPIO_ALT_FN_2_OUT);
1030         }
1031         pxa_gpio_mode(GPIO74_LCD_FCLK_MD);
1032         pxa_gpio_mode(GPIO75_LCD_LCLK_MD);
1033         pxa_gpio_mode(GPIO76_LCD_PCLK_MD);
1034
1035         if ((lccr0 & LCCR0_PAS) == 0)
1036                 pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD);
1037 }
1038
1039 static void pxafb_enable_controller(struct pxafb_info *fbi)
1040 {
1041         pr_debug("pxafb: Enabling LCD controller\n");
1042         pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
1043         pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
1044         pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
1045         pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
1046         pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
1047         pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
1048
1049         /* enable LCD controller clock */
1050         clk_enable(fbi->clk);
1051
1052         if (fbi->lccr0 & LCCR0_LCDT)
1053                 return;
1054
1055         /* Sequence from 11.7.10 */
1056         lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1057         lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1058         lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1059         lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1060
1061         lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1062         lcd_writel(fbi, FDADR1, fbi->fdadr[1]);
1063         lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1064 }
1065
1066 static void pxafb_disable_controller(struct pxafb_info *fbi)
1067 {
1068         uint32_t lccr0;
1069
1070 #ifdef CONFIG_FB_PXA_SMARTPANEL
1071         if (fbi->lccr0 & LCCR0_LCDT) {
1072                 wait_for_completion_timeout(&fbi->refresh_done,
1073                                 200 * HZ / 1000);
1074                 return;
1075         }
1076 #endif
1077
1078         /* Clear LCD Status Register */
1079         lcd_writel(fbi, LCSR, 0xffffffff);
1080
1081         lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM;
1082         lcd_writel(fbi, LCCR0, lccr0);
1083         lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS);
1084
1085         wait_for_completion_timeout(&fbi->disable_done, 200 * HZ / 1000);
1086
1087         /* disable LCD controller clock */
1088         clk_disable(fbi->clk);
1089 }
1090
1091 /*
1092  *  pxafb_handle_irq: Handle 'LCD DONE' interrupts.
1093  */
1094 static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
1095 {
1096         struct pxafb_info *fbi = dev_id;
1097         unsigned int lccr0, lcsr = lcd_readl(fbi, LCSR);
1098
1099         if (lcsr & LCSR_LDD) {
1100                 lccr0 = lcd_readl(fbi, LCCR0);
1101                 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
1102                 complete(&fbi->disable_done);
1103         }
1104
1105 #ifdef CONFIG_FB_PXA_SMARTPANEL
1106         if (lcsr & LCSR_CMD_INT)
1107                 complete(&fbi->command_done);
1108 #endif
1109
1110         lcd_writel(fbi, LCSR, lcsr);
1111         return IRQ_HANDLED;
1112 }
1113
1114 /*
1115  * This function must be called from task context only, since it will
1116  * sleep when disabling the LCD controller, or if we get two contending
1117  * processes trying to alter state.
1118  */
1119 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
1120 {
1121         u_int old_state;
1122
1123         mutex_lock(&fbi->ctrlr_lock);
1124
1125         old_state = fbi->state;
1126
1127         /*
1128          * Hack around fbcon initialisation.
1129          */
1130         if (old_state == C_STARTUP && state == C_REENABLE)
1131                 state = C_ENABLE;
1132
1133         switch (state) {
1134         case C_DISABLE_CLKCHANGE:
1135                 /*
1136                  * Disable controller for clock change.  If the
1137                  * controller is already disabled, then do nothing.
1138                  */
1139                 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
1140                         fbi->state = state;
1141                         /* TODO __pxafb_lcd_power(fbi, 0); */
1142                         pxafb_disable_controller(fbi);
1143                 }
1144                 break;
1145
1146         case C_DISABLE_PM:
1147         case C_DISABLE:
1148                 /*
1149                  * Disable controller
1150                  */
1151                 if (old_state != C_DISABLE) {
1152                         fbi->state = state;
1153                         __pxafb_backlight_power(fbi, 0);
1154                         __pxafb_lcd_power(fbi, 0);
1155                         if (old_state != C_DISABLE_CLKCHANGE)
1156                                 pxafb_disable_controller(fbi);
1157                 }
1158                 break;
1159
1160         case C_ENABLE_CLKCHANGE:
1161                 /*
1162                  * Enable the controller after clock change.  Only
1163                  * do this if we were disabled for the clock change.
1164                  */
1165                 if (old_state == C_DISABLE_CLKCHANGE) {
1166                         fbi->state = C_ENABLE;
1167                         pxafb_enable_controller(fbi);
1168                         /* TODO __pxafb_lcd_power(fbi, 1); */
1169                 }
1170                 break;
1171
1172         case C_REENABLE:
1173                 /*
1174                  * Re-enable the controller only if it was already
1175                  * enabled.  This is so we reprogram the control
1176                  * registers.
1177                  */
1178                 if (old_state == C_ENABLE) {
1179                         __pxafb_lcd_power(fbi, 0);
1180                         pxafb_disable_controller(fbi);
1181                         pxafb_setup_gpio(fbi);
1182                         pxafb_enable_controller(fbi);
1183                         __pxafb_lcd_power(fbi, 1);
1184                 }
1185                 break;
1186
1187         case C_ENABLE_PM:
1188                 /*
1189                  * Re-enable the controller after PM.  This is not
1190                  * perfect - think about the case where we were doing
1191                  * a clock change, and we suspended half-way through.
1192                  */
1193                 if (old_state != C_DISABLE_PM)
1194                         break;
1195                 /* fall through */
1196
1197         case C_ENABLE:
1198                 /*
1199                  * Power up the LCD screen, enable controller, and
1200                  * turn on the backlight.
1201                  */
1202                 if (old_state != C_ENABLE) {
1203                         fbi->state = C_ENABLE;
1204                         pxafb_setup_gpio(fbi);
1205                         pxafb_enable_controller(fbi);
1206                         __pxafb_lcd_power(fbi, 1);
1207                         __pxafb_backlight_power(fbi, 1);
1208                 }
1209                 break;
1210         }
1211         mutex_unlock(&fbi->ctrlr_lock);
1212 }
1213
1214 /*
1215  * Our LCD controller task (which is called when we blank or unblank)
1216  * via keventd.
1217  */
1218 static void pxafb_task(struct work_struct *work)
1219 {
1220         struct pxafb_info *fbi =
1221                 container_of(work, struct pxafb_info, task);
1222         u_int state = xchg(&fbi->task_state, -1);
1223
1224         set_ctrlr_state(fbi, state);
1225 }
1226
1227 #ifdef CONFIG_CPU_FREQ
1228 /*
1229  * CPU clock speed change handler.  We need to adjust the LCD timing
1230  * parameters when the CPU clock is adjusted by the power management
1231  * subsystem.
1232  *
1233  * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
1234  */
1235 static int
1236 pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
1237 {
1238         struct pxafb_info *fbi = TO_INF(nb, freq_transition);
1239         /* TODO struct cpufreq_freqs *f = data; */
1240         u_int pcd;
1241
1242         switch (val) {
1243         case CPUFREQ_PRECHANGE:
1244                 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1245                 break;
1246
1247         case CPUFREQ_POSTCHANGE:
1248                 pcd = get_pcd(fbi, fbi->fb.var.pixclock);
1249                 set_hsync_time(fbi, pcd);
1250                 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) |
1251                                   LCCR3_PixClkDiv(pcd);
1252                 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1253                 break;
1254         }
1255         return 0;
1256 }
1257
1258 static int
1259 pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
1260 {
1261         struct pxafb_info *fbi = TO_INF(nb, freq_policy);
1262         struct fb_var_screeninfo *var = &fbi->fb.var;
1263         struct cpufreq_policy *policy = data;
1264
1265         switch (val) {
1266         case CPUFREQ_ADJUST:
1267         case CPUFREQ_INCOMPATIBLE:
1268                 pr_debug("min dma period: %d ps, "
1269                         "new clock %d kHz\n", pxafb_display_dma_period(var),
1270                         policy->max);
1271                 /* TODO: fill in min/max values */
1272                 break;
1273         }
1274         return 0;
1275 }
1276 #endif
1277
1278 #ifdef CONFIG_PM
1279 /*
1280  * Power management hooks.  Note that we won't be called from IRQ context,
1281  * unlike the blank functions above, so we may sleep.
1282  */
1283 static int pxafb_suspend(struct platform_device *dev, pm_message_t state)
1284 {
1285         struct pxafb_info *fbi = platform_get_drvdata(dev);
1286
1287         set_ctrlr_state(fbi, C_DISABLE_PM);
1288         return 0;
1289 }
1290
1291 static int pxafb_resume(struct platform_device *dev)
1292 {
1293         struct pxafb_info *fbi = platform_get_drvdata(dev);
1294
1295         set_ctrlr_state(fbi, C_ENABLE_PM);
1296         return 0;
1297 }
1298 #else
1299 #define pxafb_suspend   NULL
1300 #define pxafb_resume    NULL
1301 #endif
1302
1303 /*
1304  * pxafb_map_video_memory():
1305  *      Allocates the DRAM memory for the frame buffer.  This buffer is
1306  *      remapped into a non-cached, non-buffered, memory region to
1307  *      allow palette and pixel writes to occur without flushing the
1308  *      cache.  Once this area is remapped, all virtual memory
1309  *      access to the video memory should occur at the new region.
1310  */
1311 static int __devinit pxafb_map_video_memory(struct pxafb_info *fbi)
1312 {
1313         /*
1314          * We reserve one page for the palette, plus the size
1315          * of the framebuffer.
1316          */
1317         fbi->video_offset = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
1318         fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + fbi->video_offset);
1319         fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
1320                                               &fbi->map_dma, GFP_KERNEL);
1321
1322         if (fbi->map_cpu) {
1323                 /* prevent initial garbage on screen */
1324                 memset(fbi->map_cpu, 0, fbi->map_size);
1325                 fbi->fb.screen_base = fbi->map_cpu + fbi->video_offset;
1326                 fbi->screen_dma = fbi->map_dma + fbi->video_offset;
1327
1328                 /*
1329                  * FIXME: this is actually the wrong thing to place in
1330                  * smem_start.  But fbdev suffers from the problem that
1331                  * it needs an API which doesn't exist (in this case,
1332                  * dma_writecombine_mmap)
1333                  */
1334                 fbi->fb.fix.smem_start = fbi->screen_dma;
1335                 fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16;
1336
1337                 fbi->dma_buff = (void *) fbi->map_cpu;
1338                 fbi->dma_buff_phys = fbi->map_dma;
1339                 fbi->palette_cpu = (u16 *) fbi->dma_buff->palette;
1340
1341                 pr_debug("pxafb: palette_mem_size = 0x%08x\n", fbi->palette_size*sizeof(u16));
1342
1343 #ifdef CONFIG_FB_PXA_SMARTPANEL
1344                 fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
1345                 fbi->n_smart_cmds = 0;
1346 #endif
1347         }
1348
1349         return fbi->map_cpu ? 0 : -ENOMEM;
1350 }
1351
1352 static void pxafb_decode_mode_info(struct pxafb_info *fbi,
1353                                    struct pxafb_mode_info *modes,
1354                                    unsigned int num_modes)
1355 {
1356         unsigned int i, smemlen;
1357
1358         pxafb_setmode(&fbi->fb.var, &modes[0]);
1359
1360         for (i = 0; i < num_modes; i++) {
1361                 smemlen = modes[i].xres * modes[i].yres * modes[i].bpp / 8;
1362                 if (smemlen > fbi->fb.fix.smem_len)
1363                         fbi->fb.fix.smem_len = smemlen;
1364         }
1365 }
1366
1367 static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1368                                    struct pxafb_mach_info *inf)
1369 {
1370         unsigned int lcd_conn = inf->lcd_conn;
1371
1372         fbi->cmap_inverse       = inf->cmap_inverse;
1373         fbi->cmap_static        = inf->cmap_static;
1374
1375         switch (lcd_conn & 0xf) {
1376         case LCD_TYPE_MONO_STN:
1377                 fbi->lccr0 = LCCR0_CMS;
1378                 break;
1379         case LCD_TYPE_MONO_DSTN:
1380                 fbi->lccr0 = LCCR0_CMS | LCCR0_SDS;
1381                 break;
1382         case LCD_TYPE_COLOR_STN:
1383                 fbi->lccr0 = 0;
1384                 break;
1385         case LCD_TYPE_COLOR_DSTN:
1386                 fbi->lccr0 = LCCR0_SDS;
1387                 break;
1388         case LCD_TYPE_COLOR_TFT:
1389                 fbi->lccr0 = LCCR0_PAS;
1390                 break;
1391         case LCD_TYPE_SMART_PANEL:
1392                 fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS;
1393                 break;
1394         default:
1395                 /* fall back to backward compatibility way */
1396                 fbi->lccr0 = inf->lccr0;
1397                 fbi->lccr3 = inf->lccr3;
1398                 fbi->lccr4 = inf->lccr4;
1399                 goto decode_mode;
1400         }
1401
1402         if (lcd_conn == LCD_MONO_STN_8BPP)
1403                 fbi->lccr0 |= LCCR0_DPD;
1404
1405         fbi->lccr0 |= (lcd_conn & LCD_ALTERNATE_MAPPING) ? LCCR0_LDDALT : 0;
1406
1407         fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff);
1408         fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
1409         fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL)  ? LCCR3_PCP : 0;
1410
1411 decode_mode:
1412         pxafb_decode_mode_info(fbi, inf->modes, inf->num_modes);
1413 }
1414
1415 static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
1416 {
1417         struct pxafb_info *fbi;
1418         void *addr;
1419         struct pxafb_mach_info *inf = dev->platform_data;
1420
1421         /* Alloc the pxafb_info and pseudo_palette in one step */
1422         fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1423         if (!fbi)
1424                 return NULL;
1425
1426         memset(fbi, 0, sizeof(struct pxafb_info));
1427         fbi->dev = dev;
1428
1429         fbi->clk = clk_get(dev, "LCDCLK");
1430         if (IS_ERR(fbi->clk)) {
1431                 kfree(fbi);
1432                 return NULL;
1433         }
1434
1435         strcpy(fbi->fb.fix.id, PXA_NAME);
1436
1437         fbi->fb.fix.type        = FB_TYPE_PACKED_PIXELS;
1438         fbi->fb.fix.type_aux    = 0;
1439         fbi->fb.fix.xpanstep    = 0;
1440         fbi->fb.fix.ypanstep    = 0;
1441         fbi->fb.fix.ywrapstep   = 0;
1442         fbi->fb.fix.accel       = FB_ACCEL_NONE;
1443
1444         fbi->fb.var.nonstd      = 0;
1445         fbi->fb.var.activate    = FB_ACTIVATE_NOW;
1446         fbi->fb.var.height      = -1;
1447         fbi->fb.var.width       = -1;
1448         fbi->fb.var.accel_flags = 0;
1449         fbi->fb.var.vmode       = FB_VMODE_NONINTERLACED;
1450
1451         fbi->fb.fbops           = &pxafb_ops;
1452         fbi->fb.flags           = FBINFO_DEFAULT;
1453         fbi->fb.node            = -1;
1454
1455         addr = fbi;
1456         addr = addr + sizeof(struct pxafb_info);
1457         fbi->fb.pseudo_palette  = addr;
1458
1459         fbi->state              = C_STARTUP;
1460         fbi->task_state         = (u_char)-1;
1461
1462         pxafb_decode_mach_info(fbi, inf);
1463
1464         init_waitqueue_head(&fbi->ctrlr_wait);
1465         INIT_WORK(&fbi->task, pxafb_task);
1466         mutex_init(&fbi->ctrlr_lock);
1467         init_completion(&fbi->disable_done);
1468 #ifdef CONFIG_FB_PXA_SMARTPANEL
1469         init_completion(&fbi->command_done);
1470         init_completion(&fbi->refresh_done);
1471 #endif
1472
1473         return fbi;
1474 }
1475
1476 #ifdef CONFIG_FB_PXA_PARAMETERS
1477 static int __devinit parse_opt_mode(struct device *dev, const char *this_opt)
1478 {
1479         struct pxafb_mach_info *inf = dev->platform_data;
1480
1481         const char *name = this_opt+5;
1482         unsigned int namelen = strlen(name);
1483         int res_specified = 0, bpp_specified = 0;
1484         unsigned int xres = 0, yres = 0, bpp = 0;
1485         int yres_specified = 0;
1486         int i;
1487         for (i = namelen-1; i >= 0; i--) {
1488                 switch (name[i]) {
1489                 case '-':
1490                         namelen = i;
1491                         if (!bpp_specified && !yres_specified) {
1492                                 bpp = simple_strtoul(&name[i+1], NULL, 0);
1493                                 bpp_specified = 1;
1494                         } else
1495                                 goto done;
1496                         break;
1497                 case 'x':
1498                         if (!yres_specified) {
1499                                 yres = simple_strtoul(&name[i+1], NULL, 0);
1500                                 yres_specified = 1;
1501                         } else
1502                                 goto done;
1503                         break;
1504                 case '0' ... '9':
1505                         break;
1506                 default:
1507                         goto done;
1508                 }
1509         }
1510         if (i < 0 && yres_specified) {
1511                 xres = simple_strtoul(name, NULL, 0);
1512                 res_specified = 1;
1513         }
1514 done:
1515         if (res_specified) {
1516                 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1517                 inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1518         }
1519         if (bpp_specified)
1520                 switch (bpp) {
1521                 case 1:
1522                 case 2:
1523                 case 4:
1524                 case 8:
1525                 case 16:
1526                         inf->modes[0].bpp = bpp;
1527                         dev_info(dev, "overriding bit depth: %d\n", bpp);
1528                         break;
1529                 default:
1530                         dev_err(dev, "Depth %d is not valid\n", bpp);
1531                         return -EINVAL;
1532                 }
1533         return 0;
1534 }
1535
1536 static int __devinit parse_opt(struct device *dev, char *this_opt)
1537 {
1538         struct pxafb_mach_info *inf = dev->platform_data;
1539         struct pxafb_mode_info *mode = &inf->modes[0];
1540         char s[64];
1541
1542         s[0] = '\0';
1543
1544         if (!strncmp(this_opt, "mode:", 5)) {
1545                 return parse_opt_mode(dev, this_opt);
1546         } else if (!strncmp(this_opt, "pixclock:", 9)) {
1547                 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1548                 sprintf(s, "pixclock: %ld\n", mode->pixclock);
1549         } else if (!strncmp(this_opt, "left:", 5)) {
1550                 mode->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1551                 sprintf(s, "left: %u\n", mode->left_margin);
1552         } else if (!strncmp(this_opt, "right:", 6)) {
1553                 mode->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1554                 sprintf(s, "right: %u\n", mode->right_margin);
1555         } else if (!strncmp(this_opt, "upper:", 6)) {
1556                 mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1557                 sprintf(s, "upper: %u\n", mode->upper_margin);
1558         } else if (!strncmp(this_opt, "lower:", 6)) {
1559                 mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1560                 sprintf(s, "lower: %u\n", mode->lower_margin);
1561         } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1562                 mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1563                 sprintf(s, "hsynclen: %u\n", mode->hsync_len);
1564         } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1565                 mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1566                 sprintf(s, "vsynclen: %u\n", mode->vsync_len);
1567         } else if (!strncmp(this_opt, "hsync:", 6)) {
1568                 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1569                         sprintf(s, "hsync: Active Low\n");
1570                         mode->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1571                 } else {
1572                         sprintf(s, "hsync: Active High\n");
1573                         mode->sync |= FB_SYNC_HOR_HIGH_ACT;
1574                 }
1575         } else if (!strncmp(this_opt, "vsync:", 6)) {
1576                 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1577                         sprintf(s, "vsync: Active Low\n");
1578                         mode->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1579                 } else {
1580                         sprintf(s, "vsync: Active High\n");
1581                         mode->sync |= FB_SYNC_VERT_HIGH_ACT;
1582                 }
1583         } else if (!strncmp(this_opt, "dpc:", 4)) {
1584                 if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1585                         sprintf(s, "double pixel clock: false\n");
1586                         inf->lccr3 &= ~LCCR3_DPC;
1587                 } else {
1588                         sprintf(s, "double pixel clock: true\n");
1589                         inf->lccr3 |= LCCR3_DPC;
1590                 }
1591         } else if (!strncmp(this_opt, "outputen:", 9)) {
1592                 if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1593                         sprintf(s, "output enable: active low\n");
1594                         inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1595                 } else {
1596                         sprintf(s, "output enable: active high\n");
1597                         inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1598                 }
1599         } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1600                 if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1601                         sprintf(s, "pixel clock polarity: falling edge\n");
1602                         inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1603                 } else {
1604                         sprintf(s, "pixel clock polarity: rising edge\n");
1605                         inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1606                 }
1607         } else if (!strncmp(this_opt, "color", 5)) {
1608                 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1609         } else if (!strncmp(this_opt, "mono", 4)) {
1610                 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1611         } else if (!strncmp(this_opt, "active", 6)) {
1612                 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1613         } else if (!strncmp(this_opt, "passive", 7)) {
1614                 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1615         } else if (!strncmp(this_opt, "single", 6)) {
1616                 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1617         } else if (!strncmp(this_opt, "dual", 4)) {
1618                 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1619         } else if (!strncmp(this_opt, "4pix", 4)) {
1620                 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1621         } else if (!strncmp(this_opt, "8pix", 4)) {
1622                 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1623         } else {
1624                 dev_err(dev, "unknown option: %s\n", this_opt);
1625                 return -EINVAL;
1626         }
1627
1628         if (s[0] != '\0')
1629                 dev_info(dev, "override %s", s);
1630
1631         return 0;
1632 }
1633
1634 static int __devinit pxafb_parse_options(struct device *dev, char *options)
1635 {
1636         char *this_opt;
1637         int ret;
1638
1639         if (!options || !*options)
1640                 return 0;
1641
1642         dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1643
1644         /* could be made table driven or similar?... */
1645         while ((this_opt = strsep(&options, ",")) != NULL) {
1646                 ret = parse_opt(dev, this_opt);
1647                 if (ret)
1648                         return ret;
1649         }
1650         return 0;
1651 }
1652
1653 static char g_options[256] __devinitdata = "";
1654
1655 #ifndef MODULE
1656 static int __init pxafb_setup_options(void)
1657 {
1658         char *options = NULL;
1659
1660         if (fb_get_options("pxafb", &options))
1661                 return -ENODEV;
1662
1663         if (options)
1664                 strlcpy(g_options, options, sizeof(g_options));
1665
1666         return 0;
1667 }
1668 #else
1669 #define pxafb_setup_options()           (0)
1670
1671 module_param_string(options, g_options, sizeof(g_options), 0);
1672 MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1673 #endif
1674
1675 #else
1676 #define pxafb_parse_options(...)        (0)
1677 #define pxafb_setup_options()           (0)
1678 #endif
1679
1680 #ifdef DEBUG_VAR
1681 /* Check for various illegal bit-combinations. Currently only
1682  * a warning is given. */
1683 static void __devinit pxafb_check_options(struct device *dev,
1684                                           struct pxafb_mach_info *inf)
1685 {
1686         if (inf->lcd_conn)
1687                 return;
1688
1689         if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
1690                 dev_warn(dev, "machine LCCR0 setting contains "
1691                                 "illegal bits: %08x\n",
1692                         inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
1693         if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
1694                 dev_warn(dev, "machine LCCR3 setting contains "
1695                                 "illegal bits: %08x\n",
1696                         inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
1697         if (inf->lccr0 & LCCR0_DPD &&
1698             ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
1699              (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
1700              (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
1701                 dev_warn(dev, "Double Pixel Data (DPD) mode is "
1702                                 "only valid in passive mono"
1703                                 " single panel mode\n");
1704         if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
1705             (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
1706                 dev_warn(dev, "Dual panel only valid in passive mode\n");
1707         if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
1708              (inf->modes->upper_margin || inf->modes->lower_margin))
1709                 dev_warn(dev, "Upper and lower margins must be 0 in "
1710                                 "passive mode\n");
1711 }
1712 #else
1713 #define pxafb_check_options(...)        do {} while (0)
1714 #endif
1715
1716 static int __devinit pxafb_probe(struct platform_device *dev)
1717 {
1718         struct pxafb_info *fbi;
1719         struct pxafb_mach_info *inf;
1720         struct resource *r;
1721         int irq, ret;
1722
1723         dev_dbg(&dev->dev, "pxafb_probe\n");
1724
1725         inf = dev->dev.platform_data;
1726         ret = -ENOMEM;
1727         fbi = NULL;
1728         if (!inf)
1729                 goto failed;
1730
1731         ret = pxafb_parse_options(&dev->dev, g_options);
1732         if (ret < 0)
1733                 goto failed;
1734
1735         pxafb_check_options(&dev->dev, inf);
1736
1737         dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
1738                         inf->modes->xres,
1739                         inf->modes->yres,
1740                         inf->modes->bpp);
1741         if (inf->modes->xres == 0 ||
1742             inf->modes->yres == 0 ||
1743             inf->modes->bpp == 0) {
1744                 dev_err(&dev->dev, "Invalid resolution or bit depth\n");
1745                 ret = -EINVAL;
1746                 goto failed;
1747         }
1748         pxafb_backlight_power = inf->pxafb_backlight_power;
1749         pxafb_lcd_power = inf->pxafb_lcd_power;
1750         fbi = pxafb_init_fbinfo(&dev->dev);
1751         if (!fbi) {
1752                 /* only reason for pxafb_init_fbinfo to fail is kmalloc */
1753                 dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
1754                 ret = -ENOMEM;
1755                 goto failed;
1756         }
1757
1758         r = platform_get_resource(dev, IORESOURCE_MEM, 0);
1759         if (r == NULL) {
1760                 dev_err(&dev->dev, "no I/O memory resource defined\n");
1761                 ret = -ENODEV;
1762                 goto failed_fbi;
1763         }
1764
1765         r = request_mem_region(r->start, r->end - r->start + 1, dev->name);
1766         if (r == NULL) {
1767                 dev_err(&dev->dev, "failed to request I/O memory\n");
1768                 ret = -EBUSY;
1769                 goto failed_fbi;
1770         }
1771
1772         fbi->mmio_base = ioremap(r->start, r->end - r->start + 1);
1773         if (fbi->mmio_base == NULL) {
1774                 dev_err(&dev->dev, "failed to map I/O memory\n");
1775                 ret = -EBUSY;
1776                 goto failed_free_res;
1777         }
1778
1779         /* Initialize video memory */
1780         ret = pxafb_map_video_memory(fbi);
1781         if (ret) {
1782                 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
1783                 ret = -ENOMEM;
1784                 goto failed_free_io;
1785         }
1786
1787         irq = platform_get_irq(dev, 0);
1788         if (irq < 0) {
1789                 dev_err(&dev->dev, "no IRQ defined\n");
1790                 ret = -ENODEV;
1791                 goto failed_free_mem;
1792         }
1793
1794         ret = request_irq(irq, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi);
1795         if (ret) {
1796                 dev_err(&dev->dev, "request_irq failed: %d\n", ret);
1797                 ret = -EBUSY;
1798                 goto failed_free_mem;
1799         }
1800
1801 #ifdef CONFIG_FB_PXA_SMARTPANEL
1802         ret = pxafb_smart_init(fbi);
1803         if (ret) {
1804                 dev_err(&dev->dev, "failed to initialize smartpanel\n");
1805                 goto failed_free_irq;
1806         }
1807 #endif
1808         /*
1809          * This makes sure that our colour bitfield
1810          * descriptors are correctly initialised.
1811          */
1812         ret = pxafb_check_var(&fbi->fb.var, &fbi->fb);
1813         if (ret) {
1814                 dev_err(&dev->dev, "failed to get suitable mode\n");
1815                 goto failed_free_irq;
1816         }
1817
1818         ret = pxafb_set_par(&fbi->fb);
1819         if (ret) {
1820                 dev_err(&dev->dev, "Failed to set parameters\n");
1821                 goto failed_free_irq;
1822         }
1823
1824         platform_set_drvdata(dev, fbi);
1825
1826         ret = register_framebuffer(&fbi->fb);
1827         if (ret < 0) {
1828                 dev_err(&dev->dev,
1829                         "Failed to register framebuffer device: %d\n", ret);
1830                 goto failed_free_cmap;
1831         }
1832
1833 #ifdef CONFIG_CPU_FREQ
1834         fbi->freq_transition.notifier_call = pxafb_freq_transition;
1835         fbi->freq_policy.notifier_call = pxafb_freq_policy;
1836         cpufreq_register_notifier(&fbi->freq_transition,
1837                                 CPUFREQ_TRANSITION_NOTIFIER);
1838         cpufreq_register_notifier(&fbi->freq_policy,
1839                                 CPUFREQ_POLICY_NOTIFIER);
1840 #endif
1841
1842         /*
1843          * Ok, now enable the LCD controller
1844          */
1845         set_ctrlr_state(fbi, C_ENABLE);
1846
1847         return 0;
1848
1849 failed_free_cmap:
1850         if (fbi->fb.cmap.len)
1851                 fb_dealloc_cmap(&fbi->fb.cmap);
1852 failed_free_irq:
1853         free_irq(irq, fbi);
1854 failed_free_mem:
1855         dma_free_writecombine(&dev->dev, fbi->map_size,
1856                         fbi->map_cpu, fbi->map_dma);
1857 failed_free_io:
1858         iounmap(fbi->mmio_base);
1859 failed_free_res:
1860         release_mem_region(r->start, r->end - r->start + 1);
1861 failed_fbi:
1862         clk_put(fbi->clk);
1863         platform_set_drvdata(dev, NULL);
1864         kfree(fbi);
1865 failed:
1866         return ret;
1867 }
1868
1869 static int __devexit pxafb_remove(struct platform_device *dev)
1870 {
1871         struct pxafb_info *fbi = platform_get_drvdata(dev);
1872         struct resource *r;
1873         int irq;
1874         struct fb_info *info;
1875
1876         if (!fbi)
1877                 return 0;
1878
1879         info = &fbi->fb;
1880
1881         unregister_framebuffer(info);
1882
1883         pxafb_disable_controller(fbi);
1884
1885         if (fbi->fb.cmap.len)
1886                 fb_dealloc_cmap(&fbi->fb.cmap);
1887
1888         irq = platform_get_irq(dev, 0);
1889         free_irq(irq, fbi);
1890
1891         dma_free_writecombine(&dev->dev, fbi->map_size,
1892                                         fbi->map_cpu, fbi->map_dma);
1893
1894         iounmap(fbi->mmio_base);
1895
1896         r = platform_get_resource(dev, IORESOURCE_MEM, 0);
1897         release_mem_region(r->start, r->end - r->start + 1);
1898
1899         clk_put(fbi->clk);
1900         kfree(fbi);
1901
1902         return 0;
1903 }
1904
1905 static struct platform_driver pxafb_driver = {
1906         .probe          = pxafb_probe,
1907         .remove         = pxafb_remove,
1908         .suspend        = pxafb_suspend,
1909         .resume         = pxafb_resume,
1910         .driver         = {
1911                 .owner  = THIS_MODULE,
1912                 .name   = "pxa2xx-fb",
1913         },
1914 };
1915
1916 static int __init pxafb_init(void)
1917 {
1918         if (pxafb_setup_options())
1919                 return -EINVAL;
1920
1921         return platform_driver_register(&pxafb_driver);
1922 }
1923
1924 static void __exit pxafb_exit(void)
1925 {
1926         platform_driver_unregister(&pxafb_driver);
1927 }
1928
1929 module_init(pxafb_init);
1930 module_exit(pxafb_exit);
1931
1932 MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
1933 MODULE_LICENSE("GPL");