Merge branch 'master' into upstream
[linux-2.6] / arch / arm / mm / proc-arm6_7.S
1 /*
2  *  linux/arch/arm/mm/proc-arm6,7.S
3  *
4  *  Copyright (C) 1997-2000 Russell King
5  *  hacked for non-paged-MM by Hyok S. Choi, 2003.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  *
11  *  These are the low level assembler for performing cache and TLB
12  *  functions on the ARM610 & ARM710.
13  */
14 #include <linux/linkage.h>
15 #include <linux/init.h>
16 #include <asm/assembler.h>
17 #include <asm/asm-offsets.h>
18 #include <asm/pgtable-hwdef.h>
19 #include <asm/pgtable.h>
20 #include <asm/procinfo.h>
21 #include <asm/ptrace.h>
22
23 ENTRY(cpu_arm6_dcache_clean_area)
24 ENTRY(cpu_arm7_dcache_clean_area)
25                 mov     pc, lr
26
27 /*
28  * Function: arm6_7_data_abort ()
29  *
30  * Params  : r2 = address of aborted instruction
31  *         : sp = pointer to registers
32  *
33  * Purpose : obtain information about current aborted instruction
34  *
35  * Returns : r0 = address of abort
36  *         : r1 = FSR
37  */
38
39 ENTRY(cpu_arm7_data_abort)
40         mrc     p15, 0, r1, c5, c0, 0           @ get FSR
41         mrc     p15, 0, r0, c6, c0, 0           @ get FAR
42         ldr     r8, [r0]                        @ read arm instruction
43         tst     r8, #1 << 20                    @ L = 0 -> write?
44         orreq   r1, r1, #1 << 11                @ yes.
45         and     r7, r8, #15 << 24
46         add     pc, pc, r7, lsr #22             @ Now branch to the relevant processing routine
47         nop
48
49 /* 0 */ b       .data_unknown
50 /* 1 */ mov     pc, lr                          @ swp
51 /* 2 */ b       .data_unknown
52 /* 3 */ b       .data_unknown
53 /* 4 */ b       .data_arm_lateldrpostconst      @ ldr   rd, [rn], #m
54 /* 5 */ b       .data_arm_lateldrpreconst       @ ldr   rd, [rn, #m]
55 /* 6 */ b       .data_arm_lateldrpostreg        @ ldr   rd, [rn], rm
56 /* 7 */ b       .data_arm_lateldrprereg         @ ldr   rd, [rn, rm]
57 /* 8 */ b       .data_arm_ldmstm                @ ldm*a rn, <rlist>
58 /* 9 */ b       .data_arm_ldmstm                @ ldm*b rn, <rlist>
59 /* a */ b       .data_unknown
60 /* b */ b       .data_unknown
61 /* c */ mov     pc, lr                          @ ldc   rd, [rn], #m    @ Same as ldr   rd, [rn], #m
62 /* d */ mov     pc, lr                          @ ldc   rd, [rn, #m]
63 /* e */ b       .data_unknown
64 /* f */
65 .data_unknown:  @ Part of jumptable
66         mov     r0, r2
67         mov     r1, r8
68         mov     r2, sp
69         bl      baddataabort
70         b       ret_from_exception
71
72 ENTRY(cpu_arm6_data_abort)
73         mrc     p15, 0, r1, c5, c0, 0           @ get FSR
74         mrc     p15, 0, r0, c6, c0, 0           @ get FAR
75         ldr     r8, [r2]                        @ read arm instruction
76         tst     r8, #1 << 20                    @ L = 0 -> write?
77         orreq   r1, r1, #1 << 11                @ yes.
78         and     r7, r8, #14 << 24
79         teq     r7, #8 << 24                    @ was it ldm/stm
80         movne   pc, lr
81
82 .data_arm_ldmstm:
83         tst     r8, #1 << 21                    @ check writeback bit
84         moveq   pc, lr                          @ no writeback -> no fixup
85         mov     r7, #0x11
86         orr     r7, r7, #0x1100
87         and     r6, r8, r7
88         and     r2, r8, r7, lsl #1
89         add     r6, r6, r2, lsr #1
90         and     r2, r8, r7, lsl #2
91         add     r6, r6, r2, lsr #2
92         and     r2, r8, r7, lsl #3
93         add     r6, r6, r2, lsr #3
94         add     r6, r6, r6, lsr #8
95         add     r6, r6, r6, lsr #4
96         and     r6, r6, #15                     @ r6 = no. of registers to transfer.
97         and     r5, r8, #15 << 16               @ Extract 'n' from instruction
98         ldr     r7, [sp, r5, lsr #14]           @ Get register 'Rn'
99         tst     r8, #1 << 23                    @ Check U bit
100         subne   r7, r7, r6, lsl #2              @ Undo increment
101         addeq   r7, r7, r6, lsl #2              @ Undo decrement
102         str     r7, [sp, r5, lsr #14]           @ Put register 'Rn'
103         mov     pc, lr
104
105 .data_arm_apply_r6_and_rn:
106         and     r5, r8, #15 << 16               @ Extract 'n' from instruction
107         ldr     r7, [sp, r5, lsr #14]           @ Get register 'Rn'
108         tst     r8, #1 << 23                    @ Check U bit
109         subne   r7, r7, r6                      @ Undo incrmenet
110         addeq   r7, r7, r6                      @ Undo decrement
111         str     r7, [sp, r5, lsr #14]           @ Put register 'Rn'
112         mov     pc, lr
113
114 .data_arm_lateldrpreconst:
115         tst     r8, #1 << 21                    @ check writeback bit
116         moveq   pc, lr                          @ no writeback -> no fixup
117 .data_arm_lateldrpostconst:
118         movs    r2, r8, lsl #20                 @ Get offset
119         moveq   pc, lr                          @ zero -> no fixup
120         and     r5, r8, #15 << 16               @ Extract 'n' from instruction
121         ldr     r7, [sp, r5, lsr #14]           @ Get register 'Rn'
122         tst     r8, #1 << 23                    @ Check U bit
123         subne   r7, r7, r2, lsr #20             @ Undo increment
124         addeq   r7, r7, r2, lsr #20             @ Undo decrement
125         str     r7, [sp, r5, lsr #14]           @ Put register 'Rn'
126         mov     pc, lr
127
128 .data_arm_lateldrprereg:
129         tst     r8, #1 << 21                    @ check writeback bit
130         moveq   pc, lr                          @ no writeback -> no fixup
131 .data_arm_lateldrpostreg:
132         and     r7, r8, #15                     @ Extract 'm' from instruction
133         ldr     r6, [sp, r7, lsl #2]            @ Get register 'Rm'
134         mov     r5, r8, lsr #7                  @ get shift count
135         ands    r5, r5, #31
136         and     r7, r8, #0x70                   @ get shift type
137         orreq   r7, r7, #8                      @ shift count = 0
138         add     pc, pc, r7
139         nop
140
141         mov     r6, r6, lsl r5                  @ 0: LSL #!0
142         b       .data_arm_apply_r6_and_rn
143         b       .data_arm_apply_r6_and_rn       @ 1: LSL #0
144         nop
145         b       .data_unknown                   @ 2: MUL?
146         nop
147         b       .data_unknown                   @ 3: MUL?
148         nop
149         mov     r6, r6, lsr r5                  @ 4: LSR #!0
150         b       .data_arm_apply_r6_and_rn
151         mov     r6, r6, lsr #32                 @ 5: LSR #32
152         b       .data_arm_apply_r6_and_rn
153         b       .data_unknown                   @ 6: MUL?
154         nop
155         b       .data_unknown                   @ 7: MUL?
156         nop
157         mov     r6, r6, asr r5                  @ 8: ASR #!0
158         b       .data_arm_apply_r6_and_rn
159         mov     r6, r6, asr #32                 @ 9: ASR #32
160         b       .data_arm_apply_r6_and_rn
161         b       .data_unknown                   @ A: MUL?
162         nop
163         b       .data_unknown                   @ B: MUL?
164         nop
165         mov     r6, r6, ror r5                  @ C: ROR #!0
166         b       .data_arm_apply_r6_and_rn
167         mov     r6, r6, rrx                     @ D: RRX
168         b       .data_arm_apply_r6_and_rn
169         b       .data_unknown                   @ E: MUL?
170         nop
171         b       .data_unknown                   @ F: MUL?
172
173 /*
174  * Function: arm6_7_proc_init (void)
175  *         : arm6_7_proc_fin (void)
176  *
177  * Notes   : This processor does not require these
178  */
179 ENTRY(cpu_arm6_proc_init)
180 ENTRY(cpu_arm7_proc_init)
181                 mov     pc, lr
182
183 ENTRY(cpu_arm6_proc_fin)
184 ENTRY(cpu_arm7_proc_fin)
185                 mov     r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
186                 msr     cpsr_c, r0
187                 mov     r0, #0x31                       @ ....S..DP...M
188                 mcr     p15, 0, r0, c1, c0, 0           @ disable caches
189                 mov     pc, lr
190
191 ENTRY(cpu_arm6_do_idle)
192 ENTRY(cpu_arm7_do_idle)
193                 mov     pc, lr
194
195 /*
196  * Function: arm6_7_switch_mm(unsigned long pgd_phys)
197  * Params  : pgd_phys   Physical address of page table
198  * Purpose : Perform a task switch, saving the old processes state, and restoring
199  *           the new.
200  */
201 ENTRY(cpu_arm6_switch_mm)
202 ENTRY(cpu_arm7_switch_mm)
203 #ifdef CONFIG_MMU
204                 mov     r1, #0
205                 mcr     p15, 0, r1, c7, c0, 0           @ flush cache
206                 mcr     p15, 0, r0, c2, c0, 0           @ update page table ptr
207                 mcr     p15, 0, r1, c5, c0, 0           @ flush TLBs
208 #endif
209                 mov     pc, lr
210
211 /*
212  * Function: arm6_7_set_pte(pte_t *ptep, pte_t pte)
213  * Params  : r0 = Address to set
214  *         : r1 = value to set
215  * Purpose : Set a PTE and flush it out of any WB cache
216  */
217                 .align  5
218 ENTRY(cpu_arm6_set_pte)
219 ENTRY(cpu_arm7_set_pte)
220 #ifdef CONFIG_MMU
221                 str     r1, [r0], #-2048                @ linux version
222
223                 eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
224
225                 bic     r2, r1, #PTE_SMALL_AP_MASK
226                 bic     r2, r2, #PTE_TYPE_MASK
227                 orr     r2, r2, #PTE_TYPE_SMALL
228
229                 tst     r1, #L_PTE_USER                 @ User?
230                 orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
231
232                 tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
233                 orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
234
235                 tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young
236                 movne   r2, #0
237
238                 str     r2, [r0]                        @ hardware version
239 #endif /* CONFIG_MMU */
240                 mov     pc, lr
241
242 /*
243  * Function: _arm6_7_reset
244  * Params  : r0 = address to jump to
245  * Notes   : This sets up everything for a reset
246  */
247 ENTRY(cpu_arm6_reset)
248 ENTRY(cpu_arm7_reset)
249                 mov     r1, #0
250                 mcr     p15, 0, r1, c7, c0, 0           @ flush cache
251 #ifdef CONFIG_MMU
252                 mcr     p15, 0, r1, c5, c0, 0           @ flush TLB
253 #endif
254                 mov     r1, #0x30
255                 mcr     p15, 0, r1, c1, c0, 0           @ turn off MMU etc
256                 mov     pc, r0
257
258                 __INIT
259
260                 .type   __arm6_setup, #function
261 __arm6_setup:   mov     r0, #0
262                 mcr     p15, 0, r0, c7, c0              @ flush caches on v3
263 #ifdef CONFIG_MMU
264                 mcr     p15, 0, r0, c5, c0              @ flush TLBs on v3
265                 mov     r0, #0x3d                       @ . ..RS BLDP WCAM
266                 orr     r0, r0, #0x100                  @ . ..01 0011 1101
267 #else
268                 mov     r0, #0x3c                       @ . ..RS BLDP WCA.
269 #endif
270                 mov     pc, lr
271                 .size   __arm6_setup, . - __arm6_setup
272
273                 .type   __arm7_setup, #function
274 __arm7_setup:   mov     r0, #0
275                 mcr     p15, 0, r0, c7, c0              @ flush caches on v3
276 #ifdef CONFIG_MMU
277                 mcr     p15, 0, r0, c5, c0              @ flush TLBs on v3
278                 mcr     p15, 0, r0, c3, c0              @ load domain access register
279                 mov     r0, #0x7d                       @ . ..RS BLDP WCAM
280                 orr     r0, r0, #0x100                  @ . ..01 0111 1101
281 #else
282                 mov     r0, #0x7c                       @ . ..RS BLDP WCA.
283 #endif
284                 mov     pc, lr
285                 .size   __arm7_setup, . - __arm7_setup
286
287                 __INITDATA
288
289 /*
290  * Purpose : Function pointers used to access above functions - all calls
291  *           come through these
292  */
293                 .type   arm6_processor_functions, #object
294 ENTRY(arm6_processor_functions)
295                 .word   cpu_arm6_data_abort
296                 .word   cpu_arm6_proc_init
297                 .word   cpu_arm6_proc_fin
298                 .word   cpu_arm6_reset
299                 .word   cpu_arm6_do_idle
300                 .word   cpu_arm6_dcache_clean_area
301                 .word   cpu_arm6_switch_mm
302                 .word   cpu_arm6_set_pte
303                 .size   arm6_processor_functions, . - arm6_processor_functions
304
305 /*
306  * Purpose : Function pointers used to access above functions - all calls
307  *           come through these
308  */
309                 .type   arm7_processor_functions, #object
310 ENTRY(arm7_processor_functions)
311                 .word   cpu_arm7_data_abort
312                 .word   cpu_arm7_proc_init
313                 .word   cpu_arm7_proc_fin
314                 .word   cpu_arm7_reset
315                 .word   cpu_arm7_do_idle
316                 .word   cpu_arm7_dcache_clean_area
317                 .word   cpu_arm7_switch_mm
318                 .word   cpu_arm7_set_pte
319                 .size   arm7_processor_functions, . - arm7_processor_functions
320
321                 .section ".rodata"
322
323                 .type   cpu_arch_name, #object
324 cpu_arch_name:  .asciz  "armv3"
325                 .size   cpu_arch_name, . - cpu_arch_name
326
327                 .type   cpu_elf_name, #object
328 cpu_elf_name:   .asciz  "v3"
329                 .size   cpu_elf_name, . - cpu_elf_name
330
331                 .type   cpu_arm6_name, #object
332 cpu_arm6_name:  .asciz  "ARM6"
333                 .size   cpu_arm6_name, . - cpu_arm6_name
334
335                 .type   cpu_arm610_name, #object
336 cpu_arm610_name:
337                 .asciz  "ARM610"
338                 .size   cpu_arm610_name, . - cpu_arm610_name
339
340                 .type   cpu_arm7_name, #object
341 cpu_arm7_name:  .asciz  "ARM7"
342                 .size   cpu_arm7_name, . - cpu_arm7_name
343
344                 .type   cpu_arm710_name, #object
345 cpu_arm710_name:
346                 .asciz  "ARM710"
347                 .size   cpu_arm710_name, . - cpu_arm710_name
348
349                 .align
350
351                 .section ".proc.info.init", #alloc, #execinstr
352
353                 .type   __arm6_proc_info, #object
354 __arm6_proc_info:
355                 .long   0x41560600
356                 .long   0xfffffff0
357                 .long   0x00000c1e
358                 .long   PMD_TYPE_SECT | \
359                         PMD_BIT4 | \
360                         PMD_SECT_AP_WRITE | \
361                         PMD_SECT_AP_READ
362                 b       __arm6_setup
363                 .long   cpu_arch_name
364                 .long   cpu_elf_name
365                 .long   HWCAP_SWP | HWCAP_26BIT
366                 .long   cpu_arm6_name
367                 .long   arm6_processor_functions
368                 .long   v3_tlb_fns
369                 .long   v3_user_fns
370                 .long   v3_cache_fns
371                 .size   __arm6_proc_info, . - __arm6_proc_info
372
373                 .type   __arm610_proc_info, #object
374 __arm610_proc_info:
375                 .long   0x41560610
376                 .long   0xfffffff0
377                 .long   0x00000c1e
378                 .long   PMD_TYPE_SECT | \
379                         PMD_BIT4 | \
380                         PMD_SECT_AP_WRITE | \
381                         PMD_SECT_AP_READ
382                 b       __arm6_setup
383                 .long   cpu_arch_name
384                 .long   cpu_elf_name
385                 .long   HWCAP_SWP | HWCAP_26BIT
386                 .long   cpu_arm610_name
387                 .long   arm6_processor_functions
388                 .long   v3_tlb_fns
389                 .long   v3_user_fns
390                 .long   v3_cache_fns
391                 .size   __arm610_proc_info, . - __arm610_proc_info
392
393                 .type   __arm7_proc_info, #object
394 __arm7_proc_info:
395                 .long   0x41007000
396                 .long   0xffffff00
397                 .long   0x00000c1e
398                 .long   PMD_TYPE_SECT | \
399                         PMD_BIT4 | \
400                         PMD_SECT_AP_WRITE | \
401                         PMD_SECT_AP_READ
402                 b       __arm7_setup
403                 .long   cpu_arch_name
404                 .long   cpu_elf_name
405                 .long   HWCAP_SWP | HWCAP_26BIT
406                 .long   cpu_arm7_name
407                 .long   arm7_processor_functions
408                 .long   v3_tlb_fns
409                 .long   v3_user_fns
410                 .long   v3_cache_fns
411                 .size   __arm7_proc_info, . - __arm7_proc_info
412
413                 .type   __arm710_proc_info, #object
414 __arm710_proc_info:
415                 .long   0x41007100
416                 .long   0xfff8ff00
417                 .long   PMD_TYPE_SECT | \
418                         PMD_SECT_BUFFERABLE | \
419                         PMD_SECT_CACHEABLE | \
420                         PMD_BIT4 | \
421                         PMD_SECT_AP_WRITE | \
422                         PMD_SECT_AP_READ
423                 .long   PMD_TYPE_SECT | \
424                         PMD_BIT4 | \
425                         PMD_SECT_AP_WRITE | \
426                         PMD_SECT_AP_READ
427                 b       __arm7_setup
428                 .long   cpu_arch_name
429                 .long   cpu_elf_name
430                 .long   HWCAP_SWP | HWCAP_26BIT
431                 .long   cpu_arm710_name
432                 .long   arm7_processor_functions
433                 .long   v3_tlb_fns
434                 .long   v3_user_fns
435                 .long   v3_cache_fns
436                 .size   __arm710_proc_info, . - __arm710_proc_info