2 * SuperH Timer Support - CMT
4 * Copyright (C) 2008 Magnus Damm
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/init.h>
21 #include <linux/bootmem.h>
22 #include <linux/platform_device.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/ioport.h>
27 #include <linux/clk.h>
28 #include <linux/irq.h>
29 #include <linux/err.h>
30 #include <linux/clocksource.h>
31 #include <linux/clockchips.h>
32 #include <linux/sh_cmt.h>
35 void __iomem *mapbase;
37 unsigned long width; /* 16 or 32 bit version of hardware block */
38 unsigned long overflow_bit;
39 unsigned long clear_bits;
40 struct irqaction irqaction;
41 struct platform_device *pdev;
44 unsigned long match_value;
45 unsigned long next_match_value;
46 unsigned long max_match_value;
49 struct clock_event_device ced;
50 unsigned long total_cycles;
53 static DEFINE_SPINLOCK(sh_cmt_lock);
55 #define CMSTR -1 /* shared register */
56 #define CMCSR 0 /* channel register */
57 #define CMCNT 1 /* channel register */
58 #define CMCOR 2 /* channel register */
60 static inline unsigned long sh_cmt_read(struct sh_cmt_priv *p, int reg_nr)
62 struct sh_cmt_config *cfg = p->pdev->dev.platform_data;
63 void __iomem *base = p->mapbase;
66 if (reg_nr == CMSTR) {
68 base -= cfg->channel_offset;
76 if ((reg_nr == CMCNT) || (reg_nr == CMCOR))
77 return ioread32(base + offs);
80 return ioread16(base + offs);
83 static inline void sh_cmt_write(struct sh_cmt_priv *p, int reg_nr,
86 struct sh_cmt_config *cfg = p->pdev->dev.platform_data;
87 void __iomem *base = p->mapbase;
90 if (reg_nr == CMSTR) {
92 base -= cfg->channel_offset;
100 if ((reg_nr == CMCNT) || (reg_nr == CMCOR)) {
101 iowrite32(value, base + offs);
106 iowrite16(value, base + offs);
109 static unsigned long sh_cmt_get_counter(struct sh_cmt_priv *p,
112 unsigned long v1, v2, v3;
114 /* Make sure the timer value is stable. Stolen from acpi_pm.c */
116 v1 = sh_cmt_read(p, CMCNT);
117 v2 = sh_cmt_read(p, CMCNT);
118 v3 = sh_cmt_read(p, CMCNT);
119 } while (unlikely((v1 > v2 && v1 < v3) || (v2 > v3 && v2 < v1)
120 || (v3 > v1 && v3 < v2)));
122 *has_wrapped = sh_cmt_read(p, CMCSR) & p->overflow_bit;
127 static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start)
129 struct sh_cmt_config *cfg = p->pdev->dev.platform_data;
130 unsigned long flags, value;
132 /* start stop register shared by multiple timer channels */
133 spin_lock_irqsave(&sh_cmt_lock, flags);
134 value = sh_cmt_read(p, CMSTR);
137 value |= 1 << cfg->timer_bit;
139 value &= ~(1 << cfg->timer_bit);
141 sh_cmt_write(p, CMSTR, value);
142 spin_unlock_irqrestore(&sh_cmt_lock, flags);
145 static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate)
147 struct sh_cmt_config *cfg = p->pdev->dev.platform_data;
151 ret = clk_enable(p->clk);
153 pr_err("sh_cmt: cannot enable clock \"%s\"\n", cfg->clk);
156 *rate = clk_get_rate(p->clk) / 8;
158 /* make sure channel is disabled */
159 sh_cmt_start_stop_ch(p, 0);
161 /* configure channel, periodic mode and maximum timeout */
163 sh_cmt_write(p, CMCSR, 0);
165 sh_cmt_write(p, CMCSR, 0x01a4);
167 sh_cmt_write(p, CMCOR, 0xffffffff);
168 sh_cmt_write(p, CMCNT, 0);
171 sh_cmt_start_stop_ch(p, 1);
175 static void sh_cmt_disable(struct sh_cmt_priv *p)
177 /* disable channel */
178 sh_cmt_start_stop_ch(p, 0);
185 #define FLAG_CLOCKEVENT (1 << 0)
186 #define FLAG_CLOCKSOURCE (1 << 1)
187 #define FLAG_REPROGRAM (1 << 2)
188 #define FLAG_SKIPEVENT (1 << 3)
189 #define FLAG_IRQCONTEXT (1 << 4)
191 static void sh_cmt_clock_event_program_verify(struct sh_cmt_priv *p,
194 unsigned long new_match;
195 unsigned long value = p->next_match_value;
196 unsigned long delay = 0;
197 unsigned long now = 0;
200 now = sh_cmt_get_counter(p, &has_wrapped);
201 p->flags |= FLAG_REPROGRAM; /* force reprogram */
204 /* we're competing with the interrupt handler.
205 * -> let the interrupt handler reprogram the timer.
206 * -> interrupt number two handles the event.
208 p->flags |= FLAG_SKIPEVENT;
216 /* reprogram the timer hardware,
217 * but don't save the new match value yet.
219 new_match = now + value + delay;
220 if (new_match > p->max_match_value)
221 new_match = p->max_match_value;
223 sh_cmt_write(p, CMCOR, new_match);
225 now = sh_cmt_get_counter(p, &has_wrapped);
226 if (has_wrapped && (new_match > p->match_value)) {
227 /* we are changing to a greater match value,
228 * so this wrap must be caused by the counter
229 * matching the old value.
230 * -> first interrupt reprograms the timer.
231 * -> interrupt number two handles the event.
233 p->flags |= FLAG_SKIPEVENT;
238 /* we are changing to a smaller match value,
239 * so the wrap must be caused by the counter
240 * matching the new value.
241 * -> save programmed match value.
242 * -> let isr handle the event.
244 p->match_value = new_match;
248 /* be safe: verify hardware settings */
249 if (now < new_match) {
250 /* timer value is below match value, all good.
251 * this makes sure we won't miss any match events.
252 * -> save programmed match value.
253 * -> let isr handle the event.
255 p->match_value = new_match;
259 /* the counter has reached a value greater
260 * than our new match value. and since the
261 * has_wrapped flag isn't set we must have
262 * programmed a too close event.
263 * -> increase delay and retry.
271 pr_warning("sh_cmt: too long delay\n");
276 static void sh_cmt_set_next(struct sh_cmt_priv *p, unsigned long delta)
280 if (delta > p->max_match_value)
281 pr_warning("sh_cmt: delta out of range\n");
283 spin_lock_irqsave(&p->lock, flags);
284 p->next_match_value = delta;
285 sh_cmt_clock_event_program_verify(p, 0);
286 spin_unlock_irqrestore(&p->lock, flags);
289 static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
291 struct sh_cmt_priv *p = dev_id;
294 sh_cmt_write(p, CMCSR, sh_cmt_read(p, CMCSR) & p->clear_bits);
296 /* update clock source counter to begin with if enabled
297 * the wrap flag should be cleared by the timer specific
298 * isr before we end up here.
300 if (p->flags & FLAG_CLOCKSOURCE)
301 p->total_cycles += p->match_value;
303 if (!(p->flags & FLAG_REPROGRAM))
304 p->next_match_value = p->max_match_value;
306 p->flags |= FLAG_IRQCONTEXT;
308 if (p->flags & FLAG_CLOCKEVENT) {
309 if (!(p->flags & FLAG_SKIPEVENT)) {
310 if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT) {
311 p->next_match_value = p->max_match_value;
312 p->flags |= FLAG_REPROGRAM;
315 p->ced.event_handler(&p->ced);
319 p->flags &= ~FLAG_SKIPEVENT;
321 if (p->flags & FLAG_REPROGRAM) {
322 p->flags &= ~FLAG_REPROGRAM;
323 sh_cmt_clock_event_program_verify(p, 1);
325 if (p->flags & FLAG_CLOCKEVENT)
326 if ((p->ced.mode == CLOCK_EVT_MODE_SHUTDOWN)
327 || (p->match_value == p->next_match_value))
328 p->flags &= ~FLAG_REPROGRAM;
331 p->flags &= ~FLAG_IRQCONTEXT;
336 static int sh_cmt_start(struct sh_cmt_priv *p, unsigned long flag)
341 spin_lock_irqsave(&p->lock, flags);
343 if (!(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
344 ret = sh_cmt_enable(p, &p->rate);
350 /* setup timeout if no clockevent */
351 if ((flag == FLAG_CLOCKSOURCE) && (!(p->flags & FLAG_CLOCKEVENT)))
352 sh_cmt_set_next(p, p->max_match_value);
354 spin_unlock_irqrestore(&p->lock, flags);
359 static void sh_cmt_stop(struct sh_cmt_priv *p, unsigned long flag)
364 spin_lock_irqsave(&p->lock, flags);
366 f = p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);
369 if (f && !(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
372 /* adjust the timeout to maximum if only clocksource left */
373 if ((flag == FLAG_CLOCKEVENT) && (p->flags & FLAG_CLOCKSOURCE))
374 sh_cmt_set_next(p, p->max_match_value);
376 spin_unlock_irqrestore(&p->lock, flags);
379 static struct sh_cmt_priv *ced_to_sh_cmt(struct clock_event_device *ced)
381 return container_of(ced, struct sh_cmt_priv, ced);
384 static void sh_cmt_clock_event_start(struct sh_cmt_priv *p, int periodic)
386 struct clock_event_device *ced = &p->ced;
388 sh_cmt_start(p, FLAG_CLOCKEVENT);
390 /* TODO: calculate good shift from rate and counter bit width */
393 ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
394 ced->max_delta_ns = clockevent_delta2ns(p->max_match_value, ced);
395 ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);
398 sh_cmt_set_next(p, (p->rate + HZ/2) / HZ);
400 sh_cmt_set_next(p, p->max_match_value);
403 static void sh_cmt_clock_event_mode(enum clock_event_mode mode,
404 struct clock_event_device *ced)
406 struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
408 /* deal with old setting first */
410 case CLOCK_EVT_MODE_PERIODIC:
411 case CLOCK_EVT_MODE_ONESHOT:
412 sh_cmt_stop(p, FLAG_CLOCKEVENT);
419 case CLOCK_EVT_MODE_PERIODIC:
420 pr_info("sh_cmt: %s used for periodic clock events\n",
422 sh_cmt_clock_event_start(p, 1);
424 case CLOCK_EVT_MODE_ONESHOT:
425 pr_info("sh_cmt: %s used for oneshot clock events\n",
427 sh_cmt_clock_event_start(p, 0);
429 case CLOCK_EVT_MODE_SHUTDOWN:
430 case CLOCK_EVT_MODE_UNUSED:
431 sh_cmt_stop(p, FLAG_CLOCKEVENT);
438 static int sh_cmt_clock_event_next(unsigned long delta,
439 struct clock_event_device *ced)
441 struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
443 BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
444 if (likely(p->flags & FLAG_IRQCONTEXT))
445 p->next_match_value = delta;
447 sh_cmt_set_next(p, delta);
452 static void sh_cmt_register_clockevent(struct sh_cmt_priv *p,
453 char *name, unsigned long rating)
455 struct clock_event_device *ced = &p->ced;
457 memset(ced, 0, sizeof(*ced));
460 ced->features = CLOCK_EVT_FEAT_PERIODIC;
461 ced->features |= CLOCK_EVT_FEAT_ONESHOT;
462 ced->rating = rating;
463 ced->cpumask = cpumask_of(0);
464 ced->set_next_event = sh_cmt_clock_event_next;
465 ced->set_mode = sh_cmt_clock_event_mode;
467 pr_info("sh_cmt: %s used for clock events\n", ced->name);
468 ced->mult = 1; /* work around misplaced WARN_ON() in clockevents.c */
469 clockevents_register_device(ced);
472 int sh_cmt_register(struct sh_cmt_priv *p, char *name,
473 unsigned long clockevent_rating,
474 unsigned long clocksource_rating)
476 if (p->width == (sizeof(p->max_match_value) * 8))
477 p->max_match_value = ~0;
479 p->max_match_value = (1 << p->width) - 1;
481 p->match_value = p->max_match_value;
482 spin_lock_init(&p->lock);
484 if (clockevent_rating)
485 sh_cmt_register_clockevent(p, name, clockevent_rating);
490 static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
492 struct sh_cmt_config *cfg = pdev->dev.platform_data;
493 struct resource *res;
497 memset(p, 0, sizeof(*p));
501 dev_err(&p->pdev->dev, "missing platform data\n");
505 platform_set_drvdata(pdev, p);
507 res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
509 dev_err(&p->pdev->dev, "failed to get I/O memory\n");
513 irq = platform_get_irq(p->pdev, 0);
515 dev_err(&p->pdev->dev, "failed to get irq\n");
519 /* map memory, let mapbase point to our channel */
520 p->mapbase = ioremap_nocache(res->start, resource_size(res));
521 if (p->mapbase == NULL) {
522 pr_err("sh_cmt: failed to remap I/O memory\n");
526 /* request irq using setup_irq() (too early for request_irq()) */
527 p->irqaction.name = cfg->name;
528 p->irqaction.handler = sh_cmt_interrupt;
529 p->irqaction.dev_id = p;
530 p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL;
531 p->irqaction.mask = CPU_MASK_NONE;
532 ret = setup_irq(irq, &p->irqaction);
534 pr_err("sh_cmt: failed to request irq %d\n", irq);
538 /* get hold of clock */
539 p->clk = clk_get(&p->pdev->dev, cfg->clk);
540 if (IS_ERR(p->clk)) {
541 pr_err("sh_cmt: cannot get clock \"%s\"\n", cfg->clk);
542 ret = PTR_ERR(p->clk);
546 if (resource_size(res) == 6) {
548 p->overflow_bit = 0x80;
549 p->clear_bits = ~0xc0;
552 p->overflow_bit = 0x8000;
553 p->clear_bits = ~0xc000;
556 return sh_cmt_register(p, cfg->name,
557 cfg->clockevent_rating,
558 cfg->clocksource_rating);
567 static int __devinit sh_cmt_probe(struct platform_device *pdev)
569 struct sh_cmt_priv *p = platform_get_drvdata(pdev);
572 p = kmalloc(sizeof(*p), GFP_KERNEL);
574 dev_err(&pdev->dev, "failed to allocate driver data\n");
578 ret = sh_cmt_setup(p, pdev);
582 platform_set_drvdata(pdev, NULL);
587 static int __devexit sh_cmt_remove(struct platform_device *pdev)
589 return -EBUSY; /* cannot unregister clockevent and clocksource */
592 static struct platform_driver sh_cmt_device_driver = {
593 .probe = sh_cmt_probe,
594 .remove = __devexit_p(sh_cmt_remove),
600 static int __init sh_cmt_init(void)
602 return platform_driver_register(&sh_cmt_device_driver);
605 static void __exit sh_cmt_exit(void)
607 platform_driver_unregister(&sh_cmt_device_driver);
610 module_init(sh_cmt_init);
611 module_exit(sh_cmt_exit);
613 MODULE_AUTHOR("Magnus Damm");
614 MODULE_DESCRIPTION("SuperH CMT Timer Driver");
615 MODULE_LICENSE("GPL v2");