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   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/delay.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/workqueue.h>
  25 #include <linux/timer.h>
  26 #include <linux/clk.h>
  27 #include <linux/mmc/host.h>
  28 #include <linux/io.h>
  29 #include <linux/semaphore.h>
  30 #include <mach/dma.h>
  31 #include <mach/hardware.h>
  32 #include <mach/board.h>
  33 #include <mach/mmc.h>
  34 #include <mach/cpu.h>
  35
  36 /* OMAP HSMMC Host Controller Registers */
  37 #define OMAP_HSMMC_SYSCONFIG    0x0010
  38 #define OMAP_HSMMC_CON          0x002C
  39 #define OMAP_HSMMC_BLK          0x0104
  40 #define OMAP_HSMMC_ARG          0x0108
  41 #define OMAP_HSMMC_CMD          0x010C
  42 #define OMAP_HSMMC_RSP10        0x0110
  43 #define OMAP_HSMMC_RSP32        0x0114
  44 #define OMAP_HSMMC_RSP54        0x0118
  45 #define OMAP_HSMMC_RSP76        0x011C
  46 #define OMAP_HSMMC_DATA         0x0120
  47 #define OMAP_HSMMC_HCTL         0x0128
  48 #define OMAP_HSMMC_SYSCTL       0x012C
  49 #define OMAP_HSMMC_STAT         0x0130
  50 #define OMAP_HSMMC_IE           0x0134
  51 #define OMAP_HSMMC_ISE          0x0138
  52 #define OMAP_HSMMC_CAPA         0x0140
  53
  54 #define VS18                    (1 << 26)
  55 #define VS30                    (1 << 25)
  56 #define SDVS18                  (0x5 << 9)
  57 #define SDVS30                  (0x6 << 9)
  58 #define SDVS33                  (0x7 << 9)
  59 #define SDVSCLR                 0xFFFFF1FF
  60 #define SDVSDET                 0x00000400
  61 #define AUTOIDLE                0x1
  62 #define SDBP                    (1 << 8)
  63 #define DTO                     0xe
  64 #define ICE                     0x1
  65 #define ICS                     0x2
  66 #define CEN                     (1 << 2)
  67 #define CLKD_MASK               0x0000FFC0
  68 #define CLKD_SHIFT              6
  69 #define DTO_MASK                0x000F0000
  70 #define DTO_SHIFT               16
  71 #define INT_EN_MASK             0x307F0033
  72 #define INIT_STREAM             (1 << 1)
  73 #define DP_SELECT               (1 << 21)
  74 #define DDIR                    (1 << 4)
  75 #define DMA_EN                  0x1
  76 #define MSBS                    (1 << 5)
  77 #define BCE                     (1 << 1)
  78 #define FOUR_BIT                (1 << 1)
  79 #define CC                      0x1
  80 #define TC                      0x02
  81 #define OD                      0x1
  82 #define ERR                     (1 << 15)
  83 #define CMD_TIMEOUT             (1 << 16)
  84 #define DATA_TIMEOUT            (1 << 20)
  85 #define CMD_CRC                 (1 << 17)
  86 #define DATA_CRC                (1 << 21)
  87 #define CARD_ERR                (1 << 28)
  88 #define STAT_CLEAR              0xFFFFFFFF
  89 #define INIT_STREAM_CMD         0x00000000
  90 #define DUAL_VOLT_OCR_BIT       7
  91 #define SRC                     (1 << 25)
  92 #define SRD                     (1 << 26)
  93
  94 /*
  95  * FIXME: Most likely all the data using these _DEVID defines should come
  96  * from the platform_data, or implemented in controller and slot specific
  97  * functions.
  98  */
  99 #define OMAP_MMC1_DEVID         0
 100 #define OMAP_MMC2_DEVID         1
 101
 102 #define OMAP_MMC_DATADIR_NONE   0
 103 #define OMAP_MMC_DATADIR_READ   1
 104 #define OMAP_MMC_DATADIR_WRITE  2
 105 #define MMC_TIMEOUT_MS          20
 106 #define OMAP_MMC_MASTER_CLOCK   96000000
 107 #define DRIVER_NAME             "mmci-omap-hs"
 108
 109 /*
 110  * One controller can have multiple slots, like on some omap boards using
 111  * omap.c controller driver. Luckily this is not currently done on any known
 112  * omap_hsmmc.c device.
 113  */
 114 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 115
 116 /*
 117  * MMC Host controller read/write API's
 118  */
 119 #define OMAP_HSMMC_READ(base, reg)      \
 120         __raw_readl((base) + OMAP_HSMMC_##reg)
 121
 122 #define OMAP_HSMMC_WRITE(base, reg, val) \
 123         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 124
 125 struct mmc_omap_host {
 126         struct  device          *dev;
 127         struct  mmc_host        *mmc;
 128         struct  mmc_request     *mrq;
 129         struct  mmc_command     *cmd;
 130         struct  mmc_data        *data;
 131         struct  clk             *fclk;
 132         struct  clk             *iclk;
 133         struct  clk             *dbclk;
 134         struct  semaphore       sem;
 135         struct  work_struct     mmc_carddetect_work;
 136         void    __iomem         *base;
 137         resource_size_t         mapbase;
 138         unsigned int            id;
 139         unsigned int            dma_len;
 140         unsigned int            dma_dir;
 141         unsigned char           bus_mode;
 142         unsigned char           datadir;
 143         u32                     *buffer;
 144         u32                     bytesleft;
 145         int                     suspended;
 146         int                     irq;
 147         int                     carddetect;
 148         int                     use_dma, dma_ch;
 149         int                     initstr;
 150         int                     slot_id;
 151         int                     dbclk_enabled;
 152         struct  omap_mmc_platform_data  *pdata;
 153 };
 154
 155 /*
 156  * Stop clock to the card
 157  */
 158 static void omap_mmc_stop_clock(struct mmc_omap_host *host)
 159 {
 160         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 161                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 162         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 163                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 164 }
 165
 166 /*
 167  * Send init stream sequence to card
 168  * before sending IDLE command
 169  */
 170 static void send_init_stream(struct mmc_omap_host *host)
 171 {
 172         int reg = 0;
 173         unsigned long timeout;
 174
 175         disable_irq(host->irq);
 176         OMAP_HSMMC_WRITE(host->base, CON,
 177                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 178         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 179
 180         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 181         while ((reg != CC) && time_before(jiffies, timeout))
 182                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 183
 184         OMAP_HSMMC_WRITE(host->base, CON,
 185                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 186         enable_irq(host->irq);
 187 }
 188
 189 static inline
 190 int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
 191 {
 192         int r = 1;
 193
 194         if (host->pdata->slots[host->slot_id].get_cover_state)
 195                 r = host->pdata->slots[host->slot_id].get_cover_state(host->dev,
 196                         host->slot_id);
 197         return r;
 198 }
 199
 200 static ssize_t
 201 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 202                            char *buf)
 203 {
 204         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 205         struct mmc_omap_host *host = mmc_priv(mmc);
 206
 207         return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
 208                        "open");
 209 }
 210
 211 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 212
 213 static ssize_t
 214 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 215                         char *buf)
 216 {
 217         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 218         struct mmc_omap_host *host = mmc_priv(mmc);
 219         struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
 220
 221         return sprintf(buf, "slot:%s\n", slot.name);
 222 }
 223
 224 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 225
 226 /*
 227  * Configure the response type and send the cmd.
 228  */
 229 static void
 230 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
 231         struct mmc_data *data)
 232 {
 233         int cmdreg = 0, resptype = 0, cmdtype = 0;
 234
 235         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 236                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 237         host->cmd = cmd;
 238
 239         /*
 240          * Clear status bits and enable interrupts
 241          */
 242         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 243         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 244         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 245
 246         if (cmd->flags & MMC_RSP_PRESENT) {
 247                 if (cmd->flags & MMC_RSP_136)
 248                         resptype = 1;
 249                 else
 250                         resptype = 2;
 251         }
 252
 253         /*
 254          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 255          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 256          * a val of 0x3, rest 0x0.
 257          */
 258         if (cmd == host->mrq->stop)
 259                 cmdtype = 0x3;
 260
 261         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 262
 263         if (data) {
 264                 cmdreg |= DP_SELECT | MSBS | BCE;
 265                 if (data->flags & MMC_DATA_READ)
 266                         cmdreg |= DDIR;
 267                 else
 268                         cmdreg &= ~(DDIR);
 269         }
 270
 271         if (host->use_dma)
 272                 cmdreg |= DMA_EN;
 273
 274         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 275         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 276 }
 277
 278 /*
 279  * Notify the transfer complete to MMC core
 280  */
 281 static void
 282 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 283 {
 284         host->data = NULL;
 285
 286         if (host->use_dma && host->dma_ch != -1)
 287                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
 288                         host->dma_dir);
 289
 290         host->datadir = OMAP_MMC_DATADIR_NONE;
 291
 292         if (!data->error)
 293                 data->bytes_xfered += data->blocks * (data->blksz);
 294         else
 295                 data->bytes_xfered = 0;
 296
 297         if (!data->stop) {
 298                 host->mrq = NULL;
 299                 mmc_request_done(host->mmc, data->mrq);
 300                 return;
 301         }
 302         mmc_omap_start_command(host, data->stop, NULL);
 303 }
 304
 305 /*
 306  * Notify the core about command completion
 307  */
 308 static void
 309 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 310 {
 311         host->cmd = NULL;
 312
 313         if (cmd->flags & MMC_RSP_PRESENT) {
 314                 if (cmd->flags & MMC_RSP_136) {
 315                         /* response type 2 */
 316                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 317                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 318                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 319                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 320                 } else {
 321                         /* response types 1, 1b, 3, 4, 5, 6 */
 322                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 323                 }
 324         }
 325         if (host->data == NULL || cmd->error) {
 326                 host->mrq = NULL;
 327                 mmc_request_done(host->mmc, cmd->mrq);
 328         }
 329 }
 330
 331 /*
 332  * DMA clean up for command errors
 333  */
 334 static void mmc_dma_cleanup(struct mmc_omap_host *host)
 335 {
 336         host->data->error = -ETIMEDOUT;
 337
 338         if (host->use_dma && host->dma_ch != -1) {
 339                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
 340                         host->dma_dir);
 341                 omap_free_dma(host->dma_ch);
 342                 host->dma_ch = -1;
 343                 up(&host->sem);
 344         }
 345         host->data = NULL;
 346         host->datadir = OMAP_MMC_DATADIR_NONE;
 347 }
 348
 349 /*
 350  * Readable error output
 351  */
 352 #ifdef CONFIG_MMC_DEBUG
 353 static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
 354 {
 355         /* --- means reserved bit without definition at documentation */
 356         static const char *mmc_omap_status_bits[] = {
 357                 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
 358                 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
 359                 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
 360                 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
 361         };
 362         char res[256];
 363         char *buf = res;
 364         int len, i;
 365
 366         len = sprintf(buf, "MMC IRQ 0x%x :", status);
 367         buf += len;
 368
 369         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 370                 if (status & (1 << i)) {
 371                         len = sprintf(buf, " %s", mmc_omap_status_bits[i]);
 372                         buf += len;
 373                 }
 374
 375         dev_dbg(mmc_dev(host->mmc), "%s\n", res);
 376 }
 377 #endif  /* CONFIG_MMC_DEBUG */
 378
 379
 380 /*
 381  * MMC controller IRQ handler
 382  */
 383 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 384 {
 385         struct mmc_omap_host *host = dev_id;
 386         struct mmc_data *data;
 387         int end_cmd = 0, end_trans = 0, status;
 388
 389         if (host->cmd == NULL && host->data == NULL) {
 390                 OMAP_HSMMC_WRITE(host->base, STAT,
 391                         OMAP_HSMMC_READ(host->base, STAT));
 392                 return IRQ_HANDLED;
 393         }
 394
 395         data = host->data;
 396         status = OMAP_HSMMC_READ(host->base, STAT);
 397         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
 398
 399         if (status & ERR) {
 400 #ifdef CONFIG_MMC_DEBUG
 401                 mmc_omap_report_irq(host, status);
 402 #endif
 403                 if ((status & CMD_TIMEOUT) ||
 404                         (status & CMD_CRC)) {
 405                         if (host->cmd) {
 406                                 if (status & CMD_TIMEOUT) {
 407                                         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 408                                                 OMAP_HSMMC_READ(host->base,
 409                                                                 SYSCTL) | SRC);
 410                                         while (OMAP_HSMMC_READ(host->base,
 411                                                         SYSCTL) & SRC)
 412                                                 ;
 413
 414                                         host->cmd->error = -ETIMEDOUT;
 415                                 } else {
 416                                         host->cmd->error = -EILSEQ;
 417                                 }
 418                                 end_cmd = 1;
 419                         }
 420                         if (host->data) {
 421                                 mmc_dma_cleanup(host);
 422                                 OMAP_HSMMC_WRITE(host->base, SYSCTL,
 423                                         OMAP_HSMMC_READ(host->base,
 424                                                         SYSCTL) | SRD);
 425                                 while (OMAP_HSMMC_READ(host->base,
 426                                                 SYSCTL) & SRD)
 427                                         ;
 428                         }
 429                 }
 430                 if ((status & DATA_TIMEOUT) ||
 431                         (status & DATA_CRC)) {
 432                         if (host->data) {
 433                                 if (status & DATA_TIMEOUT)
 434                                         mmc_dma_cleanup(host);
 435                                 else
 436                                         host->data->error = -EILSEQ;
 437                                 OMAP_HSMMC_WRITE(host->base, SYSCTL,
 438                                         OMAP_HSMMC_READ(host->base,
 439                                                         SYSCTL) | SRD);
 440                                 while (OMAP_HSMMC_READ(host->base,
 441                                                 SYSCTL) & SRD)
 442                                         ;
 443                                 end_trans = 1;
 444                         }
 445                 }
 446                 if (status & CARD_ERR) {
 447                         dev_dbg(mmc_dev(host->mmc),
 448                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
 449                         if (host->cmd)
 450                                 end_cmd = 1;
 451                         if (host->data)
 452                                 end_trans = 1;
 453                 }
 454         }
 455
 456         OMAP_HSMMC_WRITE(host->base, STAT, status);
 457
 458         if (end_cmd || (status & CC))
 459                 mmc_omap_cmd_done(host, host->cmd);
 460         if (end_trans || (status & TC))
 461                 mmc_omap_xfer_done(host, data);
 462
 463         return IRQ_HANDLED;
 464 }
 465
 466 /*
 467  * Switch MMC interface voltage ... only relevant for MMC1.
 468  *
 469  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
 470  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
 471  * Some chips, like eMMC ones, use internal transceivers.
 472  */
 473 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
 474 {
 475         u32 reg_val = 0;
 476         int ret;
 477
 478         if (host->id != OMAP_MMC1_DEVID)
 479                 return 0;
 480
 481         /* Disable the clocks */
 482         clk_disable(host->fclk);
 483         clk_disable(host->iclk);
 484         clk_disable(host->dbclk);
 485
 486         /* Turn the power off */
 487         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 488         if (ret != 0)
 489                 goto err;
 490
 491         /* Turn the power ON with given VDD 1.8 or 3.0v */
 492         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
 493         if (ret != 0)
 494                 goto err;
 495
 496         clk_enable(host->fclk);
 497         clk_enable(host->iclk);
 498         clk_enable(host->dbclk);
 499
 500         OMAP_HSMMC_WRITE(host->base, HCTL,
 501                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
 502         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
 503
 504         /*
 505          * If a MMC dual voltage card is detected, the set_ios fn calls
 506          * this fn with VDD bit set for 1.8V. Upon card removal from the
 507          * slot, omap_mmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
 508          *
 509          * Cope with a bit of slop in the range ... per data sheets:
 510          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
 511          *    but recommended values are 1.71V to 1.89V
 512          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
 513          *    but recommended values are 2.7V to 3.3V
 514          *
 515          * Board setup code shouldn't permit anything very out-of-range.
 516          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
 517          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
 518          */
 519         if ((1 << vdd) <= MMC_VDD_23_24)
 520                 reg_val |= SDVS18;
 521         else
 522                 reg_val |= SDVS30;
 523
 524         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
 525
 526         OMAP_HSMMC_WRITE(host->base, HCTL,
 527                 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 528
 529         return 0;
 530 err:
 531         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
 532         return ret;
 533 }
 534
 535 /*
 536  * Work Item to notify the core about card insertion/removal
 537  */
 538 static void mmc_omap_detect(struct work_struct *work)
 539 {
 540         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 541                                                 mmc_carddetect_work);
 542         struct omap_mmc_slot_data *slot = &mmc_slot(host);
 543
 544         host->carddetect = slot->card_detect(slot->card_detect_irq);
 545
 546         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
 547         if (host->carddetect) {
 548                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
 549         } else {
 550                 OMAP_HSMMC_WRITE(host->base, SYSCTL,
 551                         OMAP_HSMMC_READ(host->base, SYSCTL) | SRD);
 552                 while (OMAP_HSMMC_READ(host->base, SYSCTL) & SRD)
 553                         ;
 554
 555                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
 556         }
 557 }
 558
 559 /*
 560  * ISR for handling card insertion and removal
 561  */
 562 static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
 563 {
 564         struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
 565
 566         schedule_work(&host->mmc_carddetect_work);
 567
 568         return IRQ_HANDLED;
 569 }
 570
 571 /*
 572  * DMA call back function
 573  */
 574 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 575 {
 576         struct mmc_omap_host *host = data;
 577
 578         if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
 579                 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
 580
 581         if (host->dma_ch < 0)
 582                 return;
 583
 584         omap_free_dma(host->dma_ch);
 585         host->dma_ch = -1;
 586         /*
 587          * DMA Callback: run in interrupt context.
 588          * mutex_unlock will through a kernel warning if used.
 589          */
 590         up(&host->sem);
 591 }
 592
 593 /*
 594  * Configure dma src and destination parameters
 595  */
 596 static int mmc_omap_config_dma_param(int sync_dir, struct mmc_omap_host *host,
 597                                 struct mmc_data *data)
 598 {
 599         if (sync_dir == 0) {
 600                 omap_set_dma_dest_params(host->dma_ch, 0,
 601                         OMAP_DMA_AMODE_CONSTANT,
 602                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 603                 omap_set_dma_src_params(host->dma_ch, 0,
 604                         OMAP_DMA_AMODE_POST_INC,
 605                         sg_dma_address(&data->sg[0]), 0, 0);
 606         } else {
 607                 omap_set_dma_src_params(host->dma_ch, 0,
 608                         OMAP_DMA_AMODE_CONSTANT,
 609                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 610                 omap_set_dma_dest_params(host->dma_ch, 0,
 611                         OMAP_DMA_AMODE_POST_INC,
 612                         sg_dma_address(&data->sg[0]), 0, 0);
 613         }
 614         return 0;
 615 }
 616 /*
 617  * Routine to configure and start DMA for the MMC card
 618  */
 619 static int
 620 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
 621 {
 622         int sync_dev, sync_dir = 0;
 623         int dma_ch = 0, ret = 0, err = 1;
 624         struct mmc_data *data = req->data;
 625
 626         /*
 627          * If for some reason the DMA transfer is still active,
 628          * we wait for timeout period and free the dma
 629          */
 630         if (host->dma_ch != -1) {
 631                 set_current_state(TASK_UNINTERRUPTIBLE);
 632                 schedule_timeout(100);
 633                 if (down_trylock(&host->sem)) {
 634                         omap_free_dma(host->dma_ch);
 635                         host->dma_ch = -1;
 636                         up(&host->sem);
 637                         return err;
 638                 }
 639         } else {
 640                 if (down_trylock(&host->sem))
 641                         return err;
 642         }
 643
 644         if (!(data->flags & MMC_DATA_WRITE)) {
 645                 host->dma_dir = DMA_FROM_DEVICE;
 646                 if (host->id == OMAP_MMC1_DEVID)
 647                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 648                 else
 649                         sync_dev = OMAP24XX_DMA_MMC2_RX;
 650         } else {
 651                 host->dma_dir = DMA_TO_DEVICE;
 652                 if (host->id == OMAP_MMC1_DEVID)
 653                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 654                 else
 655                         sync_dev = OMAP24XX_DMA_MMC2_TX;
 656         }
 657
 658         ret = omap_request_dma(sync_dev, "MMC/SD", mmc_omap_dma_cb,
 659                         host, &dma_ch);
 660         if (ret != 0) {
 661                 dev_dbg(mmc_dev(host->mmc),
 662                         "%s: omap_request_dma() failed with %d\n",
 663                         mmc_hostname(host->mmc), ret);
 664                 return ret;
 665         }
 666
 667         host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 668                         data->sg_len, host->dma_dir);
 669         host->dma_ch = dma_ch;
 670
 671         if (!(data->flags & MMC_DATA_WRITE))
 672                 mmc_omap_config_dma_param(1, host, data);
 673         else
 674                 mmc_omap_config_dma_param(0, host, data);
 675
 676         if ((data->blksz % 4) == 0)
 677                 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
 678                         (data->blksz / 4), data->blocks, OMAP_DMA_SYNC_FRAME,
 679                         sync_dev, sync_dir);
 680         else
 681                 /* REVISIT: The MMC buffer increments only when MSB is written.
 682                  * Return error for blksz which is non multiple of four.
 683                  */
 684                 return -EINVAL;
 685
 686         omap_start_dma(dma_ch);
 687         return 0;
 688 }
 689
 690 static void set_data_timeout(struct mmc_omap_host *host,
 691                              struct mmc_request *req)
 692 {
 693         unsigned int timeout, cycle_ns;
 694         uint32_t reg, clkd, dto = 0;
 695
 696         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
 697         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
 698         if (clkd == 0)
 699                 clkd = 1;
 700
 701         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
 702         timeout = req->data->timeout_ns / cycle_ns;
 703         timeout += req->data->timeout_clks;
 704         if (timeout) {
 705                 while ((timeout & 0x80000000) == 0) {
 706                         dto += 1;
 707                         timeout <<= 1;
 708                 }
 709                 dto = 31 - dto;
 710                 timeout <<= 1;
 711                 if (timeout && dto)
 712                         dto += 1;
 713                 if (dto >= 13)
 714                         dto -= 13;
 715                 else
 716                         dto = 0;
 717                 if (dto > 14)
 718                         dto = 14;
 719         }
 720
 721         reg &= ~DTO_MASK;
 722         reg |= dto << DTO_SHIFT;
 723         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
 724 }
 725
 726 /*
 727  * Configure block length for MMC/SD cards and initiate the transfer.
 728  */
 729 static int
 730 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 731 {
 732         int ret;
 733         host->data = req->data;
 734
 735         if (req->data == NULL) {
 736                 host->datadir = OMAP_MMC_DATADIR_NONE;
 737                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
 738                 return 0;
 739         }
 740
 741         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
 742                                         | (req->data->blocks << 16));
 743         set_data_timeout(host, req);
 744
 745         host->datadir = (req->data->flags & MMC_DATA_WRITE) ?
 746                         OMAP_MMC_DATADIR_WRITE : OMAP_MMC_DATADIR_READ;
 747
 748         if (host->use_dma) {
 749                 ret = mmc_omap_start_dma_transfer(host, req);
 750                 if (ret != 0) {
 751                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
 752                         return ret;
 753                 }
 754         }
 755         return 0;
 756 }
 757
 758 /*
 759  * Request function. for read/write operation
 760  */
 761 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
 762 {
 763         struct mmc_omap_host *host = mmc_priv(mmc);
 764
 765         WARN_ON(host->mrq != NULL);
 766         host->mrq = req;
 767         mmc_omap_prepare_data(host, req);
 768         mmc_omap_start_command(host, req->cmd, req->data);
 769 }
 770
 771
 772 /* Routine to configure clock values. Exposed API to core */
 773 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 774 {
 775         struct mmc_omap_host *host = mmc_priv(mmc);
 776         u16 dsor = 0;
 777         unsigned long regval;
 778         unsigned long timeout;
 779
 780         switch (ios->power_mode) {
 781         case MMC_POWER_OFF:
 782                 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 783                 /*
 784                  * Reset interface voltage to 3V if it's 1.8V now;
 785                  * only relevant on MMC-1, the others always use 1.8V.
 786                  *
 787                  * REVISIT: If we are able to detect cards after unplugging
 788                  * a 1.8V card, this code should not be needed.
 789                  */
 790                 if (host->id != OMAP_MMC1_DEVID)
 791                         break;
 792                 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
 793                         int vdd = fls(host->mmc->ocr_avail) - 1;
 794                         if (omap_mmc_switch_opcond(host, vdd) != 0)
 795                                 host->mmc->ios.vdd = vdd;
 796                 }
 797                 break;
 798         case MMC_POWER_UP:
 799                 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
 800                 break;
 801         }
 802
 803         switch (mmc->ios.bus_width) {
 804         case MMC_BUS_WIDTH_4:
 805                 OMAP_HSMMC_WRITE(host->base, HCTL,
 806                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 807                 break;
 808         case MMC_BUS_WIDTH_1:
 809                 OMAP_HSMMC_WRITE(host->base, HCTL,
 810                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 811                 break;
 812         }
 813
 814         if (host->id == OMAP_MMC1_DEVID) {
 815                 /* Only MMC1 can interface at 3V without some flavor
 816                  * of external transceiver; but they all handle 1.8V.
 817                  */
 818                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
 819                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
 820                                 /*
 821                                  * The mmc_select_voltage fn of the core does
 822                                  * not seem to set the power_mode to
 823                                  * MMC_POWER_UP upon recalculating the voltage.
 824                                  * vdd 1.8v.
 825                                  */
 826                                 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
 827                                         dev_dbg(mmc_dev(host->mmc),
 828                                                 "Switch operation failed\n");
 829                 }
 830         }
 831
 832         if (ios->clock) {
 833                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
 834                 if (dsor < 1)
 835                         dsor = 1;
 836
 837                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
 838                         dsor++;
 839
 840                 if (dsor > 250)
 841                         dsor = 250;
 842         }
 843         omap_mmc_stop_clock(host);
 844         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 845         regval = regval & ~(CLKD_MASK);
 846         regval = regval | (dsor << 6) | (DTO << 16);
 847         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 848         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 849                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 850
 851         /* Wait till the ICS bit is set */
 852         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 853         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
 854                 && time_before(jiffies, timeout))
 855                 msleep(1);
 856
 857         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 858                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 859
 860         if (ios->power_mode == MMC_POWER_ON)
 861                 send_init_stream(host);
 862
 863         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 864                 OMAP_HSMMC_WRITE(host->base, CON,
 865                                 OMAP_HSMMC_READ(host->base, CON) | OD);
 866 }
 867
 868 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
 869 {
 870         struct mmc_omap_host *host = mmc_priv(mmc);
 871         struct omap_mmc_platform_data *pdata = host->pdata;
 872
 873         if (!pdata->slots[0].card_detect)
 874                 return -ENOSYS;
 875         return pdata->slots[0].card_detect(pdata->slots[0].card_detect_irq);
 876 }
 877
 878 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
 879 {
 880         struct mmc_omap_host *host = mmc_priv(mmc);
 881         struct omap_mmc_platform_data *pdata = host->pdata;
 882
 883         if (!pdata->slots[0].get_ro)
 884                 return -ENOSYS;
 885         return pdata->slots[0].get_ro(host->dev, 0);
 886 }
 887
 888 static struct mmc_host_ops mmc_omap_ops = {
 889         .request = omap_mmc_request,
 890         .set_ios = omap_mmc_set_ios,
 891         .get_cd = omap_hsmmc_get_cd,
 892         .get_ro = omap_hsmmc_get_ro,
 893         /* NYET -- enable_sdio_irq */
 894 };
 895
 896 static int __init omap_mmc_probe(struct platform_device *pdev)
 897 {
 898         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
 899         struct mmc_host *mmc;
 900         struct mmc_omap_host *host = NULL;
 901         struct resource *res;
 902         int ret = 0, irq;
 903         u32 hctl, capa;
 904
 905         if (pdata == NULL) {
 906                 dev_err(&pdev->dev, "Platform Data is missing\n");
 907                 return -ENXIO;
 908         }
 909
 910         if (pdata->nr_slots == 0) {
 911                 dev_err(&pdev->dev, "No Slots\n");
 912                 return -ENXIO;
 913         }
 914
 915         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 916         irq = platform_get_irq(pdev, 0);
 917         if (res == NULL || irq < 0)
 918                 return -ENXIO;
 919
 920         res = request_mem_region(res->start, res->end - res->start + 1,
 921                                                         pdev->name);
 922         if (res == NULL)
 923                 return -EBUSY;
 924
 925         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
 926         if (!mmc) {
 927                 ret = -ENOMEM;
 928                 goto err;
 929         }
 930
 931         host            = mmc_priv(mmc);
 932         host->mmc       = mmc;
 933         host->pdata     = pdata;
 934         host->dev       = &pdev->dev;
 935         host->use_dma   = 1;
 936         host->dev->dma_mask = &pdata->dma_mask;
 937         host->dma_ch    = -1;
 938         host->irq       = irq;
 939         host->id        = pdev->id;
 940         host->slot_id   = 0;
 941         host->mapbase   = res->start;
 942         host->base      = ioremap(host->mapbase, SZ_4K);
 943
 944         platform_set_drvdata(pdev, host);
 945         INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
 946
 947         mmc->ops        = &mmc_omap_ops;
 948         mmc->f_min      = 400000;
 949         mmc->f_max      = 52000000;
 950
 951         sema_init(&host->sem, 1);
 952
 953         host->iclk = clk_get(&pdev->dev, "mmchs_ick");
 954         if (IS_ERR(host->iclk)) {
 955                 ret = PTR_ERR(host->iclk);
 956                 host->iclk = NULL;
 957                 goto err1;
 958         }
 959         host->fclk = clk_get(&pdev->dev, "mmchs_fck");
 960         if (IS_ERR(host->fclk)) {
 961                 ret = PTR_ERR(host->fclk);
 962                 host->fclk = NULL;
 963                 clk_put(host->iclk);
 964                 goto err1;
 965         }
 966
 967         if (clk_enable(host->fclk) != 0) {
 968                 clk_put(host->iclk);
 969                 clk_put(host->fclk);
 970                 goto err1;
 971         }
 972
 973         if (clk_enable(host->iclk) != 0) {
 974                 clk_disable(host->fclk);
 975                 clk_put(host->iclk);
 976                 clk_put(host->fclk);
 977                 goto err1;
 978         }
 979
 980         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
 981         /*
 982          * MMC can still work without debounce clock.
 983          */
 984         if (IS_ERR(host->dbclk))
 985                 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n");
 986         else
 987                 if (clk_enable(host->dbclk) != 0)
 988                         dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
 989                                                         " clk failed\n");
 990                 else
 991                         host->dbclk_enabled = 1;
 992
 993 #ifdef CONFIG_MMC_BLOCK_BOUNCE
 994         mmc->max_phys_segs = 1;
 995         mmc->max_hw_segs = 1;
 996 #endif
 997         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
 998         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
 999         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1000         mmc->max_seg_size = mmc->max_req_size;
1001
1002         mmc->ocr_avail = mmc_slot(host).ocr_mask;
1003         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1004
1005         if (pdata->slots[host->slot_id].wires >= 4)
1006                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1007
1008         /* Only MMC1 supports 3.0V */
1009         if (host->id == OMAP_MMC1_DEVID) {
1010                 hctl = SDVS30;
1011                 capa = VS30 | VS18;
1012         } else {
1013                 hctl = SDVS18;
1014                 capa = VS18;
1015         }
1016
1017         OMAP_HSMMC_WRITE(host->base, HCTL,
1018                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
1019
1020         OMAP_HSMMC_WRITE(host->base, CAPA,
1021                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
1022
1023         /* Set the controller to AUTO IDLE mode */
1024         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
1025                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
1026
1027         /* Set SD bus power bit */
1028         OMAP_HSMMC_WRITE(host->base, HCTL,
1029                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1030
1031         /* Request IRQ for MMC operations */
1032         ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
1033                         mmc_hostname(mmc), host);
1034         if (ret) {
1035                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1036                 goto err_irq;
1037         }
1038
1039         if (pdata->init != NULL) {
1040                 if (pdata->init(&pdev->dev) != 0) {
1041                         dev_dbg(mmc_dev(host->mmc),
1042                                 "Unable to configure MMC IRQs\n");
1043                         goto err_irq_cd_init;
1044                 }
1045         }
1046
1047         /* Request IRQ for card detect */
1048         if ((mmc_slot(host).card_detect_irq) && (mmc_slot(host).card_detect)) {
1049                 ret = request_irq(mmc_slot(host).card_detect_irq,
1050                                   omap_mmc_cd_handler,
1051                                   IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1052                                           | IRQF_DISABLED,
1053                                   mmc_hostname(mmc), host);
1054                 if (ret) {
1055                         dev_dbg(mmc_dev(host->mmc),
1056                                 "Unable to grab MMC CD IRQ\n");
1057                         goto err_irq_cd;
1058                 }
1059         }
1060
1061         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1062         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1063
1064         mmc_add_host(mmc);
1065
1066         if (host->pdata->slots[host->slot_id].name != NULL) {
1067                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1068                 if (ret < 0)
1069                         goto err_slot_name;
1070         }
1071         if (mmc_slot(host).card_detect_irq && mmc_slot(host).card_detect &&
1072                         host->pdata->slots[host->slot_id].get_cover_state) {
1073                 ret = device_create_file(&mmc->class_dev,
1074                                         &dev_attr_cover_switch);
1075                 if (ret < 0)
1076                         goto err_cover_switch;
1077         }
1078
1079         return 0;
1080
1081 err_cover_switch:
1082         device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1083 err_slot_name:
1084         mmc_remove_host(mmc);
1085 err_irq_cd:
1086         free_irq(mmc_slot(host).card_detect_irq, host);
1087 err_irq_cd_init:
1088         free_irq(host->irq, host);
1089 err_irq:
1090         clk_disable(host->fclk);
1091         clk_disable(host->iclk);
1092         clk_put(host->fclk);
1093         clk_put(host->iclk);
1094         if (host->dbclk_enabled) {
1095                 clk_disable(host->dbclk);
1096                 clk_put(host->dbclk);
1097         }
1098
1099 err1:
1100         iounmap(host->base);
1101 err:
1102         dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1103         release_mem_region(res->start, res->end - res->start + 1);
1104         if (host)
1105                 mmc_free_host(mmc);
1106         return ret;
1107 }
1108
1109 static int omap_mmc_remove(struct platform_device *pdev)
1110 {
1111         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1112         struct resource *res;
1113
1114         if (host) {
1115                 mmc_remove_host(host->mmc);
1116                 if (host->pdata->cleanup)
1117                         host->pdata->cleanup(&pdev->dev);
1118                 free_irq(host->irq, host);
1119                 if (mmc_slot(host).card_detect_irq)
1120                         free_irq(mmc_slot(host).card_detect_irq, host);
1121                 flush_scheduled_work();
1122
1123                 clk_disable(host->fclk);
1124                 clk_disable(host->iclk);
1125                 clk_put(host->fclk);
1126                 clk_put(host->iclk);
1127                 if (host->dbclk_enabled) {
1128                         clk_disable(host->dbclk);
1129                         clk_put(host->dbclk);
1130                 }
1131
1132                 mmc_free_host(host->mmc);
1133                 iounmap(host->base);
1134         }
1135
1136         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1137         if (res)
1138                 release_mem_region(res->start, res->end - res->start + 1);
1139         platform_set_drvdata(pdev, NULL);
1140
1141         return 0;
1142 }
1143
1144 #ifdef CONFIG_PM
1145 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1146 {
1147         int ret = 0;
1148         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1149
1150         if (host && host->suspended)
1151                 return 0;
1152
1153         if (host) {
1154                 ret = mmc_suspend_host(host->mmc, state);
1155                 if (ret == 0) {
1156                         host->suspended = 1;
1157
1158                         OMAP_HSMMC_WRITE(host->base, ISE, 0);
1159                         OMAP_HSMMC_WRITE(host->base, IE, 0);
1160
1161                         if (host->pdata->suspend) {
1162                                 ret = host->pdata->suspend(&pdev->dev,
1163                                                                 host->slot_id);
1164                                 if (ret)
1165                                         dev_dbg(mmc_dev(host->mmc),
1166                                                 "Unable to handle MMC board"
1167                                                 " level suspend\n");
1168                         }
1169
1170                         if (host->id == OMAP_MMC1_DEVID
1171                                         && !(OMAP_HSMMC_READ(host->base, HCTL)
1172                                                         & SDVSDET)) {
1173                                 OMAP_HSMMC_WRITE(host->base, HCTL,
1174                                         OMAP_HSMMC_READ(host->base, HCTL)
1175                                         & SDVSCLR);
1176                                 OMAP_HSMMC_WRITE(host->base, HCTL,
1177                                         OMAP_HSMMC_READ(host->base, HCTL)
1178                                         | SDVS30);
1179                                 OMAP_HSMMC_WRITE(host->base, HCTL,
1180                                         OMAP_HSMMC_READ(host->base, HCTL)
1181                                         | SDBP);
1182                         }
1183
1184                         clk_disable(host->fclk);
1185                         clk_disable(host->iclk);
1186                         clk_disable(host->dbclk);
1187                 }
1188
1189         }
1190         return ret;
1191 }
1192
1193 /* Routine to resume the MMC device */
1194 static int omap_mmc_resume(struct platform_device *pdev)
1195 {
1196         int ret = 0;
1197         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1198
1199         if (host && !host->suspended)
1200                 return 0;
1201
1202         if (host) {
1203
1204                 ret = clk_enable(host->fclk);
1205                 if (ret)
1206                         goto clk_en_err;
1207
1208                 ret = clk_enable(host->iclk);
1209                 if (ret) {
1210                         clk_disable(host->fclk);
1211                         clk_put(host->fclk);
1212                         goto clk_en_err;
1213                 }
1214
1215                 if (clk_enable(host->dbclk) != 0)
1216                         dev_dbg(mmc_dev(host->mmc),
1217                                         "Enabling debounce clk failed\n");
1218
1219                 if (host->pdata->resume) {
1220                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
1221                         if (ret)
1222                                 dev_dbg(mmc_dev(host->mmc),
1223                                         "Unmask interrupt failed\n");
1224                 }
1225
1226                 /* Notify the core to resume the host */
1227                 ret = mmc_resume_host(host->mmc);
1228                 if (ret == 0)
1229                         host->suspended = 0;
1230         }
1231
1232         return ret;
1233
1234 clk_en_err:
1235         dev_dbg(mmc_dev(host->mmc),
1236                 "Failed to enable MMC clocks during resume\n");
1237         return ret;
1238 }
1239
1240 #else
1241 #define omap_mmc_suspend        NULL
1242 #define omap_mmc_resume         NULL
1243 #endif
1244
1245 static struct platform_driver omap_mmc_driver = {
1246         .probe          = omap_mmc_probe,
1247         .remove         = omap_mmc_remove,
1248         .suspend        = omap_mmc_suspend,
1249         .resume         = omap_mmc_resume,
1250         .driver         = {
1251                 .name = DRIVER_NAME,
1252                 .owner = THIS_MODULE,
1253         },
1254 };
1255
1256 static int __init omap_mmc_init(void)
1257 {
1258         /* Register the MMC driver */
1259         return platform_driver_register(&omap_mmc_driver);
1260 }
1261
1262 static void __exit omap_mmc_cleanup(void)
1263 {
1264         /* Unregister MMC driver */
1265         platform_driver_unregister(&omap_mmc_driver);
1266 }
1267
1268 module_init(omap_mmc_init);
1269 module_exit(omap_mmc_cleanup);
1270
1271 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1272 MODULE_LICENSE("GPL");
1273 MODULE_ALIAS("platform:" DRIVER_NAME);
1274 MODULE_AUTHOR("Texas Instruments Inc");