git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/rt2x00/rt2400pci.c

   1 /*
   2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2400pci
  23         Abstract: rt2400pci device specific routines.
  24         Supported chipsets: RT2460.
  25  */
  26
  27 #include <linux/delay.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/init.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/eeprom_93cx6.h>
  34
  35 #include "rt2x00.h"
  36 #include "rt2x00pci.h"
  37 #include "rt2400pci.h"
  38
  39 /*
  40  * Register access.
  41  * All access to the CSR registers will go through the methods
  42  * rt2x00pci_register_read and rt2x00pci_register_write.
  43  * BBP and RF register require indirect register access,
  44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  45  * These indirect registers work with busy bits,
  46  * and we will try maximal REGISTER_BUSY_COUNT times to access
  47  * the register while taking a REGISTER_BUSY_DELAY us delay
  48  * between each attampt. When the busy bit is still set at that time,
  49  * the access attempt is considered to have failed,
  50  * and we will print an error.
  51  */
  52 static u32 rt2400pci_bbp_check(struct rt2x00_dev *rt2x00dev)
  53 {
  54         u32 reg;
  55         unsigned int i;
  56
  57         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  58                 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
  59                 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
  60                         break;
  61                 udelay(REGISTER_BUSY_DELAY);
  62         }
  63
  64         return reg;
  65 }
  66
  67 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  68                                 const unsigned int word, const u8 value)
  69 {
  70         u32 reg;
  71
  72         /*
  73          * Wait until the BBP becomes ready.
  74          */
  75         reg = rt2400pci_bbp_check(rt2x00dev);
  76         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
  77                 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
  78                 return;
  79         }
  80
  81         /*
  82          * Write the data into the BBP.
  83          */
  84         reg = 0;
  85         rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  86         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  87         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  88         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  89
  90         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  91 }
  92
  93 static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  94                                const unsigned int word, u8 *value)
  95 {
  96         u32 reg;
  97
  98         /*
  99          * Wait until the BBP becomes ready.
 100          */
 101         reg = rt2400pci_bbp_check(rt2x00dev);
 102         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 103                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 104                 return;
 105         }
 106
 107         /*
 108          * Write the request into the BBP.
 109          */
 110         reg = 0;
 111         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
 112         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 113         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 114
 115         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 116
 117         /*
 118          * Wait until the BBP becomes ready.
 119          */
 120         reg = rt2400pci_bbp_check(rt2x00dev);
 121         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 122                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 123                 *value = 0xff;
 124                 return;
 125         }
 126
 127         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 128 }
 129
 130 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
 131                                const unsigned int word, const u32 value)
 132 {
 133         u32 reg;
 134         unsigned int i;
 135
 136         if (!word)
 137                 return;
 138
 139         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 140                 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
 141                 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
 142                         goto rf_write;
 143                 udelay(REGISTER_BUSY_DELAY);
 144         }
 145
 146         ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
 147         return;
 148
 149 rf_write:
 150         reg = 0;
 151         rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 152         rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 153         rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 154         rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 155
 156         rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 157         rt2x00_rf_write(rt2x00dev, word, value);
 158 }
 159
 160 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 161 {
 162         struct rt2x00_dev *rt2x00dev = eeprom->data;
 163         u32 reg;
 164
 165         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 166
 167         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 168         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 169         eeprom->reg_data_clock =
 170             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 171         eeprom->reg_chip_select =
 172             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 173 }
 174
 175 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 176 {
 177         struct rt2x00_dev *rt2x00dev = eeprom->data;
 178         u32 reg = 0;
 179
 180         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 181         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 182         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 183                            !!eeprom->reg_data_clock);
 184         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 185                            !!eeprom->reg_chip_select);
 186
 187         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 188 }
 189
 190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 191 static const struct rt2x00debug rt2400pci_rt2x00debug = {
 192         .owner  = THIS_MODULE,
 193         .csr    = {
 194                 .read           = rt2x00pci_register_read,
 195                 .write          = rt2x00pci_register_write,
 196                 .flags          = RT2X00DEBUGFS_OFFSET,
 197                 .word_base      = CSR_REG_BASE,
 198                 .word_size      = sizeof(u32),
 199                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 200         },
 201         .eeprom = {
 202                 .read           = rt2x00_eeprom_read,
 203                 .write          = rt2x00_eeprom_write,
 204                 .word_base      = EEPROM_BASE,
 205                 .word_size      = sizeof(u16),
 206                 .word_count     = EEPROM_SIZE / sizeof(u16),
 207         },
 208         .bbp    = {
 209                 .read           = rt2400pci_bbp_read,
 210                 .write          = rt2400pci_bbp_write,
 211                 .word_base      = BBP_BASE,
 212                 .word_size      = sizeof(u8),
 213                 .word_count     = BBP_SIZE / sizeof(u8),
 214         },
 215         .rf     = {
 216                 .read           = rt2x00_rf_read,
 217                 .write          = rt2400pci_rf_write,
 218                 .word_base      = RF_BASE,
 219                 .word_size      = sizeof(u32),
 220                 .word_count     = RF_SIZE / sizeof(u32),
 221         },
 222 };
 223 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 224
 225 #ifdef CONFIG_RT2X00_LIB_RFKILL
 226 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 227 {
 228         u32 reg;
 229
 230         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 231         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
 232 }
 233 #else
 234 #define rt2400pci_rfkill_poll   NULL
 235 #endif /* CONFIG_RT2X00_LIB_RFKILL */
 236
 237 #ifdef CONFIG_RT2X00_LIB_LEDS
 238 static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
 239                                      enum led_brightness brightness)
 240 {
 241         struct rt2x00_led *led =
 242             container_of(led_cdev, struct rt2x00_led, led_dev);
 243         unsigned int enabled = brightness != LED_OFF;
 244         u32 reg;
 245
 246         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 247
 248         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
 249                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
 250         else if (led->type == LED_TYPE_ACTIVITY)
 251                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
 252
 253         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 254 }
 255
 256 static int rt2400pci_blink_set(struct led_classdev *led_cdev,
 257                                unsigned long *delay_on,
 258                                unsigned long *delay_off)
 259 {
 260         struct rt2x00_led *led =
 261             container_of(led_cdev, struct rt2x00_led, led_dev);
 262         u32 reg;
 263
 264         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 265         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
 266         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
 267         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 268
 269         return 0;
 270 }
 271
 272 static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
 273                                struct rt2x00_led *led,
 274                                enum led_type type)
 275 {
 276         led->rt2x00dev = rt2x00dev;
 277         led->type = type;
 278         led->led_dev.brightness_set = rt2400pci_brightness_set;
 279         led->led_dev.blink_set = rt2400pci_blink_set;
 280         led->flags = LED_INITIALIZED;
 281 }
 282 #endif /* CONFIG_RT2X00_LIB_LEDS */
 283
 284 /*
 285  * Configuration handlers.
 286  */
 287 static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
 288                                     const unsigned int filter_flags)
 289 {
 290         u32 reg;
 291
 292         /*
 293          * Start configuration steps.
 294          * Note that the version error will always be dropped
 295          * since there is no filter for it at this time.
 296          */
 297         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 298         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
 299                            !(filter_flags & FIF_FCSFAIL));
 300         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
 301                            !(filter_flags & FIF_PLCPFAIL));
 302         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
 303                            !(filter_flags & FIF_CONTROL));
 304         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
 305                            !(filter_flags & FIF_PROMISC_IN_BSS));
 306         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
 307                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 308                            !rt2x00dev->intf_ap_count);
 309         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
 310         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 311 }
 312
 313 static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
 314                                   struct rt2x00_intf *intf,
 315                                   struct rt2x00intf_conf *conf,
 316                                   const unsigned int flags)
 317 {
 318         unsigned int bcn_preload;
 319         u32 reg;
 320
 321         if (flags & CONFIG_UPDATE_TYPE) {
 322                 /*
 323                  * Enable beacon config
 324                  */
 325                 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
 326                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 327                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
 328                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 329
 330                 /*
 331                  * Enable synchronisation.
 332                  */
 333                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 334                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 335                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
 336                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 337                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 338         }
 339
 340         if (flags & CONFIG_UPDATE_MAC)
 341                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
 342                                               conf->mac, sizeof(conf->mac));
 343
 344         if (flags & CONFIG_UPDATE_BSSID)
 345                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
 346                                               conf->bssid, sizeof(conf->bssid));
 347 }
 348
 349 static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
 350                                  struct rt2x00lib_erp *erp)
 351 {
 352         int preamble_mask;
 353         u32 reg;
 354
 355         /*
 356          * When short preamble is enabled, we should set bit 0x08
 357          */
 358         preamble_mask = erp->short_preamble << 3;
 359
 360         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 361         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
 362                            erp->ack_timeout);
 363         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
 364                            erp->ack_consume_time);
 365         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 366
 367         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 368         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
 369         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 370         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
 371         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 372
 373         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 374         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
 375         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 376         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
 377         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 378
 379         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 380         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
 381         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 382         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
 383         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 384
 385         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 386         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
 387         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 388         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
 389         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 390
 391         rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
 392
 393         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 394         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
 395         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 396
 397         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 398         rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
 399         rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
 400         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 401
 402         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 403         rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
 404         rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
 405         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 406 }
 407
 408 static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
 409                                  struct antenna_setup *ant)
 410 {
 411         u8 r1;
 412         u8 r4;
 413
 414         /*
 415          * We should never come here because rt2x00lib is supposed
 416          * to catch this and send us the correct antenna explicitely.
 417          */
 418         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 419                ant->tx == ANTENNA_SW_DIVERSITY);
 420
 421         rt2400pci_bbp_read(rt2x00dev, 4, &r4);
 422         rt2400pci_bbp_read(rt2x00dev, 1, &r1);
 423
 424         /*
 425          * Configure the TX antenna.
 426          */
 427         switch (ant->tx) {
 428         case ANTENNA_HW_DIVERSITY:
 429                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
 430                 break;
 431         case ANTENNA_A:
 432                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
 433                 break;
 434         case ANTENNA_B:
 435         default:
 436                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
 437                 break;
 438         }
 439
 440         /*
 441          * Configure the RX antenna.
 442          */
 443         switch (ant->rx) {
 444         case ANTENNA_HW_DIVERSITY:
 445                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
 446                 break;
 447         case ANTENNA_A:
 448                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
 449                 break;
 450         case ANTENNA_B:
 451         default:
 452                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
 453                 break;
 454         }
 455
 456         rt2400pci_bbp_write(rt2x00dev, 4, r4);
 457         rt2400pci_bbp_write(rt2x00dev, 1, r1);
 458 }
 459
 460 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
 461                                      struct rf_channel *rf)
 462 {
 463         /*
 464          * Switch on tuning bits.
 465          */
 466         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
 467         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
 468
 469         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 470         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
 471         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 472
 473         /*
 474          * RF2420 chipset don't need any additional actions.
 475          */
 476         if (rt2x00_rf(&rt2x00dev->chip, RF2420))
 477                 return;
 478
 479         /*
 480          * For the RT2421 chipsets we need to write an invalid
 481          * reference clock rate to activate auto_tune.
 482          * After that we set the value back to the correct channel.
 483          */
 484         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 485         rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
 486         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 487
 488         msleep(1);
 489
 490         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 491         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
 492         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 493
 494         msleep(1);
 495
 496         /*
 497          * Switch off tuning bits.
 498          */
 499         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
 500         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
 501
 502         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 503         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 504
 505         /*
 506          * Clear false CRC during channel switch.
 507          */
 508         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
 509 }
 510
 511 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
 512 {
 513         rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
 514 }
 515
 516 static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 517                                          struct rt2x00lib_conf *libconf)
 518 {
 519         u32 reg;
 520
 521         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 522         rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
 523                            libconf->conf->long_frame_max_tx_count);
 524         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
 525                            libconf->conf->short_frame_max_tx_count);
 526         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 527 }
 528
 529 static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
 530                                       struct rt2x00lib_conf *libconf)
 531 {
 532         u32 reg;
 533
 534         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 535         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 536         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 537         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 538
 539         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 540         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
 541                            libconf->conf->beacon_int * 16);
 542         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
 543                            libconf->conf->beacon_int * 16);
 544         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 545 }
 546
 547 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
 548                              struct rt2x00lib_conf *libconf,
 549                              const unsigned int flags)
 550 {
 551         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
 552                 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
 553         if (flags & IEEE80211_CONF_CHANGE_POWER)
 554                 rt2400pci_config_txpower(rt2x00dev,
 555                                          libconf->conf->power_level);
 556         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
 557                 rt2400pci_config_retry_limit(rt2x00dev, libconf);
 558         if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
 559                 rt2400pci_config_duration(rt2x00dev, libconf);
 560 }
 561
 562 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
 563                                 const int cw_min, const int cw_max)
 564 {
 565         u32 reg;
 566
 567         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 568         rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
 569         rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
 570         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 571 }
 572
 573 /*
 574  * Link tuning
 575  */
 576 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
 577                                  struct link_qual *qual)
 578 {
 579         u32 reg;
 580         u8 bbp;
 581
 582         /*
 583          * Update FCS error count from register.
 584          */
 585         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 586         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 587
 588         /*
 589          * Update False CCA count from register.
 590          */
 591         rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
 592         qual->false_cca = bbp;
 593 }
 594
 595 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
 596 {
 597         rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
 598         rt2x00dev->link.vgc_level = 0x08;
 599 }
 600
 601 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
 602 {
 603         u8 reg;
 604
 605         /*
 606          * The link tuner should not run longer then 60 seconds,
 607          * and should run once every 2 seconds.
 608          */
 609         if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
 610                 return;
 611
 612         /*
 613          * Base r13 link tuning on the false cca count.
 614          */
 615         rt2400pci_bbp_read(rt2x00dev, 13, &reg);
 616
 617         if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
 618                 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
 619                 rt2x00dev->link.vgc_level = reg;
 620         } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
 621                 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
 622                 rt2x00dev->link.vgc_level = reg;
 623         }
 624 }
 625
 626 /*
 627  * Initialization functions.
 628  */
 629 static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
 630                                    struct queue_entry *entry)
 631 {
 632         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 633         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 634         u32 word;
 635
 636         rt2x00_desc_read(entry_priv->desc, 2, &word);
 637         rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
 638         rt2x00_desc_write(entry_priv->desc, 2, word);
 639
 640         rt2x00_desc_read(entry_priv->desc, 1, &word);
 641         rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
 642         rt2x00_desc_write(entry_priv->desc, 1, word);
 643
 644         rt2x00_desc_read(entry_priv->desc, 0, &word);
 645         rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 646         rt2x00_desc_write(entry_priv->desc, 0, word);
 647 }
 648
 649 static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev,
 650                                    struct queue_entry *entry)
 651 {
 652         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 653         u32 word;
 654
 655         rt2x00_desc_read(entry_priv->desc, 0, &word);
 656         rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 657         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 658         rt2x00_desc_write(entry_priv->desc, 0, word);
 659 }
 660
 661 static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
 662 {
 663         struct queue_entry_priv_pci *entry_priv;
 664         u32 reg;
 665
 666         /*
 667          * Initialize registers.
 668          */
 669         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 670         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
 671         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
 672         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
 673         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
 674         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 675
 676         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 677         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 678         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 679                            entry_priv->desc_dma);
 680         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 681
 682         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 683         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 684         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 685                            entry_priv->desc_dma);
 686         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 687
 688         entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
 689         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 690         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 691                            entry_priv->desc_dma);
 692         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 693
 694         entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
 695         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 696         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 697                            entry_priv->desc_dma);
 698         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 699
 700         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 701         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 702         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
 703         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 704
 705         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 706         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 707         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
 708                            entry_priv->desc_dma);
 709         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 710
 711         return 0;
 712 }
 713
 714 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
 715 {
 716         u32 reg;
 717
 718         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 719         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 720         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
 721         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 722
 723         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 724         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 725         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 726         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 727         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 728
 729         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 730         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 731                            (rt2x00dev->rx->data_size / 128));
 732         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 733
 734         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 735         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
 736         rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
 737         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
 738         rt2x00_set_field32(&reg, CSR14_TCFP, 0);
 739         rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
 740         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 741         rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
 742         rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
 743         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 744
 745         rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
 746
 747         rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
 748         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
 749         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
 750         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
 751         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
 752         rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
 753
 754         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 755         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
 756         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 757         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
 758         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 759         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
 760         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 761         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 762
 763         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 764
 765         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 766                 return -EBUSY;
 767
 768         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
 769         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
 770
 771         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
 772         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 773         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
 774
 775         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
 776         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
 777         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
 778         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
 779         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
 780         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
 781
 782         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 783         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
 784         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
 785         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
 786         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 787
 788         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 789         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
 790         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
 791         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 792
 793         /*
 794          * We must clear the FCS and FIFO error count.
 795          * These registers are cleared on read,
 796          * so we may pass a useless variable to store the value.
 797          */
 798         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 799         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
 800
 801         return 0;
 802 }
 803
 804 static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
 805 {
 806         unsigned int i;
 807         u8 value;
 808
 809         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 810                 rt2400pci_bbp_read(rt2x00dev, 0, &value);
 811                 if ((value != 0xff) && (value != 0x00))
 812                         return 0;
 813                 udelay(REGISTER_BUSY_DELAY);
 814         }
 815
 816         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
 817         return -EACCES;
 818 }
 819
 820 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 821 {
 822         unsigned int i;
 823         u16 eeprom;
 824         u8 reg_id;
 825         u8 value;
 826
 827         if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
 828                 return -EACCES;
 829
 830         rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
 831         rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
 832         rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
 833         rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
 834         rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
 835         rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
 836         rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
 837         rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
 838         rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
 839         rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
 840         rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
 841         rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
 842         rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
 843         rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
 844
 845         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
 846                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
 847
 848                 if (eeprom != 0xffff && eeprom != 0x0000) {
 849                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
 850                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
 851                         rt2400pci_bbp_write(rt2x00dev, reg_id, value);
 852                 }
 853         }
 854
 855         return 0;
 856 }
 857
 858 /*
 859  * Device state switch handlers.
 860  */
 861 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
 862                                 enum dev_state state)
 863 {
 864         u32 reg;
 865
 866         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 867         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
 868                            (state == STATE_RADIO_RX_OFF) ||
 869                            (state == STATE_RADIO_RX_OFF_LINK));
 870         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 871 }
 872
 873 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 874                                  enum dev_state state)
 875 {
 876         int mask = (state == STATE_RADIO_IRQ_OFF);
 877         u32 reg;
 878
 879         /*
 880          * When interrupts are being enabled, the interrupt registers
 881          * should clear the register to assure a clean state.
 882          */
 883         if (state == STATE_RADIO_IRQ_ON) {
 884                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
 885                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
 886         }
 887
 888         /*
 889          * Only toggle the interrupts bits we are going to use.
 890          * Non-checked interrupt bits are disabled by default.
 891          */
 892         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
 893         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
 894         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
 895         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
 896         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
 897         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
 898         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
 899 }
 900
 901 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
 902 {
 903         /*
 904          * Initialize all registers.
 905          */
 906         if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
 907                      rt2400pci_init_registers(rt2x00dev) ||
 908                      rt2400pci_init_bbp(rt2x00dev)))
 909                 return -EIO;
 910
 911         return 0;
 912 }
 913
 914 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
 915 {
 916         u32 reg;
 917
 918         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
 919
 920         /*
 921          * Disable synchronisation.
 922          */
 923         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
 924
 925         /*
 926          * Cancel RX and TX.
 927          */
 928         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
 929         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
 930         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
 931 }
 932
 933 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
 934                                enum dev_state state)
 935 {
 936         u32 reg;
 937         unsigned int i;
 938         char put_to_sleep;
 939         char bbp_state;
 940         char rf_state;
 941
 942         put_to_sleep = (state != STATE_AWAKE);
 943
 944         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
 945         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
 946         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
 947         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
 948         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
 949         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
 950
 951         /*
 952          * Device is not guaranteed to be in the requested state yet.
 953          * We must wait until the register indicates that the
 954          * device has entered the correct state.
 955          */
 956         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 957                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
 958                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
 959                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
 960                 if (bbp_state == state && rf_state == state)
 961                         return 0;
 962                 msleep(10);
 963         }
 964
 965         return -EBUSY;
 966 }
 967
 968 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
 969                                       enum dev_state state)
 970 {
 971         int retval = 0;
 972
 973         switch (state) {
 974         case STATE_RADIO_ON:
 975                 retval = rt2400pci_enable_radio(rt2x00dev);
 976                 break;
 977         case STATE_RADIO_OFF:
 978                 rt2400pci_disable_radio(rt2x00dev);
 979                 break;
 980         case STATE_RADIO_RX_ON:
 981         case STATE_RADIO_RX_ON_LINK:
 982         case STATE_RADIO_RX_OFF:
 983         case STATE_RADIO_RX_OFF_LINK:
 984                 rt2400pci_toggle_rx(rt2x00dev, state);
 985                 break;
 986         case STATE_RADIO_IRQ_ON:
 987         case STATE_RADIO_IRQ_OFF:
 988                 rt2400pci_toggle_irq(rt2x00dev, state);
 989                 break;
 990         case STATE_DEEP_SLEEP:
 991         case STATE_SLEEP:
 992         case STATE_STANDBY:
 993         case STATE_AWAKE:
 994                 retval = rt2400pci_set_state(rt2x00dev, state);
 995                 break;
 996         default:
 997                 retval = -ENOTSUPP;
 998                 break;
 999         }
1000
1001         if (unlikely(retval))
1002                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1003                       state, retval);
1004
1005         return retval;
1006 }
1007
1008 /*
1009  * TX descriptor initialization
1010  */
1011 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1012                                     struct sk_buff *skb,
1013                                     struct txentry_desc *txdesc)
1014 {
1015         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1016         struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1017         __le32 *txd = skbdesc->desc;
1018         u32 word;
1019
1020         /*
1021          * Start writing the descriptor words.
1022          */
1023         rt2x00_desc_read(entry_priv->desc, 1, &word);
1024         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1025         rt2x00_desc_write(entry_priv->desc, 1, word);
1026
1027         rt2x00_desc_read(txd, 2, &word);
1028         rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, skb->len);
1029         rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skb->len);
1030         rt2x00_desc_write(txd, 2, word);
1031
1032         rt2x00_desc_read(txd, 3, &word);
1033         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1034         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1035         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1036         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1037         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1038         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1039         rt2x00_desc_write(txd, 3, word);
1040
1041         rt2x00_desc_read(txd, 4, &word);
1042         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
1043         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1044         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1045         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
1046         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1047         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1048         rt2x00_desc_write(txd, 4, word);
1049
1050         rt2x00_desc_read(txd, 0, &word);
1051         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1052         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1053         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1054                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1055         rt2x00_set_field32(&word, TXD_W0_ACK,
1056                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1057         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1058                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1059         rt2x00_set_field32(&word, TXD_W0_RTS,
1060                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1061         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1062         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1063                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1064         rt2x00_desc_write(txd, 0, word);
1065 }
1066
1067 /*
1068  * TX data initialization
1069  */
1070 static void rt2400pci_write_beacon(struct queue_entry *entry)
1071 {
1072         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1073         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1074         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1075         u32 word;
1076         u32 reg;
1077
1078         /*
1079          * Disable beaconing while we are reloading the beacon data,
1080          * otherwise we might be sending out invalid data.
1081          */
1082         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1083         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1084         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1085         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1086         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1087
1088         /*
1089          * Replace rt2x00lib allocated descriptor with the
1090          * pointer to the _real_ hardware descriptor.
1091          * After that, map the beacon to DMA and update the
1092          * descriptor.
1093          */
1094         memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1095         skbdesc->desc = entry_priv->desc;
1096
1097         rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1098
1099         rt2x00_desc_read(entry_priv->desc, 1, &word);
1100         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1101         rt2x00_desc_write(entry_priv->desc, 1, word);
1102 }
1103
1104 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1105                                     const enum data_queue_qid queue)
1106 {
1107         u32 reg;
1108
1109         if (queue == QID_BEACON) {
1110                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1111                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1112                         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1113                         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1114                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1115                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1116                 }
1117                 return;
1118         }
1119
1120         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1121         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1122         rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1123         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1124         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1125 }
1126
1127 /*
1128  * RX control handlers
1129  */
1130 static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1131                                   struct rxdone_entry_desc *rxdesc)
1132 {
1133         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1134         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1135         u32 word0;
1136         u32 word2;
1137         u32 word3;
1138         u32 word4;
1139         u64 tsf;
1140         u32 rx_low;
1141         u32 rx_high;
1142
1143         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1144         rt2x00_desc_read(entry_priv->desc, 2, &word2);
1145         rt2x00_desc_read(entry_priv->desc, 3, &word3);
1146         rt2x00_desc_read(entry_priv->desc, 4, &word4);
1147
1148         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1149                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1150         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1151                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1152
1153         /*
1154          * We only get the lower 32bits from the timestamp,
1155          * to get the full 64bits we must complement it with
1156          * the timestamp from get_tsf().
1157          * Note that when a wraparound of the lower 32bits
1158          * has occurred between the frame arrival and the get_tsf()
1159          * call, we must decrease the higher 32bits with 1 to get
1160          * to correct value.
1161          */
1162         tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw);
1163         rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1164         rx_high = upper_32_bits(tsf);
1165
1166         if ((u32)tsf <= rx_low)
1167                 rx_high--;
1168
1169         /*
1170          * Obtain the status about this packet.
1171          * The signal is the PLCP value, and needs to be stripped
1172          * of the preamble bit (0x08).
1173          */
1174         rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
1175         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
1176         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
1177             entry->queue->rt2x00dev->rssi_offset;
1178         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1179
1180         rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1181         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1182                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1183 }
1184
1185 /*
1186  * Interrupt functions.
1187  */
1188 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1189                              const enum data_queue_qid queue_idx)
1190 {
1191         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1192         struct queue_entry_priv_pci *entry_priv;
1193         struct queue_entry *entry;
1194         struct txdone_entry_desc txdesc;
1195         u32 word;
1196
1197         while (!rt2x00queue_empty(queue)) {
1198                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1199                 entry_priv = entry->priv_data;
1200                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1201
1202                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1203                     !rt2x00_get_field32(word, TXD_W0_VALID))
1204                         break;
1205
1206                 /*
1207                  * Obtain the status about this packet.
1208                  */
1209                 txdesc.flags = 0;
1210                 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1211                 case 0: /* Success */
1212                 case 1: /* Success with retry */
1213                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1214                         break;
1215                 case 2: /* Failure, excessive retries */
1216                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1217                         /* Don't break, this is a failed frame! */
1218                 default: /* Failure */
1219                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1220                 }
1221                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1222
1223                 rt2x00lib_txdone(entry, &txdesc);
1224         }
1225 }
1226
1227 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1228 {
1229         struct rt2x00_dev *rt2x00dev = dev_instance;
1230         u32 reg;
1231
1232         /*
1233          * Get the interrupt sources & saved to local variable.
1234          * Write register value back to clear pending interrupts.
1235          */
1236         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1237         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1238
1239         if (!reg)
1240                 return IRQ_NONE;
1241
1242         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1243                 return IRQ_HANDLED;
1244
1245         /*
1246          * Handle interrupts, walk through all bits
1247          * and run the tasks, the bits are checked in order of
1248          * priority.
1249          */
1250
1251         /*
1252          * 1 - Beacon timer expired interrupt.
1253          */
1254         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1255                 rt2x00lib_beacondone(rt2x00dev);
1256
1257         /*
1258          * 2 - Rx ring done interrupt.
1259          */
1260         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1261                 rt2x00pci_rxdone(rt2x00dev);
1262
1263         /*
1264          * 3 - Atim ring transmit done interrupt.
1265          */
1266         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1267                 rt2400pci_txdone(rt2x00dev, QID_ATIM);
1268
1269         /*
1270          * 4 - Priority ring transmit done interrupt.
1271          */
1272         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1273                 rt2400pci_txdone(rt2x00dev, QID_AC_BE);
1274
1275         /*
1276          * 5 - Tx ring transmit done interrupt.
1277          */
1278         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1279                 rt2400pci_txdone(rt2x00dev, QID_AC_BK);
1280
1281         return IRQ_HANDLED;
1282 }
1283
1284 /*
1285  * Device probe functions.
1286  */
1287 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1288 {
1289         struct eeprom_93cx6 eeprom;
1290         u32 reg;
1291         u16 word;
1292         u8 *mac;
1293
1294         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1295
1296         eeprom.data = rt2x00dev;
1297         eeprom.register_read = rt2400pci_eepromregister_read;
1298         eeprom.register_write = rt2400pci_eepromregister_write;
1299         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1300             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1301         eeprom.reg_data_in = 0;
1302         eeprom.reg_data_out = 0;
1303         eeprom.reg_data_clock = 0;
1304         eeprom.reg_chip_select = 0;
1305
1306         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1307                                EEPROM_SIZE / sizeof(u16));
1308
1309         /*
1310          * Start validation of the data that has been read.
1311          */
1312         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1313         if (!is_valid_ether_addr(mac)) {
1314                 random_ether_addr(mac);
1315                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1316         }
1317
1318         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1319         if (word == 0xffff) {
1320                 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1321                 return -EINVAL;
1322         }
1323
1324         return 0;
1325 }
1326
1327 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1328 {
1329         u32 reg;
1330         u16 value;
1331         u16 eeprom;
1332
1333         /*
1334          * Read EEPROM word for configuration.
1335          */
1336         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1337
1338         /*
1339          * Identify RF chipset.
1340          */
1341         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1342         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1343         rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1344
1345         if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1346             !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1347                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1348                 return -ENODEV;
1349         }
1350
1351         /*
1352          * Identify default antenna configuration.
1353          */
1354         rt2x00dev->default_ant.tx =
1355             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1356         rt2x00dev->default_ant.rx =
1357             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1358
1359         /*
1360          * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1361          * I am not 100% sure about this, but the legacy drivers do not
1362          * indicate antenna swapping in software is required when
1363          * diversity is enabled.
1364          */
1365         if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1366                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1367         if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1368                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1369
1370         /*
1371          * Store led mode, for correct led behaviour.
1372          */
1373 #ifdef CONFIG_RT2X00_LIB_LEDS
1374         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1375
1376         rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1377         if (value == LED_MODE_TXRX_ACTIVITY)
1378                 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1379                                    LED_TYPE_ACTIVITY);
1380 #endif /* CONFIG_RT2X00_LIB_LEDS */
1381
1382         /*
1383          * Detect if this device has an hardware controlled radio.
1384          */
1385 #ifdef CONFIG_RT2X00_LIB_RFKILL
1386         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1387                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1388 #endif /* CONFIG_RT2X00_LIB_RFKILL */
1389
1390         /*
1391          * Check if the BBP tuning should be enabled.
1392          */
1393         if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1394                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1395
1396         return 0;
1397 }
1398
1399 /*
1400  * RF value list for RF2420 & RF2421
1401  * Supports: 2.4 GHz
1402  */
1403 static const struct rf_channel rf_vals_b[] = {
1404         { 1,  0x00022058, 0x000c1fda, 0x00000101, 0 },
1405         { 2,  0x00022058, 0x000c1fee, 0x00000101, 0 },
1406         { 3,  0x00022058, 0x000c2002, 0x00000101, 0 },
1407         { 4,  0x00022058, 0x000c2016, 0x00000101, 0 },
1408         { 5,  0x00022058, 0x000c202a, 0x00000101, 0 },
1409         { 6,  0x00022058, 0x000c203e, 0x00000101, 0 },
1410         { 7,  0x00022058, 0x000c2052, 0x00000101, 0 },
1411         { 8,  0x00022058, 0x000c2066, 0x00000101, 0 },
1412         { 9,  0x00022058, 0x000c207a, 0x00000101, 0 },
1413         { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1414         { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1415         { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1416         { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1417         { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1418 };
1419
1420 static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1421 {
1422         struct hw_mode_spec *spec = &rt2x00dev->spec;
1423         struct channel_info *info;
1424         char *tx_power;
1425         unsigned int i;
1426
1427         /*
1428          * Initialize all hw fields.
1429          */
1430         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1431                                IEEE80211_HW_SIGNAL_DBM;
1432         rt2x00dev->hw->extra_tx_headroom = 0;
1433
1434         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1435         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1436                                 rt2x00_eeprom_addr(rt2x00dev,
1437                                                    EEPROM_MAC_ADDR_0));
1438
1439         /*
1440          * Initialize hw_mode information.
1441          */
1442         spec->supported_bands = SUPPORT_BAND_2GHZ;
1443         spec->supported_rates = SUPPORT_RATE_CCK;
1444
1445         spec->num_channels = ARRAY_SIZE(rf_vals_b);
1446         spec->channels = rf_vals_b;
1447
1448         /*
1449          * Create channel information array
1450          */
1451         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1452         if (!info)
1453                 return -ENOMEM;
1454
1455         spec->channels_info = info;
1456
1457         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1458         for (i = 0; i < 14; i++)
1459                 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1460
1461         return 0;
1462 }
1463
1464 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1465 {
1466         int retval;
1467
1468         /*
1469          * Allocate eeprom data.
1470          */
1471         retval = rt2400pci_validate_eeprom(rt2x00dev);
1472         if (retval)
1473                 return retval;
1474
1475         retval = rt2400pci_init_eeprom(rt2x00dev);
1476         if (retval)
1477                 return retval;
1478
1479         /*
1480          * Initialize hw specifications.
1481          */
1482         retval = rt2400pci_probe_hw_mode(rt2x00dev);
1483         if (retval)
1484                 return retval;
1485
1486         /*
1487          * This device requires the atim queue and DMA-mapped skbs.
1488          */
1489         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1490         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1491
1492         /*
1493          * Set the rssi offset.
1494          */
1495         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1496
1497         return 0;
1498 }
1499
1500 /*
1501  * IEEE80211 stack callback functions.
1502  */
1503 static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue,
1504                              const struct ieee80211_tx_queue_params *params)
1505 {
1506         struct rt2x00_dev *rt2x00dev = hw->priv;
1507
1508         /*
1509          * We don't support variating cw_min and cw_max variables
1510          * per queue. So by default we only configure the TX queue,
1511          * and ignore all other configurations.
1512          */
1513         if (queue != 0)
1514                 return -EINVAL;
1515
1516         if (rt2x00mac_conf_tx(hw, queue, params))
1517                 return -EINVAL;
1518
1519         /*
1520          * Write configuration to register.
1521          */
1522         rt2400pci_config_cw(rt2x00dev,
1523                             rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1524
1525         return 0;
1526 }
1527
1528 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1529 {
1530         struct rt2x00_dev *rt2x00dev = hw->priv;
1531         u64 tsf;
1532         u32 reg;
1533
1534         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1535         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1536         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1537         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1538
1539         return tsf;
1540 }
1541
1542 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1543 {
1544         struct rt2x00_dev *rt2x00dev = hw->priv;
1545         u32 reg;
1546
1547         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1548         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1549 }
1550
1551 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1552         .tx                     = rt2x00mac_tx,
1553         .start                  = rt2x00mac_start,
1554         .stop                   = rt2x00mac_stop,
1555         .add_interface          = rt2x00mac_add_interface,
1556         .remove_interface       = rt2x00mac_remove_interface,
1557         .config                 = rt2x00mac_config,
1558         .config_interface       = rt2x00mac_config_interface,
1559         .configure_filter       = rt2x00mac_configure_filter,
1560         .get_stats              = rt2x00mac_get_stats,
1561         .bss_info_changed       = rt2x00mac_bss_info_changed,
1562         .conf_tx                = rt2400pci_conf_tx,
1563         .get_tx_stats           = rt2x00mac_get_tx_stats,
1564         .get_tsf                = rt2400pci_get_tsf,
1565         .tx_last_beacon         = rt2400pci_tx_last_beacon,
1566 };
1567
1568 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1569         .irq_handler            = rt2400pci_interrupt,
1570         .probe_hw               = rt2400pci_probe_hw,
1571         .initialize             = rt2x00pci_initialize,
1572         .uninitialize           = rt2x00pci_uninitialize,
1573         .init_rxentry           = rt2400pci_init_rxentry,
1574         .init_txentry           = rt2400pci_init_txentry,
1575         .set_device_state       = rt2400pci_set_device_state,
1576         .rfkill_poll            = rt2400pci_rfkill_poll,
1577         .link_stats             = rt2400pci_link_stats,
1578         .reset_tuner            = rt2400pci_reset_tuner,
1579         .link_tuner             = rt2400pci_link_tuner,
1580         .write_tx_desc          = rt2400pci_write_tx_desc,
1581         .write_tx_data          = rt2x00pci_write_tx_data,
1582         .write_beacon           = rt2400pci_write_beacon,
1583         .kick_tx_queue          = rt2400pci_kick_tx_queue,
1584         .fill_rxdone            = rt2400pci_fill_rxdone,
1585         .config_filter          = rt2400pci_config_filter,
1586         .config_intf            = rt2400pci_config_intf,
1587         .config_erp             = rt2400pci_config_erp,
1588         .config_ant             = rt2400pci_config_ant,
1589         .config                 = rt2400pci_config,
1590 };
1591
1592 static const struct data_queue_desc rt2400pci_queue_rx = {
1593         .entry_num              = RX_ENTRIES,
1594         .data_size              = DATA_FRAME_SIZE,
1595         .desc_size              = RXD_DESC_SIZE,
1596         .priv_size              = sizeof(struct queue_entry_priv_pci),
1597 };
1598
1599 static const struct data_queue_desc rt2400pci_queue_tx = {
1600         .entry_num              = TX_ENTRIES,
1601         .data_size              = DATA_FRAME_SIZE,
1602         .desc_size              = TXD_DESC_SIZE,
1603         .priv_size              = sizeof(struct queue_entry_priv_pci),
1604 };
1605
1606 static const struct data_queue_desc rt2400pci_queue_bcn = {
1607         .entry_num              = BEACON_ENTRIES,
1608         .data_size              = MGMT_FRAME_SIZE,
1609         .desc_size              = TXD_DESC_SIZE,
1610         .priv_size              = sizeof(struct queue_entry_priv_pci),
1611 };
1612
1613 static const struct data_queue_desc rt2400pci_queue_atim = {
1614         .entry_num              = ATIM_ENTRIES,
1615         .data_size              = DATA_FRAME_SIZE,
1616         .desc_size              = TXD_DESC_SIZE,
1617         .priv_size              = sizeof(struct queue_entry_priv_pci),
1618 };
1619
1620 static const struct rt2x00_ops rt2400pci_ops = {
1621         .name           = KBUILD_MODNAME,
1622         .max_sta_intf   = 1,
1623         .max_ap_intf    = 1,
1624         .eeprom_size    = EEPROM_SIZE,
1625         .rf_size        = RF_SIZE,
1626         .tx_queues      = NUM_TX_QUEUES,
1627         .rx             = &rt2400pci_queue_rx,
1628         .tx             = &rt2400pci_queue_tx,
1629         .bcn            = &rt2400pci_queue_bcn,
1630         .atim           = &rt2400pci_queue_atim,
1631         .lib            = &rt2400pci_rt2x00_ops,
1632         .hw             = &rt2400pci_mac80211_ops,
1633 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1634         .debugfs        = &rt2400pci_rt2x00debug,
1635 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1636 };
1637
1638 /*
1639  * RT2400pci module information.
1640  */
1641 static struct pci_device_id rt2400pci_device_table[] = {
1642         { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1643         { 0, }
1644 };
1645
1646 MODULE_AUTHOR(DRV_PROJECT);
1647 MODULE_VERSION(DRV_VERSION);
1648 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1649 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1650 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1651 MODULE_LICENSE("GPL");
1652
1653 static struct pci_driver rt2400pci_driver = {
1654         .name           = KBUILD_MODNAME,
1655         .id_table       = rt2400pci_device_table,
1656         .probe          = rt2x00pci_probe,
1657         .remove         = __devexit_p(rt2x00pci_remove),
1658         .suspend        = rt2x00pci_suspend,
1659         .resume         = rt2x00pci_resume,
1660 };
1661
1662 static int __init rt2400pci_init(void)
1663 {
1664         return pci_register_driver(&rt2400pci_driver);
1665 }
1666
1667 static void __exit rt2400pci_exit(void)
1668 {
1669         pci_unregister_driver(&rt2400pci_driver);
1670 }
1671
1672 module_init(rt2400pci_init);
1673 module_exit(rt2400pci_exit);