git.oblomov.eu Git - linux-2.6/blob - drivers/char/synclinkmp.c

   1 /*
   2  * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink Multiport
   5  * high speed multiprotocol serial adapter.
   6  *
   7  * written by Paul Fulghum for Microgate Corporation
   8  * paulkf@microgate.com
   9  *
  10  * Microgate and SyncLink are trademarks of Microgate Corporation
  11  *
  12  * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
  13  * This code is released under the GNU General Public License (GPL)
  14  *
  15  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  16  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  19  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  20  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  25  * OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
  29 #if defined(__i386__)
  30 #  define BREAKPOINT() asm("   int $3");
  31 #else
  32 #  define BREAKPOINT() { }
  33 #endif
  34
  35 #define MAX_DEVICES 12
  36
  37 #include <linux/config.h>
  38 #include <linux/module.h>
  39 #include <linux/errno.h>
  40 #include <linux/signal.h>
  41 #include <linux/sched.h>
  42 #include <linux/timer.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/pci.h>
  45 #include <linux/tty.h>
  46 #include <linux/tty_flip.h>
  47 #include <linux/serial.h>
  48 #include <linux/major.h>
  49 #include <linux/string.h>
  50 #include <linux/fcntl.h>
  51 #include <linux/ptrace.h>
  52 #include <linux/ioport.h>
  53 #include <linux/mm.h>
  54 #include <linux/slab.h>
  55 #include <linux/netdevice.h>
  56 #include <linux/vmalloc.h>
  57 #include <linux/init.h>
  58 #include <linux/delay.h>
  59 #include <linux/ioctl.h>
  60
  61 #include <asm/system.h>
  62 #include <asm/io.h>
  63 #include <asm/irq.h>
  64 #include <asm/dma.h>
  65 #include <linux/bitops.h>
  66 #include <asm/types.h>
  67 #include <linux/termios.h>
  68 #include <linux/workqueue.h>
  69 #include <linux/hdlc.h>
  70
  71 #ifdef CONFIG_HDLC_MODULE
  72 #define CONFIG_HDLC 1
  73 #endif
  74
  75 #define GET_USER(error,value,addr) error = get_user(value,addr)
  76 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  77 #define PUT_USER(error,value,addr) error = put_user(value,addr)
  78 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  79
  80 #include <asm/uaccess.h>
  81
  82 #include "linux/synclink.h"
  83
  84 static MGSL_PARAMS default_params = {
  85         MGSL_MODE_HDLC,                 /* unsigned long mode */
  86         0,                              /* unsigned char loopback; */
  87         HDLC_FLAG_UNDERRUN_ABORT15,     /* unsigned short flags; */
  88         HDLC_ENCODING_NRZI_SPACE,       /* unsigned char encoding; */
  89         0,                              /* unsigned long clock_speed; */
  90         0xff,                           /* unsigned char addr_filter; */
  91         HDLC_CRC_16_CCITT,              /* unsigned short crc_type; */
  92         HDLC_PREAMBLE_LENGTH_8BITS,     /* unsigned char preamble_length; */
  93         HDLC_PREAMBLE_PATTERN_NONE,     /* unsigned char preamble; */
  94         9600,                           /* unsigned long data_rate; */
  95         8,                              /* unsigned char data_bits; */
  96         1,                              /* unsigned char stop_bits; */
  97         ASYNC_PARITY_NONE               /* unsigned char parity; */
  98 };
  99
 100 /* size in bytes of DMA data buffers */
 101 #define SCABUFSIZE      1024
 102 #define SCA_MEM_SIZE    0x40000
 103 #define SCA_BASE_SIZE   512
 104 #define SCA_REG_SIZE    16
 105 #define SCA_MAX_PORTS   4
 106 #define SCAMAXDESC      128
 107
 108 #define BUFFERLISTSIZE  4096
 109
 110 /* SCA-I style DMA buffer descriptor */
 111 typedef struct _SCADESC
 112 {
 113         u16     next;           /* lower l6 bits of next descriptor addr */
 114         u16     buf_ptr;        /* lower 16 bits of buffer addr */
 115         u8      buf_base;       /* upper 8 bits of buffer addr */
 116         u8      pad1;
 117         u16     length;         /* length of buffer */
 118         u8      status;         /* status of buffer */
 119         u8      pad2;
 120 } SCADESC, *PSCADESC;
 121
 122 typedef struct _SCADESC_EX
 123 {
 124         /* device driver bookkeeping section */
 125         char    *virt_addr;     /* virtual address of data buffer */
 126         u16     phys_entry;     /* lower 16-bits of physical address of this descriptor */
 127 } SCADESC_EX, *PSCADESC_EX;
 128
 129 /* The queue of BH actions to be performed */
 130
 131 #define BH_RECEIVE  1
 132 #define BH_TRANSMIT 2
 133 #define BH_STATUS   4
 134
 135 #define IO_PIN_SHUTDOWN_LIMIT 100
 136
 137 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
 138
 139 struct  _input_signal_events {
 140         int     ri_up;
 141         int     ri_down;
 142         int     dsr_up;
 143         int     dsr_down;
 144         int     dcd_up;
 145         int     dcd_down;
 146         int     cts_up;
 147         int     cts_down;
 148 };
 149
 150 /*
 151  * Device instance data structure
 152  */
 153 typedef struct _synclinkmp_info {
 154         void *if_ptr;                           /* General purpose pointer (used by SPPP) */
 155         int                     magic;
 156         int                     flags;
 157         int                     count;          /* count of opens */
 158         int                     line;
 159         unsigned short          close_delay;
 160         unsigned short          closing_wait;   /* time to wait before closing */
 161
 162         struct mgsl_icount      icount;
 163
 164         struct tty_struct       *tty;
 165         int                     timeout;
 166         int                     x_char;         /* xon/xoff character */
 167         int                     blocked_open;   /* # of blocked opens */
 168         u16                     read_status_mask1;  /* break detection (SR1 indications) */
 169         u16                     read_status_mask2;  /* parity/framing/overun (SR2 indications) */
 170         unsigned char           ignore_status_mask1;  /* break detection (SR1 indications) */
 171         unsigned char           ignore_status_mask2;  /* parity/framing/overun (SR2 indications) */
 172         unsigned char           *tx_buf;
 173         int                     tx_put;
 174         int                     tx_get;
 175         int                     tx_count;
 176
 177         wait_queue_head_t       open_wait;
 178         wait_queue_head_t       close_wait;
 179
 180         wait_queue_head_t       status_event_wait_q;
 181         wait_queue_head_t       event_wait_q;
 182         struct timer_list       tx_timer;       /* HDLC transmit timeout timer */
 183         struct _synclinkmp_info *next_device;   /* device list link */
 184         struct timer_list       status_timer;   /* input signal status check timer */
 185
 186         spinlock_t lock;                /* spinlock for synchronizing with ISR */
 187         struct work_struct task;                        /* task structure for scheduling bh */
 188
 189         u32 max_frame_size;                     /* as set by device config */
 190
 191         u32 pending_bh;
 192
 193         int bh_running;                         /* Protection from multiple */
 194         int isr_overflow;
 195         int bh_requested;
 196
 197         int dcd_chkcount;                       /* check counts to prevent */
 198         int cts_chkcount;                       /* too many IRQs if a signal */
 199         int dsr_chkcount;                       /* is floating */
 200         int ri_chkcount;
 201
 202         char *buffer_list;                      /* virtual address of Rx & Tx buffer lists */
 203         unsigned long buffer_list_phys;
 204
 205         unsigned int rx_buf_count;              /* count of total allocated Rx buffers */
 206         SCADESC *rx_buf_list;                   /* list of receive buffer entries */
 207         SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
 208         unsigned int current_rx_buf;
 209
 210         unsigned int tx_buf_count;              /* count of total allocated Tx buffers */
 211         SCADESC *tx_buf_list;           /* list of transmit buffer entries */
 212         SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
 213         unsigned int last_tx_buf;
 214
 215         unsigned char *tmp_rx_buf;
 216         unsigned int tmp_rx_buf_count;
 217
 218         int rx_enabled;
 219         int rx_overflow;
 220
 221         int tx_enabled;
 222         int tx_active;
 223         u32 idle_mode;
 224
 225         unsigned char ie0_value;
 226         unsigned char ie1_value;
 227         unsigned char ie2_value;
 228         unsigned char ctrlreg_value;
 229         unsigned char old_signals;
 230
 231         char device_name[25];                   /* device instance name */
 232
 233         int port_count;
 234         int adapter_num;
 235         int port_num;
 236
 237         struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
 238
 239         unsigned int bus_type;                  /* expansion bus type (ISA,EISA,PCI) */
 240
 241         unsigned int irq_level;                 /* interrupt level */
 242         unsigned long irq_flags;
 243         int irq_requested;                      /* nonzero if IRQ requested */
 244
 245         MGSL_PARAMS params;                     /* communications parameters */
 246
 247         unsigned char serial_signals;           /* current serial signal states */
 248
 249         int irq_occurred;                       /* for diagnostics use */
 250         unsigned int init_error;                /* Initialization startup error */
 251
 252         u32 last_mem_alloc;
 253         unsigned char* memory_base;             /* shared memory address (PCI only) */
 254         u32 phys_memory_base;
 255         int shared_mem_requested;
 256
 257         unsigned char* sca_base;                /* HD64570 SCA Memory address */
 258         u32 phys_sca_base;
 259         u32 sca_offset;
 260         int sca_base_requested;
 261
 262         unsigned char* lcr_base;                /* local config registers (PCI only) */
 263         u32 phys_lcr_base;
 264         u32 lcr_offset;
 265         int lcr_mem_requested;
 266
 267         unsigned char* statctrl_base;           /* status/control register memory */
 268         u32 phys_statctrl_base;
 269         u32 statctrl_offset;
 270         int sca_statctrl_requested;
 271
 272         u32 misc_ctrl_value;
 273         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 274         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 275         BOOLEAN drop_rts_on_tx_done;
 276
 277         struct  _input_signal_events    input_signal_events;
 278
 279         /* SPPP/Cisco HDLC device parts */
 280         int netcount;
 281         int dosyncppp;
 282         spinlock_t netlock;
 283
 284 #ifdef CONFIG_HDLC
 285         struct net_device *netdev;
 286 #endif
 287
 288 } SLMP_INFO;
 289
 290 #define MGSL_MAGIC 0x5401
 291
 292 /*
 293  * define serial signal status change macros
 294  */
 295 #define MISCSTATUS_DCD_LATCHED  (SerialSignal_DCD<<8)   /* indicates change in DCD */
 296 #define MISCSTATUS_RI_LATCHED   (SerialSignal_RI<<8)    /* indicates change in RI */
 297 #define MISCSTATUS_CTS_LATCHED  (SerialSignal_CTS<<8)   /* indicates change in CTS */
 298 #define MISCSTATUS_DSR_LATCHED  (SerialSignal_DSR<<8)   /* change in DSR */
 299
 300 /* Common Register macros */
 301 #define LPR     0x00
 302 #define PABR0   0x02
 303 #define PABR1   0x03
 304 #define WCRL    0x04
 305 #define WCRM    0x05
 306 #define WCRH    0x06
 307 #define DPCR    0x08
 308 #define DMER    0x09
 309 #define ISR0    0x10
 310 #define ISR1    0x11
 311 #define ISR2    0x12
 312 #define IER0    0x14
 313 #define IER1    0x15
 314 #define IER2    0x16
 315 #define ITCR    0x18
 316 #define INTVR   0x1a
 317 #define IMVR    0x1c
 318
 319 /* MSCI Register macros */
 320 #define TRB     0x20
 321 #define TRBL    0x20
 322 #define TRBH    0x21
 323 #define SR0     0x22
 324 #define SR1     0x23
 325 #define SR2     0x24
 326 #define SR3     0x25
 327 #define FST     0x26
 328 #define IE0     0x28
 329 #define IE1     0x29
 330 #define IE2     0x2a
 331 #define FIE     0x2b
 332 #define CMD     0x2c
 333 #define MD0     0x2e
 334 #define MD1     0x2f
 335 #define MD2     0x30
 336 #define CTL     0x31
 337 #define SA0     0x32
 338 #define SA1     0x33
 339 #define IDL     0x34
 340 #define TMC     0x35
 341 #define RXS     0x36
 342 #define TXS     0x37
 343 #define TRC0    0x38
 344 #define TRC1    0x39
 345 #define RRC     0x3a
 346 #define CST0    0x3c
 347 #define CST1    0x3d
 348
 349 /* Timer Register Macros */
 350 #define TCNT    0x60
 351 #define TCNTL   0x60
 352 #define TCNTH   0x61
 353 #define TCONR   0x62
 354 #define TCONRL  0x62
 355 #define TCONRH  0x63
 356 #define TMCS    0x64
 357 #define TEPR    0x65
 358
 359 /* DMA Controller Register macros */
 360 #define DARL    0x80
 361 #define DARH    0x81
 362 #define DARB    0x82
 363 #define BAR     0x80
 364 #define BARL    0x80
 365 #define BARH    0x81
 366 #define BARB    0x82
 367 #define SAR     0x84
 368 #define SARL    0x84
 369 #define SARH    0x85
 370 #define SARB    0x86
 371 #define CPB     0x86
 372 #define CDA     0x88
 373 #define CDAL    0x88
 374 #define CDAH    0x89
 375 #define EDA     0x8a
 376 #define EDAL    0x8a
 377 #define EDAH    0x8b
 378 #define BFL     0x8c
 379 #define BFLL    0x8c
 380 #define BFLH    0x8d
 381 #define BCR     0x8e
 382 #define BCRL    0x8e
 383 #define BCRH    0x8f
 384 #define DSR     0x90
 385 #define DMR     0x91
 386 #define FCT     0x93
 387 #define DIR     0x94
 388 #define DCMD    0x95
 389
 390 /* combine with timer or DMA register address */
 391 #define TIMER0  0x00
 392 #define TIMER1  0x08
 393 #define TIMER2  0x10
 394 #define TIMER3  0x18
 395 #define RXDMA   0x00
 396 #define TXDMA   0x20
 397
 398 /* SCA Command Codes */
 399 #define NOOP            0x00
 400 #define TXRESET         0x01
 401 #define TXENABLE        0x02
 402 #define TXDISABLE       0x03
 403 #define TXCRCINIT       0x04
 404 #define TXCRCEXCL       0x05
 405 #define TXEOM           0x06
 406 #define TXABORT         0x07
 407 #define MPON            0x08
 408 #define TXBUFCLR        0x09
 409 #define RXRESET         0x11
 410 #define RXENABLE        0x12
 411 #define RXDISABLE       0x13
 412 #define RXCRCINIT       0x14
 413 #define RXREJECT        0x15
 414 #define SEARCHMP        0x16
 415 #define RXCRCEXCL       0x17
 416 #define RXCRCCALC       0x18
 417 #define CHRESET         0x21
 418 #define HUNT            0x31
 419
 420 /* DMA command codes */
 421 #define SWABORT         0x01
 422 #define FEICLEAR        0x02
 423
 424 /* IE0 */
 425 #define TXINTE          BIT7
 426 #define RXINTE          BIT6
 427 #define TXRDYE          BIT1
 428 #define RXRDYE          BIT0
 429
 430 /* IE1 & SR1 */
 431 #define UDRN    BIT7
 432 #define IDLE    BIT6
 433 #define SYNCD   BIT4
 434 #define FLGD    BIT4
 435 #define CCTS    BIT3
 436 #define CDCD    BIT2
 437 #define BRKD    BIT1
 438 #define ABTD    BIT1
 439 #define GAPD    BIT1
 440 #define BRKE    BIT0
 441 #define IDLD    BIT0
 442
 443 /* IE2 & SR2 */
 444 #define EOM     BIT7
 445 #define PMP     BIT6
 446 #define SHRT    BIT6
 447 #define PE      BIT5
 448 #define ABT     BIT5
 449 #define FRME    BIT4
 450 #define RBIT    BIT4
 451 #define OVRN    BIT3
 452 #define CRCE    BIT2
 453
 454
 455 /*
 456  * Global linked list of SyncLink devices
 457  */
 458 static SLMP_INFO *synclinkmp_device_list = NULL;
 459 static int synclinkmp_adapter_count = -1;
 460 static int synclinkmp_device_count = 0;
 461
 462 /*
 463  * Set this param to non-zero to load eax with the
 464  * .text section address and breakpoint on module load.
 465  * This is useful for use with gdb and add-symbol-file command.
 466  */
 467 static int break_on_load=0;
 468
 469 /*
 470  * Driver major number, defaults to zero to get auto
 471  * assigned major number. May be forced as module parameter.
 472  */
 473 static int ttymajor=0;
 474
 475 /*
 476  * Array of user specified options for ISA adapters.
 477  */
 478 static int debug_level = 0;
 479 static int maxframe[MAX_DEVICES] = {0,};
 480 static int dosyncppp[MAX_DEVICES] = {0,};
 481
 482 module_param(break_on_load, bool, 0);
 483 module_param(ttymajor, int, 0);
 484 module_param(debug_level, int, 0);
 485 module_param_array(maxframe, int, NULL, 0);
 486 module_param_array(dosyncppp, int, NULL, 0);
 487
 488 static char *driver_name = "SyncLink MultiPort driver";
 489 static char *driver_version = "$Revision: 4.38 $";
 490
 491 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 492 static void synclinkmp_remove_one(struct pci_dev *dev);
 493
 494 static struct pci_device_id synclinkmp_pci_tbl[] = {
 495         { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
 496         { 0, }, /* terminate list */
 497 };
 498 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
 499
 500 MODULE_LICENSE("GPL");
 501
 502 static struct pci_driver synclinkmp_pci_driver = {
 503         .owner          = THIS_MODULE,
 504         .name           = "synclinkmp",
 505         .id_table       = synclinkmp_pci_tbl,
 506         .probe          = synclinkmp_init_one,
 507         .remove         = __devexit_p(synclinkmp_remove_one),
 508 };
 509
 510
 511 static struct tty_driver *serial_driver;
 512
 513 /* number of characters left in xmit buffer before we ask for more */
 514 #define WAKEUP_CHARS 256
 515
 516
 517 /* tty callbacks */
 518
 519 static int  open(struct tty_struct *tty, struct file * filp);
 520 static void close(struct tty_struct *tty, struct file * filp);
 521 static void hangup(struct tty_struct *tty);
 522 static void set_termios(struct tty_struct *tty, struct termios *old_termios);
 523
 524 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 525 static void put_char(struct tty_struct *tty, unsigned char ch);
 526 static void send_xchar(struct tty_struct *tty, char ch);
 527 static void wait_until_sent(struct tty_struct *tty, int timeout);
 528 static int  write_room(struct tty_struct *tty);
 529 static void flush_chars(struct tty_struct *tty);
 530 static void flush_buffer(struct tty_struct *tty);
 531 static void tx_hold(struct tty_struct *tty);
 532 static void tx_release(struct tty_struct *tty);
 533
 534 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 535 static int  read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
 536 static int  chars_in_buffer(struct tty_struct *tty);
 537 static void throttle(struct tty_struct * tty);
 538 static void unthrottle(struct tty_struct * tty);
 539 static void set_break(struct tty_struct *tty, int break_state);
 540
 541 #ifdef CONFIG_HDLC
 542 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 543 static void hdlcdev_tx_done(SLMP_INFO *info);
 544 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
 545 static int  hdlcdev_init(SLMP_INFO *info);
 546 static void hdlcdev_exit(SLMP_INFO *info);
 547 #endif
 548
 549 /* ioctl handlers */
 550
 551 static int  get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
 552 static int  get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 553 static int  set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 554 static int  get_txidle(SLMP_INFO *info, int __user *idle_mode);
 555 static int  set_txidle(SLMP_INFO *info, int idle_mode);
 556 static int  tx_enable(SLMP_INFO *info, int enable);
 557 static int  tx_abort(SLMP_INFO *info);
 558 static int  rx_enable(SLMP_INFO *info, int enable);
 559 static int  modem_input_wait(SLMP_INFO *info,int arg);
 560 static int  wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
 561 static int  tiocmget(struct tty_struct *tty, struct file *file);
 562 static int  tiocmset(struct tty_struct *tty, struct file *file,
 563                      unsigned int set, unsigned int clear);
 564 static void set_break(struct tty_struct *tty, int break_state);
 565
 566 static void add_device(SLMP_INFO *info);
 567 static void device_init(int adapter_num, struct pci_dev *pdev);
 568 static int  claim_resources(SLMP_INFO *info);
 569 static void release_resources(SLMP_INFO *info);
 570
 571 static int  startup(SLMP_INFO *info);
 572 static int  block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
 573 static void shutdown(SLMP_INFO *info);
 574 static void program_hw(SLMP_INFO *info);
 575 static void change_params(SLMP_INFO *info);
 576
 577 static int  init_adapter(SLMP_INFO *info);
 578 static int  register_test(SLMP_INFO *info);
 579 static int  irq_test(SLMP_INFO *info);
 580 static int  loopback_test(SLMP_INFO *info);
 581 static int  adapter_test(SLMP_INFO *info);
 582 static int  memory_test(SLMP_INFO *info);
 583
 584 static void reset_adapter(SLMP_INFO *info);
 585 static void reset_port(SLMP_INFO *info);
 586 static void async_mode(SLMP_INFO *info);
 587 static void hdlc_mode(SLMP_INFO *info);
 588
 589 static void rx_stop(SLMP_INFO *info);
 590 static void rx_start(SLMP_INFO *info);
 591 static void rx_reset_buffers(SLMP_INFO *info);
 592 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
 593 static int  rx_get_frame(SLMP_INFO *info);
 594
 595 static void tx_start(SLMP_INFO *info);
 596 static void tx_stop(SLMP_INFO *info);
 597 static void tx_load_fifo(SLMP_INFO *info);
 598 static void tx_set_idle(SLMP_INFO *info);
 599 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
 600
 601 static void get_signals(SLMP_INFO *info);
 602 static void set_signals(SLMP_INFO *info);
 603 static void enable_loopback(SLMP_INFO *info, int enable);
 604 static void set_rate(SLMP_INFO *info, u32 data_rate);
 605
 606 static int  bh_action(SLMP_INFO *info);
 607 static void bh_handler(void* Context);
 608 static void bh_receive(SLMP_INFO *info);
 609 static void bh_transmit(SLMP_INFO *info);
 610 static void bh_status(SLMP_INFO *info);
 611 static void isr_timer(SLMP_INFO *info);
 612 static void isr_rxint(SLMP_INFO *info);
 613 static void isr_rxrdy(SLMP_INFO *info);
 614 static void isr_txint(SLMP_INFO *info);
 615 static void isr_txrdy(SLMP_INFO *info);
 616 static void isr_rxdmaok(SLMP_INFO *info);
 617 static void isr_rxdmaerror(SLMP_INFO *info);
 618 static void isr_txdmaok(SLMP_INFO *info);
 619 static void isr_txdmaerror(SLMP_INFO *info);
 620 static void isr_io_pin(SLMP_INFO *info, u16 status);
 621
 622 static int  alloc_dma_bufs(SLMP_INFO *info);
 623 static void free_dma_bufs(SLMP_INFO *info);
 624 static int  alloc_buf_list(SLMP_INFO *info);
 625 static int  alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
 626 static int  alloc_tmp_rx_buf(SLMP_INFO *info);
 627 static void free_tmp_rx_buf(SLMP_INFO *info);
 628
 629 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
 630 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
 631 static void tx_timeout(unsigned long context);
 632 static void status_timeout(unsigned long context);
 633
 634 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
 635 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
 636 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
 637 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
 638 static unsigned char read_status_reg(SLMP_INFO * info);
 639 static void write_control_reg(SLMP_INFO * info);
 640
 641
 642 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
 643 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
 644 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
 645
 646 static u32 misc_ctrl_value = 0x007e4040;
 647 static u32 lcr1_brdr_value = 0x00800028;
 648
 649 static u32 read_ahead_count = 8;
 650
 651 /* DPCR, DMA Priority Control
 652  *
 653  * 07..05  Not used, must be 0
 654  * 04      BRC, bus release condition: 0=all transfers complete
 655  *              1=release after 1 xfer on all channels
 656  * 03      CCC, channel change condition: 0=every cycle
 657  *              1=after each channel completes all xfers
 658  * 02..00  PR<2..0>, priority 100=round robin
 659  *
 660  * 00000100 = 0x00
 661  */
 662 static unsigned char dma_priority = 0x04;
 663
 664 // Number of bytes that can be written to shared RAM
 665 // in a single write operation
 666 static u32 sca_pci_load_interval = 64;
 667
 668 /*
 669  * 1st function defined in .text section. Calling this function in
 670  * init_module() followed by a breakpoint allows a remote debugger
 671  * (gdb) to get the .text address for the add-symbol-file command.
 672  * This allows remote debugging of dynamically loadable modules.
 673  */
 674 static void* synclinkmp_get_text_ptr(void);
 675 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
 676
 677 static inline int sanity_check(SLMP_INFO *info,
 678                                char *name, const char *routine)
 679 {
 680 #ifdef SANITY_CHECK
 681         static const char *badmagic =
 682                 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
 683         static const char *badinfo =
 684                 "Warning: null synclinkmp_struct for (%s) in %s\n";
 685
 686         if (!info) {
 687                 printk(badinfo, name, routine);
 688                 return 1;
 689         }
 690         if (info->magic != MGSL_MAGIC) {
 691                 printk(badmagic, name, routine);
 692                 return 1;
 693         }
 694 #else
 695         if (!info)
 696                 return 1;
 697 #endif
 698         return 0;
 699 }
 700
 701 /**
 702  * line discipline callback wrappers
 703  *
 704  * The wrappers maintain line discipline references
 705  * while calling into the line discipline.
 706  *
 707  * ldisc_receive_buf  - pass receive data to line discipline
 708  */
 709
 710 static void ldisc_receive_buf(struct tty_struct *tty,
 711                               const __u8 *data, char *flags, int count)
 712 {
 713         struct tty_ldisc *ld;
 714         if (!tty)
 715                 return;
 716         ld = tty_ldisc_ref(tty);
 717         if (ld) {
 718                 if (ld->receive_buf)
 719                         ld->receive_buf(tty, data, flags, count);
 720                 tty_ldisc_deref(ld);
 721         }
 722 }
 723
 724 /* tty callbacks */
 725
 726 /* Called when a port is opened.  Init and enable port.
 727  */
 728 static int open(struct tty_struct *tty, struct file *filp)
 729 {
 730         SLMP_INFO *info;
 731         int retval, line;
 732         unsigned long flags;
 733
 734         line = tty->index;
 735         if ((line < 0) || (line >= synclinkmp_device_count)) {
 736                 printk("%s(%d): open with invalid line #%d.\n",
 737                         __FILE__,__LINE__,line);
 738                 return -ENODEV;
 739         }
 740
 741         info = synclinkmp_device_list;
 742         while(info && info->line != line)
 743                 info = info->next_device;
 744         if (sanity_check(info, tty->name, "open"))
 745                 return -ENODEV;
 746         if ( info->init_error ) {
 747                 printk("%s(%d):%s device is not allocated, init error=%d\n",
 748                         __FILE__,__LINE__,info->device_name,info->init_error);
 749                 return -ENODEV;
 750         }
 751
 752         tty->driver_data = info;
 753         info->tty = tty;
 754
 755         if (debug_level >= DEBUG_LEVEL_INFO)
 756                 printk("%s(%d):%s open(), old ref count = %d\n",
 757                          __FILE__,__LINE__,tty->driver->name, info->count);
 758
 759         /* If port is closing, signal caller to try again */
 760         if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
 761                 if (info->flags & ASYNC_CLOSING)
 762                         interruptible_sleep_on(&info->close_wait);
 763                 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
 764                         -EAGAIN : -ERESTARTSYS);
 765                 goto cleanup;
 766         }
 767
 768         info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 769
 770         spin_lock_irqsave(&info->netlock, flags);
 771         if (info->netcount) {
 772                 retval = -EBUSY;
 773                 spin_unlock_irqrestore(&info->netlock, flags);
 774                 goto cleanup;
 775         }
 776         info->count++;
 777         spin_unlock_irqrestore(&info->netlock, flags);
 778
 779         if (info->count == 1) {
 780                 /* 1st open on this device, init hardware */
 781                 retval = startup(info);
 782                 if (retval < 0)
 783                         goto cleanup;
 784         }
 785
 786         retval = block_til_ready(tty, filp, info);
 787         if (retval) {
 788                 if (debug_level >= DEBUG_LEVEL_INFO)
 789                         printk("%s(%d):%s block_til_ready() returned %d\n",
 790                                  __FILE__,__LINE__, info->device_name, retval);
 791                 goto cleanup;
 792         }
 793
 794         if (debug_level >= DEBUG_LEVEL_INFO)
 795                 printk("%s(%d):%s open() success\n",
 796                          __FILE__,__LINE__, info->device_name);
 797         retval = 0;
 798
 799 cleanup:
 800         if (retval) {
 801                 if (tty->count == 1)
 802                         info->tty = NULL; /* tty layer will release tty struct */
 803                 if(info->count)
 804                         info->count--;
 805         }
 806
 807         return retval;
 808 }
 809
 810 /* Called when port is closed. Wait for remaining data to be
 811  * sent. Disable port and free resources.
 812  */
 813 static void close(struct tty_struct *tty, struct file *filp)
 814 {
 815         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
 816
 817         if (sanity_check(info, tty->name, "close"))
 818                 return;
 819
 820         if (debug_level >= DEBUG_LEVEL_INFO)
 821                 printk("%s(%d):%s close() entry, count=%d\n",
 822                          __FILE__,__LINE__, info->device_name, info->count);
 823
 824         if (!info->count)
 825                 return;
 826
 827         if (tty_hung_up_p(filp))
 828                 goto cleanup;
 829
 830         if ((tty->count == 1) && (info->count != 1)) {
 831                 /*
 832                  * tty->count is 1 and the tty structure will be freed.
 833                  * info->count should be one in this case.
 834                  * if it's not, correct it so that the port is shutdown.
 835                  */
 836                 printk("%s(%d):%s close: bad refcount; tty->count is 1, "
 837                        "info->count is %d\n",
 838                          __FILE__,__LINE__, info->device_name, info->count);
 839                 info->count = 1;
 840         }
 841
 842         info->count--;
 843
 844         /* if at least one open remaining, leave hardware active */
 845         if (info->count)
 846                 goto cleanup;
 847
 848         info->flags |= ASYNC_CLOSING;
 849
 850         /* set tty->closing to notify line discipline to
 851          * only process XON/XOFF characters. Only the N_TTY
 852          * discipline appears to use this (ppp does not).
 853          */
 854         tty->closing = 1;
 855
 856         /* wait for transmit data to clear all layers */
 857
 858         if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
 859                 if (debug_level >= DEBUG_LEVEL_INFO)
 860                         printk("%s(%d):%s close() calling tty_wait_until_sent\n",
 861                                  __FILE__,__LINE__, info->device_name );
 862                 tty_wait_until_sent(tty, info->closing_wait);
 863         }
 864
 865         if (info->flags & ASYNC_INITIALIZED)
 866                 wait_until_sent(tty, info->timeout);
 867
 868         if (tty->driver->flush_buffer)
 869                 tty->driver->flush_buffer(tty);
 870
 871         tty_ldisc_flush(tty);
 872
 873         shutdown(info);
 874
 875         tty->closing = 0;
 876         info->tty = NULL;
 877
 878         if (info->blocked_open) {
 879                 if (info->close_delay) {
 880                         msleep_interruptible(jiffies_to_msecs(info->close_delay));
 881                 }
 882                 wake_up_interruptible(&info->open_wait);
 883         }
 884
 885         info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
 886
 887         wake_up_interruptible(&info->close_wait);
 888
 889 cleanup:
 890         if (debug_level >= DEBUG_LEVEL_INFO)
 891                 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
 892                         tty->driver->name, info->count);
 893 }
 894
 895 /* Called by tty_hangup() when a hangup is signaled.
 896  * This is the same as closing all open descriptors for the port.
 897  */
 898 static void hangup(struct tty_struct *tty)
 899 {
 900         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 901
 902         if (debug_level >= DEBUG_LEVEL_INFO)
 903                 printk("%s(%d):%s hangup()\n",
 904                          __FILE__,__LINE__, info->device_name );
 905
 906         if (sanity_check(info, tty->name, "hangup"))
 907                 return;
 908
 909         flush_buffer(tty);
 910         shutdown(info);
 911
 912         info->count = 0;
 913         info->flags &= ~ASYNC_NORMAL_ACTIVE;
 914         info->tty = NULL;
 915
 916         wake_up_interruptible(&info->open_wait);
 917 }
 918
 919 /* Set new termios settings
 920  */
 921 static void set_termios(struct tty_struct *tty, struct termios *old_termios)
 922 {
 923         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 924         unsigned long flags;
 925
 926         if (debug_level >= DEBUG_LEVEL_INFO)
 927                 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
 928                         tty->driver->name );
 929
 930         /* just return if nothing has changed */
 931         if ((tty->termios->c_cflag == old_termios->c_cflag)
 932             && (RELEVANT_IFLAG(tty->termios->c_iflag)
 933                 == RELEVANT_IFLAG(old_termios->c_iflag)))
 934           return;
 935
 936         change_params(info);
 937
 938         /* Handle transition to B0 status */
 939         if (old_termios->c_cflag & CBAUD &&
 940             !(tty->termios->c_cflag & CBAUD)) {
 941                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 942                 spin_lock_irqsave(&info->lock,flags);
 943                 set_signals(info);
 944                 spin_unlock_irqrestore(&info->lock,flags);
 945         }
 946
 947         /* Handle transition away from B0 status */
 948         if (!(old_termios->c_cflag & CBAUD) &&
 949             tty->termios->c_cflag & CBAUD) {
 950                 info->serial_signals |= SerialSignal_DTR;
 951                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 952                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 953                         info->serial_signals |= SerialSignal_RTS;
 954                 }
 955                 spin_lock_irqsave(&info->lock,flags);
 956                 set_signals(info);
 957                 spin_unlock_irqrestore(&info->lock,flags);
 958         }
 959
 960         /* Handle turning off CRTSCTS */
 961         if (old_termios->c_cflag & CRTSCTS &&
 962             !(tty->termios->c_cflag & CRTSCTS)) {
 963                 tty->hw_stopped = 0;
 964                 tx_release(tty);
 965         }
 966 }
 967
 968 /* Send a block of data
 969  *
 970  * Arguments:
 971  *
 972  *      tty             pointer to tty information structure
 973  *      buf             pointer to buffer containing send data
 974  *      count           size of send data in bytes
 975  *
 976  * Return Value:        number of characters written
 977  */
 978 static int write(struct tty_struct *tty,
 979                  const unsigned char *buf, int count)
 980 {
 981         int     c, ret = 0;
 982         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 983         unsigned long flags;
 984
 985         if (debug_level >= DEBUG_LEVEL_INFO)
 986                 printk("%s(%d):%s write() count=%d\n",
 987                        __FILE__,__LINE__,info->device_name,count);
 988
 989         if (sanity_check(info, tty->name, "write"))
 990                 goto cleanup;
 991
 992         if (!tty || !info->tx_buf)
 993                 goto cleanup;
 994
 995         if (info->params.mode == MGSL_MODE_HDLC) {
 996                 if (count > info->max_frame_size) {
 997                         ret = -EIO;
 998                         goto cleanup;
 999                 }
1000                 if (info->tx_active)
1001                         goto cleanup;
1002                 if (info->tx_count) {
1003                         /* send accumulated data from send_char() calls */
1004                         /* as frame and wait before accepting more data. */
1005                         tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1006                         goto start;
1007                 }
1008                 ret = info->tx_count = count;
1009                 tx_load_dma_buffer(info, buf, count);
1010                 goto start;
1011         }
1012
1013         for (;;) {
1014                 c = min_t(int, count,
1015                         min(info->max_frame_size - info->tx_count - 1,
1016                             info->max_frame_size - info->tx_put));
1017                 if (c <= 0)
1018                         break;
1019
1020                 memcpy(info->tx_buf + info->tx_put, buf, c);
1021
1022                 spin_lock_irqsave(&info->lock,flags);
1023                 info->tx_put += c;
1024                 if (info->tx_put >= info->max_frame_size)
1025                         info->tx_put -= info->max_frame_size;
1026                 info->tx_count += c;
1027                 spin_unlock_irqrestore(&info->lock,flags);
1028
1029                 buf += c;
1030                 count -= c;
1031                 ret += c;
1032         }
1033
1034         if (info->params.mode == MGSL_MODE_HDLC) {
1035                 if (count) {
1036                         ret = info->tx_count = 0;
1037                         goto cleanup;
1038                 }
1039                 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1040         }
1041 start:
1042         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1043                 spin_lock_irqsave(&info->lock,flags);
1044                 if (!info->tx_active)
1045                         tx_start(info);
1046                 spin_unlock_irqrestore(&info->lock,flags);
1047         }
1048
1049 cleanup:
1050         if (debug_level >= DEBUG_LEVEL_INFO)
1051                 printk( "%s(%d):%s write() returning=%d\n",
1052                         __FILE__,__LINE__,info->device_name,ret);
1053         return ret;
1054 }
1055
1056 /* Add a character to the transmit buffer.
1057  */
1058 static void put_char(struct tty_struct *tty, unsigned char ch)
1059 {
1060         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1061         unsigned long flags;
1062
1063         if ( debug_level >= DEBUG_LEVEL_INFO ) {
1064                 printk( "%s(%d):%s put_char(%d)\n",
1065                         __FILE__,__LINE__,info->device_name,ch);
1066         }
1067
1068         if (sanity_check(info, tty->name, "put_char"))
1069                 return;
1070
1071         if (!tty || !info->tx_buf)
1072                 return;
1073
1074         spin_lock_irqsave(&info->lock,flags);
1075
1076         if ( (info->params.mode != MGSL_MODE_HDLC) ||
1077              !info->tx_active ) {
1078
1079                 if (info->tx_count < info->max_frame_size - 1) {
1080                         info->tx_buf[info->tx_put++] = ch;
1081                         if (info->tx_put >= info->max_frame_size)
1082                                 info->tx_put -= info->max_frame_size;
1083                         info->tx_count++;
1084                 }
1085         }
1086
1087         spin_unlock_irqrestore(&info->lock,flags);
1088 }
1089
1090 /* Send a high-priority XON/XOFF character
1091  */
1092 static void send_xchar(struct tty_struct *tty, char ch)
1093 {
1094         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1095         unsigned long flags;
1096
1097         if (debug_level >= DEBUG_LEVEL_INFO)
1098                 printk("%s(%d):%s send_xchar(%d)\n",
1099                          __FILE__,__LINE__, info->device_name, ch );
1100
1101         if (sanity_check(info, tty->name, "send_xchar"))
1102                 return;
1103
1104         info->x_char = ch;
1105         if (ch) {
1106                 /* Make sure transmit interrupts are on */
1107                 spin_lock_irqsave(&info->lock,flags);
1108                 if (!info->tx_enabled)
1109                         tx_start(info);
1110                 spin_unlock_irqrestore(&info->lock,flags);
1111         }
1112 }
1113
1114 /* Wait until the transmitter is empty.
1115  */
1116 static void wait_until_sent(struct tty_struct *tty, int timeout)
1117 {
1118         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1119         unsigned long orig_jiffies, char_time;
1120
1121         if (!info )
1122                 return;
1123
1124         if (debug_level >= DEBUG_LEVEL_INFO)
1125                 printk("%s(%d):%s wait_until_sent() entry\n",
1126                          __FILE__,__LINE__, info->device_name );
1127
1128         if (sanity_check(info, tty->name, "wait_until_sent"))
1129                 return;
1130
1131         if (!(info->flags & ASYNC_INITIALIZED))
1132                 goto exit;
1133
1134         orig_jiffies = jiffies;
1135
1136         /* Set check interval to 1/5 of estimated time to
1137          * send a character, and make it at least 1. The check
1138          * interval should also be less than the timeout.
1139          * Note: use tight timings here to satisfy the NIST-PCTS.
1140          */
1141
1142         if ( info->params.data_rate ) {
1143                 char_time = info->timeout/(32 * 5);
1144                 if (!char_time)
1145                         char_time++;
1146         } else
1147                 char_time = 1;
1148
1149         if (timeout)
1150                 char_time = min_t(unsigned long, char_time, timeout);
1151
1152         if ( info->params.mode == MGSL_MODE_HDLC ) {
1153                 while (info->tx_active) {
1154                         msleep_interruptible(jiffies_to_msecs(char_time));
1155                         if (signal_pending(current))
1156                                 break;
1157                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1158                                 break;
1159                 }
1160         } else {
1161                 //TODO: determine if there is something similar to USC16C32
1162                 //      TXSTATUS_ALL_SENT status
1163                 while ( info->tx_active && info->tx_enabled) {
1164                         msleep_interruptible(jiffies_to_msecs(char_time));
1165                         if (signal_pending(current))
1166                                 break;
1167                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1168                                 break;
1169                 }
1170         }
1171
1172 exit:
1173         if (debug_level >= DEBUG_LEVEL_INFO)
1174                 printk("%s(%d):%s wait_until_sent() exit\n",
1175                          __FILE__,__LINE__, info->device_name );
1176 }
1177
1178 /* Return the count of free bytes in transmit buffer
1179  */
1180 static int write_room(struct tty_struct *tty)
1181 {
1182         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1183         int ret;
1184
1185         if (sanity_check(info, tty->name, "write_room"))
1186                 return 0;
1187
1188         if (info->params.mode == MGSL_MODE_HDLC) {
1189                 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1190         } else {
1191                 ret = info->max_frame_size - info->tx_count - 1;
1192                 if (ret < 0)
1193                         ret = 0;
1194         }
1195
1196         if (debug_level >= DEBUG_LEVEL_INFO)
1197                 printk("%s(%d):%s write_room()=%d\n",
1198                        __FILE__, __LINE__, info->device_name, ret);
1199
1200         return ret;
1201 }
1202
1203 /* enable transmitter and send remaining buffered characters
1204  */
1205 static void flush_chars(struct tty_struct *tty)
1206 {
1207         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1208         unsigned long flags;
1209
1210         if ( debug_level >= DEBUG_LEVEL_INFO )
1211                 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1212                         __FILE__,__LINE__,info->device_name,info->tx_count);
1213
1214         if (sanity_check(info, tty->name, "flush_chars"))
1215                 return;
1216
1217         if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1218             !info->tx_buf)
1219                 return;
1220
1221         if ( debug_level >= DEBUG_LEVEL_INFO )
1222                 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1223                         __FILE__,__LINE__,info->device_name );
1224
1225         spin_lock_irqsave(&info->lock,flags);
1226
1227         if (!info->tx_active) {
1228                 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1229                         info->tx_count ) {
1230                         /* operating in synchronous (frame oriented) mode */
1231                         /* copy data from circular tx_buf to */
1232                         /* transmit DMA buffer. */
1233                         tx_load_dma_buffer(info,
1234                                  info->tx_buf,info->tx_count);
1235                 }
1236                 tx_start(info);
1237         }
1238
1239         spin_unlock_irqrestore(&info->lock,flags);
1240 }
1241
1242 /* Discard all data in the send buffer
1243  */
1244 static void flush_buffer(struct tty_struct *tty)
1245 {
1246         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1247         unsigned long flags;
1248
1249         if (debug_level >= DEBUG_LEVEL_INFO)
1250                 printk("%s(%d):%s flush_buffer() entry\n",
1251                          __FILE__,__LINE__, info->device_name );
1252
1253         if (sanity_check(info, tty->name, "flush_buffer"))
1254                 return;
1255
1256         spin_lock_irqsave(&info->lock,flags);
1257         info->tx_count = info->tx_put = info->tx_get = 0;
1258         del_timer(&info->tx_timer);
1259         spin_unlock_irqrestore(&info->lock,flags);
1260
1261         wake_up_interruptible(&tty->write_wait);
1262         tty_wakeup(tty);
1263 }
1264
1265 /* throttle (stop) transmitter
1266  */
1267 static void tx_hold(struct tty_struct *tty)
1268 {
1269         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1270         unsigned long flags;
1271
1272         if (sanity_check(info, tty->name, "tx_hold"))
1273                 return;
1274
1275         if ( debug_level >= DEBUG_LEVEL_INFO )
1276                 printk("%s(%d):%s tx_hold()\n",
1277                         __FILE__,__LINE__,info->device_name);
1278
1279         spin_lock_irqsave(&info->lock,flags);
1280         if (info->tx_enabled)
1281                 tx_stop(info);
1282         spin_unlock_irqrestore(&info->lock,flags);
1283 }
1284
1285 /* release (start) transmitter
1286  */
1287 static void tx_release(struct tty_struct *tty)
1288 {
1289         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1290         unsigned long flags;
1291
1292         if (sanity_check(info, tty->name, "tx_release"))
1293                 return;
1294
1295         if ( debug_level >= DEBUG_LEVEL_INFO )
1296                 printk("%s(%d):%s tx_release()\n",
1297                         __FILE__,__LINE__,info->device_name);
1298
1299         spin_lock_irqsave(&info->lock,flags);
1300         if (!info->tx_enabled)
1301                 tx_start(info);
1302         spin_unlock_irqrestore(&info->lock,flags);
1303 }
1304
1305 /* Service an IOCTL request
1306  *
1307  * Arguments:
1308  *
1309  *      tty     pointer to tty instance data
1310  *      file    pointer to associated file object for device
1311  *      cmd     IOCTL command code
1312  *      arg     command argument/context
1313  *
1314  * Return Value:        0 if success, otherwise error code
1315  */
1316 static int ioctl(struct tty_struct *tty, struct file *file,
1317                  unsigned int cmd, unsigned long arg)
1318 {
1319         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1320         int error;
1321         struct mgsl_icount cnow;        /* kernel counter temps */
1322         struct serial_icounter_struct __user *p_cuser;  /* user space */
1323         unsigned long flags;
1324         void __user *argp = (void __user *)arg;
1325
1326         if (debug_level >= DEBUG_LEVEL_INFO)
1327                 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1328                         info->device_name, cmd );
1329
1330         if (sanity_check(info, tty->name, "ioctl"))
1331                 return -ENODEV;
1332
1333         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1334             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1335                 if (tty->flags & (1 << TTY_IO_ERROR))
1336                     return -EIO;
1337         }
1338
1339         switch (cmd) {
1340         case MGSL_IOCGPARAMS:
1341                 return get_params(info, argp);
1342         case MGSL_IOCSPARAMS:
1343                 return set_params(info, argp);
1344         case MGSL_IOCGTXIDLE:
1345                 return get_txidle(info, argp);
1346         case MGSL_IOCSTXIDLE:
1347                 return set_txidle(info, (int)arg);
1348         case MGSL_IOCTXENABLE:
1349                 return tx_enable(info, (int)arg);
1350         case MGSL_IOCRXENABLE:
1351                 return rx_enable(info, (int)arg);
1352         case MGSL_IOCTXABORT:
1353                 return tx_abort(info);
1354         case MGSL_IOCGSTATS:
1355                 return get_stats(info, argp);
1356         case MGSL_IOCWAITEVENT:
1357                 return wait_mgsl_event(info, argp);
1358         case MGSL_IOCLOOPTXDONE:
1359                 return 0; // TODO: Not supported, need to document
1360                 /* Wait for modem input (DCD,RI,DSR,CTS) change
1361                  * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1362                  */
1363         case TIOCMIWAIT:
1364                 return modem_input_wait(info,(int)arg);
1365
1366                 /*
1367                  * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1368                  * Return: write counters to the user passed counter struct
1369                  * NB: both 1->0 and 0->1 transitions are counted except for
1370                  *     RI where only 0->1 is counted.
1371                  */
1372         case TIOCGICOUNT:
1373                 spin_lock_irqsave(&info->lock,flags);
1374                 cnow = info->icount;
1375                 spin_unlock_irqrestore(&info->lock,flags);
1376                 p_cuser = argp;
1377                 PUT_USER(error,cnow.cts, &p_cuser->cts);
1378                 if (error) return error;
1379                 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
1380                 if (error) return error;
1381                 PUT_USER(error,cnow.rng, &p_cuser->rng);
1382                 if (error) return error;
1383                 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
1384                 if (error) return error;
1385                 PUT_USER(error,cnow.rx, &p_cuser->rx);
1386                 if (error) return error;
1387                 PUT_USER(error,cnow.tx, &p_cuser->tx);
1388                 if (error) return error;
1389                 PUT_USER(error,cnow.frame, &p_cuser->frame);
1390                 if (error) return error;
1391                 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
1392                 if (error) return error;
1393                 PUT_USER(error,cnow.parity, &p_cuser->parity);
1394                 if (error) return error;
1395                 PUT_USER(error,cnow.brk, &p_cuser->brk);
1396                 if (error) return error;
1397                 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
1398                 if (error) return error;
1399                 return 0;
1400         default:
1401                 return -ENOIOCTLCMD;
1402         }
1403         return 0;
1404 }
1405
1406 /*
1407  * /proc fs routines....
1408  */
1409
1410 static inline int line_info(char *buf, SLMP_INFO *info)
1411 {
1412         char    stat_buf[30];
1413         int     ret;
1414         unsigned long flags;
1415
1416         ret = sprintf(buf, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1417                        "\tIRQ=%d MaxFrameSize=%u\n",
1418                 info->device_name,
1419                 info->phys_sca_base,
1420                 info->phys_memory_base,
1421                 info->phys_statctrl_base,
1422                 info->phys_lcr_base,
1423                 info->irq_level,
1424                 info->max_frame_size );
1425
1426         /* output current serial signal states */
1427         spin_lock_irqsave(&info->lock,flags);
1428         get_signals(info);
1429         spin_unlock_irqrestore(&info->lock,flags);
1430
1431         stat_buf[0] = 0;
1432         stat_buf[1] = 0;
1433         if (info->serial_signals & SerialSignal_RTS)
1434                 strcat(stat_buf, "|RTS");
1435         if (info->serial_signals & SerialSignal_CTS)
1436                 strcat(stat_buf, "|CTS");
1437         if (info->serial_signals & SerialSignal_DTR)
1438                 strcat(stat_buf, "|DTR");
1439         if (info->serial_signals & SerialSignal_DSR)
1440                 strcat(stat_buf, "|DSR");
1441         if (info->serial_signals & SerialSignal_DCD)
1442                 strcat(stat_buf, "|CD");
1443         if (info->serial_signals & SerialSignal_RI)
1444                 strcat(stat_buf, "|RI");
1445
1446         if (info->params.mode == MGSL_MODE_HDLC) {
1447                 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1448                               info->icount.txok, info->icount.rxok);
1449                 if (info->icount.txunder)
1450                         ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1451                 if (info->icount.txabort)
1452                         ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1453                 if (info->icount.rxshort)
1454                         ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1455                 if (info->icount.rxlong)
1456                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1457                 if (info->icount.rxover)
1458                         ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1459                 if (info->icount.rxcrc)
1460                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc);
1461         } else {
1462                 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1463                               info->icount.tx, info->icount.rx);
1464                 if (info->icount.frame)
1465                         ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1466                 if (info->icount.parity)
1467                         ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1468                 if (info->icount.brk)
1469                         ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1470                 if (info->icount.overrun)
1471                         ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1472         }
1473
1474         /* Append serial signal status to end */
1475         ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1476
1477         ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1478          info->tx_active,info->bh_requested,info->bh_running,
1479          info->pending_bh);
1480
1481         return ret;
1482 }
1483
1484 /* Called to print information about devices
1485  */
1486 int read_proc(char *page, char **start, off_t off, int count,
1487               int *eof, void *data)
1488 {
1489         int len = 0, l;
1490         off_t   begin = 0;
1491         SLMP_INFO *info;
1492
1493         len += sprintf(page, "synclinkmp driver:%s\n", driver_version);
1494
1495         info = synclinkmp_device_list;
1496         while( info ) {
1497                 l = line_info(page + len, info);
1498                 len += l;
1499                 if (len+begin > off+count)
1500                         goto done;
1501                 if (len+begin < off) {
1502                         begin += len;
1503                         len = 0;
1504                 }
1505                 info = info->next_device;
1506         }
1507
1508         *eof = 1;
1509 done:
1510         if (off >= len+begin)
1511                 return 0;
1512         *start = page + (off-begin);
1513         return ((count < begin+len-off) ? count : begin+len-off);
1514 }
1515
1516 /* Return the count of bytes in transmit buffer
1517  */
1518 static int chars_in_buffer(struct tty_struct *tty)
1519 {
1520         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1521
1522         if (sanity_check(info, tty->name, "chars_in_buffer"))
1523                 return 0;
1524
1525         if (debug_level >= DEBUG_LEVEL_INFO)
1526                 printk("%s(%d):%s chars_in_buffer()=%d\n",
1527                        __FILE__, __LINE__, info->device_name, info->tx_count);
1528
1529         return info->tx_count;
1530 }
1531
1532 /* Signal remote device to throttle send data (our receive data)
1533  */
1534 static void throttle(struct tty_struct * tty)
1535 {
1536         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1537         unsigned long flags;
1538
1539         if (debug_level >= DEBUG_LEVEL_INFO)
1540                 printk("%s(%d):%s throttle() entry\n",
1541                          __FILE__,__LINE__, info->device_name );
1542
1543         if (sanity_check(info, tty->name, "throttle"))
1544                 return;
1545
1546         if (I_IXOFF(tty))
1547                 send_xchar(tty, STOP_CHAR(tty));
1548
1549         if (tty->termios->c_cflag & CRTSCTS) {
1550                 spin_lock_irqsave(&info->lock,flags);
1551                 info->serial_signals &= ~SerialSignal_RTS;
1552                 set_signals(info);
1553                 spin_unlock_irqrestore(&info->lock,flags);
1554         }
1555 }
1556
1557 /* Signal remote device to stop throttling send data (our receive data)
1558  */
1559 static void unthrottle(struct tty_struct * tty)
1560 {
1561         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1562         unsigned long flags;
1563
1564         if (debug_level >= DEBUG_LEVEL_INFO)
1565                 printk("%s(%d):%s unthrottle() entry\n",
1566                          __FILE__,__LINE__, info->device_name );
1567
1568         if (sanity_check(info, tty->name, "unthrottle"))
1569                 return;
1570
1571         if (I_IXOFF(tty)) {
1572                 if (info->x_char)
1573                         info->x_char = 0;
1574                 else
1575                         send_xchar(tty, START_CHAR(tty));
1576         }
1577
1578         if (tty->termios->c_cflag & CRTSCTS) {
1579                 spin_lock_irqsave(&info->lock,flags);
1580                 info->serial_signals |= SerialSignal_RTS;
1581                 set_signals(info);
1582                 spin_unlock_irqrestore(&info->lock,flags);
1583         }
1584 }
1585
1586 /* set or clear transmit break condition
1587  * break_state  -1=set break condition, 0=clear
1588  */
1589 static void set_break(struct tty_struct *tty, int break_state)
1590 {
1591         unsigned char RegValue;
1592         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1593         unsigned long flags;
1594
1595         if (debug_level >= DEBUG_LEVEL_INFO)
1596                 printk("%s(%d):%s set_break(%d)\n",
1597                          __FILE__,__LINE__, info->device_name, break_state);
1598
1599         if (sanity_check(info, tty->name, "set_break"))
1600                 return;
1601
1602         spin_lock_irqsave(&info->lock,flags);
1603         RegValue = read_reg(info, CTL);
1604         if (break_state == -1)
1605                 RegValue |= BIT3;
1606         else
1607                 RegValue &= ~BIT3;
1608         write_reg(info, CTL, RegValue);
1609         spin_unlock_irqrestore(&info->lock,flags);
1610 }
1611
1612 #ifdef CONFIG_HDLC
1613
1614 /**
1615  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1616  * set encoding and frame check sequence (FCS) options
1617  *
1618  * dev       pointer to network device structure
1619  * encoding  serial encoding setting
1620  * parity    FCS setting
1621  *
1622  * returns 0 if success, otherwise error code
1623  */
1624 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1625                           unsigned short parity)
1626 {
1627         SLMP_INFO *info = dev_to_port(dev);
1628         unsigned char  new_encoding;
1629         unsigned short new_crctype;
1630
1631         /* return error if TTY interface open */
1632         if (info->count)
1633                 return -EBUSY;
1634
1635         switch (encoding)
1636         {
1637         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1638         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1639         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1640         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1641         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1642         default: return -EINVAL;
1643         }
1644
1645         switch (parity)
1646         {
1647         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1648         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1649         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1650         default: return -EINVAL;
1651         }
1652
1653         info->params.encoding = new_encoding;
1654         info->params.crc_type = new_crctype;;
1655
1656         /* if network interface up, reprogram hardware */
1657         if (info->netcount)
1658                 program_hw(info);
1659
1660         return 0;
1661 }
1662
1663 /**
1664  * called by generic HDLC layer to send frame
1665  *
1666  * skb  socket buffer containing HDLC frame
1667  * dev  pointer to network device structure
1668  *
1669  * returns 0 if success, otherwise error code
1670  */
1671 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1672 {
1673         SLMP_INFO *info = dev_to_port(dev);
1674         struct net_device_stats *stats = hdlc_stats(dev);
1675         unsigned long flags;
1676
1677         if (debug_level >= DEBUG_LEVEL_INFO)
1678                 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1679
1680         /* stop sending until this frame completes */
1681         netif_stop_queue(dev);
1682
1683         /* copy data to device buffers */
1684         info->tx_count = skb->len;
1685         tx_load_dma_buffer(info, skb->data, skb->len);
1686
1687         /* update network statistics */
1688         stats->tx_packets++;
1689         stats->tx_bytes += skb->len;
1690
1691         /* done with socket buffer, so free it */
1692         dev_kfree_skb(skb);
1693
1694         /* save start time for transmit timeout detection */
1695         dev->trans_start = jiffies;
1696
1697         /* start hardware transmitter if necessary */
1698         spin_lock_irqsave(&info->lock,flags);
1699         if (!info->tx_active)
1700                 tx_start(info);
1701         spin_unlock_irqrestore(&info->lock,flags);
1702
1703         return 0;
1704 }
1705
1706 /**
1707  * called by network layer when interface enabled
1708  * claim resources and initialize hardware
1709  *
1710  * dev  pointer to network device structure
1711  *
1712  * returns 0 if success, otherwise error code
1713  */
1714 static int hdlcdev_open(struct net_device *dev)
1715 {
1716         SLMP_INFO *info = dev_to_port(dev);
1717         int rc;
1718         unsigned long flags;
1719
1720         if (debug_level >= DEBUG_LEVEL_INFO)
1721                 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1722
1723         /* generic HDLC layer open processing */
1724         if ((rc = hdlc_open(dev)))
1725                 return rc;
1726
1727         /* arbitrate between network and tty opens */
1728         spin_lock_irqsave(&info->netlock, flags);
1729         if (info->count != 0 || info->netcount != 0) {
1730                 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1731                 spin_unlock_irqrestore(&info->netlock, flags);
1732                 return -EBUSY;
1733         }
1734         info->netcount=1;
1735         spin_unlock_irqrestore(&info->netlock, flags);
1736
1737         /* claim resources and init adapter */
1738         if ((rc = startup(info)) != 0) {
1739                 spin_lock_irqsave(&info->netlock, flags);
1740                 info->netcount=0;
1741                 spin_unlock_irqrestore(&info->netlock, flags);
1742                 return rc;
1743         }
1744
1745         /* assert DTR and RTS, apply hardware settings */
1746         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1747         program_hw(info);
1748
1749         /* enable network layer transmit */
1750         dev->trans_start = jiffies;
1751         netif_start_queue(dev);
1752
1753         /* inform generic HDLC layer of current DCD status */
1754         spin_lock_irqsave(&info->lock, flags);
1755         get_signals(info);
1756         spin_unlock_irqrestore(&info->lock, flags);
1757         hdlc_set_carrier(info->serial_signals & SerialSignal_DCD, dev);
1758
1759         return 0;
1760 }
1761
1762 /**
1763  * called by network layer when interface is disabled
1764  * shutdown hardware and release resources
1765  *
1766  * dev  pointer to network device structure
1767  *
1768  * returns 0 if success, otherwise error code
1769  */
1770 static int hdlcdev_close(struct net_device *dev)
1771 {
1772         SLMP_INFO *info = dev_to_port(dev);
1773         unsigned long flags;
1774
1775         if (debug_level >= DEBUG_LEVEL_INFO)
1776                 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1777
1778         netif_stop_queue(dev);
1779
1780         /* shutdown adapter and release resources */
1781         shutdown(info);
1782
1783         hdlc_close(dev);
1784
1785         spin_lock_irqsave(&info->netlock, flags);
1786         info->netcount=0;
1787         spin_unlock_irqrestore(&info->netlock, flags);
1788
1789         return 0;
1790 }
1791
1792 /**
1793  * called by network layer to process IOCTL call to network device
1794  *
1795  * dev  pointer to network device structure
1796  * ifr  pointer to network interface request structure
1797  * cmd  IOCTL command code
1798  *
1799  * returns 0 if success, otherwise error code
1800  */
1801 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1802 {
1803         const size_t size = sizeof(sync_serial_settings);
1804         sync_serial_settings new_line;
1805         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1806         SLMP_INFO *info = dev_to_port(dev);
1807         unsigned int flags;
1808
1809         if (debug_level >= DEBUG_LEVEL_INFO)
1810                 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1811
1812         /* return error if TTY interface open */
1813         if (info->count)
1814                 return -EBUSY;
1815
1816         if (cmd != SIOCWANDEV)
1817                 return hdlc_ioctl(dev, ifr, cmd);
1818
1819         switch(ifr->ifr_settings.type) {
1820         case IF_GET_IFACE: /* return current sync_serial_settings */
1821
1822                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1823                 if (ifr->ifr_settings.size < size) {
1824                         ifr->ifr_settings.size = size; /* data size wanted */
1825                         return -ENOBUFS;
1826                 }
1827
1828                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1829                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1830                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1831                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1832
1833                 switch (flags){
1834                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1835                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1836                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1837                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1838                 default: new_line.clock_type = CLOCK_DEFAULT;
1839                 }
1840
1841                 new_line.clock_rate = info->params.clock_speed;
1842                 new_line.loopback   = info->params.loopback ? 1:0;
1843
1844                 if (copy_to_user(line, &new_line, size))
1845                         return -EFAULT;
1846                 return 0;
1847
1848         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1849
1850                 if(!capable(CAP_NET_ADMIN))
1851                         return -EPERM;
1852                 if (copy_from_user(&new_line, line, size))
1853                         return -EFAULT;
1854
1855                 switch (new_line.clock_type)
1856                 {
1857                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1858                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1859                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1860                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1861                 case CLOCK_DEFAULT:  flags = info->params.flags &
1862                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1863                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1864                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1865                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1866                 default: return -EINVAL;
1867                 }
1868
1869                 if (new_line.loopback != 0 && new_line.loopback != 1)
1870                         return -EINVAL;
1871
1872                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1873                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1874                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1875                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1876                 info->params.flags |= flags;
1877
1878                 info->params.loopback = new_line.loopback;
1879
1880                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1881                         info->params.clock_speed = new_line.clock_rate;
1882                 else
1883                         info->params.clock_speed = 0;
1884
1885                 /* if network interface up, reprogram hardware */
1886                 if (info->netcount)
1887                         program_hw(info);
1888                 return 0;
1889
1890         default:
1891                 return hdlc_ioctl(dev, ifr, cmd);
1892         }
1893 }
1894
1895 /**
1896  * called by network layer when transmit timeout is detected
1897  *
1898  * dev  pointer to network device structure
1899  */
1900 static void hdlcdev_tx_timeout(struct net_device *dev)
1901 {
1902         SLMP_INFO *info = dev_to_port(dev);
1903         struct net_device_stats *stats = hdlc_stats(dev);
1904         unsigned long flags;
1905
1906         if (debug_level >= DEBUG_LEVEL_INFO)
1907                 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1908
1909         stats->tx_errors++;
1910         stats->tx_aborted_errors++;
1911
1912         spin_lock_irqsave(&info->lock,flags);
1913         tx_stop(info);
1914         spin_unlock_irqrestore(&info->lock,flags);
1915
1916         netif_wake_queue(dev);
1917 }
1918
1919 /**
1920  * called by device driver when transmit completes
1921  * reenable network layer transmit if stopped
1922  *
1923  * info  pointer to device instance information
1924  */
1925 static void hdlcdev_tx_done(SLMP_INFO *info)
1926 {
1927         if (netif_queue_stopped(info->netdev))
1928                 netif_wake_queue(info->netdev);
1929 }
1930
1931 /**
1932  * called by device driver when frame received
1933  * pass frame to network layer
1934  *
1935  * info  pointer to device instance information
1936  * buf   pointer to buffer contianing frame data
1937  * size  count of data bytes in buf
1938  */
1939 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1940 {
1941         struct sk_buff *skb = dev_alloc_skb(size);
1942         struct net_device *dev = info->netdev;
1943         struct net_device_stats *stats = hdlc_stats(dev);
1944
1945         if (debug_level >= DEBUG_LEVEL_INFO)
1946                 printk("hdlcdev_rx(%s)\n",dev->name);
1947
1948         if (skb == NULL) {
1949                 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
1950                 stats->rx_dropped++;
1951                 return;
1952         }
1953
1954         memcpy(skb_put(skb, size),buf,size);
1955
1956         skb->protocol = hdlc_type_trans(skb, info->netdev);
1957
1958         stats->rx_packets++;
1959         stats->rx_bytes += size;
1960
1961         netif_rx(skb);
1962
1963         info->netdev->last_rx = jiffies;
1964 }
1965
1966 /**
1967  * called by device driver when adding device instance
1968  * do generic HDLC initialization
1969  *
1970  * info  pointer to device instance information
1971  *
1972  * returns 0 if success, otherwise error code
1973  */
1974 static int hdlcdev_init(SLMP_INFO *info)
1975 {
1976         int rc;
1977         struct net_device *dev;
1978         hdlc_device *hdlc;
1979
1980         /* allocate and initialize network and HDLC layer objects */
1981
1982         if (!(dev = alloc_hdlcdev(info))) {
1983                 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1984                 return -ENOMEM;
1985         }
1986
1987         /* for network layer reporting purposes only */
1988         dev->mem_start = info->phys_sca_base;
1989         dev->mem_end   = info->phys_sca_base + SCA_BASE_SIZE - 1;
1990         dev->irq       = info->irq_level;
1991
1992         /* network layer callbacks and settings */
1993         dev->do_ioctl       = hdlcdev_ioctl;
1994         dev->open           = hdlcdev_open;
1995         dev->stop           = hdlcdev_close;
1996         dev->tx_timeout     = hdlcdev_tx_timeout;
1997         dev->watchdog_timeo = 10*HZ;
1998         dev->tx_queue_len   = 50;
1999
2000         /* generic HDLC layer callbacks and settings */
2001         hdlc         = dev_to_hdlc(dev);
2002         hdlc->attach = hdlcdev_attach;
2003         hdlc->xmit   = hdlcdev_xmit;
2004
2005         /* register objects with HDLC layer */
2006         if ((rc = register_hdlc_device(dev))) {
2007                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
2008                 free_netdev(dev);
2009                 return rc;
2010         }
2011
2012         info->netdev = dev;
2013         return 0;
2014 }
2015
2016 /**
2017  * called by device driver when removing device instance
2018  * do generic HDLC cleanup
2019  *
2020  * info  pointer to device instance information
2021  */
2022 static void hdlcdev_exit(SLMP_INFO *info)
2023 {
2024         unregister_hdlc_device(info->netdev);
2025         free_netdev(info->netdev);
2026         info->netdev = NULL;
2027 }
2028
2029 #endif /* CONFIG_HDLC */
2030
2031
2032 /* Return next bottom half action to perform.
2033  * Return Value:        BH action code or 0 if nothing to do.
2034  */
2035 int bh_action(SLMP_INFO *info)
2036 {
2037         unsigned long flags;
2038         int rc = 0;
2039
2040         spin_lock_irqsave(&info->lock,flags);
2041
2042         if (info->pending_bh & BH_RECEIVE) {
2043                 info->pending_bh &= ~BH_RECEIVE;
2044                 rc = BH_RECEIVE;
2045         } else if (info->pending_bh & BH_TRANSMIT) {
2046                 info->pending_bh &= ~BH_TRANSMIT;
2047                 rc = BH_TRANSMIT;
2048         } else if (info->pending_bh & BH_STATUS) {
2049                 info->pending_bh &= ~BH_STATUS;
2050                 rc = BH_STATUS;
2051         }
2052
2053         if (!rc) {
2054                 /* Mark BH routine as complete */
2055                 info->bh_running   = 0;
2056                 info->bh_requested = 0;
2057         }
2058
2059         spin_unlock_irqrestore(&info->lock,flags);
2060
2061         return rc;
2062 }
2063
2064 /* Perform bottom half processing of work items queued by ISR.
2065  */
2066 void bh_handler(void* Context)
2067 {
2068         SLMP_INFO *info = (SLMP_INFO*)Context;
2069         int action;
2070
2071         if (!info)
2072                 return;
2073
2074         if ( debug_level >= DEBUG_LEVEL_BH )
2075                 printk( "%s(%d):%s bh_handler() entry\n",
2076                         __FILE__,__LINE__,info->device_name);
2077
2078         info->bh_running = 1;
2079
2080         while((action = bh_action(info)) != 0) {
2081
2082                 /* Process work item */
2083                 if ( debug_level >= DEBUG_LEVEL_BH )
2084                         printk( "%s(%d):%s bh_handler() work item action=%d\n",
2085                                 __FILE__,__LINE__,info->device_name, action);
2086
2087                 switch (action) {
2088
2089                 case BH_RECEIVE:
2090                         bh_receive(info);
2091                         break;
2092                 case BH_TRANSMIT:
2093                         bh_transmit(info);
2094                         break;
2095                 case BH_STATUS:
2096                         bh_status(info);
2097                         break;
2098                 default:
2099                         /* unknown work item ID */
2100                         printk("%s(%d):%s Unknown work item ID=%08X!\n",
2101                                 __FILE__,__LINE__,info->device_name,action);
2102                         break;
2103                 }
2104         }
2105
2106         if ( debug_level >= DEBUG_LEVEL_BH )
2107                 printk( "%s(%d):%s bh_handler() exit\n",
2108                         __FILE__,__LINE__,info->device_name);
2109 }
2110
2111 void bh_receive(SLMP_INFO *info)
2112 {
2113         if ( debug_level >= DEBUG_LEVEL_BH )
2114                 printk( "%s(%d):%s bh_receive()\n",
2115                         __FILE__,__LINE__,info->device_name);
2116
2117         while( rx_get_frame(info) );
2118 }
2119
2120 void bh_transmit(SLMP_INFO *info)
2121 {
2122         struct tty_struct *tty = info->tty;
2123
2124         if ( debug_level >= DEBUG_LEVEL_BH )
2125                 printk( "%s(%d):%s bh_transmit() entry\n",
2126                         __FILE__,__LINE__,info->device_name);
2127
2128         if (tty) {
2129                 tty_wakeup(tty);
2130                 wake_up_interruptible(&tty->write_wait);
2131         }
2132 }
2133
2134 void bh_status(SLMP_INFO *info)
2135 {
2136         if ( debug_level >= DEBUG_LEVEL_BH )
2137                 printk( "%s(%d):%s bh_status() entry\n",
2138                         __FILE__,__LINE__,info->device_name);
2139
2140         info->ri_chkcount = 0;
2141         info->dsr_chkcount = 0;
2142         info->dcd_chkcount = 0;
2143         info->cts_chkcount = 0;
2144 }
2145
2146 void isr_timer(SLMP_INFO * info)
2147 {
2148         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2149
2150         /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2151         write_reg(info, IER2, 0);
2152
2153         /* TMCS, Timer Control/Status Register
2154          *
2155          * 07      CMF, Compare match flag (read only) 1=match
2156          * 06      ECMI, CMF Interrupt Enable: 0=disabled
2157          * 05      Reserved, must be 0
2158          * 04      TME, Timer Enable
2159          * 03..00  Reserved, must be 0
2160          *
2161          * 0000 0000
2162          */
2163         write_reg(info, (unsigned char)(timer + TMCS), 0);
2164
2165         info->irq_occurred = TRUE;
2166
2167         if ( debug_level >= DEBUG_LEVEL_ISR )
2168                 printk("%s(%d):%s isr_timer()\n",
2169                         __FILE__,__LINE__,info->device_name);
2170 }
2171
2172 void isr_rxint(SLMP_INFO * info)
2173 {
2174         struct tty_struct *tty = info->tty;
2175         struct  mgsl_icount *icount = &info->icount;
2176         unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2177         unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2178
2179         /* clear status bits */
2180         if (status)
2181                 write_reg(info, SR1, status);
2182
2183         if (status2)
2184                 write_reg(info, SR2, status2);
2185
2186         if ( debug_level >= DEBUG_LEVEL_ISR )
2187                 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2188                         __FILE__,__LINE__,info->device_name,status,status2);
2189
2190         if (info->params.mode == MGSL_MODE_ASYNC) {
2191                 if (status & BRKD) {
2192                         icount->brk++;
2193
2194                         /* process break detection if tty control
2195                          * is not set to ignore it
2196                          */
2197                         if ( tty ) {
2198                                 if (!(status & info->ignore_status_mask1)) {
2199                                         if (info->read_status_mask1 & BRKD) {
2200                                                 *tty->flip.flag_buf_ptr = TTY_BREAK;
2201                                                 if (info->flags & ASYNC_SAK)
2202                                                         do_SAK(tty);
2203                                         }
2204                                 }
2205                         }
2206                 }
2207         }
2208         else {
2209                 if (status & (FLGD|IDLD)) {
2210                         if (status & FLGD)
2211                                 info->icount.exithunt++;
2212                         else if (status & IDLD)
2213                                 info->icount.rxidle++;
2214                         wake_up_interruptible(&info->event_wait_q);
2215                 }
2216         }
2217
2218         if (status & CDCD) {
2219                 /* simulate a common modem status change interrupt
2220                  * for our handler
2221                  */
2222                 get_signals( info );
2223                 isr_io_pin(info,
2224                         MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2225         }
2226 }
2227
2228 /*
2229  * handle async rx data interrupts
2230  */
2231 void isr_rxrdy(SLMP_INFO * info)
2232 {
2233         u16 status;
2234         unsigned char DataByte;
2235         struct tty_struct *tty = info->tty;
2236         struct  mgsl_icount *icount = &info->icount;
2237
2238         if ( debug_level >= DEBUG_LEVEL_ISR )
2239                 printk("%s(%d):%s isr_rxrdy\n",
2240                         __FILE__,__LINE__,info->device_name);
2241
2242         while((status = read_reg(info,CST0)) & BIT0)
2243         {
2244                 DataByte = read_reg(info,TRB);
2245
2246                 if ( tty ) {
2247                         if (tty->flip.count >= TTY_FLIPBUF_SIZE)
2248                                 continue;
2249
2250                         *tty->flip.char_buf_ptr = DataByte;
2251                         *tty->flip.flag_buf_ptr = 0;
2252                 }
2253
2254                 icount->rx++;
2255
2256                 if ( status & (PE + FRME + OVRN) ) {
2257                         printk("%s(%d):%s rxerr=%04X\n",
2258                                 __FILE__,__LINE__,info->device_name,status);
2259
2260                         /* update error statistics */
2261                         if (status & PE)
2262                                 icount->parity++;
2263                         else if (status & FRME)
2264                                 icount->frame++;
2265                         else if (status & OVRN)
2266                                 icount->overrun++;
2267
2268                         /* discard char if tty control flags say so */
2269                         if (status & info->ignore_status_mask2)
2270                                 continue;
2271
2272                         status &= info->read_status_mask2;
2273
2274                         if ( tty ) {
2275                                 if (status & PE)
2276                                         *tty->flip.flag_buf_ptr = TTY_PARITY;
2277                                 else if (status & FRME)
2278                                         *tty->flip.flag_buf_ptr = TTY_FRAME;
2279                                 if (status & OVRN) {
2280                                         /* Overrun is special, since it's
2281                                          * reported immediately, and doesn't
2282                                          * affect the current character
2283                                          */
2284                                         if (tty->flip.count < TTY_FLIPBUF_SIZE) {
2285                                                 tty->flip.count++;
2286                                                 tty->flip.flag_buf_ptr++;
2287                                                 tty->flip.char_buf_ptr++;
2288                                                 *tty->flip.flag_buf_ptr = TTY_OVERRUN;
2289                                         }
2290                                 }
2291                         }
2292                 }       /* end of if (error) */
2293
2294                 if ( tty ) {
2295                         tty->flip.flag_buf_ptr++;
2296                         tty->flip.char_buf_ptr++;
2297                         tty->flip.count++;
2298                 }
2299         }
2300
2301         if ( debug_level >= DEBUG_LEVEL_ISR ) {
2302                 printk("%s(%d):%s isr_rxrdy() flip count=%d\n",
2303                         __FILE__,__LINE__,info->device_name,
2304                         tty ? tty->flip.count : 0);
2305                 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2306                         __FILE__,__LINE__,info->device_name,
2307                         icount->rx,icount->brk,icount->parity,
2308                         icount->frame,icount->overrun);
2309         }
2310
2311         if ( tty && tty->flip.count )
2312                 tty_flip_buffer_push(tty);
2313 }
2314
2315 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2316 {
2317         if ( debug_level >= DEBUG_LEVEL_ISR )
2318                 printk("%s(%d):%s isr_txeom status=%02x\n",
2319                         __FILE__,__LINE__,info->device_name,status);
2320
2321         write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2322         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2323         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2324
2325         if (status & UDRN) {
2326                 write_reg(info, CMD, TXRESET);
2327                 write_reg(info, CMD, TXENABLE);
2328         } else
2329                 write_reg(info, CMD, TXBUFCLR);
2330
2331         /* disable and clear tx interrupts */
2332         info->ie0_value &= ~TXRDYE;
2333         info->ie1_value &= ~(IDLE + UDRN);
2334         write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2335         write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2336
2337         if ( info->tx_active ) {
2338                 if (info->params.mode != MGSL_MODE_ASYNC) {
2339                         if (status & UDRN)
2340                                 info->icount.txunder++;
2341                         else if (status & IDLE)
2342                                 info->icount.txok++;
2343                 }
2344
2345                 info->tx_active = 0;
2346                 info->tx_count = info->tx_put = info->tx_get = 0;
2347
2348                 del_timer(&info->tx_timer);
2349
2350                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2351                         info->serial_signals &= ~SerialSignal_RTS;
2352                         info->drop_rts_on_tx_done = 0;
2353                         set_signals(info);
2354                 }
2355
2356 #ifdef CONFIG_HDLC
2357                 if (info->netcount)
2358                         hdlcdev_tx_done(info);
2359                 else
2360 #endif
2361                 {
2362                         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2363                                 tx_stop(info);
2364                                 return;
2365                         }
2366                         info->pending_bh |= BH_TRANSMIT;
2367                 }
2368         }
2369 }
2370
2371
2372 /*
2373  * handle tx status interrupts
2374  */
2375 void isr_txint(SLMP_INFO * info)
2376 {
2377         unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2378
2379         /* clear status bits */
2380         write_reg(info, SR1, status);
2381
2382         if ( debug_level >= DEBUG_LEVEL_ISR )
2383                 printk("%s(%d):%s isr_txint status=%02x\n",
2384                         __FILE__,__LINE__,info->device_name,status);
2385
2386         if (status & (UDRN + IDLE))
2387                 isr_txeom(info, status);
2388
2389         if (status & CCTS) {
2390                 /* simulate a common modem status change interrupt
2391                  * for our handler
2392                  */
2393                 get_signals( info );
2394                 isr_io_pin(info,
2395                         MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2396
2397         }
2398 }
2399
2400 /*
2401  * handle async tx data interrupts
2402  */
2403 void isr_txrdy(SLMP_INFO * info)
2404 {
2405         if ( debug_level >= DEBUG_LEVEL_ISR )
2406                 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2407                         __FILE__,__LINE__,info->device_name,info->tx_count);
2408
2409         if (info->params.mode != MGSL_MODE_ASYNC) {
2410                 /* disable TXRDY IRQ, enable IDLE IRQ */
2411                 info->ie0_value &= ~TXRDYE;
2412                 info->ie1_value |= IDLE;
2413                 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2414                 return;
2415         }
2416
2417         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2418                 tx_stop(info);
2419                 return;
2420         }
2421
2422         if ( info->tx_count )
2423                 tx_load_fifo( info );
2424         else {
2425                 info->tx_active = 0;
2426                 info->ie0_value &= ~TXRDYE;
2427                 write_reg(info, IE0, info->ie0_value);
2428         }
2429
2430         if (info->tx_count < WAKEUP_CHARS)
2431                 info->pending_bh |= BH_TRANSMIT;
2432 }
2433
2434 void isr_rxdmaok(SLMP_INFO * info)
2435 {
2436         /* BIT7 = EOT (end of transfer)
2437          * BIT6 = EOM (end of message/frame)
2438          */
2439         unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2440
2441         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2442         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2443
2444         if ( debug_level >= DEBUG_LEVEL_ISR )
2445                 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2446                         __FILE__,__LINE__,info->device_name,status);
2447
2448         info->pending_bh |= BH_RECEIVE;
2449 }
2450
2451 void isr_rxdmaerror(SLMP_INFO * info)
2452 {
2453         /* BIT5 = BOF (buffer overflow)
2454          * BIT4 = COF (counter overflow)
2455          */
2456         unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2457
2458         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2459         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2460
2461         if ( debug_level >= DEBUG_LEVEL_ISR )
2462                 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2463                         __FILE__,__LINE__,info->device_name,status);
2464
2465         info->rx_overflow = TRUE;
2466         info->pending_bh |= BH_RECEIVE;
2467 }
2468
2469 void isr_txdmaok(SLMP_INFO * info)
2470 {
2471         unsigned char status_reg1 = read_reg(info, SR1);
2472
2473         write_reg(info, TXDMA + DIR, 0x00);     /* disable Tx DMA IRQs */
2474         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2475         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2476
2477         if ( debug_level >= DEBUG_LEVEL_ISR )
2478                 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2479                         __FILE__,__LINE__,info->device_name,status_reg1);
2480
2481         /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2482         write_reg16(info, TRC0, 0);
2483         info->ie0_value |= TXRDYE;
2484         write_reg(info, IE0, info->ie0_value);
2485 }
2486
2487 void isr_txdmaerror(SLMP_INFO * info)
2488 {
2489         /* BIT5 = BOF (buffer overflow)
2490          * BIT4 = COF (counter overflow)
2491          */
2492         unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2493
2494         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2495         write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2496
2497         if ( debug_level >= DEBUG_LEVEL_ISR )
2498                 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2499                         __FILE__,__LINE__,info->device_name,status);
2500 }
2501
2502 /* handle input serial signal changes
2503  */
2504 void isr_io_pin( SLMP_INFO *info, u16 status )
2505 {
2506         struct  mgsl_icount *icount;
2507
2508         if ( debug_level >= DEBUG_LEVEL_ISR )
2509                 printk("%s(%d):isr_io_pin status=%04X\n",
2510                         __FILE__,__LINE__,status);
2511
2512         if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2513                       MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2514                 icount = &info->icount;
2515                 /* update input line counters */
2516                 if (status & MISCSTATUS_RI_LATCHED) {
2517                         icount->rng++;
2518                         if ( status & SerialSignal_RI )
2519                                 info->input_signal_events.ri_up++;
2520                         else
2521                                 info->input_signal_events.ri_down++;
2522                 }
2523                 if (status & MISCSTATUS_DSR_LATCHED) {
2524                         icount->dsr++;
2525                         if ( status & SerialSignal_DSR )
2526                                 info->input_signal_events.dsr_up++;
2527                         else
2528                                 info->input_signal_events.dsr_down++;
2529                 }
2530                 if (status & MISCSTATUS_DCD_LATCHED) {
2531                         if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2532                                 info->ie1_value &= ~CDCD;
2533                                 write_reg(info, IE1, info->ie1_value);
2534                         }
2535                         icount->dcd++;
2536                         if (status & SerialSignal_DCD) {
2537                                 info->input_signal_events.dcd_up++;
2538                         } else
2539                                 info->input_signal_events.dcd_down++;
2540 #ifdef CONFIG_HDLC
2541                         if (info->netcount)
2542                                 hdlc_set_carrier(status & SerialSignal_DCD, info->netdev);
2543 #endif
2544                 }
2545                 if (status & MISCSTATUS_CTS_LATCHED)
2546                 {
2547                         if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2548                                 info->ie1_value &= ~CCTS;
2549                                 write_reg(info, IE1, info->ie1_value);
2550                         }
2551                         icount->cts++;
2552                         if ( status & SerialSignal_CTS )
2553                                 info->input_signal_events.cts_up++;
2554                         else
2555                                 info->input_signal_events.cts_down++;
2556                 }
2557                 wake_up_interruptible(&info->status_event_wait_q);
2558                 wake_up_interruptible(&info->event_wait_q);
2559
2560                 if ( (info->flags & ASYNC_CHECK_CD) &&
2561                      (status & MISCSTATUS_DCD_LATCHED) ) {
2562                         if ( debug_level >= DEBUG_LEVEL_ISR )
2563                                 printk("%s CD now %s...", info->device_name,
2564                                        (status & SerialSignal_DCD) ? "on" : "off");
2565                         if (status & SerialSignal_DCD)
2566                                 wake_up_interruptible(&info->open_wait);
2567                         else {
2568                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2569                                         printk("doing serial hangup...");
2570                                 if (info->tty)
2571                                         tty_hangup(info->tty);
2572                         }
2573                 }
2574
2575                 if ( (info->flags & ASYNC_CTS_FLOW) &&
2576                      (status & MISCSTATUS_CTS_LATCHED) ) {
2577                         if ( info->tty ) {
2578                                 if (info->tty->hw_stopped) {
2579                                         if (status & SerialSignal_CTS) {
2580                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2581                                                         printk("CTS tx start...");
2582                                                 info->tty->hw_stopped = 0;
2583                                                 tx_start(info);
2584                                                 info->pending_bh |= BH_TRANSMIT;
2585                                                 return;
2586                                         }
2587                                 } else {
2588                                         if (!(status & SerialSignal_CTS)) {
2589                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2590                                                         printk("CTS tx stop...");
2591                                                 info->tty->hw_stopped = 1;
2592                                                 tx_stop(info);
2593                                         }
2594                                 }
2595                         }
2596                 }
2597         }
2598
2599         info->pending_bh |= BH_STATUS;
2600 }
2601
2602 /* Interrupt service routine entry point.
2603  *
2604  * Arguments:
2605  *      irq             interrupt number that caused interrupt
2606  *      dev_id          device ID supplied during interrupt registration
2607  *      regs            interrupted processor context
2608  */
2609 static irqreturn_t synclinkmp_interrupt(int irq, void *dev_id,
2610                                         struct pt_regs *regs)
2611 {
2612         SLMP_INFO * info;
2613         unsigned char status, status0, status1=0;
2614         unsigned char dmastatus, dmastatus0, dmastatus1=0;
2615         unsigned char timerstatus0, timerstatus1=0;
2616         unsigned char shift;
2617         unsigned int i;
2618         unsigned short tmp;
2619
2620         if ( debug_level >= DEBUG_LEVEL_ISR )
2621                 printk("%s(%d): synclinkmp_interrupt(%d)entry.\n",
2622                         __FILE__,__LINE__,irq);
2623
2624         info = (SLMP_INFO *)dev_id;
2625         if (!info)
2626                 return IRQ_NONE;
2627
2628         spin_lock(&info->lock);
2629
2630         for(;;) {
2631
2632                 /* get status for SCA0 (ports 0-1) */
2633                 tmp = read_reg16(info, ISR0);   /* get ISR0 and ISR1 in one read */
2634                 status0 = (unsigned char)tmp;
2635                 dmastatus0 = (unsigned char)(tmp>>8);
2636                 timerstatus0 = read_reg(info, ISR2);
2637
2638                 if ( debug_level >= DEBUG_LEVEL_ISR )
2639                         printk("%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2640                                 __FILE__,__LINE__,info->device_name,
2641                                 status0,dmastatus0,timerstatus0);
2642
2643                 if (info->port_count == 4) {
2644                         /* get status for SCA1 (ports 2-3) */
2645                         tmp = read_reg16(info->port_array[2], ISR0);
2646                         status1 = (unsigned char)tmp;
2647                         dmastatus1 = (unsigned char)(tmp>>8);
2648                         timerstatus1 = read_reg(info->port_array[2], ISR2);
2649
2650                         if ( debug_level >= DEBUG_LEVEL_ISR )
2651                                 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2652                                         __FILE__,__LINE__,info->device_name,
2653                                         status1,dmastatus1,timerstatus1);
2654                 }
2655
2656                 if (!status0 && !dmastatus0 && !timerstatus0 &&
2657                          !status1 && !dmastatus1 && !timerstatus1)
2658                         break;
2659
2660                 for(i=0; i < info->port_count ; i++) {
2661                         if (info->port_array[i] == NULL)
2662                                 continue;
2663                         if (i < 2) {
2664                                 status = status0;
2665                                 dmastatus = dmastatus0;
2666                         } else {
2667                                 status = status1;
2668                                 dmastatus = dmastatus1;
2669                         }
2670
2671                         shift = i & 1 ? 4 :0;
2672
2673                         if (status & BIT0 << shift)
2674                                 isr_rxrdy(info->port_array[i]);
2675                         if (status & BIT1 << shift)
2676                                 isr_txrdy(info->port_array[i]);
2677                         if (status & BIT2 << shift)
2678                                 isr_rxint(info->port_array[i]);
2679                         if (status & BIT3 << shift)
2680                                 isr_txint(info->port_array[i]);
2681
2682                         if (dmastatus & BIT0 << shift)
2683                                 isr_rxdmaerror(info->port_array[i]);
2684                         if (dmastatus & BIT1 << shift)
2685                                 isr_rxdmaok(info->port_array[i]);
2686                         if (dmastatus & BIT2 << shift)
2687                                 isr_txdmaerror(info->port_array[i]);
2688                         if (dmastatus & BIT3 << shift)
2689                                 isr_txdmaok(info->port_array[i]);
2690                 }
2691
2692                 if (timerstatus0 & (BIT5 | BIT4))
2693                         isr_timer(info->port_array[0]);
2694                 if (timerstatus0 & (BIT7 | BIT6))
2695                         isr_timer(info->port_array[1]);
2696                 if (timerstatus1 & (BIT5 | BIT4))
2697                         isr_timer(info->port_array[2]);
2698                 if (timerstatus1 & (BIT7 | BIT6))
2699                         isr_timer(info->port_array[3]);
2700         }
2701
2702         for(i=0; i < info->port_count ; i++) {
2703                 SLMP_INFO * port = info->port_array[i];
2704
2705                 /* Request bottom half processing if there's something
2706                  * for it to do and the bh is not already running.
2707                  *
2708                  * Note: startup adapter diags require interrupts.
2709                  * do not request bottom half processing if the
2710                  * device is not open in a normal mode.
2711                  */
2712                 if ( port && (port->count || port->netcount) &&
2713                      port->pending_bh && !port->bh_running &&
2714                      !port->bh_requested ) {
2715                         if ( debug_level >= DEBUG_LEVEL_ISR )
2716                                 printk("%s(%d):%s queueing bh task.\n",
2717                                         __FILE__,__LINE__,port->device_name);
2718                         schedule_work(&port->task);
2719                         port->bh_requested = 1;
2720                 }
2721         }
2722
2723         spin_unlock(&info->lock);
2724
2725         if ( debug_level >= DEBUG_LEVEL_ISR )
2726                 printk("%s(%d):synclinkmp_interrupt(%d)exit.\n",
2727                         __FILE__,__LINE__,irq);
2728         return IRQ_HANDLED;
2729 }
2730
2731 /* Initialize and start device.
2732  */
2733 static int startup(SLMP_INFO * info)
2734 {
2735         if ( debug_level >= DEBUG_LEVEL_INFO )
2736                 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2737
2738         if (info->flags & ASYNC_INITIALIZED)
2739                 return 0;
2740
2741         if (!info->tx_buf) {
2742                 info->tx_buf = (unsigned char *)kmalloc(info->max_frame_size, GFP_KERNEL);
2743                 if (!info->tx_buf) {
2744                         printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2745                                 __FILE__,__LINE__,info->device_name);
2746                         return -ENOMEM;
2747                 }
2748         }
2749
2750         info->pending_bh = 0;
2751
2752         memset(&info->icount, 0, sizeof(info->icount));
2753
2754         /* program hardware for current parameters */
2755         reset_port(info);
2756
2757         change_params(info);
2758
2759         info->status_timer.expires = jiffies + msecs_to_jiffies(10);
2760         add_timer(&info->status_timer);
2761
2762         if (info->tty)
2763                 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2764
2765         info->flags |= ASYNC_INITIALIZED;
2766
2767         return 0;
2768 }
2769
2770 /* Called by close() and hangup() to shutdown hardware
2771  */
2772 static void shutdown(SLMP_INFO * info)
2773 {
2774         unsigned long flags;
2775
2776         if (!(info->flags & ASYNC_INITIALIZED))
2777                 return;
2778
2779         if (debug_level >= DEBUG_LEVEL_INFO)
2780                 printk("%s(%d):%s synclinkmp_shutdown()\n",
2781                          __FILE__,__LINE__, info->device_name );
2782
2783         /* clear status wait queue because status changes */
2784         /* can't happen after shutting down the hardware */
2785         wake_up_interruptible(&info->status_event_wait_q);
2786         wake_up_interruptible(&info->event_wait_q);
2787
2788         del_timer(&info->tx_timer);
2789         del_timer(&info->status_timer);
2790
2791         if (info->tx_buf) {
2792                 kfree(info->tx_buf);
2793                 info->tx_buf = NULL;
2794         }
2795
2796         spin_lock_irqsave(&info->lock,flags);
2797
2798         reset_port(info);
2799
2800         if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2801                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2802                 set_signals(info);
2803         }
2804
2805         spin_unlock_irqrestore(&info->lock,flags);
2806
2807         if (info->tty)
2808                 set_bit(TTY_IO_ERROR, &info->tty->flags);
2809
2810         info->flags &= ~ASYNC_INITIALIZED;
2811 }
2812
2813 static void program_hw(SLMP_INFO *info)
2814 {
2815         unsigned long flags;
2816
2817         spin_lock_irqsave(&info->lock,flags);
2818
2819         rx_stop(info);
2820         tx_stop(info);
2821
2822         info->tx_count = info->tx_put = info->tx_get = 0;
2823
2824         if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2825                 hdlc_mode(info);
2826         else
2827                 async_mode(info);
2828
2829         set_signals(info);
2830
2831         info->dcd_chkcount = 0;
2832         info->cts_chkcount = 0;
2833         info->ri_chkcount = 0;
2834         info->dsr_chkcount = 0;
2835
2836         info->ie1_value |= (CDCD|CCTS);
2837         write_reg(info, IE1, info->ie1_value);
2838
2839         get_signals(info);
2840
2841         if (info->netcount || (info->tty && info->tty->termios->c_cflag & CREAD) )
2842                 rx_start(info);
2843
2844         spin_unlock_irqrestore(&info->lock,flags);
2845 }
2846
2847 /* Reconfigure adapter based on new parameters
2848  */
2849 static void change_params(SLMP_INFO *info)
2850 {
2851         unsigned cflag;
2852         int bits_per_char;
2853
2854         if (!info->tty || !info->tty->termios)
2855                 return;
2856
2857         if (debug_level >= DEBUG_LEVEL_INFO)
2858                 printk("%s(%d):%s change_params()\n",
2859                          __FILE__,__LINE__, info->device_name );
2860
2861         cflag = info->tty->termios->c_cflag;
2862
2863         /* if B0 rate (hangup) specified then negate DTR and RTS */
2864         /* otherwise assert DTR and RTS */
2865         if (cflag & CBAUD)
2866                 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2867         else
2868                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2869
2870         /* byte size and parity */
2871
2872         switch (cflag & CSIZE) {
2873               case CS5: info->params.data_bits = 5; break;
2874               case CS6: info->params.data_bits = 6; break;
2875               case CS7: info->params.data_bits = 7; break;
2876               case CS8: info->params.data_bits = 8; break;
2877               /* Never happens, but GCC is too dumb to figure it out */
2878               default:  info->params.data_bits = 7; break;
2879               }
2880
2881         if (cflag & CSTOPB)
2882                 info->params.stop_bits = 2;
2883         else
2884                 info->params.stop_bits = 1;
2885
2886         info->params.parity = ASYNC_PARITY_NONE;
2887         if (cflag & PARENB) {
2888                 if (cflag & PARODD)
2889                         info->params.parity = ASYNC_PARITY_ODD;
2890                 else
2891                         info->params.parity = ASYNC_PARITY_EVEN;
2892 #ifdef CMSPAR
2893                 if (cflag & CMSPAR)
2894                         info->params.parity = ASYNC_PARITY_SPACE;
2895 #endif
2896         }
2897
2898         /* calculate number of jiffies to transmit a full
2899          * FIFO (32 bytes) at specified data rate
2900          */
2901         bits_per_char = info->params.data_bits +
2902                         info->params.stop_bits + 1;
2903
2904         /* if port data rate is set to 460800 or less then
2905          * allow tty settings to override, otherwise keep the
2906          * current data rate.
2907          */
2908         if (info->params.data_rate <= 460800) {
2909                 info->params.data_rate = tty_get_baud_rate(info->tty);
2910         }
2911
2912         if ( info->params.data_rate ) {
2913                 info->timeout = (32*HZ*bits_per_char) /
2914                                 info->params.data_rate;
2915         }
2916         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2917
2918         if (cflag & CRTSCTS)
2919                 info->flags |= ASYNC_CTS_FLOW;
2920         else
2921                 info->flags &= ~ASYNC_CTS_FLOW;
2922
2923         if (cflag & CLOCAL)
2924                 info->flags &= ~ASYNC_CHECK_CD;
2925         else
2926                 info->flags |= ASYNC_CHECK_CD;
2927
2928         /* process tty input control flags */
2929
2930         info->read_status_mask2 = OVRN;
2931         if (I_INPCK(info->tty))
2932                 info->read_status_mask2 |= PE | FRME;
2933         if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2934                 info->read_status_mask1 |= BRKD;
2935         if (I_IGNPAR(info->tty))
2936                 info->ignore_status_mask2 |= PE | FRME;
2937         if (I_IGNBRK(info->tty)) {
2938                 info->ignore_status_mask1 |= BRKD;
2939                 /* If ignoring parity and break indicators, ignore
2940                  * overruns too.  (For real raw support).
2941                  */
2942                 if (I_IGNPAR(info->tty))
2943                         info->ignore_status_mask2 |= OVRN;
2944         }
2945
2946         program_hw(info);
2947 }
2948
2949 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2950 {
2951         int err;
2952
2953         if (debug_level >= DEBUG_LEVEL_INFO)
2954                 printk("%s(%d):%s get_params()\n",
2955                          __FILE__,__LINE__, info->device_name);
2956
2957         if (!user_icount) {
2958                 memset(&info->icount, 0, sizeof(info->icount));
2959         } else {
2960                 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2961                 if (err)
2962                         return -EFAULT;
2963         }
2964
2965         return 0;
2966 }
2967
2968 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2969 {
2970         int err;
2971         if (debug_level >= DEBUG_LEVEL_INFO)
2972                 printk("%s(%d):%s get_params()\n",
2973                          __FILE__,__LINE__, info->device_name);
2974
2975         COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2976         if (err) {
2977                 if ( debug_level >= DEBUG_LEVEL_INFO )
2978                         printk( "%s(%d):%s get_params() user buffer copy failed\n",
2979                                 __FILE__,__LINE__,info->device_name);
2980                 return -EFAULT;
2981         }
2982
2983         return 0;
2984 }
2985
2986 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2987 {
2988         unsigned long flags;
2989         MGSL_PARAMS tmp_params;
2990         int err;
2991
2992         if (debug_level >= DEBUG_LEVEL_INFO)
2993                 printk("%s(%d):%s set_params\n",
2994                         __FILE__,__LINE__,info->device_name );
2995         COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2996         if (err) {
2997                 if ( debug_level >= DEBUG_LEVEL_INFO )
2998                         printk( "%s(%d):%s set_params() user buffer copy failed\n",
2999                                 __FILE__,__LINE__,info->device_name);
3000                 return -EFAULT;
3001         }
3002
3003         spin_lock_irqsave(&info->lock,flags);
3004         memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
3005         spin_unlock_irqrestore(&info->lock,flags);
3006
3007         change_params(info);
3008
3009         return 0;
3010 }
3011
3012 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
3013 {
3014         int err;
3015
3016         if (debug_level >= DEBUG_LEVEL_INFO)
3017                 printk("%s(%d):%s get_txidle()=%d\n",
3018                          __FILE__,__LINE__, info->device_name, info->idle_mode);
3019
3020         COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
3021         if (err) {
3022                 if ( debug_level >= DEBUG_LEVEL_INFO )
3023                         printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
3024                                 __FILE__,__LINE__,info->device_name);
3025                 return -EFAULT;
3026         }
3027
3028         return 0;
3029 }
3030
3031 static int set_txidle(SLMP_INFO * info, int idle_mode)
3032 {
3033         unsigned long flags;
3034
3035         if (debug_level >= DEBUG_LEVEL_INFO)
3036                 printk("%s(%d):%s set_txidle(%d)\n",
3037                         __FILE__,__LINE__,info->device_name, idle_mode );
3038
3039         spin_lock_irqsave(&info->lock,flags);
3040         info->idle_mode = idle_mode;
3041         tx_set_idle( info );
3042         spin_unlock_irqrestore(&info->lock,flags);
3043         return 0;
3044 }
3045
3046 static int tx_enable(SLMP_INFO * info, int enable)
3047 {
3048         unsigned long flags;
3049
3050         if (debug_level >= DEBUG_LEVEL_INFO)
3051                 printk("%s(%d):%s tx_enable(%d)\n",
3052                         __FILE__,__LINE__,info->device_name, enable);
3053
3054         spin_lock_irqsave(&info->lock,flags);
3055         if ( enable ) {
3056                 if ( !info->tx_enabled ) {
3057                         tx_start(info);
3058                 }
3059         } else {
3060                 if ( info->tx_enabled )
3061                         tx_stop(info);
3062         }
3063         spin_unlock_irqrestore(&info->lock,flags);
3064         return 0;
3065 }
3066
3067 /* abort send HDLC frame
3068  */
3069 static int tx_abort(SLMP_INFO * info)
3070 {
3071         unsigned long flags;
3072
3073         if (debug_level >= DEBUG_LEVEL_INFO)
3074                 printk("%s(%d):%s tx_abort()\n",
3075                         __FILE__,__LINE__,info->device_name);
3076
3077         spin_lock_irqsave(&info->lock,flags);
3078         if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
3079                 info->ie1_value &= ~UDRN;
3080                 info->ie1_value |= IDLE;
3081                 write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
3082                 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
3083
3084                 write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
3085                 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3086
3087                 write_reg(info, CMD, TXABORT);
3088         }
3089         spin_unlock_irqrestore(&info->lock,flags);
3090         return 0;
3091 }
3092
3093 static int rx_enable(SLMP_INFO * info, int enable)
3094 {
3095         unsigned long flags;
3096
3097         if (debug_level >= DEBUG_LEVEL_INFO)
3098                 printk("%s(%d):%s rx_enable(%d)\n",
3099                         __FILE__,__LINE__,info->device_name,enable);
3100
3101         spin_lock_irqsave(&info->lock,flags);
3102         if ( enable ) {
3103                 if ( !info->rx_enabled )
3104                         rx_start(info);
3105         } else {
3106                 if ( info->rx_enabled )
3107                         rx_stop(info);
3108         }
3109         spin_unlock_irqrestore(&info->lock,flags);
3110         return 0;
3111 }
3112
3113 /* wait for specified event to occur
3114  */
3115 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3116 {
3117         unsigned long flags;
3118         int s;
3119         int rc=0;
3120         struct mgsl_icount cprev, cnow;
3121         int events;
3122         int mask;
3123         struct  _input_signal_events oldsigs, newsigs;
3124         DECLARE_WAITQUEUE(wait, current);
3125
3126         COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3127         if (rc) {
3128                 return  -EFAULT;
3129         }
3130
3131         if (debug_level >= DEBUG_LEVEL_INFO)
3132                 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3133                         __FILE__,__LINE__,info->device_name,mask);
3134
3135         spin_lock_irqsave(&info->lock,flags);
3136
3137         /* return immediately if state matches requested events */
3138         get_signals(info);
3139         s = info->serial_signals;
3140
3141         events = mask &
3142                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3143                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3144                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3145                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3146         if (events) {
3147                 spin_unlock_irqrestore(&info->lock,flags);
3148                 goto exit;
3149         }
3150
3151         /* save current irq counts */
3152         cprev = info->icount;
3153         oldsigs = info->input_signal_events;
3154
3155         /* enable hunt and idle irqs if needed */
3156         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3157                 unsigned char oldval = info->ie1_value;
3158                 unsigned char newval = oldval +
3159                          (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3160                          (mask & MgslEvent_IdleReceived ? IDLD:0);
3161                 if ( oldval != newval ) {
3162                         info->ie1_value = newval;
3163                         write_reg(info, IE1, info->ie1_value);
3164                 }
3165         }
3166
3167         set_current_state(TASK_INTERRUPTIBLE);
3168         add_wait_queue(&info->event_wait_q, &wait);
3169
3170         spin_unlock_irqrestore(&info->lock,flags);
3171
3172         for(;;) {
3173                 schedule();
3174                 if (signal_pending(current)) {
3175                         rc = -ERESTARTSYS;
3176                         break;
3177                 }
3178
3179                 /* get current irq counts */
3180                 spin_lock_irqsave(&info->lock,flags);
3181                 cnow = info->icount;
3182                 newsigs = info->input_signal_events;
3183                 set_current_state(TASK_INTERRUPTIBLE);
3184                 spin_unlock_irqrestore(&info->lock,flags);
3185
3186                 /* if no change, wait aborted for some reason */
3187                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
3188                     newsigs.dsr_down == oldsigs.dsr_down &&
3189                     newsigs.dcd_up   == oldsigs.dcd_up   &&
3190                     newsigs.dcd_down == oldsigs.dcd_down &&
3191                     newsigs.cts_up   == oldsigs.cts_up   &&
3192                     newsigs.cts_down == oldsigs.cts_down &&
3193                     newsigs.ri_up    == oldsigs.ri_up    &&
3194                     newsigs.ri_down  == oldsigs.ri_down  &&
3195                     cnow.exithunt    == cprev.exithunt   &&
3196                     cnow.rxidle      == cprev.rxidle) {
3197                         rc = -EIO;
3198                         break;
3199                 }
3200
3201                 events = mask &
3202                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
3203                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3204                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
3205                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3206                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
3207                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3208                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
3209                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
3210                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
3211                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
3212                 if (events)
3213                         break;
3214
3215                 cprev = cnow;
3216                 oldsigs = newsigs;
3217         }
3218
3219         remove_wait_queue(&info->event_wait_q, &wait);
3220         set_current_state(TASK_RUNNING);
3221
3222
3223         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3224                 spin_lock_irqsave(&info->lock,flags);
3225                 if (!waitqueue_active(&info->event_wait_q)) {
3226                         /* disable enable exit hunt mode/idle rcvd IRQs */
3227                         info->ie1_value &= ~(FLGD|IDLD);
3228                         write_reg(info, IE1, info->ie1_value);
3229                 }
3230                 spin_unlock_irqrestore(&info->lock,flags);
3231         }
3232 exit:
3233         if ( rc == 0 )
3234                 PUT_USER(rc, events, mask_ptr);
3235
3236         return rc;
3237 }
3238
3239 static int modem_input_wait(SLMP_INFO *info,int arg)
3240 {
3241         unsigned long flags;
3242         int rc;
3243         struct mgsl_icount cprev, cnow;
3244         DECLARE_WAITQUEUE(wait, current);
3245
3246         /* save current irq counts */
3247         spin_lock_irqsave(&info->lock,flags);
3248         cprev = info->icount;
3249         add_wait_queue(&info->status_event_wait_q, &wait);
3250         set_current_state(TASK_INTERRUPTIBLE);
3251         spin_unlock_irqrestore(&info->lock,flags);
3252
3253         for(;;) {
3254                 schedule();
3255                 if (signal_pending(current)) {
3256                         rc = -ERESTARTSYS;
3257                         break;
3258                 }
3259
3260                 /* get new irq counts */
3261                 spin_lock_irqsave(&info->lock,flags);
3262                 cnow = info->icount;
3263                 set_current_state(TASK_INTERRUPTIBLE);
3264                 spin_unlock_irqrestore(&info->lock,flags);
3265
3266                 /* if no change, wait aborted for some reason */
3267                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3268                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3269                         rc = -EIO;
3270                         break;
3271                 }
3272
3273                 /* check for change in caller specified modem input */
3274                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3275                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3276                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3277                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3278                         rc = 0;
3279                         break;
3280                 }
3281
3282                 cprev = cnow;
3283         }
3284         remove_wait_queue(&info->status_event_wait_q, &wait);
3285         set_current_state(TASK_RUNNING);
3286         return rc;
3287 }
3288
3289 /* return the state of the serial control and status signals
3290  */
3291 static int tiocmget(struct tty_struct *tty, struct file *file)
3292 {
3293         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3294         unsigned int result;
3295         unsigned long flags;
3296
3297         spin_lock_irqsave(&info->lock,flags);
3298         get_signals(info);
3299         spin_unlock_irqrestore(&info->lock,flags);
3300
3301         result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3302                 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3303                 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3304                 ((info->serial_signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3305                 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3306                 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3307
3308         if (debug_level >= DEBUG_LEVEL_INFO)
3309                 printk("%s(%d):%s tiocmget() value=%08X\n",
3310                          __FILE__,__LINE__, info->device_name, result );
3311         return result;
3312 }
3313
3314 /* set modem control signals (DTR/RTS)
3315  */
3316 static int tiocmset(struct tty_struct *tty, struct file *file,
3317                     unsigned int set, unsigned int clear)
3318 {
3319         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3320         unsigned long flags;
3321
3322         if (debug_level >= DEBUG_LEVEL_INFO)
3323                 printk("%s(%d):%s tiocmset(%x,%x)\n",
3324                         __FILE__,__LINE__,info->device_name, set, clear);
3325
3326         if (set & TIOCM_RTS)
3327                 info->serial_signals |= SerialSignal_RTS;
3328         if (set & TIOCM_DTR)
3329                 info->serial_signals |= SerialSignal_DTR;
3330         if (clear & TIOCM_RTS)
3331                 info->serial_signals &= ~SerialSignal_RTS;
3332         if (clear & TIOCM_DTR)
3333                 info->serial_signals &= ~SerialSignal_DTR;
3334
3335         spin_lock_irqsave(&info->lock,flags);
3336         set_signals(info);
3337         spin_unlock_irqrestore(&info->lock,flags);
3338
3339         return 0;
3340 }
3341
3342
3343
3344 /* Block the current process until the specified port is ready to open.
3345  */
3346 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3347                            SLMP_INFO *info)
3348 {
3349         DECLARE_WAITQUEUE(wait, current);
3350         int             retval;
3351         int             do_clocal = 0, extra_count = 0;
3352         unsigned long   flags;
3353
3354         if (debug_level >= DEBUG_LEVEL_INFO)
3355                 printk("%s(%d):%s block_til_ready()\n",
3356                          __FILE__,__LINE__, tty->driver->name );
3357
3358         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3359                 /* nonblock mode is set or port is not enabled */
3360                 /* just verify that callout device is not active */
3361                 info->flags |= ASYNC_NORMAL_ACTIVE;
3362                 return 0;
3363         }
3364
3365         if (tty->termios->c_cflag & CLOCAL)
3366                 do_clocal = 1;
3367
3368         /* Wait for carrier detect and the line to become
3369          * free (i.e., not in use by the callout).  While we are in
3370          * this loop, info->count is dropped by one, so that
3371          * close() knows when to free things.  We restore it upon
3372          * exit, either normal or abnormal.
3373          */
3374
3375         retval = 0;
3376         add_wait_queue(&info->open_wait, &wait);
3377
3378         if (debug_level >= DEBUG_LEVEL_INFO)
3379                 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3380                          __FILE__,__LINE__, tty->driver->name, info->count );
3381
3382         spin_lock_irqsave(&info->lock, flags);
3383         if (!tty_hung_up_p(filp)) {
3384                 extra_count = 1;
3385                 info->count--;
3386         }
3387         spin_unlock_irqrestore(&info->lock, flags);
3388         info->blocked_open++;
3389
3390         while (1) {
3391                 if ((tty->termios->c_cflag & CBAUD)) {
3392                         spin_lock_irqsave(&info->lock,flags);
3393                         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3394                         set_signals(info);
3395                         spin_unlock_irqrestore(&info->lock,flags);
3396                 }
3397
3398                 set_current_state(TASK_INTERRUPTIBLE);
3399
3400                 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3401                         retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3402                                         -EAGAIN : -ERESTARTSYS;
3403                         break;
3404                 }
3405
3406                 spin_lock_irqsave(&info->lock,flags);
3407                 get_signals(info);
3408                 spin_unlock_irqrestore(&info->lock,flags);
3409
3410                 if (!(info->flags & ASYNC_CLOSING) &&
3411                     (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3412                         break;
3413                 }
3414
3415                 if (signal_pending(current)) {
3416                         retval = -ERESTARTSYS;
3417                         break;
3418                 }
3419
3420                 if (debug_level >= DEBUG_LEVEL_INFO)
3421                         printk("%s(%d):%s block_til_ready() count=%d\n",
3422                                  __FILE__,__LINE__, tty->driver->name, info->count );
3423
3424                 schedule();
3425         }
3426
3427         set_current_state(TASK_RUNNING);
3428         remove_wait_queue(&info->open_wait, &wait);
3429
3430         if (extra_count)
3431                 info->count++;
3432         info->blocked_open--;
3433
3434         if (debug_level >= DEBUG_LEVEL_INFO)
3435                 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3436                          __FILE__,__LINE__, tty->driver->name, info->count );
3437
3438         if (!retval)
3439                 info->flags |= ASYNC_NORMAL_ACTIVE;
3440
3441         return retval;
3442 }
3443
3444 int alloc_dma_bufs(SLMP_INFO *info)
3445 {
3446         unsigned short BuffersPerFrame;
3447         unsigned short BufferCount;
3448
3449         // Force allocation to start at 64K boundary for each port.
3450         // This is necessary because *all* buffer descriptors for a port
3451         // *must* be in the same 64K block. All descriptors on a port
3452         // share a common 'base' address (upper 8 bits of 24 bits) programmed
3453         // into the CBP register.
3454         info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3455
3456         /* Calculate the number of DMA buffers necessary to hold the */
3457         /* largest allowable frame size. Note: If the max frame size is */
3458         /* not an even multiple of the DMA buffer size then we need to */
3459         /* round the buffer count per frame up one. */
3460
3461         BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3462         if ( info->max_frame_size % SCABUFSIZE )
3463                 BuffersPerFrame++;
3464
3465         /* calculate total number of data buffers (SCABUFSIZE) possible
3466          * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3467          * for the descriptor list (BUFFERLISTSIZE).
3468          */
3469         BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3470
3471         /* limit number of buffers to maximum amount of descriptors */
3472         if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3473                 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3474
3475         /* use enough buffers to transmit one max size frame */
3476         info->tx_buf_count = BuffersPerFrame + 1;
3477
3478         /* never use more than half the available buffers for transmit */
3479         if (info->tx_buf_count > (BufferCount/2))
3480                 info->tx_buf_count = BufferCount/2;
3481
3482         if (info->tx_buf_count > SCAMAXDESC)
3483                 info->tx_buf_count = SCAMAXDESC;
3484
3485         /* use remaining buffers for receive */
3486         info->rx_buf_count = BufferCount - info->tx_buf_count;
3487
3488         if (info->rx_buf_count > SCAMAXDESC)
3489                 info->rx_buf_count = SCAMAXDESC;
3490
3491         if ( debug_level >= DEBUG_LEVEL_INFO )
3492                 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3493                         __FILE__,__LINE__, info->device_name,
3494                         info->tx_buf_count,info->rx_buf_count);
3495
3496         if ( alloc_buf_list( info ) < 0 ||
3497                 alloc_frame_bufs(info,
3498                                         info->rx_buf_list,
3499                                         info->rx_buf_list_ex,
3500                                         info->rx_buf_count) < 0 ||
3501                 alloc_frame_bufs(info,
3502                                         info->tx_buf_list,
3503                                         info->tx_buf_list_ex,
3504                                         info->tx_buf_count) < 0 ||
3505                 alloc_tmp_rx_buf(info) < 0 ) {
3506                 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3507                         __FILE__,__LINE__, info->device_name);
3508                 return -ENOMEM;
3509         }
3510
3511         rx_reset_buffers( info );
3512
3513         return 0;
3514 }
3515
3516 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3517  */
3518 int alloc_buf_list(SLMP_INFO *info)
3519 {
3520         unsigned int i;
3521
3522         /* build list in adapter shared memory */
3523         info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3524         info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3525         info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3526
3527         memset(info->buffer_list, 0, BUFFERLISTSIZE);
3528
3529         /* Save virtual address pointers to the receive and */
3530         /* transmit buffer lists. (Receive 1st). These pointers will */
3531         /* be used by the processor to access the lists. */
3532         info->rx_buf_list = (SCADESC *)info->buffer_list;
3533
3534         info->tx_buf_list = (SCADESC *)info->buffer_list;
3535         info->tx_buf_list += info->rx_buf_count;
3536
3537         /* Build links for circular buffer entry lists (tx and rx)
3538          *
3539          * Note: links are physical addresses read by the SCA device
3540          * to determine the next buffer entry to use.
3541          */
3542
3543         for ( i = 0; i < info->rx_buf_count; i++ ) {
3544                 /* calculate and store physical address of this buffer entry */
3545                 info->rx_buf_list_ex[i].phys_entry =
3546                         info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3547
3548                 /* calculate and store physical address of */
3549                 /* next entry in cirular list of entries */
3550                 info->rx_buf_list[i].next = info->buffer_list_phys;
3551                 if ( i < info->rx_buf_count - 1 )
3552                         info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3553
3554                 info->rx_buf_list[i].length = SCABUFSIZE;
3555         }
3556
3557         for ( i = 0; i < info->tx_buf_count; i++ ) {
3558                 /* calculate and store physical address of this buffer entry */
3559                 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3560                         ((info->rx_buf_count + i) * sizeof(SCADESC));
3561
3562                 /* calculate and store physical address of */
3563                 /* next entry in cirular list of entries */
3564
3565                 info->tx_buf_list[i].next = info->buffer_list_phys +
3566                         info->rx_buf_count * sizeof(SCADESC);
3567
3568                 if ( i < info->tx_buf_count - 1 )
3569                         info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3570         }
3571
3572         return 0;
3573 }
3574
3575 /* Allocate the frame DMA buffers used by the specified buffer list.
3576  */
3577 int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3578 {
3579         int i;
3580         unsigned long phys_addr;
3581
3582         for ( i = 0; i < count; i++ ) {
3583                 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3584                 phys_addr = info->port_array[0]->last_mem_alloc;
3585                 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3586
3587                 buf_list[i].buf_ptr  = (unsigned short)phys_addr;
3588                 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3589         }
3590
3591         return 0;
3592 }
3593
3594 void free_dma_bufs(SLMP_INFO *info)
3595 {
3596         info->buffer_list = NULL;
3597         info->rx_buf_list = NULL;
3598         info->tx_buf_list = NULL;
3599 }
3600
3601 /* allocate buffer large enough to hold max_frame_size.
3602  * This buffer is used to pass an assembled frame to the line discipline.
3603  */
3604 int alloc_tmp_rx_buf(SLMP_INFO *info)
3605 {
3606         info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3607         if (info->tmp_rx_buf == NULL)
3608                 return -ENOMEM;
3609         return 0;
3610 }
3611
3612 void free_tmp_rx_buf(SLMP_INFO *info)
3613 {
3614         if (info->tmp_rx_buf)
3615                 kfree(info->tmp_rx_buf);
3616         info->tmp_rx_buf = NULL;
3617 }
3618
3619 int claim_resources(SLMP_INFO *info)
3620 {
3621         if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3622                 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3623                         __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3624                 info->init_error = DiagStatus_AddressConflict;
3625                 goto errout;
3626         }
3627         else
3628                 info->shared_mem_requested = 1;
3629
3630         if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3631                 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3632                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3633                 info->init_error = DiagStatus_AddressConflict;
3634                 goto errout;
3635         }
3636         else
3637                 info->lcr_mem_requested = 1;
3638
3639         if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3640                 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3641                         __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3642                 info->init_error = DiagStatus_AddressConflict;
3643                 goto errout;
3644         }
3645         else
3646                 info->sca_base_requested = 1;
3647
3648         if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3649                 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3650                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3651                 info->init_error = DiagStatus_AddressConflict;
3652                 goto errout;
3653         }
3654         else
3655                 info->sca_statctrl_requested = 1;
3656
3657         info->memory_base = ioremap(info->phys_memory_base,SCA_MEM_SIZE);
3658         if (!info->memory_base) {
3659                 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3660                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3661                 info->init_error = DiagStatus_CantAssignPciResources;
3662                 goto errout;
3663         }
3664
3665         info->lcr_base = ioremap(info->phys_lcr_base,PAGE_SIZE);
3666         if (!info->lcr_base) {
3667                 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3668                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3669                 info->init_error = DiagStatus_CantAssignPciResources;
3670                 goto errout;
3671         }
3672         info->lcr_base += info->lcr_offset;
3673
3674         info->sca_base = ioremap(info->phys_sca_base,PAGE_SIZE);
3675         if (!info->sca_base) {
3676                 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3677                         __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3678                 info->init_error = DiagStatus_CantAssignPciResources;
3679                 goto errout;
3680         }
3681         info->sca_base += info->sca_offset;
3682
3683         info->statctrl_base = ioremap(info->phys_statctrl_base,PAGE_SIZE);
3684         if (!info->statctrl_base) {
3685                 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3686                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3687                 info->init_error = DiagStatus_CantAssignPciResources;
3688                 goto errout;
3689         }
3690         info->statctrl_base += info->statctrl_offset;
3691
3692         if ( !memory_test(info) ) {
3693                 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3694                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3695                 info->init_error = DiagStatus_MemoryError;
3696                 goto errout;
3697         }
3698
3699         return 0;
3700
3701 errout:
3702         release_resources( info );
3703         return -ENODEV;
3704 }
3705
3706 void release_resources(SLMP_INFO *info)
3707 {
3708         if ( debug_level >= DEBUG_LEVEL_INFO )
3709                 printk( "%s(%d):%s release_resources() entry\n",
3710                         __FILE__,__LINE__,info->device_name );
3711
3712         if ( info->irq_requested ) {
3713                 free_irq(info->irq_level, info);
3714                 info->irq_requested = 0;
3715         }
3716
3717         if ( info->shared_mem_requested ) {
3718                 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3719                 info->shared_mem_requested = 0;
3720         }
3721         if ( info->lcr_mem_requested ) {
3722                 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3723                 info->lcr_mem_requested = 0;
3724         }
3725         if ( info->sca_base_requested ) {
3726                 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3727                 info->sca_base_requested = 0;
3728         }
3729         if ( info->sca_statctrl_requested ) {
3730                 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3731                 info->sca_statctrl_requested = 0;
3732         }
3733
3734         if (info->memory_base){
3735                 iounmap(info->memory_base);
3736                 info->memory_base = NULL;
3737         }
3738
3739         if (info->sca_base) {
3740                 iounmap(info->sca_base - info->sca_offset);
3741                 info->sca_base=NULL;
3742         }
3743
3744         if (info->statctrl_base) {
3745                 iounmap(info->statctrl_base - info->statctrl_offset);
3746                 info->statctrl_base=NULL;
3747         }
3748
3749         if (info->lcr_base){
3750                 iounmap(info->lcr_base - info->lcr_offset);
3751                 info->lcr_base = NULL;
3752         }
3753
3754         if ( debug_level >= DEBUG_LEVEL_INFO )
3755                 printk( "%s(%d):%s release_resources() exit\n",
3756                         __FILE__,__LINE__,info->device_name );
3757 }
3758
3759 /* Add the specified device instance data structure to the
3760  * global linked list of devices and increment the device count.
3761  */
3762 void add_device(SLMP_INFO *info)
3763 {
3764         info->next_device = NULL;
3765         info->line = synclinkmp_device_count;
3766         sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3767
3768         if (info->line < MAX_DEVICES) {
3769                 if (maxframe[info->line])
3770                         info->max_frame_size = maxframe[info->line];
3771                 info->dosyncppp = dosyncppp[info->line];
3772         }
3773
3774         synclinkmp_device_count++;
3775
3776         if ( !synclinkmp_device_list )
3777                 synclinkmp_device_list = info;
3778         else {
3779                 SLMP_INFO *current_dev = synclinkmp_device_list;
3780                 while( current_dev->next_device )
3781                         current_dev = current_dev->next_device;
3782                 current_dev->next_device = info;
3783         }
3784
3785         if ( info->max_frame_size < 4096 )
3786                 info->max_frame_size = 4096;
3787         else if ( info->max_frame_size > 65535 )
3788                 info->max_frame_size = 65535;
3789
3790         printk( "SyncLink MultiPort %s: "
3791                 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3792                 info->device_name,
3793                 info->phys_sca_base,
3794                 info->phys_memory_base,
3795                 info->phys_statctrl_base,
3796                 info->phys_lcr_base,
3797                 info->irq_level,
3798                 info->max_frame_size );
3799
3800 #ifdef CONFIG_HDLC
3801         hdlcdev_init(info);
3802 #endif
3803 }
3804
3805 /* Allocate and initialize a device instance structure
3806  *
3807  * Return Value:        pointer to SLMP_INFO if success, otherwise NULL
3808  */
3809 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3810 {
3811         SLMP_INFO *info;
3812
3813         info = (SLMP_INFO *)kmalloc(sizeof(SLMP_INFO),
3814                  GFP_KERNEL);
3815
3816         if (!info) {
3817                 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3818                         __FILE__,__LINE__, adapter_num, port_num);
3819         } else {
3820                 memset(info, 0, sizeof(SLMP_INFO));
3821                 info->magic = MGSL_MAGIC;
3822                 INIT_WORK(&info->task, bh_handler, info);
3823                 info->max_frame_size = 4096;
3824                 info->close_delay = 5*HZ/10;
3825                 info->closing_wait = 30*HZ;
3826                 init_waitqueue_head(&info->open_wait);
3827                 init_waitqueue_head(&info->close_wait);
3828                 init_waitqueue_head(&info->status_event_wait_q);
3829                 init_waitqueue_head(&info->event_wait_q);
3830                 spin_lock_init(&info->netlock);
3831                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3832                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3833                 info->adapter_num = adapter_num;
3834                 info->port_num = port_num;
3835
3836                 /* Copy configuration info to device instance data */
3837                 info->irq_level = pdev->irq;
3838                 info->phys_lcr_base = pci_resource_start(pdev,0);
3839                 info->phys_sca_base = pci_resource_start(pdev,2);
3840                 info->phys_memory_base = pci_resource_start(pdev,3);
3841                 info->phys_statctrl_base = pci_resource_start(pdev,4);
3842
3843                 /* Because veremap only works on page boundaries we must map
3844                  * a larger area than is actually implemented for the LCR
3845                  * memory range. We map a full page starting at the page boundary.
3846                  */
3847                 info->lcr_offset    = info->phys_lcr_base & (PAGE_SIZE-1);
3848                 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3849
3850                 info->sca_offset    = info->phys_sca_base & (PAGE_SIZE-1);
3851                 info->phys_sca_base &= ~(PAGE_SIZE-1);
3852
3853                 info->statctrl_offset    = info->phys_statctrl_base & (PAGE_SIZE-1);
3854                 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3855
3856                 info->bus_type = MGSL_BUS_TYPE_PCI;
3857                 info->irq_flags = SA_SHIRQ;
3858
3859                 init_timer(&info->tx_timer);
3860                 info->tx_timer.data = (unsigned long)info;
3861                 info->tx_timer.function = tx_timeout;
3862
3863                 init_timer(&info->status_timer);
3864                 info->status_timer.data = (unsigned long)info;
3865                 info->status_timer.function = status_timeout;
3866
3867                 /* Store the PCI9050 misc control register value because a flaw
3868                  * in the PCI9050 prevents LCR registers from being read if
3869                  * BIOS assigns an LCR base address with bit 7 set.
3870                  *
3871                  * Only the misc control register is accessed for which only
3872                  * write access is needed, so set an initial value and change
3873                  * bits to the device instance data as we write the value
3874                  * to the actual misc control register.
3875                  */
3876                 info->misc_ctrl_value = 0x087e4546;
3877
3878                 /* initial port state is unknown - if startup errors
3879                  * occur, init_error will be set to indicate the
3880                  * problem. Once the port is fully initialized,
3881                  * this value will be set to 0 to indicate the
3882                  * port is available.
3883                  */
3884                 info->init_error = -1;
3885         }
3886
3887         return info;
3888 }
3889
3890 void device_init(int adapter_num, struct pci_dev *pdev)
3891 {
3892         SLMP_INFO *port_array[SCA_MAX_PORTS];
3893         int port;
3894
3895         /* allocate device instances for up to SCA_MAX_PORTS devices */
3896         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3897                 port_array[port] = alloc_dev(adapter_num,port,pdev);
3898                 if( port_array[port] == NULL ) {
3899                         for ( --port; port >= 0; --port )
3900                                 kfree(port_array[port]);
3901                         return;
3902                 }
3903         }
3904
3905         /* give copy of port_array to all ports and add to device list  */
3906         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3907                 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3908                 add_device( port_array[port] );
3909                 spin_lock_init(&port_array[port]->lock);
3910         }
3911
3912         /* Allocate and claim adapter resources */
3913         if ( !claim_resources(port_array[0]) ) {
3914
3915                 alloc_dma_bufs(port_array[0]);
3916
3917                 /* copy resource information from first port to others */
3918                 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3919                         port_array[port]->lock  = port_array[0]->lock;
3920                         port_array[port]->irq_level     = port_array[0]->irq_level;
3921                         port_array[port]->memory_base   = port_array[0]->memory_base;
3922                         port_array[port]->sca_base      = port_array[0]->sca_base;
3923                         port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3924                         port_array[port]->lcr_base      = port_array[0]->lcr_base;
3925                         alloc_dma_bufs(port_array[port]);
3926                 }
3927
3928                 if ( request_irq(port_array[0]->irq_level,
3929                                         synclinkmp_interrupt,
3930                                         port_array[0]->irq_flags,
3931                                         port_array[0]->device_name,
3932                                         port_array[0]) < 0 ) {
3933                         printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3934                                 __FILE__,__LINE__,
3935                                 port_array[0]->device_name,
3936                                 port_array[0]->irq_level );
3937                 }
3938                 else {
3939                         port_array[0]->irq_requested = 1;
3940                         adapter_test(port_array[0]);
3941                 }
3942         }
3943 }
3944
3945 static struct tty_operations ops = {
3946         .open = open,
3947         .close = close,
3948         .write = write,
3949         .put_char = put_char,
3950         .flush_chars = flush_chars,
3951         .write_room = write_room,
3952         .chars_in_buffer = chars_in_buffer,
3953         .flush_buffer = flush_buffer,
3954         .ioctl = ioctl,
3955         .throttle = throttle,
3956         .unthrottle = unthrottle,
3957         .send_xchar = send_xchar,
3958         .break_ctl = set_break,
3959         .wait_until_sent = wait_until_sent,
3960         .read_proc = read_proc,
3961         .set_termios = set_termios,
3962         .stop = tx_hold,
3963         .start = tx_release,
3964         .hangup = hangup,
3965         .tiocmget = tiocmget,
3966         .tiocmset = tiocmset,
3967 };
3968
3969 static void synclinkmp_cleanup(void)
3970 {
3971         int rc;
3972         SLMP_INFO *info;
3973         SLMP_INFO *tmp;
3974
3975         printk("Unloading %s %s\n", driver_name, driver_version);
3976
3977         if (serial_driver) {
3978                 if ((rc = tty_unregister_driver(serial_driver)))
3979                         printk("%s(%d) failed to unregister tty driver err=%d\n",
3980                                __FILE__,__LINE__,rc);
3981                 put_tty_driver(serial_driver);
3982         }
3983
3984         /* reset devices */
3985         info = synclinkmp_device_list;
3986         while(info) {
3987                 reset_port(info);
3988                 info = info->next_device;
3989         }
3990
3991         /* release devices */
3992         info = synclinkmp_device_list;
3993         while(info) {
3994 #ifdef CONFIG_HDLC
3995                 hdlcdev_exit(info);
3996 #endif
3997                 free_dma_bufs(info);
3998                 free_tmp_rx_buf(info);
3999                 if ( info->port_num == 0 ) {
4000                         if (info->sca_base)
4001                                 write_reg(info, LPR, 1); /* set low power mode */
4002                         release_resources(info);
4003                 }
4004                 tmp = info;
4005                 info = info->next_device;
4006                 kfree(tmp);
4007         }
4008
4009         pci_unregister_driver(&synclinkmp_pci_driver);
4010 }
4011
4012 /* Driver initialization entry point.
4013  */
4014
4015 static int __init synclinkmp_init(void)
4016 {
4017         int rc;
4018
4019         if (break_on_load) {
4020                 synclinkmp_get_text_ptr();
4021                 BREAKPOINT();
4022         }
4023
4024         printk("%s %s\n", driver_name, driver_version);
4025
4026         if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
4027                 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4028                 return rc;
4029         }
4030
4031         serial_driver = alloc_tty_driver(128);
4032         if (!serial_driver) {
4033                 rc = -ENOMEM;
4034                 goto error;
4035         }
4036
4037         /* Initialize the tty_driver structure */
4038
4039         serial_driver->owner = THIS_MODULE;
4040         serial_driver->driver_name = "synclinkmp";
4041         serial_driver->name = "ttySLM";
4042         serial_driver->major = ttymajor;
4043         serial_driver->minor_start = 64;
4044         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4045         serial_driver->subtype = SERIAL_TYPE_NORMAL;
4046         serial_driver->init_termios = tty_std_termios;
4047         serial_driver->init_termios.c_cflag =
4048                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4049         serial_driver->flags = TTY_DRIVER_REAL_RAW;
4050         tty_set_operations(serial_driver, &ops);
4051         if ((rc = tty_register_driver(serial_driver)) < 0) {
4052                 printk("%s(%d):Couldn't register serial driver\n",
4053                         __FILE__,__LINE__);
4054                 put_tty_driver(serial_driver);
4055                 serial_driver = NULL;
4056                 goto error;
4057         }
4058
4059         printk("%s %s, tty major#%d\n",
4060                 driver_name, driver_version,
4061                 serial_driver->major);
4062
4063         return 0;
4064
4065 error:
4066         synclinkmp_cleanup();
4067         return rc;
4068 }
4069
4070 static void __exit synclinkmp_exit(void)
4071 {
4072         synclinkmp_cleanup();
4073 }
4074
4075 module_init(synclinkmp_init);
4076 module_exit(synclinkmp_exit);
4077
4078 /* Set the port for internal loopback mode.
4079  * The TxCLK and RxCLK signals are generated from the BRG and
4080  * the TxD is looped back to the RxD internally.
4081  */
4082 void enable_loopback(SLMP_INFO *info, int enable)
4083 {
4084         if (enable) {
4085                 /* MD2 (Mode Register 2)
4086                  * 01..00  CNCT<1..0> Channel Connection 11=Local Loopback
4087                  */
4088                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4089
4090                 /* degate external TxC clock source */
4091                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4092                 write_control_reg(info);
4093
4094                 /* RXS/TXS (Rx/Tx clock source)
4095                  * 07      Reserved, must be 0
4096                  * 06..04  Clock Source, 100=BRG
4097                  * 03..00  Clock Divisor, 0000=1
4098                  */
4099                 write_reg(info, RXS, 0x40);
4100                 write_reg(info, TXS, 0x40);
4101
4102         } else {
4103                 /* MD2 (Mode Register 2)
4104                  * 01..00  CNCT<1..0> Channel connection, 0=normal
4105                  */
4106                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4107
4108                 /* RXS/TXS (Rx/Tx clock source)
4109                  * 07      Reserved, must be 0
4110                  * 06..04  Clock Source, 000=RxC/TxC Pin
4111                  * 03..00  Clock Divisor, 0000=1
4112                  */
4113                 write_reg(info, RXS, 0x00);
4114                 write_reg(info, TXS, 0x00);
4115         }
4116
4117         /* set LinkSpeed if available, otherwise default to 2Mbps */
4118         if (info->params.clock_speed)
4119                 set_rate(info, info->params.clock_speed);
4120         else
4121                 set_rate(info, 3686400);
4122 }
4123
4124 /* Set the baud rate register to the desired speed
4125  *
4126  *      data_rate       data rate of clock in bits per second
4127  *                      A data rate of 0 disables the AUX clock.
4128  */
4129 void set_rate( SLMP_INFO *info, u32 data_rate )
4130 {
4131         u32 TMCValue;
4132         unsigned char BRValue;
4133         u32 Divisor=0;
4134
4135         /* fBRG = fCLK/(TMC * 2^BR)
4136          */
4137         if (data_rate != 0) {
4138                 Divisor = 14745600/data_rate;
4139                 if (!Divisor)
4140                         Divisor = 1;
4141
4142                 TMCValue = Divisor;
4143
4144                 BRValue = 0;
4145                 if (TMCValue != 1 && TMCValue != 2) {
4146                         /* BRValue of 0 provides 50/50 duty cycle *only* when
4147                          * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4148                          * 50/50 duty cycle.
4149                          */
4150                         BRValue = 1;
4151                         TMCValue >>= 1;
4152                 }
4153
4154                 /* while TMCValue is too big for TMC register, divide
4155                  * by 2 and increment BR exponent.
4156                  */
4157                 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4158                         TMCValue >>= 1;
4159
4160                 write_reg(info, TXS,
4161                         (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4162                 write_reg(info, RXS,
4163                         (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4164                 write_reg(info, TMC, (unsigned char)TMCValue);
4165         }
4166         else {
4167                 write_reg(info, TXS,0);
4168                 write_reg(info, RXS,0);
4169                 write_reg(info, TMC, 0);
4170         }
4171 }
4172
4173 /* Disable receiver
4174  */
4175 void rx_stop(SLMP_INFO *info)
4176 {
4177         if (debug_level >= DEBUG_LEVEL_ISR)
4178                 printk("%s(%d):%s rx_stop()\n",
4179                          __FILE__,__LINE__, info->device_name );
4180
4181         write_reg(info, CMD, RXRESET);
4182
4183         info->ie0_value &= ~RXRDYE;
4184         write_reg(info, IE0, info->ie0_value);  /* disable Rx data interrupts */
4185
4186         write_reg(info, RXDMA + DSR, 0);        /* disable Rx DMA */
4187         write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4188         write_reg(info, RXDMA + DIR, 0);        /* disable Rx DMA interrupts */
4189
4190         info->rx_enabled = 0;
4191         info->rx_overflow = 0;
4192 }
4193
4194 /* enable the receiver
4195  */
4196 void rx_start(SLMP_INFO *info)
4197 {
4198         int i;
4199
4200         if (debug_level >= DEBUG_LEVEL_ISR)
4201                 printk("%s(%d):%s rx_start()\n",
4202                          __FILE__,__LINE__, info->device_name );
4203
4204         write_reg(info, CMD, RXRESET);
4205
4206         if ( info->params.mode == MGSL_MODE_HDLC ) {
4207                 /* HDLC, disabe IRQ on rxdata */
4208                 info->ie0_value &= ~RXRDYE;
4209                 write_reg(info, IE0, info->ie0_value);
4210
4211                 /* Reset all Rx DMA buffers and program rx dma */
4212                 write_reg(info, RXDMA + DSR, 0);                /* disable Rx DMA */
4213                 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4214
4215                 for (i = 0; i < info->rx_buf_count; i++) {
4216                         info->rx_buf_list[i].status = 0xff;
4217
4218                         // throttle to 4 shared memory writes at a time to prevent
4219                         // hogging local bus (keep latency time for DMA requests low).
4220                         if (!(i % 4))
4221                                 read_status_reg(info);
4222                 }
4223                 info->current_rx_buf = 0;
4224
4225                 /* set current/1st descriptor address */
4226                 write_reg16(info, RXDMA + CDA,
4227                         info->rx_buf_list_ex[0].phys_entry);
4228
4229                 /* set new last rx descriptor address */
4230                 write_reg16(info, RXDMA + EDA,
4231                         info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4232
4233                 /* set buffer length (shared by all rx dma data buffers) */
4234                 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4235
4236                 write_reg(info, RXDMA + DIR, 0x60);     /* enable Rx DMA interrupts (EOM/BOF) */
4237                 write_reg(info, RXDMA + DSR, 0xf2);     /* clear Rx DMA IRQs, enable Rx DMA */
4238         } else {
4239                 /* async, enable IRQ on rxdata */
4240                 info->ie0_value |= RXRDYE;
4241                 write_reg(info, IE0, info->ie0_value);
4242         }
4243
4244         write_reg(info, CMD, RXENABLE);
4245
4246         info->rx_overflow = FALSE;
4247         info->rx_enabled = 1;
4248 }
4249
4250 /* Enable the transmitter and send a transmit frame if
4251  * one is loaded in the DMA buffers.
4252  */
4253 void tx_start(SLMP_INFO *info)
4254 {
4255         if (debug_level >= DEBUG_LEVEL_ISR)
4256                 printk("%s(%d):%s tx_start() tx_count=%d\n",
4257                          __FILE__,__LINE__, info->device_name,info->tx_count );
4258
4259         if (!info->tx_enabled ) {
4260                 write_reg(info, CMD, TXRESET);
4261                 write_reg(info, CMD, TXENABLE);
4262                 info->tx_enabled = TRUE;
4263         }
4264
4265         if ( info->tx_count ) {
4266
4267                 /* If auto RTS enabled and RTS is inactive, then assert */
4268                 /* RTS and set a flag indicating that the driver should */
4269                 /* negate RTS when the transmission completes. */
4270
4271                 info->drop_rts_on_tx_done = 0;
4272
4273                 if (info->params.mode != MGSL_MODE_ASYNC) {
4274
4275                         if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4276                                 get_signals( info );
4277                                 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4278                                         info->serial_signals |= SerialSignal_RTS;
4279                                         set_signals( info );
4280                                         info->drop_rts_on_tx_done = 1;
4281                                 }
4282                         }
4283
4284                         write_reg16(info, TRC0,
4285                                 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4286
4287                         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4288                         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4289
4290                         /* set TX CDA (current descriptor address) */
4291                         write_reg16(info, TXDMA + CDA,
4292                                 info->tx_buf_list_ex[0].phys_entry);
4293
4294                         /* set TX EDA (last descriptor address) */
4295                         write_reg16(info, TXDMA + EDA,
4296                                 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4297
4298                         /* enable underrun IRQ */
4299                         info->ie1_value &= ~IDLE;
4300                         info->ie1_value |= UDRN;
4301                         write_reg(info, IE1, info->ie1_value);
4302                         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4303
4304                         write_reg(info, TXDMA + DIR, 0x40);             /* enable Tx DMA interrupts (EOM) */
4305                         write_reg(info, TXDMA + DSR, 0xf2);             /* clear Tx DMA IRQs, enable Tx DMA */
4306
4307                         info->tx_timer.expires = jiffies + msecs_to_jiffies(5000);
4308                         add_timer(&info->tx_timer);
4309                 }
4310                 else {
4311                         tx_load_fifo(info);
4312                         /* async, enable IRQ on txdata */
4313                         info->ie0_value |= TXRDYE;
4314                         write_reg(info, IE0, info->ie0_value);
4315                 }
4316
4317                 info->tx_active = 1;
4318         }
4319 }
4320
4321 /* stop the transmitter and DMA
4322  */
4323 void tx_stop( SLMP_INFO *info )
4324 {
4325         if (debug_level >= DEBUG_LEVEL_ISR)
4326                 printk("%s(%d):%s tx_stop()\n",
4327                          __FILE__,__LINE__, info->device_name );
4328
4329         del_timer(&info->tx_timer);
4330
4331         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4332         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4333
4334         write_reg(info, CMD, TXRESET);
4335
4336         info->ie1_value &= ~(UDRN + IDLE);
4337         write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
4338         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
4339
4340         info->ie0_value &= ~TXRDYE;
4341         write_reg(info, IE0, info->ie0_value);  /* disable tx data interrupts */
4342
4343         info->tx_enabled = 0;
4344         info->tx_active  = 0;
4345 }
4346
4347 /* Fill the transmit FIFO until the FIFO is full or
4348  * there is no more data to load.
4349  */
4350 void tx_load_fifo(SLMP_INFO *info)
4351 {
4352         u8 TwoBytes[2];
4353
4354         /* do nothing is now tx data available and no XON/XOFF pending */
4355
4356         if ( !info->tx_count && !info->x_char )
4357                 return;
4358
4359         /* load the Transmit FIFO until FIFOs full or all data sent */
4360
4361         while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4362
4363                 /* there is more space in the transmit FIFO and */
4364                 /* there is more data in transmit buffer */
4365
4366                 if ( (info->tx_count > 1) && !info->x_char ) {
4367                         /* write 16-bits */
4368                         TwoBytes[0] = info->tx_buf[info->tx_get++];
4369                         if (info->tx_get >= info->max_frame_size)
4370                                 info->tx_get -= info->max_frame_size;
4371                         TwoBytes[1] = info->tx_buf[info->tx_get++];
4372                         if (info->tx_get >= info->max_frame_size)
4373                                 info->tx_get -= info->max_frame_size;
4374
4375                         write_reg16(info, TRB, *((u16 *)TwoBytes));
4376
4377                         info->tx_count -= 2;
4378                         info->icount.tx += 2;
4379                 } else {
4380                         /* only 1 byte left to transmit or 1 FIFO slot left */
4381
4382                         if (info->x_char) {
4383                                 /* transmit pending high priority char */
4384                                 write_reg(info, TRB, info->x_char);
4385                                 info->x_char = 0;
4386                         } else {
4387                                 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4388                                 if (info->tx_get >= info->max_frame_size)
4389                                         info->tx_get -= info->max_frame_size;
4390                                 info->tx_count--;
4391                         }
4392                         info->icount.tx++;
4393                 }
4394         }
4395 }
4396
4397 /* Reset a port to a known state
4398  */
4399 void reset_port(SLMP_INFO *info)
4400 {
4401         if (info->sca_base) {
4402
4403                 tx_stop(info);
4404                 rx_stop(info);
4405
4406                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4407                 set_signals(info);
4408
4409                 /* disable all port interrupts */
4410                 info->ie0_value = 0;
4411                 info->ie1_value = 0;
4412                 info->ie2_value = 0;
4413                 write_reg(info, IE0, info->ie0_value);
4414                 write_reg(info, IE1, info->ie1_value);
4415                 write_reg(info, IE2, info->ie2_value);
4416
4417                 write_reg(info, CMD, CHRESET);
4418         }
4419 }
4420
4421 /* Reset all the ports to a known state.
4422  */
4423 void reset_adapter(SLMP_INFO *info)
4424 {
4425         int i;
4426
4427         for ( i=0; i < SCA_MAX_PORTS; ++i) {
4428                 if (info->port_array[i])
4429                         reset_port(info->port_array[i]);
4430         }
4431 }
4432
4433 /* Program port for asynchronous communications.
4434  */
4435 void async_mode(SLMP_INFO *info)
4436 {
4437
4438         unsigned char RegValue;
4439
4440         tx_stop(info);
4441         rx_stop(info);
4442
4443         /* MD0, Mode Register 0
4444          *
4445          * 07..05  PRCTL<2..0>, Protocol Mode, 000=async
4446          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4447          * 03      Reserved, must be 0
4448          * 02      CRCCC, CRC Calculation, 0=disabled
4449          * 01..00  STOP<1..0> Stop bits (00=1,10=2)
4450          *
4451          * 0000 0000
4452          */
4453         RegValue = 0x00;
4454         if (info->params.stop_bits != 1)
4455                 RegValue |= BIT1;
4456         write_reg(info, MD0, RegValue);
4457
4458         /* MD1, Mode Register 1
4459          *
4460          * 07..06  BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4461          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4462          * 03..02  RXCHR<1..0>, rx char size
4463          * 01..00  PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4464          *
4465          * 0100 0000
4466          */
4467         RegValue = 0x40;
4468         switch (info->params.data_bits) {
4469         case 7: RegValue |= BIT4 + BIT2; break;
4470         case 6: RegValue |= BIT5 + BIT3; break;
4471         case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4472         }
4473         if (info->params.parity != ASYNC_PARITY_NONE) {
4474                 RegValue |= BIT1;
4475                 if (info->params.parity == ASYNC_PARITY_ODD)
4476                         RegValue |= BIT0;
4477         }
4478         write_reg(info, MD1, RegValue);
4479
4480         /* MD2, Mode Register 2
4481          *
4482          * 07..02  Reserved, must be 0
4483          * 01..00  CNCT<1..0> Channel connection, 00=normal 11=local loopback
4484          *
4485          * 0000 0000
4486          */
4487         RegValue = 0x00;
4488         if (info->params.loopback)
4489                 RegValue |= (BIT1 + BIT0);
4490         write_reg(info, MD2, RegValue);
4491
4492         /* RXS, Receive clock source
4493          *
4494          * 07      Reserved, must be 0
4495          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4496          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4497          */
4498         RegValue=BIT6;
4499         write_reg(info, RXS, RegValue);
4500
4501         /* TXS, Transmit clock source
4502          *
4503          * 07      Reserved, must be 0
4504          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4505          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4506          */
4507         RegValue=BIT6;
4508         write_reg(info, TXS, RegValue);
4509
4510         /* Control Register
4511          *
4512          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4513          */
4514         info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4515         write_control_reg(info);
4516
4517         tx_set_idle(info);
4518
4519         /* RRC Receive Ready Control 0
4520          *
4521          * 07..05  Reserved, must be 0
4522          * 04..00  RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4523          */
4524         write_reg(info, RRC, 0x00);
4525
4526         /* TRC0 Transmit Ready Control 0
4527          *
4528          * 07..05  Reserved, must be 0
4529          * 04..00  TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4530          */
4531         write_reg(info, TRC0, 0x10);
4532
4533         /* TRC1 Transmit Ready Control 1
4534          *
4535          * 07..05  Reserved, must be 0
4536          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4537          */
4538         write_reg(info, TRC1, 0x1e);
4539
4540         /* CTL, MSCI control register
4541          *
4542          * 07..06  Reserved, set to 0
4543          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4544          * 04      IDLC, idle control, 0=mark 1=idle register
4545          * 03      BRK, break, 0=off 1 =on (async)
4546          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4547          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4548          * 00      RTS, RTS output control, 0=active 1=inactive
4549          *
4550          * 0001 0001
4551          */
4552         RegValue = 0x10;
4553         if (!(info->serial_signals & SerialSignal_RTS))
4554                 RegValue |= 0x01;
4555         write_reg(info, CTL, RegValue);
4556
4557         /* enable status interrupts */
4558         info->ie0_value |= TXINTE + RXINTE;
4559         write_reg(info, IE0, info->ie0_value);
4560
4561         /* enable break detect interrupt */
4562         info->ie1_value = BRKD;
4563         write_reg(info, IE1, info->ie1_value);
4564
4565         /* enable rx overrun interrupt */
4566         info->ie2_value = OVRN;
4567         write_reg(info, IE2, info->ie2_value);
4568
4569         set_rate( info, info->params.data_rate * 16 );
4570 }
4571
4572 /* Program the SCA for HDLC communications.
4573  */
4574 void hdlc_mode(SLMP_INFO *info)
4575 {
4576         unsigned char RegValue;
4577         u32 DpllDivisor;
4578
4579         // Can't use DPLL because SCA outputs recovered clock on RxC when
4580         // DPLL mode selected. This causes output contention with RxC receiver.
4581         // Use of DPLL would require external hardware to disable RxC receiver
4582         // when DPLL mode selected.
4583         info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4584
4585         /* disable DMA interrupts */
4586         write_reg(info, TXDMA + DIR, 0);
4587         write_reg(info, RXDMA + DIR, 0);
4588
4589         /* MD0, Mode Register 0
4590          *
4591          * 07..05  PRCTL<2..0>, Protocol Mode, 100=HDLC
4592          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4593          * 03      Reserved, must be 0
4594          * 02      CRCCC, CRC Calculation, 1=enabled
4595          * 01      CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4596          * 00      CRC0, CRC initial value, 1 = all 1s
4597          *
4598          * 1000 0001
4599          */
4600         RegValue = 0x81;
4601         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4602                 RegValue |= BIT4;
4603         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4604                 RegValue |= BIT4;
4605         if (info->params.crc_type == HDLC_CRC_16_CCITT)
4606                 RegValue |= BIT2 + BIT1;
4607         write_reg(info, MD0, RegValue);
4608
4609         /* MD1, Mode Register 1
4610          *
4611          * 07..06  ADDRS<1..0>, Address detect, 00=no addr check
4612          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits
4613          * 03..02  RXCHR<1..0>, rx char size, 00=8 bits
4614          * 01..00  PMPM<1..0>, Parity mode, 00=no parity
4615          *
4616          * 0000 0000
4617          */
4618         RegValue = 0x00;
4619         write_reg(info, MD1, RegValue);
4620
4621         /* MD2, Mode Register 2
4622          *
4623          * 07      NRZFM, 0=NRZ, 1=FM
4624          * 06..05  CODE<1..0> Encoding, 00=NRZ
4625          * 04..03  DRATE<1..0> DPLL Divisor, 00=8
4626          * 02      Reserved, must be 0
4627          * 01..00  CNCT<1..0> Channel connection, 0=normal
4628          *
4629          * 0000 0000
4630          */
4631         RegValue = 0x00;
4632         switch(info->params.encoding) {
4633         case HDLC_ENCODING_NRZI:          RegValue |= BIT5; break;
4634         case HDLC_ENCODING_BIPHASE_MARK:  RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4635         case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4636         case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break;      /* aka Manchester */
4637 #if 0
4638         case HDLC_ENCODING_NRZB:                                        /* not supported */
4639         case HDLC_ENCODING_NRZI_MARK:                                   /* not supported */
4640         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:                          /* not supported */
4641 #endif
4642         }
4643         if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4644                 DpllDivisor = 16;
4645                 RegValue |= BIT3;
4646         } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4647                 DpllDivisor = 8;
4648         } else {
4649                 DpllDivisor = 32;
4650                 RegValue |= BIT4;
4651         }
4652         write_reg(info, MD2, RegValue);
4653
4654
4655         /* RXS, Receive clock source
4656          *
4657          * 07      Reserved, must be 0
4658          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4659          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4660          */
4661         RegValue=0;
4662         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4663                 RegValue |= BIT6;
4664         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4665                 RegValue |= BIT6 + BIT5;
4666         write_reg(info, RXS, RegValue);
4667
4668         /* TXS, Transmit clock source
4669          *
4670          * 07      Reserved, must be 0
4671          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4672          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4673          */
4674         RegValue=0;
4675         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4676                 RegValue |= BIT6;
4677         if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4678                 RegValue |= BIT6 + BIT5;
4679         write_reg(info, TXS, RegValue);
4680
4681         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4682                 set_rate(info, info->params.clock_speed * DpllDivisor);
4683         else
4684                 set_rate(info, info->params.clock_speed);
4685
4686         /* GPDATA (General Purpose I/O Data Register)
4687          *
4688          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4689          */
4690         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4691                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4692         else
4693                 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4694         write_control_reg(info);
4695
4696         /* RRC Receive Ready Control 0
4697          *
4698          * 07..05  Reserved, must be 0
4699          * 04..00  RRC<4..0> Rx FIFO trigger active
4700          */
4701         write_reg(info, RRC, rx_active_fifo_level);
4702
4703         /* TRC0 Transmit Ready Control 0
4704          *
4705          * 07..05  Reserved, must be 0
4706          * 04..00  TRC<4..0> Tx FIFO trigger active
4707          */
4708         write_reg(info, TRC0, tx_active_fifo_level);
4709
4710         /* TRC1 Transmit Ready Control 1
4711          *
4712          * 07..05  Reserved, must be 0
4713          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4714          */
4715         write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4716
4717         /* DMR, DMA Mode Register
4718          *
4719          * 07..05  Reserved, must be 0
4720          * 04      TMOD, Transfer Mode: 1=chained-block
4721          * 03      Reserved, must be 0
4722          * 02      NF, Number of Frames: 1=multi-frame
4723          * 01      CNTE, Frame End IRQ Counter enable: 0=disabled
4724          * 00      Reserved, must be 0
4725          *
4726          * 0001 0100
4727          */
4728         write_reg(info, TXDMA + DMR, 0x14);
4729         write_reg(info, RXDMA + DMR, 0x14);
4730
4731         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4732         write_reg(info, RXDMA + CPB,
4733                 (unsigned char)(info->buffer_list_phys >> 16));
4734
4735         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4736         write_reg(info, TXDMA + CPB,
4737                 (unsigned char)(info->buffer_list_phys >> 16));
4738
4739         /* enable status interrupts. other code enables/disables
4740          * the individual sources for these two interrupt classes.
4741          */
4742         info->ie0_value |= TXINTE + RXINTE;
4743         write_reg(info, IE0, info->ie0_value);
4744
4745         /* CTL, MSCI control register
4746          *
4747          * 07..06  Reserved, set to 0
4748          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4749          * 04      IDLC, idle control, 0=mark 1=idle register
4750          * 03      BRK, break, 0=off 1 =on (async)
4751          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4752          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4753          * 00      RTS, RTS output control, 0=active 1=inactive
4754          *
4755          * 0001 0001
4756          */
4757         RegValue = 0x10;
4758         if (!(info->serial_signals & SerialSignal_RTS))
4759                 RegValue |= 0x01;
4760         write_reg(info, CTL, RegValue);
4761
4762         /* preamble not supported ! */
4763
4764         tx_set_idle(info);
4765         tx_stop(info);
4766         rx_stop(info);
4767
4768         set_rate(info, info->params.clock_speed);
4769
4770         if (info->params.loopback)
4771                 enable_loopback(info,1);
4772 }
4773
4774 /* Set the transmit HDLC idle mode
4775  */
4776 void tx_set_idle(SLMP_INFO *info)
4777 {
4778         unsigned char RegValue = 0xff;
4779
4780         /* Map API idle mode to SCA register bits */
4781         switch(info->idle_mode) {
4782         case HDLC_TXIDLE_FLAGS:                 RegValue = 0x7e; break;
4783         case HDLC_TXIDLE_ALT_ZEROS_ONES:        RegValue = 0xaa; break;
4784         case HDLC_TXIDLE_ZEROS:                 RegValue = 0x00; break;
4785         case HDLC_TXIDLE_ONES:                  RegValue = 0xff; break;
4786         case HDLC_TXIDLE_ALT_MARK_SPACE:        RegValue = 0xaa; break;
4787         case HDLC_TXIDLE_SPACE:                 RegValue = 0x00; break;
4788         case HDLC_TXIDLE_MARK:                  RegValue = 0xff; break;
4789         }
4790
4791         write_reg(info, IDL, RegValue);
4792 }
4793
4794 /* Query the adapter for the state of the V24 status (input) signals.
4795  */
4796 void get_signals(SLMP_INFO *info)
4797 {
4798         u16 status = read_reg(info, SR3);
4799         u16 gpstatus = read_status_reg(info);
4800         u16 testbit;
4801
4802         /* clear all serial signals except DTR and RTS */
4803         info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4804
4805         /* set serial signal bits to reflect MISR */
4806
4807         if (!(status & BIT3))
4808                 info->serial_signals |= SerialSignal_CTS;
4809
4810         if ( !(status & BIT2))
4811                 info->serial_signals |= SerialSignal_DCD;
4812
4813         testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4814         if (!(gpstatus & testbit))
4815                 info->serial_signals |= SerialSignal_RI;
4816
4817         testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4818         if (!(gpstatus & testbit))
4819                 info->serial_signals |= SerialSignal_DSR;
4820 }
4821
4822 /* Set the state of DTR and RTS based on contents of
4823  * serial_signals member of device context.
4824  */
4825 void set_signals(SLMP_INFO *info)
4826 {
4827         unsigned char RegValue;
4828         u16 EnableBit;
4829
4830         RegValue = read_reg(info, CTL);
4831         if (info->serial_signals & SerialSignal_RTS)
4832                 RegValue &= ~BIT0;
4833         else
4834                 RegValue |= BIT0;
4835         write_reg(info, CTL, RegValue);
4836
4837         // Port 0..3 DTR is ctrl reg <1,3,5,7>
4838         EnableBit = BIT1 << (info->port_num*2);
4839         if (info->serial_signals & SerialSignal_DTR)
4840                 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4841         else
4842                 info->port_array[0]->ctrlreg_value |= EnableBit;
4843         write_control_reg(info);
4844 }
4845
4846 /*******************/
4847 /* DMA Buffer Code */
4848 /*******************/
4849
4850 /* Set the count for all receive buffers to SCABUFSIZE
4851  * and set the current buffer to the first buffer. This effectively
4852  * makes all buffers free and discards any data in buffers.
4853  */
4854 void rx_reset_buffers(SLMP_INFO *info)
4855 {
4856         rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4857 }
4858
4859 /* Free the buffers used by a received frame
4860  *
4861  * info   pointer to device instance data
4862  * first  index of 1st receive buffer of frame
4863  * last   index of last receive buffer of frame
4864  */
4865 void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4866 {
4867         int done = 0;
4868
4869         while(!done) {
4870                 /* reset current buffer for reuse */
4871                 info->rx_buf_list[first].status = 0xff;
4872
4873                 if (first == last) {
4874                         done = 1;
4875                         /* set new last rx descriptor address */
4876                         write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4877                 }
4878
4879                 first++;
4880                 if (first == info->rx_buf_count)
4881                         first = 0;
4882         }
4883
4884         /* set current buffer to next buffer after last buffer of frame */
4885         info->current_rx_buf = first;
4886 }
4887
4888 /* Return a received frame from the receive DMA buffers.
4889  * Only frames received without errors are returned.
4890  *
4891  * Return Value:        1 if frame returned, otherwise 0
4892  */
4893 int rx_get_frame(SLMP_INFO *info)
4894 {
4895         unsigned int StartIndex, EndIndex;      /* index of 1st and last buffers of Rx frame */
4896         unsigned short status;
4897         unsigned int framesize = 0;
4898         int ReturnCode = 0;
4899         unsigned long flags;
4900         struct tty_struct *tty = info->tty;
4901         unsigned char addr_field = 0xff;
4902         SCADESC *desc;
4903         SCADESC_EX *desc_ex;
4904
4905 CheckAgain:
4906         /* assume no frame returned, set zero length */
4907         framesize = 0;
4908         addr_field = 0xff;
4909
4910         /*
4911          * current_rx_buf points to the 1st buffer of the next available
4912          * receive frame. To find the last buffer of the frame look for
4913          * a non-zero status field in the buffer entries. (The status
4914          * field is set by the 16C32 after completing a receive frame.
4915          */
4916         StartIndex = EndIndex = info->current_rx_buf;
4917
4918         for ( ;; ) {
4919                 desc = &info->rx_buf_list[EndIndex];
4920                 desc_ex = &info->rx_buf_list_ex[EndIndex];
4921
4922                 if (desc->status == 0xff)
4923                         goto Cleanup;   /* current desc still in use, no frames available */
4924
4925                 if (framesize == 0 && info->params.addr_filter != 0xff)
4926                         addr_field = desc_ex->virt_addr[0];
4927
4928                 framesize += desc->length;
4929
4930                 /* Status != 0 means last buffer of frame */
4931                 if (desc->status)
4932                         break;
4933
4934                 EndIndex++;
4935                 if (EndIndex == info->rx_buf_count)
4936                         EndIndex = 0;
4937
4938                 if (EndIndex == info->current_rx_buf) {
4939                         /* all buffers have been 'used' but none mark      */
4940                         /* the end of a frame. Reset buffers and receiver. */
4941                         if ( info->rx_enabled ){
4942                                 spin_lock_irqsave(&info->lock,flags);
4943                                 rx_start(info);
4944                                 spin_unlock_irqrestore(&info->lock,flags);
4945                         }
4946                         goto Cleanup;
4947                 }
4948
4949         }
4950
4951         /* check status of receive frame */
4952
4953         /* frame status is byte stored after frame data
4954          *
4955          * 7 EOM (end of msg), 1 = last buffer of frame
4956          * 6 Short Frame, 1 = short frame
4957          * 5 Abort, 1 = frame aborted
4958          * 4 Residue, 1 = last byte is partial
4959          * 3 Overrun, 1 = overrun occurred during frame reception
4960          * 2 CRC,     1 = CRC error detected
4961          *
4962          */
4963         status = desc->status;
4964
4965         /* ignore CRC bit if not using CRC (bit is undefined) */
4966         /* Note:CRC is not save to data buffer */
4967         if (info->params.crc_type == HDLC_CRC_NONE)
4968                 status &= ~BIT2;
4969
4970         if (framesize == 0 ||
4971                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4972                 /* discard 0 byte frames, this seems to occur sometime
4973                  * when remote is idling flags.
4974                  */
4975                 rx_free_frame_buffers(info, StartIndex, EndIndex);
4976                 goto CheckAgain;
4977         }
4978
4979         if (framesize < 2)
4980                 status |= BIT6;
4981
4982         if (status & (BIT6+BIT5+BIT3+BIT2)) {
4983                 /* received frame has errors,
4984                  * update counts and mark frame size as 0
4985                  */
4986                 if (status & BIT6)
4987                         info->icount.rxshort++;
4988                 else if (status & BIT5)
4989                         info->icount.rxabort++;
4990                 else if (status & BIT3)
4991                         info->icount.rxover++;
4992                 else
4993                         info->icount.rxcrc++;
4994
4995                 framesize = 0;
4996 #ifdef CONFIG_HDLC
4997                 {
4998                         struct net_device_stats *stats = hdlc_stats(info->netdev);
4999                         stats->rx_errors++;
5000                         stats->rx_frame_errors++;
5001                 }
5002 #endif
5003         }
5004
5005         if ( debug_level >= DEBUG_LEVEL_BH )
5006                 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
5007                         __FILE__,__LINE__,info->device_name,status,framesize);
5008
5009         if ( debug_level >= DEBUG_LEVEL_DATA )
5010                 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
5011                         min_t(int, framesize,SCABUFSIZE),0);
5012
5013         if (framesize) {
5014                 if (framesize > info->max_frame_size)
5015                         info->icount.rxlong++;
5016                 else {
5017                         /* copy dma buffer(s) to contiguous intermediate buffer */
5018                         int copy_count = framesize;
5019                         int index = StartIndex;
5020                         unsigned char *ptmp = info->tmp_rx_buf;
5021                         info->tmp_rx_buf_count = framesize;
5022
5023                         info->icount.rxok++;
5024
5025                         while(copy_count) {
5026                                 int partial_count = min(copy_count,SCABUFSIZE);
5027                                 memcpy( ptmp,
5028                                         info->rx_buf_list_ex[index].virt_addr,
5029                                         partial_count );
5030                                 ptmp += partial_count;
5031                                 copy_count -= partial_count;
5032
5033                                 if ( ++index == info->rx_buf_count )
5034                                         index = 0;
5035                         }
5036
5037 #ifdef CONFIG_HDLC
5038                         if (info->netcount)
5039                                 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
5040                         else
5041 #endif
5042                                 ldisc_receive_buf(tty,info->tmp_rx_buf,
5043                                                   info->flag_buf, framesize);
5044                 }
5045         }
5046         /* Free the buffers used by this frame. */
5047         rx_free_frame_buffers( info, StartIndex, EndIndex );
5048
5049         ReturnCode = 1;
5050
5051 Cleanup:
5052         if ( info->rx_enabled && info->rx_overflow ) {
5053                 /* Receiver is enabled, but needs to restarted due to
5054                  * rx buffer overflow. If buffers are empty, restart receiver.
5055                  */
5056                 if (info->rx_buf_list[EndIndex].status == 0xff) {
5057                         spin_lock_irqsave(&info->lock,flags);
5058                         rx_start(info);
5059                         spin_unlock_irqrestore(&info->lock,flags);
5060                 }
5061         }
5062
5063         return ReturnCode;
5064 }
5065
5066 /* load the transmit DMA buffer with data
5067  */
5068 void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5069 {
5070         unsigned short copy_count;
5071         unsigned int i = 0;
5072         SCADESC *desc;
5073         SCADESC_EX *desc_ex;
5074
5075         if ( debug_level >= DEBUG_LEVEL_DATA )
5076                 trace_block(info,buf, min_t(int, count,SCABUFSIZE), 1);
5077
5078         /* Copy source buffer to one or more DMA buffers, starting with
5079          * the first transmit dma buffer.
5080          */
5081         for(i=0;;)
5082         {
5083                 copy_count = min_t(unsigned short,count,SCABUFSIZE);
5084
5085                 desc = &info->tx_buf_list[i];
5086                 desc_ex = &info->tx_buf_list_ex[i];
5087
5088                 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5089
5090                 desc->length = copy_count;
5091                 desc->status = 0;
5092
5093                 buf += copy_count;
5094                 count -= copy_count;
5095
5096                 if (!count)
5097                         break;
5098
5099                 i++;
5100                 if (i >= info->tx_buf_count)
5101                         i = 0;
5102         }
5103
5104         info->tx_buf_list[i].status = 0x81;     /* set EOM and EOT status */
5105         info->last_tx_buf = ++i;
5106 }
5107
5108 int register_test(SLMP_INFO *info)
5109 {
5110         static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5111         static unsigned int count = sizeof(testval)/sizeof(unsigned char);
5112         unsigned int i;
5113         int rc = TRUE;
5114         unsigned long flags;
5115
5116         spin_lock_irqsave(&info->lock,flags);
5117         reset_port(info);
5118
5119         /* assume failure */
5120         info->init_error = DiagStatus_AddressFailure;
5121
5122         /* Write bit patterns to various registers but do it out of */
5123         /* sync, then read back and verify values. */
5124
5125         for (i = 0 ; i < count ; i++) {
5126                 write_reg(info, TMC, testval[i]);
5127                 write_reg(info, IDL, testval[(i+1)%count]);
5128                 write_reg(info, SA0, testval[(i+2)%count]);
5129                 write_reg(info, SA1, testval[(i+3)%count]);
5130
5131                 if ( (read_reg(info, TMC) != testval[i]) ||
5132                           (read_reg(info, IDL) != testval[(i+1)%count]) ||
5133                           (read_reg(info, SA0) != testval[(i+2)%count]) ||
5134                           (read_reg(info, SA1) != testval[(i+3)%count]) )
5135                 {
5136                         rc = FALSE;
5137                         break;
5138                 }
5139         }
5140
5141         reset_port(info);
5142         spin_unlock_irqrestore(&info->lock,flags);
5143
5144         return rc;
5145 }
5146
5147 int irq_test(SLMP_INFO *info)
5148 {
5149         unsigned long timeout;
5150         unsigned long flags;
5151
5152         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5153
5154         spin_lock_irqsave(&info->lock,flags);
5155         reset_port(info);
5156
5157         /* assume failure */
5158         info->init_error = DiagStatus_IrqFailure;
5159         info->irq_occurred = FALSE;
5160
5161         /* setup timer0 on SCA0 to interrupt */
5162
5163         /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5164         write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5165
5166         write_reg(info, (unsigned char)(timer + TEPR), 0);      /* timer expand prescale */
5167         write_reg16(info, (unsigned char)(timer + TCONR), 1);   /* timer constant */
5168
5169
5170         /* TMCS, Timer Control/Status Register
5171          *
5172          * 07      CMF, Compare match flag (read only) 1=match
5173          * 06      ECMI, CMF Interrupt Enable: 1=enabled
5174          * 05      Reserved, must be 0
5175          * 04      TME, Timer Enable
5176          * 03..00  Reserved, must be 0
5177          *
5178          * 0101 0000
5179          */
5180         write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5181
5182         spin_unlock_irqrestore(&info->lock,flags);
5183
5184         timeout=100;
5185         while( timeout-- && !info->irq_occurred ) {
5186                 msleep_interruptible(10);
5187         }
5188
5189         spin_lock_irqsave(&info->lock,flags);
5190         reset_port(info);
5191         spin_unlock_irqrestore(&info->lock,flags);
5192
5193         return info->irq_occurred;
5194 }
5195
5196 /* initialize individual SCA device (2 ports)
5197  */
5198 static int sca_init(SLMP_INFO *info)
5199 {
5200         /* set wait controller to single mem partition (low), no wait states */
5201         write_reg(info, PABR0, 0);      /* wait controller addr boundary 0 */
5202         write_reg(info, PABR1, 0);      /* wait controller addr boundary 1 */
5203         write_reg(info, WCRL, 0);       /* wait controller low range */
5204         write_reg(info, WCRM, 0);       /* wait controller mid range */
5205         write_reg(info, WCRH, 0);       /* wait controller high range */
5206
5207         /* DPCR, DMA Priority Control
5208          *
5209          * 07..05  Not used, must be 0
5210          * 04      BRC, bus release condition: 0=all transfers complete
5211          * 03      CCC, channel change condition: 0=every cycle
5212          * 02..00  PR<2..0>, priority 100=round robin
5213          *
5214          * 00000100 = 0x04
5215          */
5216         write_reg(info, DPCR, dma_priority);
5217
5218         /* DMA Master Enable, BIT7: 1=enable all channels */
5219         write_reg(info, DMER, 0x80);
5220
5221         /* enable all interrupt classes */
5222         write_reg(info, IER0, 0xff);    /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5223         write_reg(info, IER1, 0xff);    /* DMIB,DMIA (channels 0-3) */
5224         write_reg(info, IER2, 0xf0);    /* TIRQ (timers 0-3) */
5225
5226         /* ITCR, interrupt control register
5227          * 07      IPC, interrupt priority, 0=MSCI->DMA
5228          * 06..05  IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5229          * 04      VOS, Vector Output, 0=unmodified vector
5230          * 03..00  Reserved, must be 0
5231          */
5232         write_reg(info, ITCR, 0);
5233
5234         return TRUE;
5235 }
5236
5237 /* initialize adapter hardware
5238  */
5239 int init_adapter(SLMP_INFO *info)
5240 {
5241         int i;
5242
5243         /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5244         volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5245         u32 readval;
5246
5247         info->misc_ctrl_value |= BIT30;
5248         *MiscCtrl = info->misc_ctrl_value;
5249
5250         /*
5251          * Force at least 170ns delay before clearing
5252          * reset bit. Each read from LCR takes at least
5253          * 30ns so 10 times for 300ns to be safe.
5254          */
5255         for(i=0;i<10;i++)
5256                 readval = *MiscCtrl;
5257
5258         info->misc_ctrl_value &= ~BIT30;
5259         *MiscCtrl = info->misc_ctrl_value;
5260
5261         /* init control reg (all DTRs off, all clksel=input) */
5262         info->ctrlreg_value = 0xaa;
5263         write_control_reg(info);
5264
5265         {
5266                 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5267                 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5268
5269                 switch(read_ahead_count)
5270                 {
5271                 case 16:
5272                         lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5273                         break;
5274                 case 8:
5275                         lcr1_brdr_value |= BIT5 + BIT4;
5276                         break;
5277                 case 4:
5278                         lcr1_brdr_value |= BIT5 + BIT3;
5279                         break;
5280                 case 0:
5281                         lcr1_brdr_value |= BIT5;
5282                         break;
5283                 }
5284
5285                 *LCR1BRDR = lcr1_brdr_value;
5286                 *MiscCtrl = misc_ctrl_value;
5287         }
5288
5289         sca_init(info->port_array[0]);
5290         sca_init(info->port_array[2]);
5291
5292         return TRUE;
5293 }
5294
5295 /* Loopback an HDLC frame to test the hardware
5296  * interrupt and DMA functions.
5297  */
5298 int loopback_test(SLMP_INFO *info)
5299 {
5300 #define TESTFRAMESIZE 20
5301
5302         unsigned long timeout;
5303         u16 count = TESTFRAMESIZE;
5304         unsigned char buf[TESTFRAMESIZE];
5305         int rc = FALSE;
5306         unsigned long flags;
5307
5308         struct tty_struct *oldtty = info->tty;
5309         u32 speed = info->params.clock_speed;
5310
5311         info->params.clock_speed = 3686400;
5312         info->tty = NULL;
5313
5314         /* assume failure */
5315         info->init_error = DiagStatus_DmaFailure;
5316
5317         /* build and send transmit frame */
5318         for (count = 0; count < TESTFRAMESIZE;++count)
5319                 buf[count] = (unsigned char)count;
5320
5321         memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5322
5323         /* program hardware for HDLC and enabled receiver */
5324         spin_lock_irqsave(&info->lock,flags);
5325         hdlc_mode(info);
5326         enable_loopback(info,1);
5327         rx_start(info);
5328         info->tx_count = count;
5329         tx_load_dma_buffer(info,buf,count);
5330         tx_start(info);
5331         spin_unlock_irqrestore(&info->lock,flags);
5332
5333         /* wait for receive complete */
5334         /* Set a timeout for waiting for interrupt. */
5335         for ( timeout = 100; timeout; --timeout ) {
5336                 msleep_interruptible(10);
5337
5338                 if (rx_get_frame(info)) {
5339                         rc = TRUE;
5340                         break;
5341                 }
5342         }
5343
5344         /* verify received frame length and contents */
5345         if (rc == TRUE &&
5346                 ( info->tmp_rx_buf_count != count ||
5347                   memcmp(buf, info->tmp_rx_buf,count))) {
5348                 rc = FALSE;
5349         }
5350
5351         spin_lock_irqsave(&info->lock,flags);
5352         reset_adapter(info);
5353         spin_unlock_irqrestore(&info->lock,flags);
5354
5355         info->params.clock_speed = speed;
5356         info->tty = oldtty;
5357
5358         return rc;
5359 }
5360
5361 /* Perform diagnostics on hardware
5362  */
5363 int adapter_test( SLMP_INFO *info )
5364 {
5365         unsigned long flags;
5366         if ( debug_level >= DEBUG_LEVEL_INFO )
5367                 printk( "%s(%d):Testing device %s\n",
5368                         __FILE__,__LINE__,info->device_name );
5369
5370         spin_lock_irqsave(&info->lock,flags);
5371         init_adapter(info);
5372         spin_unlock_irqrestore(&info->lock,flags);
5373
5374         info->port_array[0]->port_count = 0;
5375
5376         if ( register_test(info->port_array[0]) &&
5377                 register_test(info->port_array[1])) {
5378
5379                 info->port_array[0]->port_count = 2;
5380
5381                 if ( register_test(info->port_array[2]) &&
5382                         register_test(info->port_array[3]) )
5383                         info->port_array[0]->port_count += 2;
5384         }
5385         else {
5386                 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5387                         __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5388                 return -ENODEV;
5389         }
5390
5391         if ( !irq_test(info->port_array[0]) ||
5392                 !irq_test(info->port_array[1]) ||
5393                  (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5394                  (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5395                 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5396                         __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5397                 return -ENODEV;
5398         }
5399
5400         if (!loopback_test(info->port_array[0]) ||
5401                 !loopback_test(info->port_array[1]) ||
5402                  (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5403                  (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5404                 printk( "%s(%d):DMA test failure for device %s\n",
5405                         __FILE__,__LINE__,info->device_name);
5406                 return -ENODEV;
5407         }
5408
5409         if ( debug_level >= DEBUG_LEVEL_INFO )
5410                 printk( "%s(%d):device %s passed diagnostics\n",
5411                         __FILE__,__LINE__,info->device_name );
5412
5413         info->port_array[0]->init_error = 0;
5414         info->port_array[1]->init_error = 0;
5415         if ( info->port_count > 2 ) {
5416                 info->port_array[2]->init_error = 0;
5417                 info->port_array[3]->init_error = 0;
5418         }
5419
5420         return 0;
5421 }
5422
5423 /* Test the shared memory on a PCI adapter.
5424  */
5425 int memory_test(SLMP_INFO *info)
5426 {
5427         static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5428                 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5429         unsigned long count = sizeof(testval)/sizeof(unsigned long);
5430         unsigned long i;
5431         unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5432         unsigned long * addr = (unsigned long *)info->memory_base;
5433
5434         /* Test data lines with test pattern at one location. */
5435
5436         for ( i = 0 ; i < count ; i++ ) {
5437                 *addr = testval[i];
5438                 if ( *addr != testval[i] )
5439                         return FALSE;
5440         }
5441
5442         /* Test address lines with incrementing pattern over */
5443         /* entire address range. */
5444
5445         for ( i = 0 ; i < limit ; i++ ) {
5446                 *addr = i * 4;
5447                 addr++;
5448         }
5449
5450         addr = (unsigned long *)info->memory_base;
5451
5452         for ( i = 0 ; i < limit ; i++ ) {
5453                 if ( *addr != i * 4 )
5454                         return FALSE;
5455                 addr++;
5456         }
5457
5458         memset( info->memory_base, 0, SCA_MEM_SIZE );
5459         return TRUE;
5460 }
5461
5462 /* Load data into PCI adapter shared memory.
5463  *
5464  * The PCI9050 releases control of the local bus
5465  * after completing the current read or write operation.
5466  *
5467  * While the PCI9050 write FIFO not empty, the
5468  * PCI9050 treats all of the writes as a single transaction
5469  * and does not release the bus. This causes DMA latency problems
5470  * at high speeds when copying large data blocks to the shared memory.
5471  *
5472  * This function breaks a write into multiple transations by
5473  * interleaving a read which flushes the write FIFO and 'completes'
5474  * the write transation. This allows any pending DMA request to gain control
5475  * of the local bus in a timely fasion.
5476  */
5477 void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5478 {
5479         /* A load interval of 16 allows for 4 32-bit writes at */
5480         /* 136ns each for a maximum latency of 542ns on the local bus.*/
5481
5482         unsigned short interval = count / sca_pci_load_interval;
5483         unsigned short i;
5484
5485         for ( i = 0 ; i < interval ; i++ )
5486         {
5487                 memcpy(dest, src, sca_pci_load_interval);
5488                 read_status_reg(info);
5489                 dest += sca_pci_load_interval;
5490                 src += sca_pci_load_interval;
5491         }
5492
5493         memcpy(dest, src, count % sca_pci_load_interval);
5494 }
5495
5496 void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5497 {
5498         int i;
5499         int linecount;
5500         if (xmit)
5501                 printk("%s tx data:\n",info->device_name);
5502         else
5503                 printk("%s rx data:\n",info->device_name);
5504
5505         while(count) {
5506                 if (count > 16)
5507                         linecount = 16;
5508                 else
5509                         linecount = count;
5510
5511                 for(i=0;i<linecount;i++)
5512                         printk("%02X ",(unsigned char)data[i]);
5513                 for(;i<17;i++)
5514                         printk("   ");
5515                 for(i=0;i<linecount;i++) {
5516                         if (data[i]>=040 && data[i]<=0176)
5517                                 printk("%c",data[i]);
5518                         else
5519                                 printk(".");
5520                 }
5521                 printk("\n");
5522
5523                 data  += linecount;
5524                 count -= linecount;
5525         }
5526 }       /* end of trace_block() */
5527
5528 /* called when HDLC frame times out
5529  * update stats and do tx completion processing
5530  */
5531 void tx_timeout(unsigned long context)
5532 {
5533         SLMP_INFO *info = (SLMP_INFO*)context;
5534         unsigned long flags;
5535
5536         if ( debug_level >= DEBUG_LEVEL_INFO )
5537                 printk( "%s(%d):%s tx_timeout()\n",
5538                         __FILE__,__LINE__,info->device_name);
5539         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5540                 info->icount.txtimeout++;
5541         }
5542         spin_lock_irqsave(&info->lock,flags);
5543         info->tx_active = 0;
5544         info->tx_count = info->tx_put = info->tx_get = 0;
5545
5546         spin_unlock_irqrestore(&info->lock,flags);
5547
5548 #ifdef CONFIG_HDLC
5549         if (info->netcount)
5550                 hdlcdev_tx_done(info);
5551         else
5552 #endif
5553                 bh_transmit(info);
5554 }
5555
5556 /* called to periodically check the DSR/RI modem signal input status
5557  */
5558 void status_timeout(unsigned long context)
5559 {
5560         u16 status = 0;
5561         SLMP_INFO *info = (SLMP_INFO*)context;
5562         unsigned long flags;
5563         unsigned char delta;
5564
5565
5566         spin_lock_irqsave(&info->lock,flags);
5567         get_signals(info);
5568         spin_unlock_irqrestore(&info->lock,flags);
5569
5570         /* check for DSR/RI state change */
5571
5572         delta = info->old_signals ^ info->serial_signals;
5573         info->old_signals = info->serial_signals;
5574
5575         if (delta & SerialSignal_DSR)
5576                 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5577
5578         if (delta & SerialSignal_RI)
5579                 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5580
5581         if (delta & SerialSignal_DCD)
5582                 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5583
5584         if (delta & SerialSignal_CTS)
5585                 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5586
5587         if (status)
5588                 isr_io_pin(info,status);
5589
5590         info->status_timer.data = (unsigned long)info;
5591         info->status_timer.function = status_timeout;
5592         info->status_timer.expires = jiffies + msecs_to_jiffies(10);
5593         add_timer(&info->status_timer);
5594 }
5595
5596
5597 /* Register Access Routines -
5598  * All registers are memory mapped
5599  */
5600 #define CALC_REGADDR() \
5601         unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5602         if (info->port_num > 1) \
5603                 RegAddr += 256;                 /* port 0-1 SCA0, 2-3 SCA1 */ \
5604         if ( info->port_num & 1) { \
5605                 if (Addr > 0x7f) \
5606                         RegAddr += 0x40;        /* DMA access */ \
5607                 else if (Addr > 0x1f && Addr < 0x60) \
5608                         RegAddr += 0x20;        /* MSCI access */ \
5609         }
5610
5611
5612 unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5613 {
5614         CALC_REGADDR();
5615         return *RegAddr;
5616 }
5617 void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5618 {
5619         CALC_REGADDR();
5620         *RegAddr = Value;
5621 }
5622
5623 u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5624 {
5625         CALC_REGADDR();
5626         return *((u16 *)RegAddr);
5627 }
5628
5629 void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5630 {
5631         CALC_REGADDR();
5632         *((u16 *)RegAddr) = Value;
5633 }
5634
5635 unsigned char read_status_reg(SLMP_INFO * info)
5636 {
5637         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5638         return *RegAddr;
5639 }
5640
5641 void write_control_reg(SLMP_INFO * info)
5642 {
5643         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5644         *RegAddr = info->port_array[0]->ctrlreg_value;
5645 }
5646
5647
5648 static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5649                                           const struct pci_device_id *ent)
5650 {
5651         if (pci_enable_device(dev)) {
5652                 printk("error enabling pci device %p\n", dev);
5653                 return -EIO;
5654         }
5655         device_init( ++synclinkmp_adapter_count, dev );
5656         return 0;
5657 }
5658
5659 static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
5660 {
5661 }