[PATCH] JMB 368 PATA detection
[linux-2.6] / drivers / ide / pci / slc90e66.c
1 /*
2  *  linux/drivers/ide/pci/slc90e66.c    Version 0.11    September 11, 2002
3  *
4  *  Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
5  *
6  * This a look-a-like variation of the ICH0 PIIX4 Ultra-66,
7  * but this keeps the ISA-Bridge and slots alive.
8  *
9  */
10
11 #include <linux/types.h>
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/hdreg.h>
17 #include <linux/ide.h>
18 #include <linux/delay.h>
19 #include <linux/init.h>
20
21 #include <asm/io.h>
22
23 static u8 slc90e66_ratemask (ide_drive_t *drive)
24 {
25         u8 mode = 2;
26
27         if (!eighty_ninty_three(drive))
28                 mode = min(mode, (u8)1);
29         return mode;
30 }
31
32 static u8 slc90e66_dma_2_pio (u8 xfer_rate) {
33         switch(xfer_rate) {
34                 case XFER_UDMA_4:
35                 case XFER_UDMA_3:
36                 case XFER_UDMA_2:
37                 case XFER_UDMA_1:
38                 case XFER_UDMA_0:
39                 case XFER_MW_DMA_2:
40                 case XFER_PIO_4:
41                         return 4;
42                 case XFER_MW_DMA_1:
43                 case XFER_PIO_3:
44                         return 3;
45                 case XFER_SW_DMA_2:
46                 case XFER_PIO_2:
47                         return 2;
48                 case XFER_MW_DMA_0:
49                 case XFER_SW_DMA_1:
50                 case XFER_SW_DMA_0:
51                 case XFER_PIO_1:
52                 case XFER_PIO_0:
53                 case XFER_PIO_SLOW:
54                 default:
55                         return 0;
56         }
57 }
58
59 /*
60  *  Based on settings done by AMI BIOS
61  *  (might be useful if drive is not registered in CMOS for any reason).
62  */
63 static void slc90e66_tune_drive (ide_drive_t *drive, u8 pio)
64 {
65         ide_hwif_t *hwif        = HWIF(drive);
66         struct pci_dev *dev     = hwif->pci_dev;
67         int is_slave            = (&hwif->drives[1] == drive);
68         int master_port         = hwif->channel ? 0x42 : 0x40;
69         int slave_port          = 0x44;
70         unsigned long flags;
71         u16 master_data;
72         u8 slave_data;
73                                  /* ISP  RTC */
74         static const u8 timings[][2]= {
75                                     { 0, 0 },
76                                     { 0, 0 },
77                                     { 1, 0 },
78                                     { 2, 1 },
79                                     { 2, 3 }, };
80
81         pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
82         spin_lock_irqsave(&ide_lock, flags);
83         pci_read_config_word(dev, master_port, &master_data);
84         if (is_slave) {
85                 master_data = master_data | 0x4000;
86                 if (pio > 1)
87                         /* enable PPE, IE and TIME */
88                         master_data = master_data | 0x0070;
89                 pci_read_config_byte(dev, slave_port, &slave_data);
90                 slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0);
91                 slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0));
92         } else {
93                 master_data = master_data & 0xccf8;
94                 if (pio > 1)
95                         /* enable PPE, IE and TIME */
96                         master_data = master_data | 0x0007;
97                 master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
98         }
99         pci_write_config_word(dev, master_port, master_data);
100         if (is_slave)
101                 pci_write_config_byte(dev, slave_port, slave_data);
102         spin_unlock_irqrestore(&ide_lock, flags);
103 }
104
105 static int slc90e66_tune_chipset (ide_drive_t *drive, u8 xferspeed)
106 {
107         ide_hwif_t *hwif        = HWIF(drive);
108         struct pci_dev *dev     = hwif->pci_dev;
109         u8 maslave              = hwif->channel ? 0x42 : 0x40;
110         u8 speed        = ide_rate_filter(slc90e66_ratemask(drive), xferspeed);
111         int sitre = 0, a_speed  = 7 << (drive->dn * 4);
112         int u_speed = 0, u_flag = 1 << drive->dn;
113         u16                     reg4042, reg44, reg48, reg4a;
114
115         pci_read_config_word(dev, maslave, &reg4042);
116         sitre = (reg4042 & 0x4000) ? 1 : 0;
117         pci_read_config_word(dev, 0x44, &reg44);
118         pci_read_config_word(dev, 0x48, &reg48);
119         pci_read_config_word(dev, 0x4a, &reg4a);
120
121         switch(speed) {
122                 case XFER_UDMA_4:       u_speed = 4 << (drive->dn * 4); break;
123                 case XFER_UDMA_3:       u_speed = 3 << (drive->dn * 4); break;
124                 case XFER_UDMA_2:       u_speed = 2 << (drive->dn * 4); break;
125                 case XFER_UDMA_1:       u_speed = 1 << (drive->dn * 4); break;
126                 case XFER_UDMA_0:       u_speed = 0 << (drive->dn * 4); break;
127                 case XFER_MW_DMA_2:
128                 case XFER_MW_DMA_1:
129                 case XFER_SW_DMA_2:     break;
130                 case XFER_PIO_4:
131                 case XFER_PIO_3:
132                 case XFER_PIO_2:
133                 case XFER_PIO_0:        break;
134                 default:                return -1;
135         }
136
137         if (speed >= XFER_UDMA_0) {
138                 if (!(reg48 & u_flag))
139                         pci_write_config_word(dev, 0x48, reg48|u_flag);
140                 /* FIXME: (reg4a & a_speed) ? */
141                 if ((reg4a & u_speed) != u_speed) {
142                         pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
143                         pci_read_config_word(dev, 0x4a, &reg4a);
144                         pci_write_config_word(dev, 0x4a, reg4a|u_speed);
145                 }
146         } else {
147                 if (reg48 & u_flag)
148                         pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
149                 if (reg4a & a_speed)
150                         pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
151         }
152
153         slc90e66_tune_drive(drive, slc90e66_dma_2_pio(speed));
154         return (ide_config_drive_speed(drive, speed));
155 }
156
157 static int slc90e66_config_drive_for_dma (ide_drive_t *drive)
158 {
159         u8 speed = ide_dma_speed(drive, slc90e66_ratemask(drive));
160
161         if (!(speed)) {
162                 u8 tspeed = ide_get_best_pio_mode(drive, 255, 5, NULL);
163                 speed = slc90e66_dma_2_pio(XFER_PIO_0 + tspeed);
164         }
165
166         (void) slc90e66_tune_chipset(drive, speed);
167         return ide_dma_enable(drive);
168 }
169
170 static int slc90e66_config_drive_xfer_rate (ide_drive_t *drive)
171 {
172         ide_hwif_t *hwif        = HWIF(drive);
173         struct hd_driveid *id   = drive->id;
174
175         drive->init_speed = 0;
176
177         if (id && (id->capability & 1) && drive->autodma) {
178
179                 if (ide_use_dma(drive)) {
180                         if (slc90e66_config_drive_for_dma(drive))
181                                 return hwif->ide_dma_on(drive);
182                 }
183
184                 goto fast_ata_pio;
185
186         } else if ((id->capability & 8) || (id->field_valid & 2)) {
187 fast_ata_pio:
188                 hwif->tuneproc(drive, 5);
189                 return hwif->ide_dma_off_quietly(drive);
190         }
191         /* IORDY not supported */
192         return 0;
193 }
194
195 static void __devinit init_hwif_slc90e66 (ide_hwif_t *hwif)
196 {
197         u8 reg47 = 0;
198         u8 mask = hwif->channel ? 0x01 : 0x02;  /* bit0:Primary */
199
200         hwif->autodma = 0;
201
202         if (!hwif->irq)
203                 hwif->irq = hwif->channel ? 15 : 14;
204
205         hwif->speedproc = &slc90e66_tune_chipset;
206         hwif->tuneproc = &slc90e66_tune_drive;
207
208         pci_read_config_byte(hwif->pci_dev, 0x47, &reg47);
209
210         if (!hwif->dma_base) {
211                 hwif->drives[0].autotune = 1;
212                 hwif->drives[1].autotune = 1;
213                 return;
214         }
215
216         hwif->atapi_dma = 1;
217         hwif->ultra_mask = 0x1f;
218         hwif->mwdma_mask = 0x07;
219         hwif->swdma_mask = 0x07;
220
221         if (!(hwif->udma_four))
222                 /* bit[0(1)]: 0:80, 1:40 */
223                 hwif->udma_four = (reg47 & mask) ? 0 : 1;
224
225         hwif->ide_dma_check = &slc90e66_config_drive_xfer_rate;
226         if (!noautodma)
227                 hwif->autodma = 1;
228         hwif->drives[0].autodma = hwif->autodma;
229         hwif->drives[1].autodma = hwif->autodma;
230 }
231
232 static ide_pci_device_t slc90e66_chipset __devinitdata = {
233         .name           = "SLC90E66",
234         .init_hwif      = init_hwif_slc90e66,
235         .channels       = 2,
236         .autodma        = AUTODMA,
237         .enablebits     = {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
238         .bootable       = ON_BOARD,
239 };
240
241 static int __devinit slc90e66_init_one(struct pci_dev *dev, const struct pci_device_id *id)
242 {
243         return ide_setup_pci_device(dev, &slc90e66_chipset);
244 }
245
246 static struct pci_device_id slc90e66_pci_tbl[] = {
247         { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1), 0},
248         { 0, },
249 };
250 MODULE_DEVICE_TABLE(pci, slc90e66_pci_tbl);
251
252 static struct pci_driver driver = {
253         .name           = "SLC90e66_IDE",
254         .id_table       = slc90e66_pci_tbl,
255         .probe          = slc90e66_init_one,
256 };
257
258 static int slc90e66_ide_init(void)
259 {
260         return ide_pci_register_driver(&driver);
261 }
262
263 module_init(slc90e66_ide_init);
264
265 MODULE_AUTHOR("Andre Hedrick");
266 MODULE_DESCRIPTION("PCI driver module for SLC90E66 IDE");
267 MODULE_LICENSE("GPL");