git.oblomov.eu Git - linux-2.6/blob - drivers/char/synclink_gt.c

   1 /*
   2  * $Id: synclink_gt.c,v 4.50 2007/07/25 19:29:25 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink GT serial adapters.
   5  *
   6  * written by Paul Fulghum for Microgate Corporation
   7  * paulkf@microgate.com
   8  *
   9  * Microgate and SyncLink are trademarks of Microgate Corporation
  10  *
  11  * This code is released under the GNU General Public License (GPL)
  12  *
  13  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  14  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  15  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  16  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  17  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  18  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  19  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  21  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  22  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  23  * OF THE POSSIBILITY OF SUCH DAMAGE.
  24  */
  25
  26 /*
  27  * DEBUG OUTPUT DEFINITIONS
  28  *
  29  * uncomment lines below to enable specific types of debug output
  30  *
  31  * DBGINFO   information - most verbose output
  32  * DBGERR    serious errors
  33  * DBGBH     bottom half service routine debugging
  34  * DBGISR    interrupt service routine debugging
  35  * DBGDATA   output receive and transmit data
  36  * DBGTBUF   output transmit DMA buffers and registers
  37  * DBGRBUF   output receive DMA buffers and registers
  38  */
  39
  40 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  41 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  42 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  43 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  44 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  45 //#define DBGTBUF(info) dump_tbufs(info)
  46 //#define DBGRBUF(info) dump_rbufs(info)
  47
  48
  49 #include <linux/module.h>
  50 #include <linux/version.h>
  51 #include <linux/errno.h>
  52 #include <linux/signal.h>
  53 #include <linux/sched.h>
  54 #include <linux/timer.h>
  55 #include <linux/interrupt.h>
  56 #include <linux/pci.h>
  57 #include <linux/tty.h>
  58 #include <linux/tty_flip.h>
  59 #include <linux/serial.h>
  60 #include <linux/major.h>
  61 #include <linux/string.h>
  62 #include <linux/fcntl.h>
  63 #include <linux/ptrace.h>
  64 #include <linux/ioport.h>
  65 #include <linux/mm.h>
  66 #include <linux/slab.h>
  67 #include <linux/netdevice.h>
  68 #include <linux/vmalloc.h>
  69 #include <linux/init.h>
  70 #include <linux/delay.h>
  71 #include <linux/ioctl.h>
  72 #include <linux/termios.h>
  73 #include <linux/bitops.h>
  74 #include <linux/workqueue.h>
  75 #include <linux/hdlc.h>
  76 #include <linux/synclink.h>
  77
  78 #include <asm/system.h>
  79 #include <asm/io.h>
  80 #include <asm/irq.h>
  81 #include <asm/dma.h>
  82 #include <asm/types.h>
  83 #include <asm/uaccess.h>
  84
  85 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
  86 #define SYNCLINK_GENERIC_HDLC 1
  87 #else
  88 #define SYNCLINK_GENERIC_HDLC 0
  89 #endif
  90
  91 /*
  92  * module identification
  93  */
  94 static char *driver_name     = "SyncLink GT";
  95 static char *driver_version  = "$Revision: 4.50 $";
  96 static char *tty_driver_name = "synclink_gt";
  97 static char *tty_dev_prefix  = "ttySLG";
  98 MODULE_LICENSE("GPL");
  99 #define MGSL_MAGIC 0x5401
 100 #define MAX_DEVICES 32
 101
 102 static struct pci_device_id pci_table[] = {
 103         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 104         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 105         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 106         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 107         {0,}, /* terminate list */
 108 };
 109 MODULE_DEVICE_TABLE(pci, pci_table);
 110
 111 static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 112 static void remove_one(struct pci_dev *dev);
 113 static struct pci_driver pci_driver = {
 114         .name           = "synclink_gt",
 115         .id_table       = pci_table,
 116         .probe          = init_one,
 117         .remove         = __devexit_p(remove_one),
 118 };
 119
 120 static bool pci_registered;
 121
 122 /*
 123  * module configuration and status
 124  */
 125 static struct slgt_info *slgt_device_list;
 126 static int slgt_device_count;
 127
 128 static int ttymajor;
 129 static int debug_level;
 130 static int maxframe[MAX_DEVICES];
 131 static int dosyncppp[MAX_DEVICES];
 132
 133 module_param(ttymajor, int, 0);
 134 module_param(debug_level, int, 0);
 135 module_param_array(maxframe, int, NULL, 0);
 136 module_param_array(dosyncppp, int, NULL, 0);
 137
 138 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
 139 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
 140 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
 141 MODULE_PARM_DESC(dosyncppp, "Enable synchronous net device, 0=disable 1=enable");
 142
 143 /*
 144  * tty support and callbacks
 145  */
 146 static struct tty_driver *serial_driver;
 147
 148 static int  open(struct tty_struct *tty, struct file * filp);
 149 static void close(struct tty_struct *tty, struct file * filp);
 150 static void hangup(struct tty_struct *tty);
 151 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 152
 153 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 154 static int put_char(struct tty_struct *tty, unsigned char ch);
 155 static void send_xchar(struct tty_struct *tty, char ch);
 156 static void wait_until_sent(struct tty_struct *tty, int timeout);
 157 static int  write_room(struct tty_struct *tty);
 158 static void flush_chars(struct tty_struct *tty);
 159 static void flush_buffer(struct tty_struct *tty);
 160 static void tx_hold(struct tty_struct *tty);
 161 static void tx_release(struct tty_struct *tty);
 162
 163 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 164 static int  read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
 165 static int  chars_in_buffer(struct tty_struct *tty);
 166 static void throttle(struct tty_struct * tty);
 167 static void unthrottle(struct tty_struct * tty);
 168 static void set_break(struct tty_struct *tty, int break_state);
 169
 170 /*
 171  * generic HDLC support and callbacks
 172  */
 173 #if SYNCLINK_GENERIC_HDLC
 174 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 175 static void hdlcdev_tx_done(struct slgt_info *info);
 176 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
 177 static int  hdlcdev_init(struct slgt_info *info);
 178 static void hdlcdev_exit(struct slgt_info *info);
 179 #endif
 180
 181
 182 /*
 183  * device specific structures, macros and functions
 184  */
 185
 186 #define SLGT_MAX_PORTS 4
 187 #define SLGT_REG_SIZE  256
 188
 189 /*
 190  * conditional wait facility
 191  */
 192 struct cond_wait {
 193         struct cond_wait *next;
 194         wait_queue_head_t q;
 195         wait_queue_t wait;
 196         unsigned int data;
 197 };
 198 static void init_cond_wait(struct cond_wait *w, unsigned int data);
 199 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
 200 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
 201 static void flush_cond_wait(struct cond_wait **head);
 202
 203 /*
 204  * DMA buffer descriptor and access macros
 205  */
 206 struct slgt_desc
 207 {
 208         __le16 count;
 209         __le16 status;
 210         __le32 pbuf;  /* physical address of data buffer */
 211         __le32 next;  /* physical address of next descriptor */
 212
 213         /* driver book keeping */
 214         char *buf;          /* virtual  address of data buffer */
 215         unsigned int pdesc; /* physical address of this descriptor */
 216         dma_addr_t buf_dma_addr;
 217 };
 218
 219 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
 220 #define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
 221 #define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
 222 #define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
 223 #define desc_count(a)      (le16_to_cpu((a).count))
 224 #define desc_status(a)     (le16_to_cpu((a).status))
 225 #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
 226 #define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
 227 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
 228 #define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
 229 #define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
 230
 231 struct _input_signal_events {
 232         int ri_up;
 233         int ri_down;
 234         int dsr_up;
 235         int dsr_down;
 236         int dcd_up;
 237         int dcd_down;
 238         int cts_up;
 239         int cts_down;
 240 };
 241
 242 /*
 243  * device instance data structure
 244  */
 245 struct slgt_info {
 246         void *if_ptr;           /* General purpose pointer (used by SPPP) */
 247
 248         struct slgt_info *next_device;  /* device list link */
 249
 250         int magic;
 251         int flags;
 252
 253         char device_name[25];
 254         struct pci_dev *pdev;
 255
 256         int port_count;  /* count of ports on adapter */
 257         int adapter_num; /* adapter instance number */
 258         int port_num;    /* port instance number */
 259
 260         /* array of pointers to port contexts on this adapter */
 261         struct slgt_info *port_array[SLGT_MAX_PORTS];
 262
 263         int                     count;          /* count of opens */
 264         int                     line;           /* tty line instance number */
 265         unsigned short          close_delay;
 266         unsigned short          closing_wait;   /* time to wait before closing */
 267
 268         struct mgsl_icount      icount;
 269
 270         struct tty_struct       *tty;
 271         int                     timeout;
 272         int                     x_char;         /* xon/xoff character */
 273         int                     blocked_open;   /* # of blocked opens */
 274         unsigned int            read_status_mask;
 275         unsigned int            ignore_status_mask;
 276
 277         wait_queue_head_t       open_wait;
 278         wait_queue_head_t       close_wait;
 279
 280         wait_queue_head_t       status_event_wait_q;
 281         wait_queue_head_t       event_wait_q;
 282         struct timer_list       tx_timer;
 283         struct timer_list       rx_timer;
 284
 285         unsigned int            gpio_present;
 286         struct cond_wait        *gpio_wait_q;
 287
 288         spinlock_t lock;        /* spinlock for synchronizing with ISR */
 289
 290         struct work_struct task;
 291         u32 pending_bh;
 292         bool bh_requested;
 293         bool bh_running;
 294
 295         int isr_overflow;
 296         bool irq_requested;     /* true if IRQ requested */
 297         bool irq_occurred;      /* for diagnostics use */
 298
 299         /* device configuration */
 300
 301         unsigned int bus_type;
 302         unsigned int irq_level;
 303         unsigned long irq_flags;
 304
 305         unsigned char __iomem * reg_addr;  /* memory mapped registers address */
 306         u32 phys_reg_addr;
 307         bool reg_addr_requested;
 308
 309         MGSL_PARAMS params;       /* communications parameters */
 310         u32 idle_mode;
 311         u32 max_frame_size;       /* as set by device config */
 312
 313         unsigned int raw_rx_size;
 314         unsigned int if_mode;
 315
 316         /* device status */
 317
 318         bool rx_enabled;
 319         bool rx_restart;
 320
 321         bool tx_enabled;
 322         bool tx_active;
 323
 324         unsigned char signals;    /* serial signal states */
 325         int init_error;  /* initialization error */
 326
 327         unsigned char *tx_buf;
 328         int tx_count;
 329
 330         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 331         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 332         bool drop_rts_on_tx_done;
 333         struct  _input_signal_events    input_signal_events;
 334
 335         int dcd_chkcount;       /* check counts to prevent */
 336         int cts_chkcount;       /* too many IRQs if a signal */
 337         int dsr_chkcount;       /* is floating */
 338         int ri_chkcount;
 339
 340         char *bufs;             /* virtual address of DMA buffer lists */
 341         dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
 342
 343         unsigned int rbuf_count;
 344         struct slgt_desc *rbufs;
 345         unsigned int rbuf_current;
 346         unsigned int rbuf_index;
 347
 348         unsigned int tbuf_count;
 349         struct slgt_desc *tbufs;
 350         unsigned int tbuf_current;
 351         unsigned int tbuf_start;
 352
 353         unsigned char *tmp_rbuf;
 354         unsigned int tmp_rbuf_count;
 355
 356         /* SPPP/Cisco HDLC device parts */
 357
 358         int netcount;
 359         int dosyncppp;
 360         spinlock_t netlock;
 361 #if SYNCLINK_GENERIC_HDLC
 362         struct net_device *netdev;
 363 #endif
 364
 365 };
 366
 367 static MGSL_PARAMS default_params = {
 368         .mode            = MGSL_MODE_HDLC,
 369         .loopback        = 0,
 370         .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
 371         .encoding        = HDLC_ENCODING_NRZI_SPACE,
 372         .clock_speed     = 0,
 373         .addr_filter     = 0xff,
 374         .crc_type        = HDLC_CRC_16_CCITT,
 375         .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
 376         .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
 377         .data_rate       = 9600,
 378         .data_bits       = 8,
 379         .stop_bits       = 1,
 380         .parity          = ASYNC_PARITY_NONE
 381 };
 382
 383
 384 #define BH_RECEIVE  1
 385 #define BH_TRANSMIT 2
 386 #define BH_STATUS   4
 387 #define IO_PIN_SHUTDOWN_LIMIT 100
 388
 389 #define DMABUFSIZE 256
 390 #define DESC_LIST_SIZE 4096
 391
 392 #define MASK_PARITY  BIT1
 393 #define MASK_FRAMING BIT0
 394 #define MASK_BREAK   BIT14
 395 #define MASK_OVERRUN BIT4
 396
 397 #define GSR   0x00 /* global status */
 398 #define JCR   0x04 /* JTAG control */
 399 #define IODR  0x08 /* GPIO direction */
 400 #define IOER  0x0c /* GPIO interrupt enable */
 401 #define IOVR  0x10 /* GPIO value */
 402 #define IOSR  0x14 /* GPIO interrupt status */
 403 #define TDR   0x80 /* tx data */
 404 #define RDR   0x80 /* rx data */
 405 #define TCR   0x82 /* tx control */
 406 #define TIR   0x84 /* tx idle */
 407 #define TPR   0x85 /* tx preamble */
 408 #define RCR   0x86 /* rx control */
 409 #define VCR   0x88 /* V.24 control */
 410 #define CCR   0x89 /* clock control */
 411 #define BDR   0x8a /* baud divisor */
 412 #define SCR   0x8c /* serial control */
 413 #define SSR   0x8e /* serial status */
 414 #define RDCSR 0x90 /* rx DMA control/status */
 415 #define TDCSR 0x94 /* tx DMA control/status */
 416 #define RDDAR 0x98 /* rx DMA descriptor address */
 417 #define TDDAR 0x9c /* tx DMA descriptor address */
 418
 419 #define RXIDLE      BIT14
 420 #define RXBREAK     BIT14
 421 #define IRQ_TXDATA  BIT13
 422 #define IRQ_TXIDLE  BIT12
 423 #define IRQ_TXUNDER BIT11 /* HDLC */
 424 #define IRQ_RXDATA  BIT10
 425 #define IRQ_RXIDLE  BIT9  /* HDLC */
 426 #define IRQ_RXBREAK BIT9  /* async */
 427 #define IRQ_RXOVER  BIT8
 428 #define IRQ_DSR     BIT7
 429 #define IRQ_CTS     BIT6
 430 #define IRQ_DCD     BIT5
 431 #define IRQ_RI      BIT4
 432 #define IRQ_ALL     0x3ff0
 433 #define IRQ_MASTER  BIT0
 434
 435 #define slgt_irq_on(info, mask) \
 436         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
 437 #define slgt_irq_off(info, mask) \
 438         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
 439
 440 static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
 441 static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
 442 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
 443 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
 444 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
 445 static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
 446
 447 static void  msc_set_vcr(struct slgt_info *info);
 448
 449 static int  startup(struct slgt_info *info);
 450 static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
 451 static void shutdown(struct slgt_info *info);
 452 static void program_hw(struct slgt_info *info);
 453 static void change_params(struct slgt_info *info);
 454
 455 static int  register_test(struct slgt_info *info);
 456 static int  irq_test(struct slgt_info *info);
 457 static int  loopback_test(struct slgt_info *info);
 458 static int  adapter_test(struct slgt_info *info);
 459
 460 static void reset_adapter(struct slgt_info *info);
 461 static void reset_port(struct slgt_info *info);
 462 static void async_mode(struct slgt_info *info);
 463 static void sync_mode(struct slgt_info *info);
 464
 465 static void rx_stop(struct slgt_info *info);
 466 static void rx_start(struct slgt_info *info);
 467 static void reset_rbufs(struct slgt_info *info);
 468 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
 469 static void rdma_reset(struct slgt_info *info);
 470 static bool rx_get_frame(struct slgt_info *info);
 471 static bool rx_get_buf(struct slgt_info *info);
 472
 473 static void tx_start(struct slgt_info *info);
 474 static void tx_stop(struct slgt_info *info);
 475 static void tx_set_idle(struct slgt_info *info);
 476 static unsigned int free_tbuf_count(struct slgt_info *info);
 477 static void reset_tbufs(struct slgt_info *info);
 478 static void tdma_reset(struct slgt_info *info);
 479 static void tdma_start(struct slgt_info *info);
 480 static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
 481
 482 static void get_signals(struct slgt_info *info);
 483 static void set_signals(struct slgt_info *info);
 484 static void enable_loopback(struct slgt_info *info);
 485 static void set_rate(struct slgt_info *info, u32 data_rate);
 486
 487 static int  bh_action(struct slgt_info *info);
 488 static void bh_handler(struct work_struct *work);
 489 static void bh_transmit(struct slgt_info *info);
 490 static void isr_serial(struct slgt_info *info);
 491 static void isr_rdma(struct slgt_info *info);
 492 static void isr_txeom(struct slgt_info *info, unsigned short status);
 493 static void isr_tdma(struct slgt_info *info);
 494
 495 static int  alloc_dma_bufs(struct slgt_info *info);
 496 static void free_dma_bufs(struct slgt_info *info);
 497 static int  alloc_desc(struct slgt_info *info);
 498 static void free_desc(struct slgt_info *info);
 499 static int  alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 500 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 501
 502 static int  alloc_tmp_rbuf(struct slgt_info *info);
 503 static void free_tmp_rbuf(struct slgt_info *info);
 504
 505 static void tx_timeout(unsigned long context);
 506 static void rx_timeout(unsigned long context);
 507
 508 /*
 509  * ioctl handlers
 510  */
 511 static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
 512 static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 513 static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 514 static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
 515 static int  set_txidle(struct slgt_info *info, int idle_mode);
 516 static int  tx_enable(struct slgt_info *info, int enable);
 517 static int  tx_abort(struct slgt_info *info);
 518 static int  rx_enable(struct slgt_info *info, int enable);
 519 static int  modem_input_wait(struct slgt_info *info,int arg);
 520 static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
 521 static int  tiocmget(struct tty_struct *tty, struct file *file);
 522 static int  tiocmset(struct tty_struct *tty, struct file *file,
 523                      unsigned int set, unsigned int clear);
 524 static void set_break(struct tty_struct *tty, int break_state);
 525 static int  get_interface(struct slgt_info *info, int __user *if_mode);
 526 static int  set_interface(struct slgt_info *info, int if_mode);
 527 static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 528 static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 529 static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 530
 531 /*
 532  * driver functions
 533  */
 534 static void add_device(struct slgt_info *info);
 535 static void device_init(int adapter_num, struct pci_dev *pdev);
 536 static int  claim_resources(struct slgt_info *info);
 537 static void release_resources(struct slgt_info *info);
 538
 539 /*
 540  * DEBUG OUTPUT CODE
 541  */
 542 #ifndef DBGINFO
 543 #define DBGINFO(fmt)
 544 #endif
 545 #ifndef DBGERR
 546 #define DBGERR(fmt)
 547 #endif
 548 #ifndef DBGBH
 549 #define DBGBH(fmt)
 550 #endif
 551 #ifndef DBGISR
 552 #define DBGISR(fmt)
 553 #endif
 554
 555 #ifdef DBGDATA
 556 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
 557 {
 558         int i;
 559         int linecount;
 560         printk("%s %s data:\n",info->device_name, label);
 561         while(count) {
 562                 linecount = (count > 16) ? 16 : count;
 563                 for(i=0; i < linecount; i++)
 564                         printk("%02X ",(unsigned char)data[i]);
 565                 for(;i<17;i++)
 566                         printk("   ");
 567                 for(i=0;i<linecount;i++) {
 568                         if (data[i]>=040 && data[i]<=0176)
 569                                 printk("%c",data[i]);
 570                         else
 571                                 printk(".");
 572                 }
 573                 printk("\n");
 574                 data  += linecount;
 575                 count -= linecount;
 576         }
 577 }
 578 #else
 579 #define DBGDATA(info, buf, size, label)
 580 #endif
 581
 582 #ifdef DBGTBUF
 583 static void dump_tbufs(struct slgt_info *info)
 584 {
 585         int i;
 586         printk("tbuf_current=%d\n", info->tbuf_current);
 587         for (i=0 ; i < info->tbuf_count ; i++) {
 588                 printk("%d: count=%04X status=%04X\n",
 589                         i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
 590         }
 591 }
 592 #else
 593 #define DBGTBUF(info)
 594 #endif
 595
 596 #ifdef DBGRBUF
 597 static void dump_rbufs(struct slgt_info *info)
 598 {
 599         int i;
 600         printk("rbuf_current=%d\n", info->rbuf_current);
 601         for (i=0 ; i < info->rbuf_count ; i++) {
 602                 printk("%d: count=%04X status=%04X\n",
 603                         i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
 604         }
 605 }
 606 #else
 607 #define DBGRBUF(info)
 608 #endif
 609
 610 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
 611 {
 612 #ifdef SANITY_CHECK
 613         if (!info) {
 614                 printk("null struct slgt_info for (%s) in %s\n", devname, name);
 615                 return 1;
 616         }
 617         if (info->magic != MGSL_MAGIC) {
 618                 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
 619                 return 1;
 620         }
 621 #else
 622         if (!info)
 623                 return 1;
 624 #endif
 625         return 0;
 626 }
 627
 628 /**
 629  * line discipline callback wrappers
 630  *
 631  * The wrappers maintain line discipline references
 632  * while calling into the line discipline.
 633  *
 634  * ldisc_receive_buf  - pass receive data to line discipline
 635  */
 636 static void ldisc_receive_buf(struct tty_struct *tty,
 637                               const __u8 *data, char *flags, int count)
 638 {
 639         struct tty_ldisc *ld;
 640         if (!tty)
 641                 return;
 642         ld = tty_ldisc_ref(tty);
 643         if (ld) {
 644                 if (ld->receive_buf)
 645                         ld->receive_buf(tty, data, flags, count);
 646                 tty_ldisc_deref(ld);
 647         }
 648 }
 649
 650 /* tty callbacks */
 651
 652 static int open(struct tty_struct *tty, struct file *filp)
 653 {
 654         struct slgt_info *info;
 655         int retval, line;
 656         unsigned long flags;
 657
 658         line = tty->index;
 659         if ((line < 0) || (line >= slgt_device_count)) {
 660                 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
 661                 return -ENODEV;
 662         }
 663
 664         info = slgt_device_list;
 665         while(info && info->line != line)
 666                 info = info->next_device;
 667         if (sanity_check(info, tty->name, "open"))
 668                 return -ENODEV;
 669         if (info->init_error) {
 670                 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
 671                 return -ENODEV;
 672         }
 673
 674         tty->driver_data = info;
 675         info->tty = tty;
 676
 677         DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->count));
 678
 679         /* If port is closing, signal caller to try again */
 680         if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
 681                 if (info->flags & ASYNC_CLOSING)
 682                         interruptible_sleep_on(&info->close_wait);
 683                 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
 684                         -EAGAIN : -ERESTARTSYS);
 685                 goto cleanup;
 686         }
 687
 688         info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 689
 690         spin_lock_irqsave(&info->netlock, flags);
 691         if (info->netcount) {
 692                 retval = -EBUSY;
 693                 spin_unlock_irqrestore(&info->netlock, flags);
 694                 goto cleanup;
 695         }
 696         info->count++;
 697         spin_unlock_irqrestore(&info->netlock, flags);
 698
 699         if (info->count == 1) {
 700                 /* 1st open on this device, init hardware */
 701                 retval = startup(info);
 702                 if (retval < 0)
 703                         goto cleanup;
 704         }
 705
 706         retval = block_til_ready(tty, filp, info);
 707         if (retval) {
 708                 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
 709                 goto cleanup;
 710         }
 711
 712         retval = 0;
 713
 714 cleanup:
 715         if (retval) {
 716                 if (tty->count == 1)
 717                         info->tty = NULL; /* tty layer will release tty struct */
 718                 if(info->count)
 719                         info->count--;
 720         }
 721
 722         DBGINFO(("%s open rc=%d\n", info->device_name, retval));
 723         return retval;
 724 }
 725
 726 static void close(struct tty_struct *tty, struct file *filp)
 727 {
 728         struct slgt_info *info = tty->driver_data;
 729
 730         if (sanity_check(info, tty->name, "close"))
 731                 return;
 732         DBGINFO(("%s close entry, count=%d\n", info->device_name, info->count));
 733
 734         if (!info->count)
 735                 return;
 736
 737         if (tty_hung_up_p(filp))
 738                 goto cleanup;
 739
 740         if ((tty->count == 1) && (info->count != 1)) {
 741                 /*
 742                  * tty->count is 1 and the tty structure will be freed.
 743                  * info->count should be one in this case.
 744                  * if it's not, correct it so that the port is shutdown.
 745                  */
 746                 DBGERR(("%s close: bad refcount; tty->count=1, "
 747                        "info->count=%d\n", info->device_name, info->count));
 748                 info->count = 1;
 749         }
 750
 751         info->count--;
 752
 753         /* if at least one open remaining, leave hardware active */
 754         if (info->count)
 755                 goto cleanup;
 756
 757         info->flags |= ASYNC_CLOSING;
 758
 759         /* set tty->closing to notify line discipline to
 760          * only process XON/XOFF characters. Only the N_TTY
 761          * discipline appears to use this (ppp does not).
 762          */
 763         tty->closing = 1;
 764
 765         /* wait for transmit data to clear all layers */
 766
 767         if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
 768                 DBGINFO(("%s call tty_wait_until_sent\n", info->device_name));
 769                 tty_wait_until_sent(tty, info->closing_wait);
 770         }
 771
 772         if (info->flags & ASYNC_INITIALIZED)
 773                 wait_until_sent(tty, info->timeout);
 774         flush_buffer(tty);
 775         tty_ldisc_flush(tty);
 776
 777         shutdown(info);
 778
 779         tty->closing = 0;
 780         info->tty = NULL;
 781
 782         if (info->blocked_open) {
 783                 if (info->close_delay) {
 784                         msleep_interruptible(jiffies_to_msecs(info->close_delay));
 785                 }
 786                 wake_up_interruptible(&info->open_wait);
 787         }
 788
 789         info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
 790
 791         wake_up_interruptible(&info->close_wait);
 792
 793 cleanup:
 794         DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->count));
 795 }
 796
 797 static void hangup(struct tty_struct *tty)
 798 {
 799         struct slgt_info *info = tty->driver_data;
 800
 801         if (sanity_check(info, tty->name, "hangup"))
 802                 return;
 803         DBGINFO(("%s hangup\n", info->device_name));
 804
 805         flush_buffer(tty);
 806         shutdown(info);
 807
 808         info->count = 0;
 809         info->flags &= ~ASYNC_NORMAL_ACTIVE;
 810         info->tty = NULL;
 811
 812         wake_up_interruptible(&info->open_wait);
 813 }
 814
 815 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 816 {
 817         struct slgt_info *info = tty->driver_data;
 818         unsigned long flags;
 819
 820         DBGINFO(("%s set_termios\n", tty->driver->name));
 821
 822         change_params(info);
 823
 824         /* Handle transition to B0 status */
 825         if (old_termios->c_cflag & CBAUD &&
 826             !(tty->termios->c_cflag & CBAUD)) {
 827                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 828                 spin_lock_irqsave(&info->lock,flags);
 829                 set_signals(info);
 830                 spin_unlock_irqrestore(&info->lock,flags);
 831         }
 832
 833         /* Handle transition away from B0 status */
 834         if (!(old_termios->c_cflag & CBAUD) &&
 835             tty->termios->c_cflag & CBAUD) {
 836                 info->signals |= SerialSignal_DTR;
 837                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 838                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 839                         info->signals |= SerialSignal_RTS;
 840                 }
 841                 spin_lock_irqsave(&info->lock,flags);
 842                 set_signals(info);
 843                 spin_unlock_irqrestore(&info->lock,flags);
 844         }
 845
 846         /* Handle turning off CRTSCTS */
 847         if (old_termios->c_cflag & CRTSCTS &&
 848             !(tty->termios->c_cflag & CRTSCTS)) {
 849                 tty->hw_stopped = 0;
 850                 tx_release(tty);
 851         }
 852 }
 853
 854 static int write(struct tty_struct *tty,
 855                  const unsigned char *buf, int count)
 856 {
 857         int ret = 0;
 858         struct slgt_info *info = tty->driver_data;
 859         unsigned long flags;
 860
 861         if (sanity_check(info, tty->name, "write"))
 862                 goto cleanup;
 863         DBGINFO(("%s write count=%d\n", info->device_name, count));
 864
 865         if (!info->tx_buf)
 866                 goto cleanup;
 867
 868         if (count > info->max_frame_size) {
 869                 ret = -EIO;
 870                 goto cleanup;
 871         }
 872
 873         if (!count)
 874                 goto cleanup;
 875
 876         if (info->params.mode == MGSL_MODE_RAW ||
 877             info->params.mode == MGSL_MODE_MONOSYNC ||
 878             info->params.mode == MGSL_MODE_BISYNC) {
 879                 unsigned int bufs_needed = (count/DMABUFSIZE);
 880                 unsigned int bufs_free = free_tbuf_count(info);
 881                 if (count % DMABUFSIZE)
 882                         ++bufs_needed;
 883                 if (bufs_needed > bufs_free)
 884                         goto cleanup;
 885         } else {
 886                 if (info->tx_active)
 887                         goto cleanup;
 888                 if (info->tx_count) {
 889                         /* send accumulated data from send_char() calls */
 890                         /* as frame and wait before accepting more data. */
 891                         tx_load(info, info->tx_buf, info->tx_count);
 892                         goto start;
 893                 }
 894         }
 895
 896         ret = info->tx_count = count;
 897         tx_load(info, buf, count);
 898         goto start;
 899
 900 start:
 901         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
 902                 spin_lock_irqsave(&info->lock,flags);
 903                 if (!info->tx_active)
 904                         tx_start(info);
 905                 else
 906                         tdma_start(info);
 907                 spin_unlock_irqrestore(&info->lock,flags);
 908         }
 909
 910 cleanup:
 911         DBGINFO(("%s write rc=%d\n", info->device_name, ret));
 912         return ret;
 913 }
 914
 915 static int put_char(struct tty_struct *tty, unsigned char ch)
 916 {
 917         struct slgt_info *info = tty->driver_data;
 918         unsigned long flags;
 919         int ret;
 920
 921         if (sanity_check(info, tty->name, "put_char"))
 922                 return 0;
 923         DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
 924         if (!info->tx_buf)
 925                 return 0;
 926         spin_lock_irqsave(&info->lock,flags);
 927         if (!info->tx_active && (info->tx_count < info->max_frame_size)) {
 928                 info->tx_buf[info->tx_count++] = ch;
 929                 ret = 1;
 930         }
 931         spin_unlock_irqrestore(&info->lock,flags);
 932         return ret;
 933 }
 934
 935 static void send_xchar(struct tty_struct *tty, char ch)
 936 {
 937         struct slgt_info *info = tty->driver_data;
 938         unsigned long flags;
 939
 940         if (sanity_check(info, tty->name, "send_xchar"))
 941                 return;
 942         DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
 943         info->x_char = ch;
 944         if (ch) {
 945                 spin_lock_irqsave(&info->lock,flags);
 946                 if (!info->tx_enabled)
 947                         tx_start(info);
 948                 spin_unlock_irqrestore(&info->lock,flags);
 949         }
 950 }
 951
 952 static void wait_until_sent(struct tty_struct *tty, int timeout)
 953 {
 954         struct slgt_info *info = tty->driver_data;
 955         unsigned long orig_jiffies, char_time;
 956
 957         if (!info )
 958                 return;
 959         if (sanity_check(info, tty->name, "wait_until_sent"))
 960                 return;
 961         DBGINFO(("%s wait_until_sent entry\n", info->device_name));
 962         if (!(info->flags & ASYNC_INITIALIZED))
 963                 goto exit;
 964
 965         orig_jiffies = jiffies;
 966
 967         /* Set check interval to 1/5 of estimated time to
 968          * send a character, and make it at least 1. The check
 969          * interval should also be less than the timeout.
 970          * Note: use tight timings here to satisfy the NIST-PCTS.
 971          */
 972
 973         lock_kernel();
 974
 975         if (info->params.data_rate) {
 976                 char_time = info->timeout/(32 * 5);
 977                 if (!char_time)
 978                         char_time++;
 979         } else
 980                 char_time = 1;
 981
 982         if (timeout)
 983                 char_time = min_t(unsigned long, char_time, timeout);
 984
 985         while (info->tx_active) {
 986                 msleep_interruptible(jiffies_to_msecs(char_time));
 987                 if (signal_pending(current))
 988                         break;
 989                 if (timeout && time_after(jiffies, orig_jiffies + timeout))
 990                         break;
 991         }
 992         unlock_kernel();
 993
 994 exit:
 995         DBGINFO(("%s wait_until_sent exit\n", info->device_name));
 996 }
 997
 998 static int write_room(struct tty_struct *tty)
 999 {
1000         struct slgt_info *info = tty->driver_data;
1001         int ret;
1002
1003         if (sanity_check(info, tty->name, "write_room"))
1004                 return 0;
1005         ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1006         DBGINFO(("%s write_room=%d\n", info->device_name, ret));
1007         return ret;
1008 }
1009
1010 static void flush_chars(struct tty_struct *tty)
1011 {
1012         struct slgt_info *info = tty->driver_data;
1013         unsigned long flags;
1014
1015         if (sanity_check(info, tty->name, "flush_chars"))
1016                 return;
1017         DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
1018
1019         if (info->tx_count <= 0 || tty->stopped ||
1020             tty->hw_stopped || !info->tx_buf)
1021                 return;
1022
1023         DBGINFO(("%s flush_chars start transmit\n", info->device_name));
1024
1025         spin_lock_irqsave(&info->lock,flags);
1026         if (!info->tx_active && info->tx_count) {
1027                 tx_load(info, info->tx_buf,info->tx_count);
1028                 tx_start(info);
1029         }
1030         spin_unlock_irqrestore(&info->lock,flags);
1031 }
1032
1033 static void flush_buffer(struct tty_struct *tty)
1034 {
1035         struct slgt_info *info = tty->driver_data;
1036         unsigned long flags;
1037
1038         if (sanity_check(info, tty->name, "flush_buffer"))
1039                 return;
1040         DBGINFO(("%s flush_buffer\n", info->device_name));
1041
1042         spin_lock_irqsave(&info->lock,flags);
1043         if (!info->tx_active)
1044                 info->tx_count = 0;
1045         spin_unlock_irqrestore(&info->lock,flags);
1046
1047         tty_wakeup(tty);
1048 }
1049
1050 /*
1051  * throttle (stop) transmitter
1052  */
1053 static void tx_hold(struct tty_struct *tty)
1054 {
1055         struct slgt_info *info = tty->driver_data;
1056         unsigned long flags;
1057
1058         if (sanity_check(info, tty->name, "tx_hold"))
1059                 return;
1060         DBGINFO(("%s tx_hold\n", info->device_name));
1061         spin_lock_irqsave(&info->lock,flags);
1062         if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1063                 tx_stop(info);
1064         spin_unlock_irqrestore(&info->lock,flags);
1065 }
1066
1067 /*
1068  * release (start) transmitter
1069  */
1070 static void tx_release(struct tty_struct *tty)
1071 {
1072         struct slgt_info *info = tty->driver_data;
1073         unsigned long flags;
1074
1075         if (sanity_check(info, tty->name, "tx_release"))
1076                 return;
1077         DBGINFO(("%s tx_release\n", info->device_name));
1078         spin_lock_irqsave(&info->lock,flags);
1079         if (!info->tx_active && info->tx_count) {
1080                 tx_load(info, info->tx_buf, info->tx_count);
1081                 tx_start(info);
1082         }
1083         spin_unlock_irqrestore(&info->lock,flags);
1084 }
1085
1086 /*
1087  * Service an IOCTL request
1088  *
1089  * Arguments
1090  *
1091  *      tty     pointer to tty instance data
1092  *      file    pointer to associated file object for device
1093  *      cmd     IOCTL command code
1094  *      arg     command argument/context
1095  *
1096  * Return 0 if success, otherwise error code
1097  */
1098 static int ioctl(struct tty_struct *tty, struct file *file,
1099                  unsigned int cmd, unsigned long arg)
1100 {
1101         struct slgt_info *info = tty->driver_data;
1102         struct mgsl_icount cnow;        /* kernel counter temps */
1103         struct serial_icounter_struct __user *p_cuser;  /* user space */
1104         unsigned long flags;
1105         void __user *argp = (void __user *)arg;
1106         int ret;
1107
1108         if (sanity_check(info, tty->name, "ioctl"))
1109                 return -ENODEV;
1110         DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1111
1112         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1113             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1114                 if (tty->flags & (1 << TTY_IO_ERROR))
1115                     return -EIO;
1116         }
1117
1118         lock_kernel();
1119
1120         switch (cmd) {
1121         case MGSL_IOCGPARAMS:
1122                 ret = get_params(info, argp);
1123                 break;
1124         case MGSL_IOCSPARAMS:
1125                 ret = set_params(info, argp);
1126                 break;
1127         case MGSL_IOCGTXIDLE:
1128                 ret = get_txidle(info, argp);
1129                 break;
1130         case MGSL_IOCSTXIDLE:
1131                 ret = set_txidle(info, (int)arg);
1132                 break;
1133         case MGSL_IOCTXENABLE:
1134                 ret = tx_enable(info, (int)arg);
1135                 break;
1136         case MGSL_IOCRXENABLE:
1137                 ret = rx_enable(info, (int)arg);
1138                 break;
1139         case MGSL_IOCTXABORT:
1140                 ret = tx_abort(info);
1141                 break;
1142         case MGSL_IOCGSTATS:
1143                 ret = get_stats(info, argp);
1144                 break;
1145         case MGSL_IOCWAITEVENT:
1146                 ret = wait_mgsl_event(info, argp);
1147                 break;
1148         case TIOCMIWAIT:
1149                 ret = modem_input_wait(info,(int)arg);
1150                 break;
1151         case MGSL_IOCGIF:
1152                 ret = get_interface(info, argp);
1153                 break;
1154         case MGSL_IOCSIF:
1155                 ret = set_interface(info,(int)arg);
1156                 break;
1157         case MGSL_IOCSGPIO:
1158                 ret = set_gpio(info, argp);
1159                 break;
1160         case MGSL_IOCGGPIO:
1161                 ret = get_gpio(info, argp);
1162                 break;
1163         case MGSL_IOCWAITGPIO:
1164                 ret = wait_gpio(info, argp);
1165                 break;
1166         case TIOCGICOUNT:
1167                 spin_lock_irqsave(&info->lock,flags);
1168                 cnow = info->icount;
1169                 spin_unlock_irqrestore(&info->lock,flags);
1170                 p_cuser = argp;
1171                 if (put_user(cnow.cts, &p_cuser->cts) ||
1172                     put_user(cnow.dsr, &p_cuser->dsr) ||
1173                     put_user(cnow.rng, &p_cuser->rng) ||
1174                     put_user(cnow.dcd, &p_cuser->dcd) ||
1175                     put_user(cnow.rx, &p_cuser->rx) ||
1176                     put_user(cnow.tx, &p_cuser->tx) ||
1177                     put_user(cnow.frame, &p_cuser->frame) ||
1178                     put_user(cnow.overrun, &p_cuser->overrun) ||
1179                     put_user(cnow.parity, &p_cuser->parity) ||
1180                     put_user(cnow.brk, &p_cuser->brk) ||
1181                     put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1182                         ret = -EFAULT;
1183                 ret = 0;
1184                 break;
1185         default:
1186                 ret = -ENOIOCTLCMD;
1187         }
1188         unlock_kernel();
1189         return ret;
1190 }
1191
1192 /*
1193  * support for 32 bit ioctl calls on 64 bit systems
1194  */
1195 #ifdef CONFIG_COMPAT
1196 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1197 {
1198         struct MGSL_PARAMS32 tmp_params;
1199
1200         DBGINFO(("%s get_params32\n", info->device_name));
1201         tmp_params.mode            = (compat_ulong_t)info->params.mode;
1202         tmp_params.loopback        = info->params.loopback;
1203         tmp_params.flags           = info->params.flags;
1204         tmp_params.encoding        = info->params.encoding;
1205         tmp_params.clock_speed     = (compat_ulong_t)info->params.clock_speed;
1206         tmp_params.addr_filter     = info->params.addr_filter;
1207         tmp_params.crc_type        = info->params.crc_type;
1208         tmp_params.preamble_length = info->params.preamble_length;
1209         tmp_params.preamble        = info->params.preamble;
1210         tmp_params.data_rate       = (compat_ulong_t)info->params.data_rate;
1211         tmp_params.data_bits       = info->params.data_bits;
1212         tmp_params.stop_bits       = info->params.stop_bits;
1213         tmp_params.parity          = info->params.parity;
1214         if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1215                 return -EFAULT;
1216         return 0;
1217 }
1218
1219 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1220 {
1221         struct MGSL_PARAMS32 tmp_params;
1222
1223         DBGINFO(("%s set_params32\n", info->device_name));
1224         if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1225                 return -EFAULT;
1226
1227         spin_lock(&info->lock);
1228         info->params.mode            = tmp_params.mode;
1229         info->params.loopback        = tmp_params.loopback;
1230         info->params.flags           = tmp_params.flags;
1231         info->params.encoding        = tmp_params.encoding;
1232         info->params.clock_speed     = tmp_params.clock_speed;
1233         info->params.addr_filter     = tmp_params.addr_filter;
1234         info->params.crc_type        = tmp_params.crc_type;
1235         info->params.preamble_length = tmp_params.preamble_length;
1236         info->params.preamble        = tmp_params.preamble;
1237         info->params.data_rate       = tmp_params.data_rate;
1238         info->params.data_bits       = tmp_params.data_bits;
1239         info->params.stop_bits       = tmp_params.stop_bits;
1240         info->params.parity          = tmp_params.parity;
1241         spin_unlock(&info->lock);
1242
1243         change_params(info);
1244
1245         return 0;
1246 }
1247
1248 static long slgt_compat_ioctl(struct tty_struct *tty, struct file *file,
1249                          unsigned int cmd, unsigned long arg)
1250 {
1251         struct slgt_info *info = tty->driver_data;
1252         int rc = -ENOIOCTLCMD;
1253
1254         if (sanity_check(info, tty->name, "compat_ioctl"))
1255                 return -ENODEV;
1256         DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1257
1258         switch (cmd) {
1259
1260         case MGSL_IOCSPARAMS32:
1261                 rc = set_params32(info, compat_ptr(arg));
1262                 break;
1263
1264         case MGSL_IOCGPARAMS32:
1265                 rc = get_params32(info, compat_ptr(arg));
1266                 break;
1267
1268         case MGSL_IOCGPARAMS:
1269         case MGSL_IOCSPARAMS:
1270         case MGSL_IOCGTXIDLE:
1271         case MGSL_IOCGSTATS:
1272         case MGSL_IOCWAITEVENT:
1273         case MGSL_IOCGIF:
1274         case MGSL_IOCSGPIO:
1275         case MGSL_IOCGGPIO:
1276         case MGSL_IOCWAITGPIO:
1277         case TIOCGICOUNT:
1278                 rc = ioctl(tty, file, cmd, (unsigned long)(compat_ptr(arg)));
1279                 break;
1280
1281         case MGSL_IOCSTXIDLE:
1282         case MGSL_IOCTXENABLE:
1283         case MGSL_IOCRXENABLE:
1284         case MGSL_IOCTXABORT:
1285         case TIOCMIWAIT:
1286         case MGSL_IOCSIF:
1287                 rc = ioctl(tty, file, cmd, arg);
1288                 break;
1289         }
1290
1291         DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1292         return rc;
1293 }
1294 #else
1295 #define slgt_compat_ioctl NULL
1296 #endif /* ifdef CONFIG_COMPAT */
1297
1298 /*
1299  * proc fs support
1300  */
1301 static inline int line_info(char *buf, struct slgt_info *info)
1302 {
1303         char stat_buf[30];
1304         int ret;
1305         unsigned long flags;
1306
1307         ret = sprintf(buf, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1308                       info->device_name, info->phys_reg_addr,
1309                       info->irq_level, info->max_frame_size);
1310
1311         /* output current serial signal states */
1312         spin_lock_irqsave(&info->lock,flags);
1313         get_signals(info);
1314         spin_unlock_irqrestore(&info->lock,flags);
1315
1316         stat_buf[0] = 0;
1317         stat_buf[1] = 0;
1318         if (info->signals & SerialSignal_RTS)
1319                 strcat(stat_buf, "|RTS");
1320         if (info->signals & SerialSignal_CTS)
1321                 strcat(stat_buf, "|CTS");
1322         if (info->signals & SerialSignal_DTR)
1323                 strcat(stat_buf, "|DTR");
1324         if (info->signals & SerialSignal_DSR)
1325                 strcat(stat_buf, "|DSR");
1326         if (info->signals & SerialSignal_DCD)
1327                 strcat(stat_buf, "|CD");
1328         if (info->signals & SerialSignal_RI)
1329                 strcat(stat_buf, "|RI");
1330
1331         if (info->params.mode != MGSL_MODE_ASYNC) {
1332                 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1333                                info->icount.txok, info->icount.rxok);
1334                 if (info->icount.txunder)
1335                         ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1336                 if (info->icount.txabort)
1337                         ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1338                 if (info->icount.rxshort)
1339                         ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1340                 if (info->icount.rxlong)
1341                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1342                 if (info->icount.rxover)
1343                         ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1344                 if (info->icount.rxcrc)
1345                         ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
1346         } else {
1347                 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1348                                info->icount.tx, info->icount.rx);
1349                 if (info->icount.frame)
1350                         ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1351                 if (info->icount.parity)
1352                         ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1353                 if (info->icount.brk)
1354                         ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1355                 if (info->icount.overrun)
1356                         ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1357         }
1358
1359         /* Append serial signal status to end */
1360         ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1361
1362         ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1363                        info->tx_active,info->bh_requested,info->bh_running,
1364                        info->pending_bh);
1365
1366         return ret;
1367 }
1368
1369 /* Called to print information about devices
1370  */
1371 static int read_proc(char *page, char **start, off_t off, int count,
1372                      int *eof, void *data)
1373 {
1374         int len = 0, l;
1375         off_t   begin = 0;
1376         struct slgt_info *info;
1377
1378         len += sprintf(page, "synclink_gt driver:%s\n", driver_version);
1379
1380         info = slgt_device_list;
1381         while( info ) {
1382                 l = line_info(page + len, info);
1383                 len += l;
1384                 if (len+begin > off+count)
1385                         goto done;
1386                 if (len+begin < off) {
1387                         begin += len;
1388                         len = 0;
1389                 }
1390                 info = info->next_device;
1391         }
1392
1393         *eof = 1;
1394 done:
1395         if (off >= len+begin)
1396                 return 0;
1397         *start = page + (off-begin);
1398         return ((count < begin+len-off) ? count : begin+len-off);
1399 }
1400
1401 /*
1402  * return count of bytes in transmit buffer
1403  */
1404 static int chars_in_buffer(struct tty_struct *tty)
1405 {
1406         struct slgt_info *info = tty->driver_data;
1407         if (sanity_check(info, tty->name, "chars_in_buffer"))
1408                 return 0;
1409         DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, info->tx_count));
1410         return info->tx_count;
1411 }
1412
1413 /*
1414  * signal remote device to throttle send data (our receive data)
1415  */
1416 static void throttle(struct tty_struct * tty)
1417 {
1418         struct slgt_info *info = tty->driver_data;
1419         unsigned long flags;
1420
1421         if (sanity_check(info, tty->name, "throttle"))
1422                 return;
1423         DBGINFO(("%s throttle\n", info->device_name));
1424         if (I_IXOFF(tty))
1425                 send_xchar(tty, STOP_CHAR(tty));
1426         if (tty->termios->c_cflag & CRTSCTS) {
1427                 spin_lock_irqsave(&info->lock,flags);
1428                 info->signals &= ~SerialSignal_RTS;
1429                 set_signals(info);
1430                 spin_unlock_irqrestore(&info->lock,flags);
1431         }
1432 }
1433
1434 /*
1435  * signal remote device to stop throttling send data (our receive data)
1436  */
1437 static void unthrottle(struct tty_struct * tty)
1438 {
1439         struct slgt_info *info = tty->driver_data;
1440         unsigned long flags;
1441
1442         if (sanity_check(info, tty->name, "unthrottle"))
1443                 return;
1444         DBGINFO(("%s unthrottle\n", info->device_name));
1445         if (I_IXOFF(tty)) {
1446                 if (info->x_char)
1447                         info->x_char = 0;
1448                 else
1449                         send_xchar(tty, START_CHAR(tty));
1450         }
1451         if (tty->termios->c_cflag & CRTSCTS) {
1452                 spin_lock_irqsave(&info->lock,flags);
1453                 info->signals |= SerialSignal_RTS;
1454                 set_signals(info);
1455                 spin_unlock_irqrestore(&info->lock,flags);
1456         }
1457 }
1458
1459 /*
1460  * set or clear transmit break condition
1461  * break_state  -1=set break condition, 0=clear
1462  */
1463 static void set_break(struct tty_struct *tty, int break_state)
1464 {
1465         struct slgt_info *info = tty->driver_data;
1466         unsigned short value;
1467         unsigned long flags;
1468
1469         if (sanity_check(info, tty->name, "set_break"))
1470                 return;
1471         DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1472
1473         spin_lock_irqsave(&info->lock,flags);
1474         value = rd_reg16(info, TCR);
1475         if (break_state == -1)
1476                 value |= BIT6;
1477         else
1478                 value &= ~BIT6;
1479         wr_reg16(info, TCR, value);
1480         spin_unlock_irqrestore(&info->lock,flags);
1481 }
1482
1483 #if SYNCLINK_GENERIC_HDLC
1484
1485 /**
1486  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1487  * set encoding and frame check sequence (FCS) options
1488  *
1489  * dev       pointer to network device structure
1490  * encoding  serial encoding setting
1491  * parity    FCS setting
1492  *
1493  * returns 0 if success, otherwise error code
1494  */
1495 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1496                           unsigned short parity)
1497 {
1498         struct slgt_info *info = dev_to_port(dev);
1499         unsigned char  new_encoding;
1500         unsigned short new_crctype;
1501
1502         /* return error if TTY interface open */
1503         if (info->count)
1504                 return -EBUSY;
1505
1506         DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1507
1508         switch (encoding)
1509         {
1510         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1511         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1512         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1513         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1514         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1515         default: return -EINVAL;
1516         }
1517
1518         switch (parity)
1519         {
1520         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1521         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1522         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1523         default: return -EINVAL;
1524         }
1525
1526         info->params.encoding = new_encoding;
1527         info->params.crc_type = new_crctype;
1528
1529         /* if network interface up, reprogram hardware */
1530         if (info->netcount)
1531                 program_hw(info);
1532
1533         return 0;
1534 }
1535
1536 /**
1537  * called by generic HDLC layer to send frame
1538  *
1539  * skb  socket buffer containing HDLC frame
1540  * dev  pointer to network device structure
1541  *
1542  * returns 0 if success, otherwise error code
1543  */
1544 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1545 {
1546         struct slgt_info *info = dev_to_port(dev);
1547         struct net_device_stats *stats = hdlc_stats(dev);
1548         unsigned long flags;
1549
1550         DBGINFO(("%s hdlc_xmit\n", dev->name));
1551
1552         /* stop sending until this frame completes */
1553         netif_stop_queue(dev);
1554
1555         /* copy data to device buffers */
1556         info->tx_count = skb->len;
1557         tx_load(info, skb->data, skb->len);
1558
1559         /* update network statistics */
1560         stats->tx_packets++;
1561         stats->tx_bytes += skb->len;
1562
1563         /* done with socket buffer, so free it */
1564         dev_kfree_skb(skb);
1565
1566         /* save start time for transmit timeout detection */
1567         dev->trans_start = jiffies;
1568
1569         /* start hardware transmitter if necessary */
1570         spin_lock_irqsave(&info->lock,flags);
1571         if (!info->tx_active)
1572                 tx_start(info);
1573         spin_unlock_irqrestore(&info->lock,flags);
1574
1575         return 0;
1576 }
1577
1578 /**
1579  * called by network layer when interface enabled
1580  * claim resources and initialize hardware
1581  *
1582  * dev  pointer to network device structure
1583  *
1584  * returns 0 if success, otherwise error code
1585  */
1586 static int hdlcdev_open(struct net_device *dev)
1587 {
1588         struct slgt_info *info = dev_to_port(dev);
1589         int rc;
1590         unsigned long flags;
1591
1592         if (!try_module_get(THIS_MODULE))
1593                 return -EBUSY;
1594
1595         DBGINFO(("%s hdlcdev_open\n", dev->name));
1596
1597         /* generic HDLC layer open processing */
1598         if ((rc = hdlc_open(dev)))
1599                 return rc;
1600
1601         /* arbitrate between network and tty opens */
1602         spin_lock_irqsave(&info->netlock, flags);
1603         if (info->count != 0 || info->netcount != 0) {
1604                 DBGINFO(("%s hdlc_open busy\n", dev->name));
1605                 spin_unlock_irqrestore(&info->netlock, flags);
1606                 return -EBUSY;
1607         }
1608         info->netcount=1;
1609         spin_unlock_irqrestore(&info->netlock, flags);
1610
1611         /* claim resources and init adapter */
1612         if ((rc = startup(info)) != 0) {
1613                 spin_lock_irqsave(&info->netlock, flags);
1614                 info->netcount=0;
1615                 spin_unlock_irqrestore(&info->netlock, flags);
1616                 return rc;
1617         }
1618
1619         /* assert DTR and RTS, apply hardware settings */
1620         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1621         program_hw(info);
1622
1623         /* enable network layer transmit */
1624         dev->trans_start = jiffies;
1625         netif_start_queue(dev);
1626
1627         /* inform generic HDLC layer of current DCD status */
1628         spin_lock_irqsave(&info->lock, flags);
1629         get_signals(info);
1630         spin_unlock_irqrestore(&info->lock, flags);
1631         if (info->signals & SerialSignal_DCD)
1632                 netif_carrier_on(dev);
1633         else
1634                 netif_carrier_off(dev);
1635         return 0;
1636 }
1637
1638 /**
1639  * called by network layer when interface is disabled
1640  * shutdown hardware and release resources
1641  *
1642  * dev  pointer to network device structure
1643  *
1644  * returns 0 if success, otherwise error code
1645  */
1646 static int hdlcdev_close(struct net_device *dev)
1647 {
1648         struct slgt_info *info = dev_to_port(dev);
1649         unsigned long flags;
1650
1651         DBGINFO(("%s hdlcdev_close\n", dev->name));
1652
1653         netif_stop_queue(dev);
1654
1655         /* shutdown adapter and release resources */
1656         shutdown(info);
1657
1658         hdlc_close(dev);
1659
1660         spin_lock_irqsave(&info->netlock, flags);
1661         info->netcount=0;
1662         spin_unlock_irqrestore(&info->netlock, flags);
1663
1664         module_put(THIS_MODULE);
1665         return 0;
1666 }
1667
1668 /**
1669  * called by network layer to process IOCTL call to network device
1670  *
1671  * dev  pointer to network device structure
1672  * ifr  pointer to network interface request structure
1673  * cmd  IOCTL command code
1674  *
1675  * returns 0 if success, otherwise error code
1676  */
1677 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1678 {
1679         const size_t size = sizeof(sync_serial_settings);
1680         sync_serial_settings new_line;
1681         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1682         struct slgt_info *info = dev_to_port(dev);
1683         unsigned int flags;
1684
1685         DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1686
1687         /* return error if TTY interface open */
1688         if (info->count)
1689                 return -EBUSY;
1690
1691         if (cmd != SIOCWANDEV)
1692                 return hdlc_ioctl(dev, ifr, cmd);
1693
1694         switch(ifr->ifr_settings.type) {
1695         case IF_GET_IFACE: /* return current sync_serial_settings */
1696
1697                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1698                 if (ifr->ifr_settings.size < size) {
1699                         ifr->ifr_settings.size = size; /* data size wanted */
1700                         return -ENOBUFS;
1701                 }
1702
1703                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1704                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1705                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1706                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1707
1708                 switch (flags){
1709                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1710                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1711                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1712                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1713                 default: new_line.clock_type = CLOCK_DEFAULT;
1714                 }
1715
1716                 new_line.clock_rate = info->params.clock_speed;
1717                 new_line.loopback   = info->params.loopback ? 1:0;
1718
1719                 if (copy_to_user(line, &new_line, size))
1720                         return -EFAULT;
1721                 return 0;
1722
1723         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1724
1725                 if(!capable(CAP_NET_ADMIN))
1726                         return -EPERM;
1727                 if (copy_from_user(&new_line, line, size))
1728                         return -EFAULT;
1729
1730                 switch (new_line.clock_type)
1731                 {
1732                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1733                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1734                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1735                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1736                 case CLOCK_DEFAULT:  flags = info->params.flags &
1737                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1738                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1739                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1740                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1741                 default: return -EINVAL;
1742                 }
1743
1744                 if (new_line.loopback != 0 && new_line.loopback != 1)
1745                         return -EINVAL;
1746
1747                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1748                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1749                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1750                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1751                 info->params.flags |= flags;
1752
1753                 info->params.loopback = new_line.loopback;
1754
1755                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1756                         info->params.clock_speed = new_line.clock_rate;
1757                 else
1758                         info->params.clock_speed = 0;
1759
1760                 /* if network interface up, reprogram hardware */
1761                 if (info->netcount)
1762                         program_hw(info);
1763                 return 0;
1764
1765         default:
1766                 return hdlc_ioctl(dev, ifr, cmd);
1767         }
1768 }
1769
1770 /**
1771  * called by network layer when transmit timeout is detected
1772  *
1773  * dev  pointer to network device structure
1774  */
1775 static void hdlcdev_tx_timeout(struct net_device *dev)
1776 {
1777         struct slgt_info *info = dev_to_port(dev);
1778         struct net_device_stats *stats = hdlc_stats(dev);
1779         unsigned long flags;
1780
1781         DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1782
1783         stats->tx_errors++;
1784         stats->tx_aborted_errors++;
1785
1786         spin_lock_irqsave(&info->lock,flags);
1787         tx_stop(info);
1788         spin_unlock_irqrestore(&info->lock,flags);
1789
1790         netif_wake_queue(dev);
1791 }
1792
1793 /**
1794  * called by device driver when transmit completes
1795  * reenable network layer transmit if stopped
1796  *
1797  * info  pointer to device instance information
1798  */
1799 static void hdlcdev_tx_done(struct slgt_info *info)
1800 {
1801         if (netif_queue_stopped(info->netdev))
1802                 netif_wake_queue(info->netdev);
1803 }
1804
1805 /**
1806  * called by device driver when frame received
1807  * pass frame to network layer
1808  *
1809  * info  pointer to device instance information
1810  * buf   pointer to buffer contianing frame data
1811  * size  count of data bytes in buf
1812  */
1813 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1814 {
1815         struct sk_buff *skb = dev_alloc_skb(size);
1816         struct net_device *dev = info->netdev;
1817         struct net_device_stats *stats = hdlc_stats(dev);
1818
1819         DBGINFO(("%s hdlcdev_rx\n", dev->name));
1820
1821         if (skb == NULL) {
1822                 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1823                 stats->rx_dropped++;
1824                 return;
1825         }
1826
1827         memcpy(skb_put(skb, size),buf,size);
1828
1829         skb->protocol = hdlc_type_trans(skb, info->netdev);
1830
1831         stats->rx_packets++;
1832         stats->rx_bytes += size;
1833
1834         netif_rx(skb);
1835
1836         info->netdev->last_rx = jiffies;
1837 }
1838
1839 /**
1840  * called by device driver when adding device instance
1841  * do generic HDLC initialization
1842  *
1843  * info  pointer to device instance information
1844  *
1845  * returns 0 if success, otherwise error code
1846  */
1847 static int hdlcdev_init(struct slgt_info *info)
1848 {
1849         int rc;
1850         struct net_device *dev;
1851         hdlc_device *hdlc;
1852
1853         /* allocate and initialize network and HDLC layer objects */
1854
1855         if (!(dev = alloc_hdlcdev(info))) {
1856                 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1857                 return -ENOMEM;
1858         }
1859
1860         /* for network layer reporting purposes only */
1861         dev->mem_start = info->phys_reg_addr;
1862         dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1863         dev->irq       = info->irq_level;
1864
1865         /* network layer callbacks and settings */
1866         dev->do_ioctl       = hdlcdev_ioctl;
1867         dev->open           = hdlcdev_open;
1868         dev->stop           = hdlcdev_close;
1869         dev->tx_timeout     = hdlcdev_tx_timeout;
1870         dev->watchdog_timeo = 10*HZ;
1871         dev->tx_queue_len   = 50;
1872
1873         /* generic HDLC layer callbacks and settings */
1874         hdlc         = dev_to_hdlc(dev);
1875         hdlc->attach = hdlcdev_attach;
1876         hdlc->xmit   = hdlcdev_xmit;
1877
1878         /* register objects with HDLC layer */
1879         if ((rc = register_hdlc_device(dev))) {
1880                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1881                 free_netdev(dev);
1882                 return rc;
1883         }
1884
1885         info->netdev = dev;
1886         return 0;
1887 }
1888
1889 /**
1890  * called by device driver when removing device instance
1891  * do generic HDLC cleanup
1892  *
1893  * info  pointer to device instance information
1894  */
1895 static void hdlcdev_exit(struct slgt_info *info)
1896 {
1897         unregister_hdlc_device(info->netdev);
1898         free_netdev(info->netdev);
1899         info->netdev = NULL;
1900 }
1901
1902 #endif /* ifdef CONFIG_HDLC */
1903
1904 /*
1905  * get async data from rx DMA buffers
1906  */
1907 static void rx_async(struct slgt_info *info)
1908 {
1909         struct tty_struct *tty = info->tty;
1910         struct mgsl_icount *icount = &info->icount;
1911         unsigned int start, end;
1912         unsigned char *p;
1913         unsigned char status;
1914         struct slgt_desc *bufs = info->rbufs;
1915         int i, count;
1916         int chars = 0;
1917         int stat;
1918         unsigned char ch;
1919
1920         start = end = info->rbuf_current;
1921
1922         while(desc_complete(bufs[end])) {
1923                 count = desc_count(bufs[end]) - info->rbuf_index;
1924                 p     = bufs[end].buf + info->rbuf_index;
1925
1926                 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1927                 DBGDATA(info, p, count, "rx");
1928
1929                 for(i=0 ; i < count; i+=2, p+=2) {
1930                         ch = *p;
1931                         icount->rx++;
1932
1933                         stat = 0;
1934
1935                         if ((status = *(p+1) & (BIT1 + BIT0))) {
1936                                 if (status & BIT1)
1937                                         icount->parity++;
1938                                 else if (status & BIT0)
1939                                         icount->frame++;
1940                                 /* discard char if tty control flags say so */
1941                                 if (status & info->ignore_status_mask)
1942                                         continue;
1943                                 if (status & BIT1)
1944                                         stat = TTY_PARITY;
1945                                 else if (status & BIT0)
1946                                         stat = TTY_FRAME;
1947                         }
1948                         if (tty) {
1949                                 tty_insert_flip_char(tty, ch, stat);
1950                                 chars++;
1951                         }
1952                 }
1953
1954                 if (i < count) {
1955                         /* receive buffer not completed */
1956                         info->rbuf_index += i;
1957                         mod_timer(&info->rx_timer, jiffies + 1);
1958                         break;
1959                 }
1960
1961                 info->rbuf_index = 0;
1962                 free_rbufs(info, end, end);
1963
1964                 if (++end == info->rbuf_count)
1965                         end = 0;
1966
1967                 /* if entire list searched then no frame available */
1968                 if (end == start)
1969                         break;
1970         }
1971
1972         if (tty && chars)
1973                 tty_flip_buffer_push(tty);
1974 }
1975
1976 /*
1977  * return next bottom half action to perform
1978  */
1979 static int bh_action(struct slgt_info *info)
1980 {
1981         unsigned long flags;
1982         int rc;
1983
1984         spin_lock_irqsave(&info->lock,flags);
1985
1986         if (info->pending_bh & BH_RECEIVE) {
1987                 info->pending_bh &= ~BH_RECEIVE;
1988                 rc = BH_RECEIVE;
1989         } else if (info->pending_bh & BH_TRANSMIT) {
1990                 info->pending_bh &= ~BH_TRANSMIT;
1991                 rc = BH_TRANSMIT;
1992         } else if (info->pending_bh & BH_STATUS) {
1993                 info->pending_bh &= ~BH_STATUS;
1994                 rc = BH_STATUS;
1995         } else {
1996                 /* Mark BH routine as complete */
1997                 info->bh_running = false;
1998                 info->bh_requested = false;
1999                 rc = 0;
2000         }
2001
2002         spin_unlock_irqrestore(&info->lock,flags);
2003
2004         return rc;
2005 }
2006
2007 /*
2008  * perform bottom half processing
2009  */
2010 static void bh_handler(struct work_struct *work)
2011 {
2012         struct slgt_info *info = container_of(work, struct slgt_info, task);
2013         int action;
2014
2015         if (!info)
2016                 return;
2017         info->bh_running = true;
2018
2019         while((action = bh_action(info))) {
2020                 switch (action) {
2021                 case BH_RECEIVE:
2022                         DBGBH(("%s bh receive\n", info->device_name));
2023                         switch(info->params.mode) {
2024                         case MGSL_MODE_ASYNC:
2025                                 rx_async(info);
2026                                 break;
2027                         case MGSL_MODE_HDLC:
2028                                 while(rx_get_frame(info));
2029                                 break;
2030                         case MGSL_MODE_RAW:
2031                         case MGSL_MODE_MONOSYNC:
2032                         case MGSL_MODE_BISYNC:
2033                                 while(rx_get_buf(info));
2034                                 break;
2035                         }
2036                         /* restart receiver if rx DMA buffers exhausted */
2037                         if (info->rx_restart)
2038                                 rx_start(info);
2039                         break;
2040                 case BH_TRANSMIT:
2041                         bh_transmit(info);
2042                         break;
2043                 case BH_STATUS:
2044                         DBGBH(("%s bh status\n", info->device_name));
2045                         info->ri_chkcount = 0;
2046                         info->dsr_chkcount = 0;
2047                         info->dcd_chkcount = 0;
2048                         info->cts_chkcount = 0;
2049                         break;
2050                 default:
2051                         DBGBH(("%s unknown action\n", info->device_name));
2052                         break;
2053                 }
2054         }
2055         DBGBH(("%s bh_handler exit\n", info->device_name));
2056 }
2057
2058 static void bh_transmit(struct slgt_info *info)
2059 {
2060         struct tty_struct *tty = info->tty;
2061
2062         DBGBH(("%s bh_transmit\n", info->device_name));
2063         if (tty)
2064                 tty_wakeup(tty);
2065 }
2066
2067 static void dsr_change(struct slgt_info *info, unsigned short status)
2068 {
2069         if (status & BIT3) {
2070                 info->signals |= SerialSignal_DSR;
2071                 info->input_signal_events.dsr_up++;
2072         } else {
2073                 info->signals &= ~SerialSignal_DSR;
2074                 info->input_signal_events.dsr_down++;
2075         }
2076         DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2077         if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2078                 slgt_irq_off(info, IRQ_DSR);
2079                 return;
2080         }
2081         info->icount.dsr++;
2082         wake_up_interruptible(&info->status_event_wait_q);
2083         wake_up_interruptible(&info->event_wait_q);
2084         info->pending_bh |= BH_STATUS;
2085 }
2086
2087 static void cts_change(struct slgt_info *info, unsigned short status)
2088 {
2089         if (status & BIT2) {
2090                 info->signals |= SerialSignal_CTS;
2091                 info->input_signal_events.cts_up++;
2092         } else {
2093                 info->signals &= ~SerialSignal_CTS;
2094                 info->input_signal_events.cts_down++;
2095         }
2096         DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2097         if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2098                 slgt_irq_off(info, IRQ_CTS);
2099                 return;
2100         }
2101         info->icount.cts++;
2102         wake_up_interruptible(&info->status_event_wait_q);
2103         wake_up_interruptible(&info->event_wait_q);
2104         info->pending_bh |= BH_STATUS;
2105
2106         if (info->flags & ASYNC_CTS_FLOW) {
2107                 if (info->tty) {
2108                         if (info->tty->hw_stopped) {
2109                                 if (info->signals & SerialSignal_CTS) {
2110                                         info->tty->hw_stopped = 0;
2111                                         info->pending_bh |= BH_TRANSMIT;
2112                                         return;
2113                                 }
2114                         } else {
2115                                 if (!(info->signals & SerialSignal_CTS))
2116                                         info->tty->hw_stopped = 1;
2117                         }
2118                 }
2119         }
2120 }
2121
2122 static void dcd_change(struct slgt_info *info, unsigned short status)
2123 {
2124         if (status & BIT1) {
2125                 info->signals |= SerialSignal_DCD;
2126                 info->input_signal_events.dcd_up++;
2127         } else {
2128                 info->signals &= ~SerialSignal_DCD;
2129                 info->input_signal_events.dcd_down++;
2130         }
2131         DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2132         if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2133                 slgt_irq_off(info, IRQ_DCD);
2134                 return;
2135         }
2136         info->icount.dcd++;
2137 #if SYNCLINK_GENERIC_HDLC
2138         if (info->netcount) {
2139                 if (info->signals & SerialSignal_DCD)
2140                         netif_carrier_on(info->netdev);
2141                 else
2142                         netif_carrier_off(info->netdev);
2143         }
2144 #endif
2145         wake_up_interruptible(&info->status_event_wait_q);
2146         wake_up_interruptible(&info->event_wait_q);
2147         info->pending_bh |= BH_STATUS;
2148
2149         if (info->flags & ASYNC_CHECK_CD) {
2150                 if (info->signals & SerialSignal_DCD)
2151                         wake_up_interruptible(&info->open_wait);
2152                 else {
2153                         if (info->tty)
2154                                 tty_hangup(info->tty);
2155                 }
2156         }
2157 }
2158
2159 static void ri_change(struct slgt_info *info, unsigned short status)
2160 {
2161         if (status & BIT0) {
2162                 info->signals |= SerialSignal_RI;
2163                 info->input_signal_events.ri_up++;
2164         } else {
2165                 info->signals &= ~SerialSignal_RI;
2166                 info->input_signal_events.ri_down++;
2167         }
2168         DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2169         if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2170                 slgt_irq_off(info, IRQ_RI);
2171                 return;
2172         }
2173         info->icount.rng++;
2174         wake_up_interruptible(&info->status_event_wait_q);
2175         wake_up_interruptible(&info->event_wait_q);
2176         info->pending_bh |= BH_STATUS;
2177 }
2178
2179 static void isr_serial(struct slgt_info *info)
2180 {
2181         unsigned short status = rd_reg16(info, SSR);
2182
2183         DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2184
2185         wr_reg16(info, SSR, status); /* clear pending */
2186
2187         info->irq_occurred = true;
2188
2189         if (info->params.mode == MGSL_MODE_ASYNC) {
2190                 if (status & IRQ_TXIDLE) {
2191                         if (info->tx_count)
2192                                 isr_txeom(info, status);
2193                 }
2194                 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2195                         info->icount.brk++;
2196                         /* process break detection if tty control allows */
2197                         if (info->tty) {
2198                                 if (!(status & info->ignore_status_mask)) {
2199                                         if (info->read_status_mask & MASK_BREAK) {
2200                                                 tty_insert_flip_char(info->tty, 0, TTY_BREAK);
2201                                                 if (info->flags & ASYNC_SAK)
2202                                                         do_SAK(info->tty);
2203                                         }
2204                                 }
2205                         }
2206                 }
2207         } else {
2208                 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2209                         isr_txeom(info, status);
2210
2211                 if (status & IRQ_RXIDLE) {
2212                         if (status & RXIDLE)
2213                                 info->icount.rxidle++;
2214                         else
2215                                 info->icount.exithunt++;
2216                         wake_up_interruptible(&info->event_wait_q);
2217                 }
2218
2219                 if (status & IRQ_RXOVER)
2220                         rx_start(info);
2221         }
2222
2223         if (status & IRQ_DSR)
2224                 dsr_change(info, status);
2225         if (status & IRQ_CTS)
2226                 cts_change(info, status);
2227         if (status & IRQ_DCD)
2228                 dcd_change(info, status);
2229         if (status & IRQ_RI)
2230                 ri_change(info, status);
2231 }
2232
2233 static void isr_rdma(struct slgt_info *info)
2234 {
2235         unsigned int status = rd_reg32(info, RDCSR);
2236
2237         DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2238
2239         /* RDCSR (rx DMA control/status)
2240          *
2241          * 31..07  reserved
2242          * 06      save status byte to DMA buffer
2243          * 05      error
2244          * 04      eol (end of list)
2245          * 03      eob (end of buffer)
2246          * 02      IRQ enable
2247          * 01      reset
2248          * 00      enable
2249          */
2250         wr_reg32(info, RDCSR, status);  /* clear pending */
2251
2252         if (status & (BIT5 + BIT4)) {
2253                 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2254                 info->rx_restart = true;
2255         }
2256         info->pending_bh |= BH_RECEIVE;
2257 }
2258
2259 static void isr_tdma(struct slgt_info *info)
2260 {
2261         unsigned int status = rd_reg32(info, TDCSR);
2262
2263         DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2264
2265         /* TDCSR (tx DMA control/status)
2266          *
2267          * 31..06  reserved
2268          * 05      error
2269          * 04      eol (end of list)
2270          * 03      eob (end of buffer)
2271          * 02      IRQ enable
2272          * 01      reset
2273          * 00      enable
2274          */
2275         wr_reg32(info, TDCSR, status);  /* clear pending */
2276
2277         if (status & (BIT5 + BIT4 + BIT3)) {
2278                 // another transmit buffer has completed
2279                 // run bottom half to get more send data from user
2280                 info->pending_bh |= BH_TRANSMIT;
2281         }
2282 }
2283
2284 static void isr_txeom(struct slgt_info *info, unsigned short status)
2285 {
2286         DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2287
2288         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2289         tdma_reset(info);
2290         reset_tbufs(info);
2291         if (status & IRQ_TXUNDER) {
2292                 unsigned short val = rd_reg16(info, TCR);
2293                 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2294                 wr_reg16(info, TCR, val); /* clear reset bit */
2295         }
2296
2297         if (info->tx_active) {
2298                 if (info->params.mode != MGSL_MODE_ASYNC) {
2299                         if (status & IRQ_TXUNDER)
2300                                 info->icount.txunder++;
2301                         else if (status & IRQ_TXIDLE)
2302                                 info->icount.txok++;
2303                 }
2304
2305                 info->tx_active = false;
2306                 info->tx_count = 0;
2307
2308                 del_timer(&info->tx_timer);
2309
2310                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2311                         info->signals &= ~SerialSignal_RTS;
2312                         info->drop_rts_on_tx_done = false;
2313                         set_signals(info);
2314                 }
2315
2316 #if SYNCLINK_GENERIC_HDLC
2317                 if (info->netcount)
2318                         hdlcdev_tx_done(info);
2319                 else
2320 #endif
2321                 {
2322                         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2323                                 tx_stop(info);
2324                                 return;
2325                         }
2326                         info->pending_bh |= BH_TRANSMIT;
2327                 }
2328         }
2329 }
2330
2331 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2332 {
2333         struct cond_wait *w, *prev;
2334
2335         /* wake processes waiting for specific transitions */
2336         for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2337                 if (w->data & changed) {
2338                         w->data = state;
2339                         wake_up_interruptible(&w->q);
2340                         if (prev != NULL)
2341                                 prev->next = w->next;
2342                         else
2343                                 info->gpio_wait_q = w->next;
2344                 } else
2345                         prev = w;
2346         }
2347 }
2348
2349 /* interrupt service routine
2350  *
2351  *      irq     interrupt number
2352  *      dev_id  device ID supplied during interrupt registration
2353  */
2354 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2355 {
2356         struct slgt_info *info = dev_id;
2357         unsigned int gsr;
2358         unsigned int i;
2359
2360         DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2361
2362         spin_lock(&info->lock);
2363
2364         while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2365                 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2366                 info->irq_occurred = true;
2367                 for(i=0; i < info->port_count ; i++) {
2368                         if (info->port_array[i] == NULL)
2369                                 continue;
2370                         if (gsr & (BIT8 << i))
2371                                 isr_serial(info->port_array[i]);
2372                         if (gsr & (BIT16 << (i*2)))
2373                                 isr_rdma(info->port_array[i]);
2374                         if (gsr & (BIT17 << (i*2)))
2375                                 isr_tdma(info->port_array[i]);
2376                 }
2377         }
2378
2379         if (info->gpio_present) {
2380                 unsigned int state;
2381                 unsigned int changed;
2382                 while ((changed = rd_reg32(info, IOSR)) != 0) {
2383                         DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2384                         /* read latched state of GPIO signals */
2385                         state = rd_reg32(info, IOVR);
2386                         /* clear pending GPIO interrupt bits */
2387                         wr_reg32(info, IOSR, changed);
2388                         for (i=0 ; i < info->port_count ; i++) {
2389                                 if (info->port_array[i] != NULL)
2390                                         isr_gpio(info->port_array[i], changed, state);
2391                         }
2392                 }
2393         }
2394
2395         for(i=0; i < info->port_count ; i++) {
2396                 struct slgt_info *port = info->port_array[i];
2397
2398                 if (port && (port->count || port->netcount) &&
2399                     port->pending_bh && !port->bh_running &&
2400                     !port->bh_requested) {
2401                         DBGISR(("%s bh queued\n", port->device_name));
2402                         schedule_work(&port->task);
2403                         port->bh_requested = true;
2404                 }
2405         }
2406
2407         spin_unlock(&info->lock);
2408
2409         DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2410         return IRQ_HANDLED;
2411 }
2412
2413 static int startup(struct slgt_info *info)
2414 {
2415         DBGINFO(("%s startup\n", info->device_name));
2416
2417         if (info->flags & ASYNC_INITIALIZED)
2418                 return 0;
2419
2420         if (!info->tx_buf) {
2421                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2422                 if (!info->tx_buf) {
2423                         DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2424                         return -ENOMEM;
2425                 }
2426         }
2427
2428         info->pending_bh = 0;
2429
2430         memset(&info->icount, 0, sizeof(info->icount));
2431
2432         /* program hardware for current parameters */
2433         change_params(info);
2434
2435         if (info->tty)
2436                 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2437
2438         info->flags |= ASYNC_INITIALIZED;
2439
2440         return 0;
2441 }
2442
2443 /*
2444  *  called by close() and hangup() to shutdown hardware
2445  */
2446 static void shutdown(struct slgt_info *info)
2447 {
2448         unsigned long flags;
2449
2450         if (!(info->flags & ASYNC_INITIALIZED))
2451                 return;
2452
2453         DBGINFO(("%s shutdown\n", info->device_name));
2454
2455         /* clear status wait queue because status changes */
2456         /* can't happen after shutting down the hardware */
2457         wake_up_interruptible(&info->status_event_wait_q);
2458         wake_up_interruptible(&info->event_wait_q);
2459
2460         del_timer_sync(&info->tx_timer);
2461         del_timer_sync(&info->rx_timer);
2462
2463         kfree(info->tx_buf);
2464         info->tx_buf = NULL;
2465
2466         spin_lock_irqsave(&info->lock,flags);
2467
2468         tx_stop(info);
2469         rx_stop(info);
2470
2471         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2472
2473         if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2474                 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2475                 set_signals(info);
2476         }
2477
2478         flush_cond_wait(&info->gpio_wait_q);
2479
2480         spin_unlock_irqrestore(&info->lock,flags);
2481
2482         if (info->tty)
2483                 set_bit(TTY_IO_ERROR, &info->tty->flags);
2484
2485         info->flags &= ~ASYNC_INITIALIZED;
2486 }
2487
2488 static void program_hw(struct slgt_info *info)
2489 {
2490         unsigned long flags;
2491
2492         spin_lock_irqsave(&info->lock,flags);
2493
2494         rx_stop(info);
2495         tx_stop(info);
2496
2497         if (info->params.mode != MGSL_MODE_ASYNC ||
2498             info->netcount)
2499                 sync_mode(info);
2500         else
2501                 async_mode(info);
2502
2503         set_signals(info);
2504
2505         info->dcd_chkcount = 0;
2506         info->cts_chkcount = 0;
2507         info->ri_chkcount = 0;
2508         info->dsr_chkcount = 0;
2509
2510         slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR);
2511         get_signals(info);
2512
2513         if (info->netcount ||
2514             (info->tty && info->tty->termios->c_cflag & CREAD))
2515                 rx_start(info);
2516
2517         spin_unlock_irqrestore(&info->lock,flags);
2518 }
2519
2520 /*
2521  * reconfigure adapter based on new parameters
2522  */
2523 static void change_params(struct slgt_info *info)
2524 {
2525         unsigned cflag;
2526         int bits_per_char;
2527
2528         if (!info->tty || !info->tty->termios)
2529                 return;
2530         DBGINFO(("%s change_params\n", info->device_name));
2531
2532         cflag = info->tty->termios->c_cflag;
2533
2534         /* if B0 rate (hangup) specified then negate DTR and RTS */
2535         /* otherwise assert DTR and RTS */
2536         if (cflag & CBAUD)
2537                 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2538         else
2539                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2540
2541         /* byte size and parity */
2542
2543         switch (cflag & CSIZE) {
2544         case CS5: info->params.data_bits = 5; break;
2545         case CS6: info->params.data_bits = 6; break;
2546         case CS7: info->params.data_bits = 7; break;
2547         case CS8: info->params.data_bits = 8; break;
2548         default:  info->params.data_bits = 7; break;
2549         }
2550
2551         info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2552
2553         if (cflag & PARENB)
2554                 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2555         else
2556                 info->params.parity = ASYNC_PARITY_NONE;
2557
2558         /* calculate number of jiffies to transmit a full
2559          * FIFO (32 bytes) at specified data rate
2560          */
2561         bits_per_char = info->params.data_bits +
2562                         info->params.stop_bits + 1;
2563
2564         info->params.data_rate = tty_get_baud_rate(info->tty);
2565
2566         if (info->params.data_rate) {
2567                 info->timeout = (32*HZ*bits_per_char) /
2568                                 info->params.data_rate;
2569         }
2570         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2571
2572         if (cflag & CRTSCTS)
2573                 info->flags |= ASYNC_CTS_FLOW;
2574         else
2575                 info->flags &= ~ASYNC_CTS_FLOW;
2576
2577         if (cflag & CLOCAL)
2578                 info->flags &= ~ASYNC_CHECK_CD;
2579         else
2580                 info->flags |= ASYNC_CHECK_CD;
2581
2582         /* process tty input control flags */
2583
2584         info->read_status_mask = IRQ_RXOVER;
2585         if (I_INPCK(info->tty))
2586                 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2587         if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2588                 info->read_status_mask |= MASK_BREAK;
2589         if (I_IGNPAR(info->tty))
2590                 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2591         if (I_IGNBRK(info->tty)) {
2592                 info->ignore_status_mask |= MASK_BREAK;
2593                 /* If ignoring parity and break indicators, ignore
2594                  * overruns too.  (For real raw support).
2595                  */
2596                 if (I_IGNPAR(info->tty))
2597                         info->ignore_status_mask |= MASK_OVERRUN;
2598         }
2599
2600         program_hw(info);
2601 }
2602
2603 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2604 {
2605         DBGINFO(("%s get_stats\n",  info->device_name));
2606         if (!user_icount) {
2607                 memset(&info->icount, 0, sizeof(info->icount));
2608         } else {
2609                 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2610                         return -EFAULT;
2611         }
2612         return 0;
2613 }
2614
2615 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2616 {
2617         DBGINFO(("%s get_params\n", info->device_name));
2618         if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2619                 return -EFAULT;
2620         return 0;
2621 }
2622
2623 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2624 {
2625         unsigned long flags;
2626         MGSL_PARAMS tmp_params;
2627
2628         DBGINFO(("%s set_params\n", info->device_name));
2629         if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2630                 return -EFAULT;
2631
2632         spin_lock_irqsave(&info->lock, flags);
2633         memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2634         spin_unlock_irqrestore(&info->lock, flags);
2635
2636         change_params(info);
2637
2638         return 0;
2639 }
2640
2641 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2642 {
2643         DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2644         if (put_user(info->idle_mode, idle_mode))
2645                 return -EFAULT;
2646         return 0;
2647 }
2648
2649 static int set_txidle(struct slgt_info *info, int idle_mode)
2650 {
2651         unsigned long flags;
2652         DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2653         spin_lock_irqsave(&info->lock,flags);
2654         info->idle_mode = idle_mode;
2655         if (info->params.mode != MGSL_MODE_ASYNC)
2656                 tx_set_idle(info);
2657         spin_unlock_irqrestore(&info->lock,flags);
2658         return 0;
2659 }
2660
2661 static int tx_enable(struct slgt_info *info, int enable)
2662 {
2663         unsigned long flags;
2664         DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2665         spin_lock_irqsave(&info->lock,flags);
2666         if (enable) {
2667                 if (!info->tx_enabled)
2668                         tx_start(info);
2669         } else {
2670                 if (info->tx_enabled)
2671                         tx_stop(info);
2672         }
2673         spin_unlock_irqrestore(&info->lock,flags);
2674         return 0;
2675 }
2676
2677 /*
2678  * abort transmit HDLC frame
2679  */
2680 static int tx_abort(struct slgt_info *info)
2681 {
2682         unsigned long flags;
2683         DBGINFO(("%s tx_abort\n", info->device_name));
2684         spin_lock_irqsave(&info->lock,flags);
2685         tdma_reset(info);
2686         spin_unlock_irqrestore(&info->lock,flags);
2687         return 0;
2688 }
2689
2690 static int rx_enable(struct slgt_info *info, int enable)
2691 {
2692         unsigned long flags;
2693         DBGINFO(("%s rx_enable(%d)\n", info->device_name, enable));
2694         spin_lock_irqsave(&info->lock,flags);
2695         if (enable) {
2696                 if (!info->rx_enabled)
2697                         rx_start(info);
2698                 else if (enable == 2) {
2699                         /* force hunt mode (write 1 to RCR[3]) */
2700                         wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2701                 }
2702         } else {
2703                 if (info->rx_enabled)
2704                         rx_stop(info);
2705         }
2706         spin_unlock_irqrestore(&info->lock,flags);
2707         return 0;
2708 }
2709
2710 /*
2711  *  wait for specified event to occur
2712  */
2713 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2714 {
2715         unsigned long flags;
2716         int s;
2717         int rc=0;
2718         struct mgsl_icount cprev, cnow;
2719         int events;
2720         int mask;
2721         struct  _input_signal_events oldsigs, newsigs;
2722         DECLARE_WAITQUEUE(wait, current);
2723
2724         if (get_user(mask, mask_ptr))
2725                 return -EFAULT;
2726
2727         DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2728
2729         spin_lock_irqsave(&info->lock,flags);
2730
2731         /* return immediately if state matches requested events */
2732         get_signals(info);
2733         s = info->signals;
2734
2735         events = mask &
2736                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2737                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2738                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2739                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2740         if (events) {
2741                 spin_unlock_irqrestore(&info->lock,flags);
2742                 goto exit;
2743         }
2744
2745         /* save current irq counts */
2746         cprev = info->icount;
2747         oldsigs = info->input_signal_events;
2748
2749         /* enable hunt and idle irqs if needed */
2750         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2751                 unsigned short val = rd_reg16(info, SCR);
2752                 if (!(val & IRQ_RXIDLE))
2753                         wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2754         }
2755
2756         set_current_state(TASK_INTERRUPTIBLE);
2757         add_wait_queue(&info->event_wait_q, &wait);
2758
2759         spin_unlock_irqrestore(&info->lock,flags);
2760
2761         for(;;) {
2762                 schedule();
2763                 if (signal_pending(current)) {
2764                         rc = -ERESTARTSYS;
2765                         break;
2766                 }
2767
2768                 /* get current irq counts */
2769                 spin_lock_irqsave(&info->lock,flags);
2770                 cnow = info->icount;
2771                 newsigs = info->input_signal_events;
2772                 set_current_state(TASK_INTERRUPTIBLE);
2773                 spin_unlock_irqrestore(&info->lock,flags);
2774
2775                 /* if no change, wait aborted for some reason */
2776                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2777                     newsigs.dsr_down == oldsigs.dsr_down &&
2778                     newsigs.dcd_up   == oldsigs.dcd_up   &&
2779                     newsigs.dcd_down == oldsigs.dcd_down &&
2780                     newsigs.cts_up   == oldsigs.cts_up   &&
2781                     newsigs.cts_down == oldsigs.cts_down &&
2782                     newsigs.ri_up    == oldsigs.ri_up    &&
2783                     newsigs.ri_down  == oldsigs.ri_down  &&
2784                     cnow.exithunt    == cprev.exithunt   &&
2785                     cnow.rxidle      == cprev.rxidle) {
2786                         rc = -EIO;
2787                         break;
2788                 }
2789
2790                 events = mask &
2791                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2792                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2793                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2794                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2795                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2796                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2797                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2798                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2799                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2800                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2801                 if (events)
2802                         break;
2803
2804                 cprev = cnow;
2805                 oldsigs = newsigs;
2806         }
2807
2808         remove_wait_queue(&info->event_wait_q, &wait);
2809         set_current_state(TASK_RUNNING);
2810
2811
2812         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2813                 spin_lock_irqsave(&info->lock,flags);
2814                 if (!waitqueue_active(&info->event_wait_q)) {
2815                         /* disable enable exit hunt mode/idle rcvd IRQs */
2816                         wr_reg16(info, SCR,
2817                                 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2818                 }
2819                 spin_unlock_irqrestore(&info->lock,flags);
2820         }
2821 exit:
2822         if (rc == 0)
2823                 rc = put_user(events, mask_ptr);
2824         return rc;
2825 }
2826
2827 static int get_interface(struct slgt_info *info, int __user *if_mode)
2828 {
2829         DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2830         if (put_user(info->if_mode, if_mode))
2831                 return -EFAULT;
2832         return 0;
2833 }
2834
2835 static int set_interface(struct slgt_info *info, int if_mode)
2836 {
2837         unsigned long flags;
2838         unsigned short val;
2839
2840         DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2841         spin_lock_irqsave(&info->lock,flags);
2842         info->if_mode = if_mode;
2843
2844         msc_set_vcr(info);
2845
2846         /* TCR (tx control) 07  1=RTS driver control */
2847         val = rd_reg16(info, TCR);
2848         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2849                 val |= BIT7;
2850         else
2851                 val &= ~BIT7;
2852         wr_reg16(info, TCR, val);
2853
2854         spin_unlock_irqrestore(&info->lock,flags);
2855         return 0;
2856 }
2857
2858 /*
2859  * set general purpose IO pin state and direction
2860  *
2861  * user_gpio fields:
2862  * state   each bit indicates a pin state
2863  * smask   set bit indicates pin state to set
2864  * dir     each bit indicates a pin direction (0=input, 1=output)
2865  * dmask   set bit indicates pin direction to set
2866  */
2867 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2868 {
2869         unsigned long flags;
2870         struct gpio_desc gpio;
2871         __u32 data;
2872
2873         if (!info->gpio_present)
2874                 return -EINVAL;
2875         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2876                 return -EFAULT;
2877         DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2878                  info->device_name, gpio.state, gpio.smask,
2879                  gpio.dir, gpio.dmask));
2880
2881         spin_lock_irqsave(&info->lock,flags);
2882         if (gpio.dmask) {
2883                 data = rd_reg32(info, IODR);
2884                 data |= gpio.dmask & gpio.dir;
2885                 data &= ~(gpio.dmask & ~gpio.dir);
2886                 wr_reg32(info, IODR, data);
2887         }
2888         if (gpio.smask) {
2889                 data = rd_reg32(info, IOVR);
2890                 data |= gpio.smask & gpio.state;
2891                 data &= ~(gpio.smask & ~gpio.state);
2892                 wr_reg32(info, IOVR, data);
2893         }
2894         spin_unlock_irqrestore(&info->lock,flags);
2895
2896         return 0;
2897 }
2898
2899 /*
2900  * get general purpose IO pin state and direction
2901  */
2902 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2903 {
2904         struct gpio_desc gpio;
2905         if (!info->gpio_present)
2906                 return -EINVAL;
2907         gpio.state = rd_reg32(info, IOVR);
2908         gpio.smask = 0xffffffff;
2909         gpio.dir   = rd_reg32(info, IODR);
2910         gpio.dmask = 0xffffffff;
2911         if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2912                 return -EFAULT;
2913         DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2914                  info->device_name, gpio.state, gpio.dir));
2915         return 0;
2916 }
2917
2918 /*
2919  * conditional wait facility
2920  */
2921 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2922 {
2923         init_waitqueue_head(&w->q);
2924         init_waitqueue_entry(&w->wait, current);
2925         w->data = data;
2926 }
2927
2928 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2929 {
2930         set_current_state(TASK_INTERRUPTIBLE);
2931         add_wait_queue(&w->q, &w->wait);
2932         w->next = *head;
2933         *head = w;
2934 }
2935
2936 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2937 {
2938         struct cond_wait *w, *prev;
2939         remove_wait_queue(&cw->q, &cw->wait);
2940         set_current_state(TASK_RUNNING);
2941         for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2942                 if (w == cw) {
2943                         if (prev != NULL)
2944                                 prev->next = w->next;
2945                         else
2946                                 *head = w->next;
2947                         break;
2948                 }
2949         }
2950 }
2951
2952 static void flush_cond_wait(struct cond_wait **head)
2953 {
2954         while (*head != NULL) {
2955                 wake_up_interruptible(&(*head)->q);
2956                 *head = (*head)->next;
2957         }
2958 }
2959
2960 /*
2961  * wait for general purpose I/O pin(s) to enter specified state
2962  *
2963  * user_gpio fields:
2964  * state - bit indicates target pin state
2965  * smask - set bit indicates watched pin
2966  *
2967  * The wait ends when at least one watched pin enters the specified
2968  * state. When 0 (no error) is returned, user_gpio->state is set to the
2969  * state of all GPIO pins when the wait ends.
2970  *
2971  * Note: Each pin may be a dedicated input, dedicated output, or
2972  * configurable input/output. The number and configuration of pins
2973  * varies with the specific adapter model. Only input pins (dedicated
2974  * or configured) can be monitored with this function.
2975  */
2976 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2977 {
2978         unsigned long flags;
2979         int rc = 0;
2980         struct gpio_desc gpio;
2981         struct cond_wait wait;
2982         u32 state;
2983
2984         if (!info->gpio_present)
2985                 return -EINVAL;
2986         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2987                 return -EFAULT;
2988         DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2989                  info->device_name, gpio.state, gpio.smask));
2990         /* ignore output pins identified by set IODR bit */
2991         if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2992                 return -EINVAL;
2993         init_cond_wait(&wait, gpio.smask);
2994
2995         spin_lock_irqsave(&info->lock, flags);
2996         /* enable interrupts for watched pins */
2997         wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
2998         /* get current pin states */
2999         state = rd_reg32(info, IOVR);
3000
3001         if (gpio.smask & ~(state ^ gpio.state)) {
3002                 /* already in target state */
3003                 gpio.state = state;
3004         } else {
3005                 /* wait for target state */
3006                 add_cond_wait(&info->gpio_wait_q, &wait);
3007                 spin_unlock_irqrestore(&info->lock, flags);
3008                 schedule();
3009                 if (signal_pending(current))
3010                         rc = -ERESTARTSYS;
3011                 else
3012                         gpio.state = wait.data;
3013                 spin_lock_irqsave(&info->lock, flags);
3014                 remove_cond_wait(&info->gpio_wait_q, &wait);
3015         }
3016
3017         /* disable all GPIO interrupts if no waiting processes */
3018         if (info->gpio_wait_q == NULL)
3019                 wr_reg32(info, IOER, 0);
3020         spin_unlock_irqrestore(&info->lock,flags);
3021
3022         if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3023                 rc = -EFAULT;
3024         return rc;
3025 }
3026
3027 static int modem_input_wait(struct slgt_info *info,int arg)
3028 {
3029         unsigned long flags;
3030         int rc;
3031         struct mgsl_icount cprev, cnow;
3032         DECLARE_WAITQUEUE(wait, current);
3033
3034         /* save current irq counts */
3035         spin_lock_irqsave(&info->lock,flags);
3036         cprev = info->icount;
3037         add_wait_queue(&info->status_event_wait_q, &wait);
3038         set_current_state(TASK_INTERRUPTIBLE);
3039         spin_unlock_irqrestore(&info->lock,flags);
3040
3041         for(;;) {
3042                 schedule();
3043                 if (signal_pending(current)) {
3044                         rc = -ERESTARTSYS;
3045                         break;
3046                 }
3047
3048                 /* get new irq counts */
3049                 spin_lock_irqsave(&info->lock,flags);
3050                 cnow = info->icount;
3051                 set_current_state(TASK_INTERRUPTIBLE);
3052                 spin_unlock_irqrestore(&info->lock,flags);
3053
3054                 /* if no change, wait aborted for some reason */
3055                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3056                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3057                         rc = -EIO;
3058                         break;
3059                 }
3060
3061                 /* check for change in caller specified modem input */
3062                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3063                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3064                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3065                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3066                         rc = 0;
3067                         break;
3068                 }
3069
3070                 cprev = cnow;
3071         }
3072         remove_wait_queue(&info->status_event_wait_q, &wait);
3073         set_current_state(TASK_RUNNING);
3074         return rc;
3075 }
3076
3077 /*
3078  *  return state of serial control and status signals
3079  */
3080 static int tiocmget(struct tty_struct *tty, struct file *file)
3081 {
3082         struct slgt_info *info = tty->driver_data;
3083         unsigned int result;
3084         unsigned long flags;
3085
3086         spin_lock_irqsave(&info->lock,flags);
3087         get_signals(info);
3088         spin_unlock_irqrestore(&info->lock,flags);
3089
3090         result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3091                 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3092                 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3093                 ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3094                 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3095                 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3096
3097         DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3098         return result;
3099 }
3100
3101 /*
3102  * set modem control signals (DTR/RTS)
3103  *
3104  *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3105  *              TIOCMSET = set/clear signal values
3106  *      value   bit mask for command
3107  */
3108 static int tiocmset(struct tty_struct *tty, struct file *file,
3109                     unsigned int set, unsigned int clear)
3110 {
3111         struct slgt_info *info = tty->driver_data;
3112         unsigned long flags;
3113
3114         DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3115
3116         if (set & TIOCM_RTS)
3117                 info->signals |= SerialSignal_RTS;
3118         if (set & TIOCM_DTR)
3119                 info->signals |= SerialSignal_DTR;
3120         if (clear & TIOCM_RTS)
3121                 info->signals &= ~SerialSignal_RTS;
3122         if (clear & TIOCM_DTR)
3123                 info->signals &= ~SerialSignal_DTR;
3124
3125         spin_lock_irqsave(&info->lock,flags);
3126         set_signals(info);
3127         spin_unlock_irqrestore(&info->lock,flags);
3128         return 0;
3129 }
3130
3131 /*
3132  *  block current process until the device is ready to open
3133  */
3134 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3135                            struct slgt_info *info)
3136 {
3137         DECLARE_WAITQUEUE(wait, current);
3138         int             retval;
3139         bool            do_clocal = false;
3140         bool            extra_count = false;
3141         unsigned long   flags;
3142
3143         DBGINFO(("%s block_til_ready\n", tty->driver->name));
3144
3145         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3146                 /* nonblock mode is set or port is not enabled */
3147                 info->flags |= ASYNC_NORMAL_ACTIVE;
3148                 return 0;
3149         }
3150
3151         if (tty->termios->c_cflag & CLOCAL)
3152                 do_clocal = true;
3153
3154         /* Wait for carrier detect and the line to become
3155          * free (i.e., not in use by the callout).  While we are in
3156          * this loop, info->count is dropped by one, so that
3157          * close() knows when to free things.  We restore it upon
3158          * exit, either normal or abnormal.
3159          */
3160
3161         retval = 0;
3162         add_wait_queue(&info->open_wait, &wait);
3163
3164         spin_lock_irqsave(&info->lock, flags);
3165         if (!tty_hung_up_p(filp)) {
3166                 extra_count = true;
3167                 info->count--;
3168         }
3169         spin_unlock_irqrestore(&info->lock, flags);
3170         info->blocked_open++;
3171
3172         while (1) {
3173                 if ((tty->termios->c_cflag & CBAUD)) {
3174                         spin_lock_irqsave(&info->lock,flags);
3175                         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3176                         set_signals(info);
3177                         spin_unlock_irqrestore(&info->lock,flags);
3178                 }
3179
3180                 set_current_state(TASK_INTERRUPTIBLE);
3181
3182                 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3183                         retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3184                                         -EAGAIN : -ERESTARTSYS;
3185                         break;
3186                 }
3187
3188                 spin_lock_irqsave(&info->lock,flags);
3189                 get_signals(info);
3190                 spin_unlock_irqrestore(&info->lock,flags);
3191
3192                 if (!(info->flags & ASYNC_CLOSING) &&
3193                     (do_clocal || (info->signals & SerialSignal_DCD)) ) {
3194                         break;
3195                 }
3196
3197                 if (signal_pending(current)) {
3198                         retval = -ERESTARTSYS;
3199                         break;
3200                 }
3201
3202                 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3203                 schedule();
3204         }
3205
3206         set_current_state(TASK_RUNNING);
3207         remove_wait_queue(&info->open_wait, &wait);
3208
3209         if (extra_count)
3210                 info->count++;
3211         info->blocked_open--;
3212
3213         if (!retval)
3214                 info->flags |= ASYNC_NORMAL_ACTIVE;
3215
3216         DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3217         return retval;
3218 }
3219
3220 static int alloc_tmp_rbuf(struct slgt_info *info)
3221 {
3222         info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3223         if (info->tmp_rbuf == NULL)
3224                 return -ENOMEM;
3225         return 0;
3226 }
3227
3228 static void free_tmp_rbuf(struct slgt_info *info)
3229 {
3230         kfree(info->tmp_rbuf);
3231         info->tmp_rbuf = NULL;
3232 }
3233
3234 /*
3235  * allocate DMA descriptor lists.
3236  */
3237 static int alloc_desc(struct slgt_info *info)
3238 {
3239         unsigned int i;
3240         unsigned int pbufs;
3241
3242         /* allocate memory to hold descriptor lists */
3243         info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3244         if (info->bufs == NULL)
3245                 return -ENOMEM;
3246
3247         memset(info->bufs, 0, DESC_LIST_SIZE);
3248
3249         info->rbufs = (struct slgt_desc*)info->bufs;
3250         info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3251
3252         pbufs = (unsigned int)info->bufs_dma_addr;
3253
3254         /*
3255          * Build circular lists of descriptors
3256          */
3257
3258         for (i=0; i < info->rbuf_count; i++) {
3259                 /* physical address of this descriptor */
3260                 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3261
3262                 /* physical address of next descriptor */
3263                 if (i == info->rbuf_count - 1)
3264                         info->rbufs[i].next = cpu_to_le32(pbufs);
3265                 else
3266                         info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3267                 set_desc_count(info->rbufs[i], DMABUFSIZE);
3268         }
3269
3270         for (i=0; i < info->tbuf_count; i++) {
3271                 /* physical address of this descriptor */
3272                 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3273
3274                 /* physical address of next descriptor */
3275                 if (i == info->tbuf_count - 1)
3276                         info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3277                 else
3278                         info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3279         }
3280
3281         return 0;
3282 }
3283
3284 static void free_desc(struct slgt_info *info)
3285 {
3286         if (info->bufs != NULL) {
3287                 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3288                 info->bufs  = NULL;
3289                 info->rbufs = NULL;
3290                 info->tbufs = NULL;
3291         }
3292 }
3293
3294 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3295 {
3296         int i;
3297         for (i=0; i < count; i++) {
3298                 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3299                         return -ENOMEM;
3300                 bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3301         }
3302         return 0;
3303 }
3304
3305 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3306 {
3307         int i;
3308         for (i=0; i < count; i++) {
3309                 if (bufs[i].buf == NULL)
3310                         continue;
3311                 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3312                 bufs[i].buf = NULL;
3313         }
3314 }
3315
3316 static int alloc_dma_bufs(struct slgt_info *info)
3317 {
3318         info->rbuf_count = 32;
3319         info->tbuf_count = 32;
3320
3321         if (alloc_desc(info) < 0 ||
3322             alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3323             alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3324             alloc_tmp_rbuf(info) < 0) {
3325                 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3326                 return -ENOMEM;
3327         }
3328         reset_rbufs(info);
3329         return 0;
3330 }
3331
3332 static void free_dma_bufs(struct slgt_info *info)
3333 {
3334         if (info->bufs) {
3335                 free_bufs(info, info->rbufs, info->rbuf_count);
3336                 free_bufs(info, info->tbufs, info->tbuf_count);
3337                 free_desc(info);
3338         }
3339         free_tmp_rbuf(info);
3340 }
3341
3342 static int claim_resources(struct slgt_info *info)
3343 {
3344         if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3345                 DBGERR(("%s reg addr conflict, addr=%08X\n",
3346                         info->device_name, info->phys_reg_addr));
3347                 info->init_error = DiagStatus_AddressConflict;
3348                 goto errout;
3349         }
3350         else
3351                 info->reg_addr_requested = true;
3352
3353         info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3354         if (!info->reg_addr) {
3355                 DBGERR(("%s cant map device registers, addr=%08X\n",
3356                         info->device_name, info->phys_reg_addr));
3357                 info->init_error = DiagStatus_CantAssignPciResources;
3358                 goto errout;
3359         }
3360         return 0;
3361
3362 errout:
3363         release_resources(info);
3364         return -ENODEV;
3365 }
3366
3367 static void release_resources(struct slgt_info *info)
3368 {
3369         if (info->irq_requested) {
3370                 free_irq(info->irq_level, info);
3371                 info->irq_requested = false;
3372         }
3373
3374         if (info->reg_addr_requested) {
3375                 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3376                 info->reg_addr_requested = false;
3377         }
3378
3379         if (info->reg_addr) {
3380                 iounmap(info->reg_addr);
3381                 info->reg_addr = NULL;
3382         }
3383 }
3384
3385 /* Add the specified device instance data structure to the
3386  * global linked list of devices and increment the device count.
3387  */
3388 static void add_device(struct slgt_info *info)
3389 {
3390         char *devstr;
3391
3392         info->next_device = NULL;
3393         info->line = slgt_device_count;
3394         sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3395
3396         if (info->line < MAX_DEVICES) {
3397                 if (maxframe[info->line])
3398                         info->max_frame_size = maxframe[info->line];
3399                 info->dosyncppp = dosyncppp[info->line];
3400         }
3401
3402         slgt_device_count++;
3403
3404         if (!slgt_device_list)
3405                 slgt_device_list = info;
3406         else {
3407                 struct slgt_info *current_dev = slgt_device_list;
3408                 while(current_dev->next_device)
3409                         current_dev = current_dev->next_device;
3410                 current_dev->next_device = info;
3411         }
3412
3413         if (info->max_frame_size < 4096)
3414                 info->max_frame_size = 4096;
3415         else if (info->max_frame_size > 65535)
3416                 info->max_frame_size = 65535;
3417
3418         switch(info->pdev->device) {
3419         case SYNCLINK_GT_DEVICE_ID:
3420                 devstr = "GT";
3421                 break;
3422         case SYNCLINK_GT2_DEVICE_ID:
3423                 devstr = "GT2";
3424                 break;
3425         case SYNCLINK_GT4_DEVICE_ID:
3426                 devstr = "GT4";
3427                 break;
3428         case SYNCLINK_AC_DEVICE_ID:
3429                 devstr = "AC";
3430                 info->params.mode = MGSL_MODE_ASYNC;
3431                 break;
3432         default:
3433                 devstr = "(unknown model)";
3434         }
3435         printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3436                 devstr, info->device_name, info->phys_reg_addr,
3437                 info->irq_level, info->max_frame_size);
3438
3439 #if SYNCLINK_GENERIC_HDLC
3440         hdlcdev_init(info);
3441 #endif
3442 }
3443
3444 /*
3445  *  allocate device instance structure, return NULL on failure
3446  */
3447 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3448 {
3449         struct slgt_info *info;
3450
3451         info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3452
3453         if (!info) {
3454                 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3455                         driver_name, adapter_num, port_num));
3456         } else {
3457                 info->magic = MGSL_MAGIC;
3458                 INIT_WORK(&info->task, bh_handler);
3459                 info->max_frame_size = 4096;
3460                 info->raw_rx_size = DMABUFSIZE;
3461                 info->close_delay = 5*HZ/10;
3462                 info->closing_wait = 30*HZ;
3463                 init_waitqueue_head(&info->open_wait);
3464                 init_waitqueue_head(&info->close_wait);
3465                 init_waitqueue_head(&info->status_event_wait_q);
3466                 init_waitqueue_head(&info->event_wait_q);
3467                 spin_lock_init(&info->netlock);
3468                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3469                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3470                 info->adapter_num = adapter_num;
3471                 info->port_num = port_num;
3472
3473                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3474                 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3475
3476                 /* Copy configuration info to device instance data */
3477                 info->pdev = pdev;
3478                 info->irq_level = pdev->irq;
3479                 info->phys_reg_addr = pci_resource_start(pdev,0);
3480
3481                 info->bus_type = MGSL_BUS_TYPE_PCI;
3482                 info->irq_flags = IRQF_SHARED;
3483
3484                 info->init_error = -1; /* assume error, set to 0 on successful init */
3485         }
3486
3487         return info;
3488 }
3489
3490 static void device_init(int adapter_num, struct pci_dev *pdev)
3491 {
3492         struct slgt_info *port_array[SLGT_MAX_PORTS];
3493         int i;
3494         int port_count = 1;
3495
3496         if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3497                 port_count = 2;
3498         else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3499                 port_count = 4;
3500
3501         /* allocate device instances for all ports */
3502         for (i=0; i < port_count; ++i) {
3503                 port_array[i] = alloc_dev(adapter_num, i, pdev);
3504                 if (port_array[i] == NULL) {
3505                         for (--i; i >= 0; --i)
3506                                 kfree(port_array[i]);
3507                         return;
3508                 }
3509         }
3510
3511         /* give copy of port_array to all ports and add to device list  */
3512         for (i=0; i < port_count; ++i) {
3513                 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3514                 add_device(port_array[i]);
3515                 port_array[i]->port_count = port_count;
3516                 spin_lock_init(&port_array[i]->lock);
3517         }
3518
3519         /* Allocate and claim adapter resources */
3520         if (!claim_resources(port_array[0])) {
3521
3522                 alloc_dma_bufs(port_array[0]);
3523
3524                 /* copy resource information from first port to others */
3525                 for (i = 1; i < port_count; ++i) {
3526                         port_array[i]->lock      = port_array[0]->lock;
3527                         port_array[i]->irq_level = port_array[0]->irq_level;
3528                         port_array[i]->reg_addr  = port_array[0]->reg_addr;
3529                         alloc_dma_bufs(port_array[i]);
3530                 }
3531
3532                 if (request_irq(port_array[0]->irq_level,
3533                                         slgt_interrupt,
3534                                         port_array[0]->irq_flags,
3535                                         port_array[0]->device_name,
3536                                         port_array[0]) < 0) {
3537                         DBGERR(("%s request_irq failed IRQ=%d\n",
3538                                 port_array[0]->device_name,
3539                                 port_array[0]->irq_level));
3540                 } else {
3541                         port_array[0]->irq_requested = true;
3542                         adapter_test(port_array[0]);
3543                         for (i=1 ; i < port_count ; i++) {
3544                                 port_array[i]->init_error = port_array[0]->init_error;
3545                                 port_array[i]->gpio_present = port_array[0]->gpio_present;
3546                         }
3547                 }
3548         }
3549
3550         for (i=0; i < port_count; ++i)
3551                 tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev));
3552 }
3553
3554 static int __devinit init_one(struct pci_dev *dev,
3555                               const struct pci_device_id *ent)
3556 {
3557         if (pci_enable_device(dev)) {
3558                 printk("error enabling pci device %p\n", dev);
3559                 return -EIO;
3560         }
3561         pci_set_master(dev);
3562         device_init(slgt_device_count, dev);
3563         return 0;
3564 }
3565
3566 static void __devexit remove_one(struct pci_dev *dev)
3567 {
3568 }
3569
3570 static const struct tty_operations ops = {
3571         .open = open,
3572         .close = close,
3573         .write = write,
3574         .put_char = put_char,
3575         .flush_chars = flush_chars,
3576         .write_room = write_room,
3577         .chars_in_buffer = chars_in_buffer,
3578         .flush_buffer = flush_buffer,
3579         .ioctl = ioctl,
3580         .compat_ioctl = slgt_compat_ioctl,
3581         .throttle = throttle,
3582         .unthrottle = unthrottle,
3583         .send_xchar = send_xchar,
3584         .break_ctl = set_break,
3585         .wait_until_sent = wait_until_sent,
3586         .read_proc = read_proc,
3587         .set_termios = set_termios,
3588         .stop = tx_hold,
3589         .start = tx_release,
3590         .hangup = hangup,
3591         .tiocmget = tiocmget,
3592         .tiocmset = tiocmset,
3593 };
3594
3595 static void slgt_cleanup(void)
3596 {
3597         int rc;
3598         struct slgt_info *info;
3599         struct slgt_info *tmp;
3600
3601         printk("unload %s %s\n", driver_name, driver_version);
3602
3603         if (serial_driver) {
3604                 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3605                         tty_unregister_device(serial_driver, info->line);
3606                 if ((rc = tty_unregister_driver(serial_driver)))
3607                         DBGERR(("tty_unregister_driver error=%d\n", rc));
3608                 put_tty_driver(serial_driver);
3609         }
3610
3611         /* reset devices */
3612         info = slgt_device_list;
3613         while(info) {
3614                 reset_port(info);
3615                 info = info->next_device;
3616         }
3617
3618         /* release devices */
3619         info = slgt_device_list;
3620         while(info) {
3621 #if SYNCLINK_GENERIC_HDLC
3622                 hdlcdev_exit(info);
3623 #endif
3624                 free_dma_bufs(info);
3625                 free_tmp_rbuf(info);
3626                 if (info->port_num == 0)
3627                         release_resources(info);
3628                 tmp = info;
3629                 info = info->next_device;
3630                 kfree(tmp);
3631         }
3632
3633         if (pci_registered)
3634                 pci_unregister_driver(&pci_driver);
3635 }
3636
3637 /*
3638  *  Driver initialization entry point.
3639  */
3640 static int __init slgt_init(void)
3641 {
3642         int rc;
3643
3644         printk("%s %s\n", driver_name, driver_version);
3645
3646         serial_driver = alloc_tty_driver(MAX_DEVICES);
3647         if (!serial_driver) {
3648                 printk("%s can't allocate tty driver\n", driver_name);
3649                 return -ENOMEM;
3650         }
3651
3652         /* Initialize the tty_driver structure */
3653
3654         serial_driver->owner = THIS_MODULE;
3655         serial_driver->driver_name = tty_driver_name;
3656         serial_driver->name = tty_dev_prefix;
3657         serial_driver->major = ttymajor;
3658         serial_driver->minor_start = 64;
3659         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3660         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3661         serial_driver->init_termios = tty_std_termios;
3662         serial_driver->init_termios.c_cflag =
3663                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3664         serial_driver->init_termios.c_ispeed = 9600;
3665         serial_driver->init_termios.c_ospeed = 9600;
3666         serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3667         tty_set_operations(serial_driver, &ops);
3668         if ((rc = tty_register_driver(serial_driver)) < 0) {
3669                 DBGERR(("%s can't register serial driver\n", driver_name));
3670                 put_tty_driver(serial_driver);
3671                 serial_driver = NULL;
3672                 goto error;
3673         }
3674
3675         printk("%s %s, tty major#%d\n",
3676                 driver_name, driver_version,
3677                 serial_driver->major);
3678
3679         slgt_device_count = 0;
3680         if ((rc = pci_register_driver(&pci_driver)) < 0) {
3681                 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3682                 goto error;
3683         }
3684         pci_registered = true;
3685
3686         if (!slgt_device_list)
3687                 printk("%s no devices found\n",driver_name);
3688
3689         return 0;
3690
3691 error:
3692         slgt_cleanup();
3693         return rc;
3694 }
3695
3696 static void __exit slgt_exit(void)
3697 {
3698         slgt_cleanup();
3699 }
3700
3701 module_init(slgt_init);
3702 module_exit(slgt_exit);
3703
3704 /*
3705  * register access routines
3706  */
3707
3708 #define CALC_REGADDR() \
3709         unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3710         if (addr >= 0x80) \
3711                 reg_addr += (info->port_num) * 32;
3712
3713 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3714 {
3715         CALC_REGADDR();
3716         return readb((void __iomem *)reg_addr);
3717 }
3718
3719 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3720 {
3721         CALC_REGADDR();
3722         writeb(value, (void __iomem *)reg_addr);
3723 }
3724
3725 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3726 {
3727         CALC_REGADDR();
3728         return readw((void __iomem *)reg_addr);
3729 }
3730
3731 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3732 {
3733         CALC_REGADDR();
3734         writew(value, (void __iomem *)reg_addr);
3735 }
3736
3737 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3738 {
3739         CALC_REGADDR();
3740         return readl((void __iomem *)reg_addr);
3741 }
3742
3743 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3744 {
3745         CALC_REGADDR();
3746         writel(value, (void __iomem *)reg_addr);
3747 }
3748
3749 static void rdma_reset(struct slgt_info *info)
3750 {
3751         unsigned int i;
3752
3753         /* set reset bit */
3754         wr_reg32(info, RDCSR, BIT1);
3755
3756         /* wait for enable bit cleared */
3757         for(i=0 ; i < 1000 ; i++)
3758                 if (!(rd_reg32(info, RDCSR) & BIT0))
3759                         break;
3760 }
3761
3762 static void tdma_reset(struct slgt_info *info)
3763 {
3764         unsigned int i;
3765
3766         /* set reset bit */
3767         wr_reg32(info, TDCSR, BIT1);
3768
3769         /* wait for enable bit cleared */
3770         for(i=0 ; i < 1000 ; i++)
3771                 if (!(rd_reg32(info, TDCSR) & BIT0))
3772                         break;
3773 }
3774
3775 /*
3776  * enable internal loopback
3777  * TxCLK and RxCLK are generated from BRG
3778  * and TxD is looped back to RxD internally.
3779  */
3780 static void enable_loopback(struct slgt_info *info)
3781 {
3782         /* SCR (serial control) BIT2=looopback enable */
3783         wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3784
3785         if (info->params.mode != MGSL_MODE_ASYNC) {
3786                 /* CCR (clock control)
3787                  * 07..05  tx clock source (010 = BRG)
3788                  * 04..02  rx clock source (010 = BRG)
3789                  * 01      auxclk enable   (0 = disable)
3790                  * 00      BRG enable      (1 = enable)
3791                  *
3792                  * 0100 1001
3793                  */
3794                 wr_reg8(info, CCR, 0x49);
3795
3796                 /* set speed if available, otherwise use default */
3797                 if (info->params.clock_speed)
3798                         set_rate(info, info->params.clock_speed);
3799                 else
3800                         set_rate(info, 3686400);
3801         }
3802 }
3803
3804 /*
3805  *  set baud rate generator to specified rate
3806  */
3807 static void set_rate(struct slgt_info *info, u32 rate)
3808 {
3809         unsigned int div;
3810         static unsigned int osc = 14745600;
3811
3812         /* div = osc/rate - 1
3813          *
3814          * Round div up if osc/rate is not integer to
3815          * force to next slowest rate.
3816          */
3817
3818         if (rate) {
3819                 div = osc/rate;
3820                 if (!(osc % rate) && div)
3821                         div--;
3822                 wr_reg16(info, BDR, (unsigned short)div);
3823         }
3824 }
3825
3826 static void rx_stop(struct slgt_info *info)
3827 {
3828         unsigned short val;
3829
3830         /* disable and reset receiver */
3831         val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3832         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3833         wr_reg16(info, RCR, val);                  /* clear reset bit */
3834
3835         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3836
3837         /* clear pending rx interrupts */
3838         wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3839
3840         rdma_reset(info);
3841
3842         info->rx_enabled = false;
3843         info->rx_restart = false;
3844 }
3845
3846 static void rx_start(struct slgt_info *info)
3847 {
3848         unsigned short val;
3849
3850         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3851
3852         /* clear pending rx overrun IRQ */
3853         wr_reg16(info, SSR, IRQ_RXOVER);
3854
3855         /* reset and disable receiver */
3856         val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3857         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3858         wr_reg16(info, RCR, val);                  /* clear reset bit */
3859
3860         rdma_reset(info);
3861         reset_rbufs(info);
3862
3863         /* set 1st descriptor address */
3864         wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3865
3866         if (info->params.mode != MGSL_MODE_ASYNC) {
3867                 /* enable rx DMA and DMA interrupt */
3868                 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3869         } else {
3870                 /* enable saving of rx status, rx DMA and DMA interrupt */
3871                 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3872         }
3873
3874         slgt_irq_on(info, IRQ_RXOVER);
3875
3876         /* enable receiver */
3877         wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3878
3879         info->rx_restart = false;
3880         info->rx_enabled = true;
3881 }
3882
3883 static void tx_start(struct slgt_info *info)
3884 {
3885         if (!info->tx_enabled) {
3886                 wr_reg16(info, TCR,
3887                          (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3888                 info->tx_enabled = true;
3889         }
3890
3891         if (info->tx_count) {
3892                 info->drop_rts_on_tx_done = false;
3893
3894                 if (info->params.mode != MGSL_MODE_ASYNC) {
3895                         if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3896                                 get_signals(info);
3897                                 if (!(info->signals & SerialSignal_RTS)) {
3898                                         info->signals |= SerialSignal_RTS;
3899                                         set_signals(info);
3900                                         info->drop_rts_on_tx_done = true;
3901                                 }
3902                         }
3903
3904                         slgt_irq_off(info, IRQ_TXDATA);
3905                         slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3906                         /* clear tx idle and underrun status bits */
3907                         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3908                         if (info->params.mode == MGSL_MODE_HDLC)
3909                                 mod_timer(&info->tx_timer, jiffies +
3910                                                 msecs_to_jiffies(5000));
3911                 } else {
3912                         slgt_irq_off(info, IRQ_TXDATA);
3913                         slgt_irq_on(info, IRQ_TXIDLE);
3914                         /* clear tx idle status bit */
3915                         wr_reg16(info, SSR, IRQ_TXIDLE);
3916                 }
3917                 tdma_start(info);
3918                 info->tx_active = true;
3919         }
3920 }
3921
3922 /*
3923  * start transmit DMA if inactive and there are unsent buffers
3924  */
3925 static void tdma_start(struct slgt_info *info)
3926 {
3927         unsigned int i;
3928
3929         if (rd_reg32(info, TDCSR) & BIT0)
3930                 return;
3931
3932         /* transmit DMA inactive, check for unsent buffers */
3933         i = info->tbuf_start;
3934         while (!desc_count(info->tbufs[i])) {
3935                 if (++i == info->tbuf_count)
3936                         i = 0;
3937                 if (i == info->tbuf_current)
3938                         return;
3939         }
3940         info->tbuf_start = i;
3941
3942         /* there are unsent buffers, start transmit DMA */
3943
3944         /* reset needed if previous error condition */
3945         tdma_reset(info);
3946
3947         /* set 1st descriptor address */
3948         wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3949         switch(info->params.mode) {
3950         case MGSL_MODE_RAW:
3951         case MGSL_MODE_MONOSYNC:
3952         case MGSL_MODE_BISYNC:
3953                 wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
3954                 break;
3955         default:
3956                 wr_reg32(info, TDCSR, BIT0); /* DMA enable */
3957         }
3958 }
3959
3960 static void tx_stop(struct slgt_info *info)
3961 {
3962         unsigned short val;
3963
3964         del_timer(&info->tx_timer);
3965
3966         tdma_reset(info);
3967
3968         /* reset and disable transmitter */
3969         val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
3970         wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3971
3972         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3973
3974         /* clear tx idle and underrun status bit */
3975         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3976
3977         reset_tbufs(info);
3978
3979         info->tx_enabled = false;
3980         info->tx_active = false;
3981 }
3982
3983 static void reset_port(struct slgt_info *info)
3984 {
3985         if (!info->reg_addr)
3986                 return;
3987
3988         tx_stop(info);
3989         rx_stop(info);
3990
3991         info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
3992         set_signals(info);
3993
3994         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3995 }
3996
3997 static void reset_adapter(struct slgt_info *info)
3998 {
3999         int i;
4000         for (i=0; i < info->port_count; ++i) {
4001                 if (info->port_array[i])
4002                         reset_port(info->port_array[i]);
4003         }
4004 }
4005
4006 static void async_mode(struct slgt_info *info)
4007 {
4008         unsigned short val;
4009
4010         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4011         tx_stop(info);
4012         rx_stop(info);
4013
4014         /* TCR (tx control)
4015          *
4016          * 15..13  mode, 010=async
4017          * 12..10  encoding, 000=NRZ
4018          * 09      parity enable
4019          * 08      1=odd parity, 0=even parity
4020          * 07      1=RTS driver control
4021          * 06      1=break enable
4022          * 05..04  character length
4023          *         00=5 bits
4024          *         01=6 bits
4025          *         10=7 bits
4026          *         11=8 bits
4027          * 03      0=1 stop bit, 1=2 stop bits
4028          * 02      reset
4029          * 01      enable
4030          * 00      auto-CTS enable
4031          */
4032         val = 0x4000;
4033
4034         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4035                 val |= BIT7;
4036
4037         if (info->params.parity != ASYNC_PARITY_NONE) {
4038                 val |= BIT9;
4039                 if (info->params.parity == ASYNC_PARITY_ODD)
4040                         val |= BIT8;
4041         }
4042
4043         switch (info->params.data_bits)
4044         {
4045         case 6: val |= BIT4; break;
4046         case 7: val |= BIT5; break;
4047         case 8: val |= BIT5 + BIT4; break;
4048         }
4049
4050         if (info->params.stop_bits != 1)
4051                 val |= BIT3;
4052
4053         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4054                 val |= BIT0;
4055
4056         wr_reg16(info, TCR, val);
4057
4058         /* RCR (rx control)
4059          *
4060          * 15..13  mode, 010=async
4061          * 12..10  encoding, 000=NRZ
4062          * 09      parity enable
4063          * 08      1=odd parity, 0=even parity
4064          * 07..06  reserved, must be 0
4065          * 05..04  character length
4066          *         00=5 bits
4067          *         01=6 bits
4068          *         10=7 bits
4069          *         11=8 bits
4070          * 03      reserved, must be zero
4071          * 02      reset
4072          * 01      enable
4073          * 00      auto-DCD enable
4074          */
4075         val = 0x4000;
4076
4077         if (info->params.parity != ASYNC_PARITY_NONE) {
4078                 val |= BIT9;
4079                 if (info->params.parity == ASYNC_PARITY_ODD)
4080                         val |= BIT8;
4081         }
4082
4083         switch (info->params.data_bits)
4084         {
4085         case 6: val |= BIT4; break;
4086         case 7: val |= BIT5; break;
4087         case 8: val |= BIT5 + BIT4; break;
4088         }
4089
4090         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4091                 val |= BIT0;
4092
4093         wr_reg16(info, RCR, val);
4094
4095         /* CCR (clock control)
4096          *
4097          * 07..05  011 = tx clock source is BRG/16
4098          * 04..02  010 = rx clock source is BRG
4099          * 01      0 = auxclk disabled
4100          * 00      1 = BRG enabled
4101          *
4102          * 0110 1001
4103          */
4104         wr_reg8(info, CCR, 0x69);
4105
4106         msc_set_vcr(info);
4107
4108         /* SCR (serial control)
4109          *
4110          * 15  1=tx req on FIFO half empty
4111          * 14  1=rx req on FIFO half full
4112          * 13  tx data  IRQ enable
4113          * 12  tx idle  IRQ enable
4114          * 11  rx break on IRQ enable
4115          * 10  rx data  IRQ enable
4116          * 09  rx break off IRQ enable
4117          * 08  overrun  IRQ enable
4118          * 07  DSR      IRQ enable
4119          * 06  CTS      IRQ enable
4120          * 05  DCD      IRQ enable
4121          * 04  RI       IRQ enable
4122          * 03  reserved, must be zero
4123          * 02  1=txd->rxd internal loopback enable
4124          * 01  reserved, must be zero
4125          * 00  1=master IRQ enable
4126          */
4127         val = BIT15 + BIT14 + BIT0;
4128         wr_reg16(info, SCR, val);
4129
4130         slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4131
4132         set_rate(info, info->params.data_rate * 16);
4133
4134         if (info->params.loopback)
4135                 enable_loopback(info);
4136 }
4137
4138 static void sync_mode(struct slgt_info *info)
4139 {
4140         unsigned short val;
4141
4142         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4143         tx_stop(info);
4144         rx_stop(info);
4145
4146         /* TCR (tx control)
4147          *
4148          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4149          * 12..10  encoding
4150          * 09      CRC enable
4151          * 08      CRC32
4152          * 07      1=RTS driver control
4153          * 06      preamble enable
4154          * 05..04  preamble length
4155          * 03      share open/close flag
4156          * 02      reset
4157          * 01      enable
4158          * 00      auto-CTS enable
4159          */
4160         val = 0;
4161
4162         switch(info->params.mode) {
4163         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4164         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4165         case MGSL_MODE_RAW:      val |= BIT13; break;
4166         }
4167         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4168                 val |= BIT7;
4169
4170         switch(info->params.encoding)
4171         {
4172         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4173         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4174         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4175         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4176         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4177         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4178         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4179         }
4180
4181         switch (info->params.crc_type & HDLC_CRC_MASK)
4182         {
4183         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4184         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4185         }
4186
4187         if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4188                 val |= BIT6;
4189
4190         switch (info->params.preamble_length)
4191         {
4192         case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4193         case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4194         case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4195         }
4196
4197         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4198                 val |= BIT0;
4199
4200         wr_reg16(info, TCR, val);
4201
4202         /* TPR (transmit preamble) */
4203
4204         switch (info->params.preamble)
4205         {
4206         case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4207         case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4208         case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4209         case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4210         case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4211         default:                          val = 0x7e; break;
4212         }
4213         wr_reg8(info, TPR, (unsigned char)val);
4214
4215         /* RCR (rx control)
4216          *
4217          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4218          * 12..10  encoding
4219          * 09      CRC enable
4220          * 08      CRC32
4221          * 07..03  reserved, must be 0
4222          * 02      reset
4223          * 01      enable
4224          * 00      auto-DCD enable
4225          */
4226         val = 0;
4227
4228         switch(info->params.mode) {
4229         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4230         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4231         case MGSL_MODE_RAW:      val |= BIT13; break;
4232         }
4233
4234         switch(info->params.encoding)
4235         {
4236         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4237         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4238         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4239         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4240         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4241         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4242         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4243         }
4244
4245         switch (info->params.crc_type & HDLC_CRC_MASK)
4246         {
4247         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4248         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4249         }
4250
4251         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4252                 val |= BIT0;
4253
4254         wr_reg16(info, RCR, val);
4255
4256         /* CCR (clock control)
4257          *
4258          * 07..05  tx clock source
4259          * 04..02  rx clock source
4260          * 01      auxclk enable
4261          * 00      BRG enable
4262          */
4263         val = 0;
4264
4265         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4266         {
4267                 // when RxC source is DPLL, BRG generates 16X DPLL
4268                 // reference clock, so take TxC from BRG/16 to get
4269                 // transmit clock at actual data rate
4270                 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4271                         val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4272                 else
4273                         val |= BIT6;    /* 010, txclk = BRG */
4274         }
4275         else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4276                 val |= BIT7;    /* 100, txclk = DPLL Input */
4277         else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4278                 val |= BIT5;    /* 001, txclk = RXC Input */
4279
4280         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4281                 val |= BIT3;    /* 010, rxclk = BRG */
4282         else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4283                 val |= BIT4;    /* 100, rxclk = DPLL */
4284         else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4285                 val |= BIT2;    /* 001, rxclk = TXC Input */
4286
4287         if (info->params.clock_speed)
4288                 val |= BIT1 + BIT0;
4289
4290         wr_reg8(info, CCR, (unsigned char)val);
4291
4292         if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4293         {
4294                 // program DPLL mode
4295                 switch(info->params.encoding)
4296                 {
4297                 case HDLC_ENCODING_BIPHASE_MARK:
4298                 case HDLC_ENCODING_BIPHASE_SPACE:
4299                         val = BIT7; break;
4300                 case HDLC_ENCODING_BIPHASE_LEVEL:
4301                 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4302                         val = BIT7 + BIT6; break;
4303                 default: val = BIT6;    // NRZ encodings
4304                 }
4305                 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4306
4307                 // DPLL requires a 16X reference clock from BRG
4308                 set_rate(info, info->params.clock_speed * 16);
4309         }
4310         else
4311                 set_rate(info, info->params.clock_speed);
4312
4313         tx_set_idle(info);
4314
4315         msc_set_vcr(info);
4316
4317         /* SCR (serial control)
4318          *
4319          * 15  1=tx req on FIFO half empty
4320          * 14  1=rx req on FIFO half full
4321          * 13  tx data  IRQ enable
4322          * 12  tx idle  IRQ enable
4323          * 11  underrun IRQ enable
4324          * 10  rx data  IRQ enable
4325          * 09  rx idle  IRQ enable
4326          * 08  overrun  IRQ enable
4327          * 07  DSR      IRQ enable
4328          * 06  CTS      IRQ enable
4329          * 05  DCD      IRQ enable
4330          * 04  RI       IRQ enable
4331          * 03  reserved, must be zero
4332          * 02  1=txd->rxd internal loopback enable
4333          * 01  reserved, must be zero
4334          * 00  1=master IRQ enable
4335          */
4336         wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4337
4338         if (info->params.loopback)
4339                 enable_loopback(info);
4340 }
4341
4342 /*
4343  *  set transmit idle mode
4344  */
4345 static void tx_set_idle(struct slgt_info *info)
4346 {
4347         unsigned char val;
4348         unsigned short tcr;
4349
4350         /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4351          * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4352          */
4353         tcr = rd_reg16(info, TCR);
4354         if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4355                 /* disable preamble, set idle size to 16 bits */
4356                 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4357                 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4358                 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4359         } else if (!(tcr & BIT6)) {
4360                 /* preamble is disabled, set idle size to 8 bits */
4361                 tcr &= ~(BIT5 + BIT4);
4362         }
4363         wr_reg16(info, TCR, tcr);
4364
4365         if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4366                 /* LSB of custom tx idle specified in tx idle register */
4367                 val = (unsigned char)(info->idle_mode & 0xff);
4368         } else {
4369                 /* standard 8 bit idle patterns */
4370                 switch(info->idle_mode)
4371                 {
4372                 case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4373                 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4374                 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4375                 case HDLC_TXIDLE_ZEROS:
4376                 case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4377                 default:                         val = 0xff;
4378                 }
4379         }
4380
4381         wr_reg8(info, TIR, val);
4382 }
4383
4384 /*
4385  * get state of V24 status (input) signals
4386  */
4387 static void get_signals(struct slgt_info *info)
4388 {
4389         unsigned short status = rd_reg16(info, SSR);
4390
4391         /* clear all serial signals except DTR and RTS */
4392         info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4393
4394         if (status & BIT3)
4395                 info->signals |= SerialSignal_DSR;
4396         if (status & BIT2)
4397                 info->signals |= SerialSignal_CTS;
4398         if (status & BIT1)
4399                 info->signals |= SerialSignal_DCD;
4400         if (status & BIT0)
4401                 info->signals |= SerialSignal_RI;
4402 }
4403
4404 /*
4405  * set V.24 Control Register based on current configuration
4406  */
4407 static void msc_set_vcr(struct slgt_info *info)
4408 {
4409         unsigned char val = 0;
4410
4411         /* VCR (V.24 control)
4412          *
4413          * 07..04  serial IF select
4414          * 03      DTR
4415          * 02      RTS
4416          * 01      LL
4417          * 00      RL
4418          */
4419
4420         switch(info->if_mode & MGSL_INTERFACE_MASK)
4421         {
4422         case MGSL_INTERFACE_RS232:
4423                 val |= BIT5; /* 0010 */
4424                 break;
4425         case MGSL_INTERFACE_V35:
4426                 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4427                 break;
4428         case MGSL_INTERFACE_RS422:
4429                 val |= BIT6; /* 0100 */
4430                 break;
4431         }
4432
4433         if (info->signals & SerialSignal_DTR)
4434                 val |= BIT3;
4435         if (info->signals & SerialSignal_RTS)
4436                 val |= BIT2;
4437         if (info->if_mode & MGSL_INTERFACE_LL)
4438                 val |= BIT1;
4439         if (info->if_mode & MGSL_INTERFACE_RL)
4440                 val |= BIT0;
4441         wr_reg8(info, VCR, val);
4442 }
4443
4444 /*
4445  * set state of V24 control (output) signals
4446  */
4447 static void set_signals(struct slgt_info *info)
4448 {
4449         unsigned char val = rd_reg8(info, VCR);
4450         if (info->signals & SerialSignal_DTR)
4451                 val |= BIT3;
4452         else
4453                 val &= ~BIT3;
4454         if (info->signals & SerialSignal_RTS)
4455                 val |= BIT2;
4456         else
4457                 val &= ~BIT2;
4458         wr_reg8(info, VCR, val);
4459 }
4460
4461 /*
4462  * free range of receive DMA buffers (i to last)
4463  */
4464 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4465 {
4466         int done = 0;
4467
4468         while(!done) {
4469                 /* reset current buffer for reuse */
4470                 info->rbufs[i].status = 0;
4471                 switch(info->params.mode) {
4472                 case MGSL_MODE_RAW:
4473                 case MGSL_MODE_MONOSYNC:
4474                 case MGSL_MODE_BISYNC:
4475                         set_desc_count(info->rbufs[i], info->raw_rx_size);
4476                         break;
4477                 default:
4478                         set_desc_count(info->rbufs[i], DMABUFSIZE);
4479                 }
4480
4481                 if (i == last)
4482                         done = 1;
4483                 if (++i == info->rbuf_count)
4484                         i = 0;
4485         }
4486         info->rbuf_current = i;
4487 }
4488
4489 /*
4490  * mark all receive DMA buffers as free
4491  */
4492 static void reset_rbufs(struct slgt_info *info)
4493 {
4494         free_rbufs(info, 0, info->rbuf_count - 1);
4495 }
4496
4497 /*
4498  * pass receive HDLC frame to upper layer
4499  *
4500  * return true if frame available, otherwise false
4501  */
4502 static bool rx_get_frame(struct slgt_info *info)
4503 {
4504         unsigned int start, end;
4505         unsigned short status;
4506         unsigned int framesize = 0;
4507         unsigned long flags;
4508         struct tty_struct *tty = info->tty;
4509         unsigned char addr_field = 0xff;
4510         unsigned int crc_size = 0;
4511
4512         switch (info->params.crc_type & HDLC_CRC_MASK) {
4513         case HDLC_CRC_16_CCITT: crc_size = 2; break;
4514         case HDLC_CRC_32_CCITT: crc_size = 4; break;
4515         }
4516
4517 check_again:
4518
4519         framesize = 0;
4520         addr_field = 0xff;
4521         start = end = info->rbuf_current;
4522
4523         for (;;) {
4524                 if (!desc_complete(info->rbufs[end]))
4525                         goto cleanup;
4526
4527                 if (framesize == 0 && info->params.addr_filter != 0xff)
4528                         addr_field = info->rbufs[end].buf[0];
4529
4530                 framesize += desc_count(info->rbufs[end]);
4531
4532                 if (desc_eof(info->rbufs[end]))
4533                         break;
4534
4535                 if (++end == info->rbuf_count)
4536                         end = 0;
4537
4538                 if (end == info->rbuf_current) {
4539                         if (info->rx_enabled){
4540                                 spin_lock_irqsave(&info->lock,flags);
4541                                 rx_start(info);
4542                                 spin_unlock_irqrestore(&info->lock,flags);
4543                         }
4544                         goto cleanup;
4545                 }
4546         }
4547
4548         /* status
4549          *
4550          * 15      buffer complete
4551          * 14..06  reserved
4552          * 05..04  residue
4553          * 02      eof (end of frame)
4554          * 01      CRC error
4555          * 00      abort
4556          */
4557         status = desc_status(info->rbufs[end]);
4558
4559         /* ignore CRC bit if not using CRC (bit is undefined) */
4560         if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4561                 status &= ~BIT1;
4562
4563         if (framesize == 0 ||
4564                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4565                 free_rbufs(info, start, end);
4566                 goto check_again;
4567         }
4568
4569         if (framesize < (2 + crc_size) || status & BIT0) {
4570                 info->icount.rxshort++;
4571                 framesize = 0;
4572         } else if (status & BIT1) {
4573                 info->icount.rxcrc++;
4574                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4575                         framesize = 0;
4576         }
4577
4578 #if SYNCLINK_GENERIC_HDLC
4579         if (framesize == 0) {
4580                 struct net_device_stats *stats = hdlc_stats(info->netdev);
4581                 stats->rx_errors++;
4582                 stats->rx_frame_errors++;
4583         }
4584 #endif
4585
4586         DBGBH(("%s rx frame status=%04X size=%d\n",
4587                 info->device_name, status, framesize));
4588         DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, DMABUFSIZE), "rx");
4589
4590         if (framesize) {
4591                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4592                         framesize -= crc_size;
4593                         crc_size = 0;
4594                 }
4595
4596                 if (framesize > info->max_frame_size + crc_size)
4597                         info->icount.rxlong++;
4598                 else {
4599                         /* copy dma buffer(s) to contiguous temp buffer */
4600                         int copy_count = framesize;
4601                         int i = start;
4602                         unsigned char *p = info->tmp_rbuf;
4603                         info->tmp_rbuf_count = framesize;
4604
4605                         info->icount.rxok++;
4606
4607                         while(copy_count) {
4608                                 int partial_count = min(copy_count, DMABUFSIZE);
4609                                 memcpy(p, info->rbufs[i].buf, partial_count);
4610                                 p += partial_count;
4611                                 copy_count -= partial_count;
4612                                 if (++i == info->rbuf_count)
4613                                         i = 0;
4614                         }
4615
4616                         if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4617                                 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4618                                 framesize++;
4619                         }
4620
4621 #if SYNCLINK_GENERIC_HDLC
4622                         if (info->netcount)
4623                                 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4624                         else
4625 #endif
4626                                 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4627                 }
4628         }
4629         free_rbufs(info, start, end);
4630         return true;
4631
4632 cleanup:
4633         return false;
4634 }
4635
4636 /*
4637  * pass receive buffer (RAW synchronous mode) to tty layer
4638  * return true if buffer available, otherwise false
4639  */
4640 static bool rx_get_buf(struct slgt_info *info)
4641 {
4642         unsigned int i = info->rbuf_current;
4643         unsigned int count;
4644
4645         if (!desc_complete(info->rbufs[i]))
4646                 return false;
4647         count = desc_count(info->rbufs[i]);
4648         switch(info->params.mode) {
4649         case MGSL_MODE_MONOSYNC:
4650         case MGSL_MODE_BISYNC:
4651                 /* ignore residue in byte synchronous modes */
4652                 if (desc_residue(info->rbufs[i]))
4653                         count--;
4654                 break;
4655         }
4656         DBGDATA(info, info->rbufs[i].buf, count, "rx");
4657         DBGINFO(("rx_get_buf size=%d\n", count));
4658         if (count)
4659                 ldisc_receive_buf(info->tty, info->rbufs[i].buf,
4660                                   info->flag_buf, count);
4661         free_rbufs(info, i, i);
4662         return true;
4663 }
4664
4665 static void reset_tbufs(struct slgt_info *info)
4666 {
4667         unsigned int i;
4668         info->tbuf_current = 0;
4669         for (i=0 ; i < info->tbuf_count ; i++) {
4670                 info->tbufs[i].status = 0;
4671                 info->tbufs[i].count  = 0;
4672         }
4673 }
4674
4675 /*
4676  * return number of free transmit DMA buffers
4677  */
4678 static unsigned int free_tbuf_count(struct slgt_info *info)
4679 {
4680         unsigned int count = 0;
4681         unsigned int i = info->tbuf_current;
4682
4683         do
4684         {
4685                 if (desc_count(info->tbufs[i]))
4686                         break; /* buffer in use */
4687                 ++count;
4688                 if (++i == info->tbuf_count)
4689                         i=0;
4690         } while (i != info->tbuf_current);
4691
4692         /* if tx DMA active, last zero count buffer is in use */
4693         if (count && (rd_reg32(info, TDCSR) & BIT0))
4694                 --count;
4695
4696         return count;
4697 }
4698
4699 /*
4700  * load transmit DMA buffer(s) with data
4701  */
4702 static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4703 {
4704         unsigned short count;
4705         unsigned int i;
4706         struct slgt_desc *d;
4707
4708         if (size == 0)
4709                 return;
4710
4711         DBGDATA(info, buf, size, "tx");
4712
4713         info->tbuf_start = i = info->tbuf_current;
4714
4715         while (size) {
4716                 d = &info->tbufs[i];
4717                 if (++i == info->tbuf_count)
4718                         i = 0;
4719
4720                 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4721                 memcpy(d->buf, buf, count);
4722
4723                 size -= count;
4724                 buf  += count;
4725
4726                 /*
4727                  * set EOF bit for last buffer of HDLC frame or
4728                  * for every buffer in raw mode
4729                  */
4730                 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4731                     info->params.mode == MGSL_MODE_RAW)
4732                         set_desc_eof(*d, 1);
4733                 else
4734                         set_desc_eof(*d, 0);
4735
4736                 set_desc_count(*d, count);
4737         }
4738
4739         info->tbuf_current = i;
4740 }
4741
4742 static int register_test(struct slgt_info *info)
4743 {
4744         static unsigned short patterns[] =
4745                 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4746         static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
4747         unsigned int i;
4748         int rc = 0;
4749
4750         for (i=0 ; i < count ; i++) {
4751                 wr_reg16(info, TIR, patterns[i]);
4752                 wr_reg16(info, BDR, patterns[(i+1)%count]);
4753                 if ((rd_reg16(info, TIR) != patterns[i]) ||
4754                     (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4755                         rc = -ENODEV;
4756                         break;
4757                 }
4758         }
4759         info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4760         info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4761         return rc;
4762 }
4763
4764 static int irq_test(struct slgt_info *info)
4765 {
4766         unsigned long timeout;
4767         unsigned long flags;
4768         struct tty_struct *oldtty = info->tty;
4769         u32 speed = info->params.data_rate;
4770
4771         info->params.data_rate = 921600;
4772         info->tty = NULL;
4773
4774         spin_lock_irqsave(&info->lock, flags);
4775         async_mode(info);
4776         slgt_irq_on(info, IRQ_TXIDLE);
4777
4778         /* enable transmitter */
4779         wr_reg16(info, TCR,
4780                 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4781
4782         /* write one byte and wait for tx idle */
4783         wr_reg16(info, TDR, 0);
4784
4785         /* assume failure */
4786         info->init_error = DiagStatus_IrqFailure;
4787         info->irq_occurred = false;
4788
4789         spin_unlock_irqrestore(&info->lock, flags);
4790
4791         timeout=100;
4792         while(timeout-- && !info->irq_occurred)
4793                 msleep_interruptible(10);
4794
4795         spin_lock_irqsave(&info->lock,flags);
4796         reset_port(info);
4797         spin_unlock_irqrestore(&info->lock,flags);
4798
4799         info->params.data_rate = speed;
4800         info->tty = oldtty;
4801
4802         info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4803         return info->irq_occurred ? 0 : -ENODEV;
4804 }
4805
4806 static int loopback_test_rx(struct slgt_info *info)
4807 {
4808         unsigned char *src, *dest;
4809         int count;
4810
4811         if (desc_complete(info->rbufs[0])) {
4812                 count = desc_count(info->rbufs[0]);
4813                 src   = info->rbufs[0].buf;
4814                 dest  = info->tmp_rbuf;
4815
4816                 for( ; count ; count-=2, src+=2) {
4817                         /* src=data byte (src+1)=status byte */
4818                         if (!(*(src+1) & (BIT9 + BIT8))) {
4819                                 *dest = *src;
4820                                 dest++;
4821                                 info->tmp_rbuf_count++;
4822                         }
4823                 }
4824                 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4825                 return 1;
4826         }
4827         return 0;
4828 }
4829
4830 static int loopback_test(struct slgt_info *info)
4831 {
4832 #define TESTFRAMESIZE 20
4833
4834         unsigned long timeout;
4835         u16 count = TESTFRAMESIZE;
4836         unsigned char buf[TESTFRAMESIZE];
4837         int rc = -ENODEV;
4838         unsigned long flags;
4839
4840         struct tty_struct *oldtty = info->tty;
4841         MGSL_PARAMS params;
4842
4843         memcpy(&params, &info->params, sizeof(params));
4844
4845         info->params.mode = MGSL_MODE_ASYNC;
4846         info->params.data_rate = 921600;
4847         info->params.loopback = 1;
4848         info->tty = NULL;
4849
4850         /* build and send transmit frame */
4851         for (count = 0; count < TESTFRAMESIZE; ++count)
4852                 buf[count] = (unsigned char)count;
4853
4854         info->tmp_rbuf_count = 0;
4855         memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4856
4857         /* program hardware for HDLC and enabled receiver */
4858         spin_lock_irqsave(&info->lock,flags);
4859         async_mode(info);
4860         rx_start(info);
4861         info->tx_count = count;
4862         tx_load(info, buf, count);
4863         tx_start(info);
4864         spin_unlock_irqrestore(&info->lock, flags);
4865
4866         /* wait for receive complete */
4867         for (timeout = 100; timeout; --timeout) {
4868                 msleep_interruptible(10);
4869                 if (loopback_test_rx(info)) {
4870                         rc = 0;
4871                         break;
4872                 }
4873         }
4874
4875         /* verify received frame length and contents */
4876         if (!rc && (info->tmp_rbuf_count != count ||
4877                   memcmp(buf, info->tmp_rbuf, count))) {
4878                 rc = -ENODEV;
4879         }
4880
4881         spin_lock_irqsave(&info->lock,flags);
4882         reset_adapter(info);
4883         spin_unlock_irqrestore(&info->lock,flags);
4884
4885         memcpy(&info->params, &params, sizeof(info->params));
4886         info->tty = oldtty;
4887
4888         info->init_error = rc ? DiagStatus_DmaFailure : 0;
4889         return rc;
4890 }
4891
4892 static int adapter_test(struct slgt_info *info)
4893 {
4894         DBGINFO(("testing %s\n", info->device_name));
4895         if (register_test(info) < 0) {
4896                 printk("register test failure %s addr=%08X\n",
4897                         info->device_name, info->phys_reg_addr);
4898         } else if (irq_test(info) < 0) {
4899                 printk("IRQ test failure %s IRQ=%d\n",
4900                         info->device_name, info->irq_level);
4901         } else if (loopback_test(info) < 0) {
4902                 printk("loopback test failure %s\n", info->device_name);
4903         }
4904         return info->init_error;
4905 }
4906
4907 /*
4908  * transmit timeout handler
4909  */
4910 static void tx_timeout(unsigned long context)
4911 {
4912         struct slgt_info *info = (struct slgt_info*)context;
4913         unsigned long flags;
4914
4915         DBGINFO(("%s tx_timeout\n", info->device_name));
4916         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
4917                 info->icount.txtimeout++;
4918         }
4919         spin_lock_irqsave(&info->lock,flags);
4920         info->tx_active = false;
4921         info->tx_count = 0;
4922         spin_unlock_irqrestore(&info->lock,flags);
4923
4924 #if SYNCLINK_GENERIC_HDLC
4925         if (info->netcount)
4926                 hdlcdev_tx_done(info);
4927         else
4928 #endif
4929                 bh_transmit(info);
4930 }
4931
4932 /*
4933  * receive buffer polling timer
4934  */
4935 static void rx_timeout(unsigned long context)
4936 {
4937         struct slgt_info *info = (struct slgt_info*)context;
4938         unsigned long flags;
4939
4940         DBGINFO(("%s rx_timeout\n", info->device_name));
4941         spin_lock_irqsave(&info->lock, flags);
4942         info->pending_bh |= BH_RECEIVE;
4943         spin_unlock_irqrestore(&info->lock, flags);
4944         bh_handler(&info->task);
4945 }
4946