git.oblomov.eu Git - linux-2.6/blob - drivers/net/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey.
   7  *
   8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
   9  * trademarks of NVIDIA Corporation in the United States and other
  10  * countries.
  11  *
  12  * Copyright (C) 2003,4,5 Manfred Spraul
  13  * Copyright (C) 2004 Andrew de Quincey (wol support)
  14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  16  * Copyright (c) 2004,2005,2006,2007,2008 NVIDIA Corporation
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License as published by
  20  * the Free Software Foundation; either version 2 of the License, or
  21  * (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, write to the Free Software
  30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  31  *
  32  * Known bugs:
  33  * We suspect that on some hardware no TX done interrupts are generated.
  34  * This means recovery from netif_stop_queue only happens if the hw timer
  35  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
  36  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
  37  * If your hardware reliably generates tx done interrupts, then you can remove
  38  * DEV_NEED_TIMERIRQ from the driver_data flags.
  39  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
  40  * superfluous timer interrupts from the nic.
  41  */
  42 #define FORCEDETH_VERSION               "0.61"
  43 #define DRV_NAME                        "forcedeth"
  44
  45 #include <linux/module.h>
  46 #include <linux/types.h>
  47 #include <linux/pci.h>
  48 #include <linux/interrupt.h>
  49 #include <linux/netdevice.h>
  50 #include <linux/etherdevice.h>
  51 #include <linux/delay.h>
  52 #include <linux/spinlock.h>
  53 #include <linux/ethtool.h>
  54 #include <linux/timer.h>
  55 #include <linux/skbuff.h>
  56 #include <linux/mii.h>
  57 #include <linux/random.h>
  58 #include <linux/init.h>
  59 #include <linux/if_vlan.h>
  60 #include <linux/dma-mapping.h>
  61
  62 #include <asm/irq.h>
  63 #include <asm/io.h>
  64 #include <asm/uaccess.h>
  65 #include <asm/system.h>
  66
  67 #if 0
  68 #define dprintk                 printk
  69 #else
  70 #define dprintk(x...)           do { } while (0)
  71 #endif
  72
  73 #define TX_WORK_PER_LOOP  64
  74 #define RX_WORK_PER_LOOP  64
  75
  76 /*
  77  * Hardware access:
  78  */
  79
  80 #define DEV_NEED_TIMERIRQ          0x000001  /* set the timer irq flag in the irq mask */
  81 #define DEV_NEED_LINKTIMER         0x000002  /* poll link settings. Relies on the timer irq */
  82 #define DEV_HAS_LARGEDESC          0x000004  /* device supports jumbo frames and needs packet format 2 */
  83 #define DEV_HAS_HIGH_DMA           0x000008  /* device supports 64bit dma */
  84 #define DEV_HAS_CHECKSUM           0x000010  /* device supports tx and rx checksum offloads */
  85 #define DEV_HAS_VLAN               0x000020  /* device supports vlan tagging and striping */
  86 #define DEV_HAS_MSI                0x000040  /* device supports MSI */
  87 #define DEV_HAS_MSI_X              0x000080  /* device supports MSI-X */
  88 #define DEV_HAS_POWER_CNTRL        0x000100  /* device supports power savings */
  89 #define DEV_HAS_STATISTICS_V1      0x000200  /* device supports hw statistics version 1 */
  90 #define DEV_HAS_STATISTICS_V2      0x000400  /* device supports hw statistics version 2 */
  91 #define DEV_HAS_STATISTICS_V3      0x000800  /* device supports hw statistics version 3 */
  92 #define DEV_HAS_TEST_EXTENDED      0x001000  /* device supports extended diagnostic test */
  93 #define DEV_HAS_MGMT_UNIT          0x002000  /* device supports management unit */
  94 #define DEV_HAS_CORRECT_MACADDR    0x004000  /* device supports correct mac address order */
  95 #define DEV_HAS_COLLISION_FIX      0x008000  /* device supports tx collision fix */
  96 #define DEV_HAS_PAUSEFRAME_TX_V1   0x010000  /* device supports tx pause frames version 1 */
  97 #define DEV_HAS_PAUSEFRAME_TX_V2   0x020000  /* device supports tx pause frames version 2 */
  98 #define DEV_HAS_PAUSEFRAME_TX_V3   0x040000  /* device supports tx pause frames version 3 */
  99 #define DEV_NEED_TX_LIMIT          0x080000  /* device needs to limit tx */
 100 #define DEV_HAS_GEAR_MODE          0x100000  /* device supports gear mode */
 101
 102 enum {
 103         NvRegIrqStatus = 0x000,
 104 #define NVREG_IRQSTAT_MIIEVENT  0x040
 105 #define NVREG_IRQSTAT_MASK              0x81ff
 106         NvRegIrqMask = 0x004,
 107 #define NVREG_IRQ_RX_ERROR              0x0001
 108 #define NVREG_IRQ_RX                    0x0002
 109 #define NVREG_IRQ_RX_NOBUF              0x0004
 110 #define NVREG_IRQ_TX_ERR                0x0008
 111 #define NVREG_IRQ_TX_OK                 0x0010
 112 #define NVREG_IRQ_TIMER                 0x0020
 113 #define NVREG_IRQ_LINK                  0x0040
 114 #define NVREG_IRQ_RX_FORCED             0x0080
 115 #define NVREG_IRQ_TX_FORCED             0x0100
 116 #define NVREG_IRQ_RECOVER_ERROR         0x8000
 117 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 118 #define NVREG_IRQMASK_CPU               0x0060
 119 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 120 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
 121 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
 122
 123 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
 124                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
 125                                         NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
 126
 127         NvRegUnknownSetupReg6 = 0x008,
 128 #define NVREG_UNKSETUP6_VAL             3
 129
 130 /*
 131  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 132  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 133  */
 134         NvRegPollingInterval = 0x00c,
 135 #define NVREG_POLL_DEFAULT_THROUGHPUT   970 /* backup tx cleanup if loop max reached */
 136 #define NVREG_POLL_DEFAULT_CPU  13
 137         NvRegMSIMap0 = 0x020,
 138         NvRegMSIMap1 = 0x024,
 139         NvRegMSIIrqMask = 0x030,
 140 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
 141         NvRegMisc1 = 0x080,
 142 #define NVREG_MISC1_PAUSE_TX    0x01
 143 #define NVREG_MISC1_HD          0x02
 144 #define NVREG_MISC1_FORCE       0x3b0f3c
 145
 146         NvRegMacReset = 0x34,
 147 #define NVREG_MAC_RESET_ASSERT  0x0F3
 148         NvRegTransmitterControl = 0x084,
 149 #define NVREG_XMITCTL_START     0x01
 150 #define NVREG_XMITCTL_MGMT_ST   0x40000000
 151 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
 152 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
 153 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
 154 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
 155 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
 156 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
 157 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
 158 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
 159 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
 160         NvRegTransmitterStatus = 0x088,
 161 #define NVREG_XMITSTAT_BUSY     0x01
 162
 163         NvRegPacketFilterFlags = 0x8c,
 164 #define NVREG_PFF_PAUSE_RX      0x08
 165 #define NVREG_PFF_ALWAYS        0x7F0000
 166 #define NVREG_PFF_PROMISC       0x80
 167 #define NVREG_PFF_MYADDR        0x20
 168 #define NVREG_PFF_LOOPBACK      0x10
 169
 170         NvRegOffloadConfig = 0x90,
 171 #define NVREG_OFFLOAD_HOMEPHY   0x601
 172 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 173         NvRegReceiverControl = 0x094,
 174 #define NVREG_RCVCTL_START      0x01
 175 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
 176         NvRegReceiverStatus = 0x98,
 177 #define NVREG_RCVSTAT_BUSY      0x01
 178
 179         NvRegSlotTime = 0x9c,
 180 #define NVREG_SLOTTIME_LEGBF_ENABLED    0x80000000
 181 #define NVREG_SLOTTIME_10_100_FULL      0x00007f00
 182 #define NVREG_SLOTTIME_1000_FULL        0x0003ff00
 183 #define NVREG_SLOTTIME_HALF             0x0000ff00
 184 #define NVREG_SLOTTIME_DEFAULT          0x00007f00
 185 #define NVREG_SLOTTIME_MASK             0x000000ff
 186
 187         NvRegTxDeferral = 0xA0,
 188 #define NVREG_TX_DEFERRAL_DEFAULT               0x15050f
 189 #define NVREG_TX_DEFERRAL_RGMII_10_100          0x16070f
 190 #define NVREG_TX_DEFERRAL_RGMII_1000            0x14050f
 191 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10      0x16190f
 192 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100     0x16300f
 193 #define NVREG_TX_DEFERRAL_MII_STRETCH           0x152000
 194         NvRegRxDeferral = 0xA4,
 195 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
 196         NvRegMacAddrA = 0xA8,
 197         NvRegMacAddrB = 0xAC,
 198         NvRegMulticastAddrA = 0xB0,
 199 #define NVREG_MCASTADDRA_FORCE  0x01
 200         NvRegMulticastAddrB = 0xB4,
 201         NvRegMulticastMaskA = 0xB8,
 202 #define NVREG_MCASTMASKA_NONE           0xffffffff
 203         NvRegMulticastMaskB = 0xBC,
 204 #define NVREG_MCASTMASKB_NONE           0xffff
 205
 206         NvRegPhyInterface = 0xC0,
 207 #define PHY_RGMII               0x10000000
 208         NvRegBackOffControl = 0xC4,
 209 #define NVREG_BKOFFCTRL_DEFAULT                 0x70000000
 210 #define NVREG_BKOFFCTRL_SEED_MASK               0x000003ff
 211 #define NVREG_BKOFFCTRL_SELECT                  24
 212 #define NVREG_BKOFFCTRL_GEAR                    12
 213
 214         NvRegTxRingPhysAddr = 0x100,
 215         NvRegRxRingPhysAddr = 0x104,
 216         NvRegRingSizes = 0x108,
 217 #define NVREG_RINGSZ_TXSHIFT 0
 218 #define NVREG_RINGSZ_RXSHIFT 16
 219         NvRegTransmitPoll = 0x10c,
 220 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
 221         NvRegLinkSpeed = 0x110,
 222 #define NVREG_LINKSPEED_FORCE 0x10000
 223 #define NVREG_LINKSPEED_10      1000
 224 #define NVREG_LINKSPEED_100     100
 225 #define NVREG_LINKSPEED_1000    50
 226 #define NVREG_LINKSPEED_MASK    (0xFFF)
 227         NvRegUnknownSetupReg5 = 0x130,
 228 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 229         NvRegTxWatermark = 0x13c,
 230 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
 231 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
 232 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
 233         NvRegTxRxControl = 0x144,
 234 #define NVREG_TXRXCTL_KICK      0x0001
 235 #define NVREG_TXRXCTL_BIT1      0x0002
 236 #define NVREG_TXRXCTL_BIT2      0x0004
 237 #define NVREG_TXRXCTL_IDLE      0x0008
 238 #define NVREG_TXRXCTL_RESET     0x0010
 239 #define NVREG_TXRXCTL_RXCHECK   0x0400
 240 #define NVREG_TXRXCTL_DESC_1    0
 241 #define NVREG_TXRXCTL_DESC_2    0x002100
 242 #define NVREG_TXRXCTL_DESC_3    0xc02200
 243 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
 244 #define NVREG_TXRXCTL_VLANINS   0x00080
 245         NvRegTxRingPhysAddrHigh = 0x148,
 246         NvRegRxRingPhysAddrHigh = 0x14C,
 247         NvRegTxPauseFrame = 0x170,
 248 #define NVREG_TX_PAUSEFRAME_DISABLE     0x0fff0080
 249 #define NVREG_TX_PAUSEFRAME_ENABLE_V1   0x01800010
 250 #define NVREG_TX_PAUSEFRAME_ENABLE_V2   0x056003f0
 251 #define NVREG_TX_PAUSEFRAME_ENABLE_V3   0x09f00880
 252         NvRegTxPauseFrameLimit = 0x174,
 253 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
 254         NvRegMIIStatus = 0x180,
 255 #define NVREG_MIISTAT_ERROR             0x0001
 256 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 257 #define NVREG_MIISTAT_MASK_RW           0x0007
 258 #define NVREG_MIISTAT_MASK_ALL          0x000f
 259         NvRegMIIMask = 0x184,
 260 #define NVREG_MII_LINKCHANGE            0x0008
 261
 262         NvRegAdapterControl = 0x188,
 263 #define NVREG_ADAPTCTL_START    0x02
 264 #define NVREG_ADAPTCTL_LINKUP   0x04
 265 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 266 #define NVREG_ADAPTCTL_RUNNING  0x100000
 267 #define NVREG_ADAPTCTL_PHYSHIFT 24
 268         NvRegMIISpeed = 0x18c,
 269 #define NVREG_MIISPEED_BIT8     (1<<8)
 270 #define NVREG_MIIDELAY  5
 271         NvRegMIIControl = 0x190,
 272 #define NVREG_MIICTL_INUSE      0x08000
 273 #define NVREG_MIICTL_WRITE      0x00400
 274 #define NVREG_MIICTL_ADDRSHIFT  5
 275         NvRegMIIData = 0x194,
 276         NvRegTxUnicast = 0x1a0,
 277         NvRegTxMulticast = 0x1a4,
 278         NvRegTxBroadcast = 0x1a8,
 279         NvRegWakeUpFlags = 0x200,
 280 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 281 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 282 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 283 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 284 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 285 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 286 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 287 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 288 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 289 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 290 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 291
 292         NvRegPatternCRC = 0x204,
 293         NvRegPatternMask = 0x208,
 294         NvRegPowerCap = 0x268,
 295 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 296 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 297 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 298         NvRegPowerState = 0x26c,
 299 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 300 #define NVREG_POWERSTATE_VALID          0x0100
 301 #define NVREG_POWERSTATE_MASK           0x0003
 302 #define NVREG_POWERSTATE_D0             0x0000
 303 #define NVREG_POWERSTATE_D1             0x0001
 304 #define NVREG_POWERSTATE_D2             0x0002
 305 #define NVREG_POWERSTATE_D3             0x0003
 306         NvRegTxCnt = 0x280,
 307         NvRegTxZeroReXmt = 0x284,
 308         NvRegTxOneReXmt = 0x288,
 309         NvRegTxManyReXmt = 0x28c,
 310         NvRegTxLateCol = 0x290,
 311         NvRegTxUnderflow = 0x294,
 312         NvRegTxLossCarrier = 0x298,
 313         NvRegTxExcessDef = 0x29c,
 314         NvRegTxRetryErr = 0x2a0,
 315         NvRegRxFrameErr = 0x2a4,
 316         NvRegRxExtraByte = 0x2a8,
 317         NvRegRxLateCol = 0x2ac,
 318         NvRegRxRunt = 0x2b0,
 319         NvRegRxFrameTooLong = 0x2b4,
 320         NvRegRxOverflow = 0x2b8,
 321         NvRegRxFCSErr = 0x2bc,
 322         NvRegRxFrameAlignErr = 0x2c0,
 323         NvRegRxLenErr = 0x2c4,
 324         NvRegRxUnicast = 0x2c8,
 325         NvRegRxMulticast = 0x2cc,
 326         NvRegRxBroadcast = 0x2d0,
 327         NvRegTxDef = 0x2d4,
 328         NvRegTxFrame = 0x2d8,
 329         NvRegRxCnt = 0x2dc,
 330         NvRegTxPause = 0x2e0,
 331         NvRegRxPause = 0x2e4,
 332         NvRegRxDropFrame = 0x2e8,
 333         NvRegVlanControl = 0x300,
 334 #define NVREG_VLANCONTROL_ENABLE        0x2000
 335         NvRegMSIXMap0 = 0x3e0,
 336         NvRegMSIXMap1 = 0x3e4,
 337         NvRegMSIXIrqStatus = 0x3f0,
 338
 339         NvRegPowerState2 = 0x600,
 340 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F15
 341 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
 342 #define NVREG_POWERSTATE2_PHY_RESET             0x0004
 343 };
 344
 345 /* Big endian: should work, but is untested */
 346 struct ring_desc {
 347         __le32 buf;
 348         __le32 flaglen;
 349 };
 350
 351 struct ring_desc_ex {
 352         __le32 bufhigh;
 353         __le32 buflow;
 354         __le32 txvlan;
 355         __le32 flaglen;
 356 };
 357
 358 union ring_type {
 359         struct ring_desc* orig;
 360         struct ring_desc_ex* ex;
 361 };
 362
 363 #define FLAG_MASK_V1 0xffff0000
 364 #define FLAG_MASK_V2 0xffffc000
 365 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 366 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 367
 368 #define NV_TX_LASTPACKET        (1<<16)
 369 #define NV_TX_RETRYERROR        (1<<19)
 370 #define NV_TX_RETRYCOUNT_MASK   (0xF<<20)
 371 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 372 #define NV_TX_DEFERRED          (1<<26)
 373 #define NV_TX_CARRIERLOST       (1<<27)
 374 #define NV_TX_LATECOLLISION     (1<<28)
 375 #define NV_TX_UNDERFLOW         (1<<29)
 376 #define NV_TX_ERROR             (1<<30)
 377 #define NV_TX_VALID             (1<<31)
 378
 379 #define NV_TX2_LASTPACKET       (1<<29)
 380 #define NV_TX2_RETRYERROR       (1<<18)
 381 #define NV_TX2_RETRYCOUNT_MASK  (0xF<<19)
 382 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 383 #define NV_TX2_DEFERRED         (1<<25)
 384 #define NV_TX2_CARRIERLOST      (1<<26)
 385 #define NV_TX2_LATECOLLISION    (1<<27)
 386 #define NV_TX2_UNDERFLOW        (1<<28)
 387 /* error and valid are the same for both */
 388 #define NV_TX2_ERROR            (1<<30)
 389 #define NV_TX2_VALID            (1<<31)
 390 #define NV_TX2_TSO              (1<<28)
 391 #define NV_TX2_TSO_SHIFT        14
 392 #define NV_TX2_TSO_MAX_SHIFT    14
 393 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 394 #define NV_TX2_CHECKSUM_L3      (1<<27)
 395 #define NV_TX2_CHECKSUM_L4      (1<<26)
 396
 397 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 398
 399 #define NV_RX_DESCRIPTORVALID   (1<<16)
 400 #define NV_RX_MISSEDFRAME       (1<<17)
 401 #define NV_RX_SUBSTRACT1        (1<<18)
 402 #define NV_RX_ERROR1            (1<<23)
 403 #define NV_RX_ERROR2            (1<<24)
 404 #define NV_RX_ERROR3            (1<<25)
 405 #define NV_RX_ERROR4            (1<<26)
 406 #define NV_RX_CRCERR            (1<<27)
 407 #define NV_RX_OVERFLOW          (1<<28)
 408 #define NV_RX_FRAMINGERR        (1<<29)
 409 #define NV_RX_ERROR             (1<<30)
 410 #define NV_RX_AVAIL             (1<<31)
 411 #define NV_RX_ERROR_MASK        (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
 412
 413 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 414 #define NV_RX2_CHECKSUM_IP      (0x10000000)
 415 #define NV_RX2_CHECKSUM_IP_TCP  (0x14000000)
 416 #define NV_RX2_CHECKSUM_IP_UDP  (0x18000000)
 417 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 418 #define NV_RX2_SUBSTRACT1       (1<<25)
 419 #define NV_RX2_ERROR1           (1<<18)
 420 #define NV_RX2_ERROR2           (1<<19)
 421 #define NV_RX2_ERROR3           (1<<20)
 422 #define NV_RX2_ERROR4           (1<<21)
 423 #define NV_RX2_CRCERR           (1<<22)
 424 #define NV_RX2_OVERFLOW         (1<<23)
 425 #define NV_RX2_FRAMINGERR       (1<<24)
 426 /* error and avail are the same for both */
 427 #define NV_RX2_ERROR            (1<<30)
 428 #define NV_RX2_AVAIL            (1<<31)
 429 #define NV_RX2_ERROR_MASK       (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
 430
 431 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 432 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 433
 434 /* Miscelaneous hardware related defines: */
 435 #define NV_PCI_REGSZ_VER1       0x270
 436 #define NV_PCI_REGSZ_VER2       0x2d4
 437 #define NV_PCI_REGSZ_VER3       0x604
 438 #define NV_PCI_REGSZ_MAX        0x604
 439
 440 /* various timeout delays: all in usec */
 441 #define NV_TXRX_RESET_DELAY     4
 442 #define NV_TXSTOP_DELAY1        10
 443 #define NV_TXSTOP_DELAY1MAX     500000
 444 #define NV_TXSTOP_DELAY2        100
 445 #define NV_RXSTOP_DELAY1        10
 446 #define NV_RXSTOP_DELAY1MAX     500000
 447 #define NV_RXSTOP_DELAY2        100
 448 #define NV_SETUP5_DELAY         5
 449 #define NV_SETUP5_DELAYMAX      50000
 450 #define NV_POWERUP_DELAY        5
 451 #define NV_POWERUP_DELAYMAX     5000
 452 #define NV_MIIBUSY_DELAY        50
 453 #define NV_MIIPHY_DELAY 10
 454 #define NV_MIIPHY_DELAYMAX      10000
 455 #define NV_MAC_RESET_DELAY      64
 456
 457 #define NV_WAKEUPPATTERNS       5
 458 #define NV_WAKEUPMASKENTRIES    4
 459
 460 /* General driver defaults */
 461 #define NV_WATCHDOG_TIMEO       (5*HZ)
 462
 463 #define RX_RING_DEFAULT         128
 464 #define TX_RING_DEFAULT         256
 465 #define RX_RING_MIN             128
 466 #define TX_RING_MIN             64
 467 #define RING_MAX_DESC_VER_1     1024
 468 #define RING_MAX_DESC_VER_2_3   16384
 469
 470 /* rx/tx mac addr + type + vlan + align + slack*/
 471 #define NV_RX_HEADERS           (64)
 472 /* even more slack. */
 473 #define NV_RX_ALLOC_PAD         (64)
 474
 475 /* maximum mtu size */
 476 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 477 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 478
 479 #define OOM_REFILL      (1+HZ/20)
 480 #define POLL_WAIT       (1+HZ/100)
 481 #define LINK_TIMEOUT    (3*HZ)
 482 #define STATS_INTERVAL  (10*HZ)
 483
 484 /*
 485  * desc_ver values:
 486  * The nic supports three different descriptor types:
 487  * - DESC_VER_1: Original
 488  * - DESC_VER_2: support for jumbo frames.
 489  * - DESC_VER_3: 64-bit format.
 490  */
 491 #define DESC_VER_1      1
 492 #define DESC_VER_2      2
 493 #define DESC_VER_3      3
 494
 495 /* PHY defines */
 496 #define PHY_OUI_MARVELL         0x5043
 497 #define PHY_OUI_CICADA          0x03f1
 498 #define PHY_OUI_VITESSE         0x01c1
 499 #define PHY_OUI_REALTEK         0x0732
 500 #define PHY_OUI_REALTEK2        0x0020
 501 #define PHYID1_OUI_MASK 0x03ff
 502 #define PHYID1_OUI_SHFT 6
 503 #define PHYID2_OUI_MASK 0xfc00
 504 #define PHYID2_OUI_SHFT 10
 505 #define PHYID2_MODEL_MASK               0x03f0
 506 #define PHY_MODEL_REALTEK_8211          0x0110
 507 #define PHY_REV_MASK                    0x0001
 508 #define PHY_REV_REALTEK_8211B           0x0000
 509 #define PHY_REV_REALTEK_8211C           0x0001
 510 #define PHY_MODEL_REALTEK_8201          0x0200
 511 #define PHY_MODEL_MARVELL_E3016         0x0220
 512 #define PHY_MARVELL_E3016_INITMASK      0x0300
 513 #define PHY_CICADA_INIT1        0x0f000
 514 #define PHY_CICADA_INIT2        0x0e00
 515 #define PHY_CICADA_INIT3        0x01000
 516 #define PHY_CICADA_INIT4        0x0200
 517 #define PHY_CICADA_INIT5        0x0004
 518 #define PHY_CICADA_INIT6        0x02000
 519 #define PHY_VITESSE_INIT_REG1   0x1f
 520 #define PHY_VITESSE_INIT_REG2   0x10
 521 #define PHY_VITESSE_INIT_REG3   0x11
 522 #define PHY_VITESSE_INIT_REG4   0x12
 523 #define PHY_VITESSE_INIT_MSK1   0xc
 524 #define PHY_VITESSE_INIT_MSK2   0x0180
 525 #define PHY_VITESSE_INIT1       0x52b5
 526 #define PHY_VITESSE_INIT2       0xaf8a
 527 #define PHY_VITESSE_INIT3       0x8
 528 #define PHY_VITESSE_INIT4       0x8f8a
 529 #define PHY_VITESSE_INIT5       0xaf86
 530 #define PHY_VITESSE_INIT6       0x8f86
 531 #define PHY_VITESSE_INIT7       0xaf82
 532 #define PHY_VITESSE_INIT8       0x0100
 533 #define PHY_VITESSE_INIT9       0x8f82
 534 #define PHY_VITESSE_INIT10      0x0
 535 #define PHY_REALTEK_INIT_REG1   0x1f
 536 #define PHY_REALTEK_INIT_REG2   0x19
 537 #define PHY_REALTEK_INIT_REG3   0x13
 538 #define PHY_REALTEK_INIT_REG4   0x14
 539 #define PHY_REALTEK_INIT_REG5   0x18
 540 #define PHY_REALTEK_INIT_REG6   0x11
 541 #define PHY_REALTEK_INIT_REG7   0x01
 542 #define PHY_REALTEK_INIT1       0x0000
 543 #define PHY_REALTEK_INIT2       0x8e00
 544 #define PHY_REALTEK_INIT3       0x0001
 545 #define PHY_REALTEK_INIT4       0xad17
 546 #define PHY_REALTEK_INIT5       0xfb54
 547 #define PHY_REALTEK_INIT6       0xf5c7
 548 #define PHY_REALTEK_INIT7       0x1000
 549 #define PHY_REALTEK_INIT8       0x0003
 550 #define PHY_REALTEK_INIT9       0x0008
 551 #define PHY_REALTEK_INIT10      0x0005
 552 #define PHY_REALTEK_INIT11      0x0200
 553 #define PHY_REALTEK_INIT_MSK1   0x0003
 554
 555 #define PHY_GIGABIT     0x0100
 556
 557 #define PHY_TIMEOUT     0x1
 558 #define PHY_ERROR       0x2
 559
 560 #define PHY_100 0x1
 561 #define PHY_1000        0x2
 562 #define PHY_HALF        0x100
 563
 564 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
 565 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
 566 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
 567 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
 568 #define NV_PAUSEFRAME_RX_REQ     0x0010
 569 #define NV_PAUSEFRAME_TX_REQ     0x0020
 570 #define NV_PAUSEFRAME_AUTONEG    0x0040
 571
 572 /* MSI/MSI-X defines */
 573 #define NV_MSI_X_MAX_VECTORS  8
 574 #define NV_MSI_X_VECTORS_MASK 0x000f
 575 #define NV_MSI_CAPABLE        0x0010
 576 #define NV_MSI_X_CAPABLE      0x0020
 577 #define NV_MSI_ENABLED        0x0040
 578 #define NV_MSI_X_ENABLED      0x0080
 579
 580 #define NV_MSI_X_VECTOR_ALL   0x0
 581 #define NV_MSI_X_VECTOR_RX    0x0
 582 #define NV_MSI_X_VECTOR_TX    0x1
 583 #define NV_MSI_X_VECTOR_OTHER 0x2
 584
 585 #define NV_RESTART_TX         0x1
 586 #define NV_RESTART_RX         0x2
 587
 588 #define NV_TX_LIMIT_COUNT     16
 589
 590 /* statistics */
 591 struct nv_ethtool_str {
 592         char name[ETH_GSTRING_LEN];
 593 };
 594
 595 static const struct nv_ethtool_str nv_estats_str[] = {
 596         { "tx_bytes" },
 597         { "tx_zero_rexmt" },
 598         { "tx_one_rexmt" },
 599         { "tx_many_rexmt" },
 600         { "tx_late_collision" },
 601         { "tx_fifo_errors" },
 602         { "tx_carrier_errors" },
 603         { "tx_excess_deferral" },
 604         { "tx_retry_error" },
 605         { "rx_frame_error" },
 606         { "rx_extra_byte" },
 607         { "rx_late_collision" },
 608         { "rx_runt" },
 609         { "rx_frame_too_long" },
 610         { "rx_over_errors" },
 611         { "rx_crc_errors" },
 612         { "rx_frame_align_error" },
 613         { "rx_length_error" },
 614         { "rx_unicast" },
 615         { "rx_multicast" },
 616         { "rx_broadcast" },
 617         { "rx_packets" },
 618         { "rx_errors_total" },
 619         { "tx_errors_total" },
 620
 621         /* version 2 stats */
 622         { "tx_deferral" },
 623         { "tx_packets" },
 624         { "rx_bytes" },
 625         { "tx_pause" },
 626         { "rx_pause" },
 627         { "rx_drop_frame" },
 628
 629         /* version 3 stats */
 630         { "tx_unicast" },
 631         { "tx_multicast" },
 632         { "tx_broadcast" }
 633 };
 634
 635 struct nv_ethtool_stats {
 636         u64 tx_bytes;
 637         u64 tx_zero_rexmt;
 638         u64 tx_one_rexmt;
 639         u64 tx_many_rexmt;
 640         u64 tx_late_collision;
 641         u64 tx_fifo_errors;
 642         u64 tx_carrier_errors;
 643         u64 tx_excess_deferral;
 644         u64 tx_retry_error;
 645         u64 rx_frame_error;
 646         u64 rx_extra_byte;
 647         u64 rx_late_collision;
 648         u64 rx_runt;
 649         u64 rx_frame_too_long;
 650         u64 rx_over_errors;
 651         u64 rx_crc_errors;
 652         u64 rx_frame_align_error;
 653         u64 rx_length_error;
 654         u64 rx_unicast;
 655         u64 rx_multicast;
 656         u64 rx_broadcast;
 657         u64 rx_packets;
 658         u64 rx_errors_total;
 659         u64 tx_errors_total;
 660
 661         /* version 2 stats */
 662         u64 tx_deferral;
 663         u64 tx_packets;
 664         u64 rx_bytes;
 665         u64 tx_pause;
 666         u64 rx_pause;
 667         u64 rx_drop_frame;
 668
 669         /* version 3 stats */
 670         u64 tx_unicast;
 671         u64 tx_multicast;
 672         u64 tx_broadcast;
 673 };
 674
 675 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
 676 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
 677 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
 678
 679 /* diagnostics */
 680 #define NV_TEST_COUNT_BASE 3
 681 #define NV_TEST_COUNT_EXTENDED 4
 682
 683 static const struct nv_ethtool_str nv_etests_str[] = {
 684         { "link      (online/offline)" },
 685         { "register  (offline)       " },
 686         { "interrupt (offline)       " },
 687         { "loopback  (offline)       " }
 688 };
 689
 690 struct register_test {
 691         __u32 reg;
 692         __u32 mask;
 693 };
 694
 695 static const struct register_test nv_registers_test[] = {
 696         { NvRegUnknownSetupReg6, 0x01 },
 697         { NvRegMisc1, 0x03c },
 698         { NvRegOffloadConfig, 0x03ff },
 699         { NvRegMulticastAddrA, 0xffffffff },
 700         { NvRegTxWatermark, 0x0ff },
 701         { NvRegWakeUpFlags, 0x07777 },
 702         { 0,0 }
 703 };
 704
 705 struct nv_skb_map {
 706         struct sk_buff *skb;
 707         dma_addr_t dma;
 708         unsigned int dma_len;
 709         struct ring_desc_ex *first_tx_desc;
 710         struct nv_skb_map *next_tx_ctx;
 711 };
 712
 713 /*
 714  * SMP locking:
 715  * All hardware access under netdev_priv(dev)->lock, except the performance
 716  * critical parts:
 717  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 718  *      by the arch code for interrupts.
 719  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
 720  *      needs netdev_priv(dev)->lock :-(
 721  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
 722  */
 723
 724 /* in dev: base, irq */
 725 struct fe_priv {
 726         spinlock_t lock;
 727
 728         struct net_device *dev;
 729         struct napi_struct napi;
 730
 731         /* General data:
 732          * Locking: spin_lock(&np->lock); */
 733         struct nv_ethtool_stats estats;
 734         int in_shutdown;
 735         u32 linkspeed;
 736         int duplex;
 737         int autoneg;
 738         int fixed_mode;
 739         int phyaddr;
 740         int wolenabled;
 741         unsigned int phy_oui;
 742         unsigned int phy_model;
 743         unsigned int phy_rev;
 744         u16 gigabit;
 745         int intr_test;
 746         int recover_error;
 747
 748         /* General data: RO fields */
 749         dma_addr_t ring_addr;
 750         struct pci_dev *pci_dev;
 751         u32 orig_mac[2];
 752         u32 irqmask;
 753         u32 desc_ver;
 754         u32 txrxctl_bits;
 755         u32 vlanctl_bits;
 756         u32 driver_data;
 757         u32 device_id;
 758         u32 register_size;
 759         int rx_csum;
 760         u32 mac_in_use;
 761
 762         void __iomem *base;
 763
 764         /* rx specific fields.
 765          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 766          */
 767         union ring_type get_rx, put_rx, first_rx, last_rx;
 768         struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
 769         struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
 770         struct nv_skb_map *rx_skb;
 771
 772         union ring_type rx_ring;
 773         unsigned int rx_buf_sz;
 774         unsigned int pkt_limit;
 775         struct timer_list oom_kick;
 776         struct timer_list nic_poll;
 777         struct timer_list stats_poll;
 778         u32 nic_poll_irq;
 779         int rx_ring_size;
 780
 781         /* media detection workaround.
 782          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 783          */
 784         int need_linktimer;
 785         unsigned long link_timeout;
 786         /*
 787          * tx specific fields.
 788          */
 789         union ring_type get_tx, put_tx, first_tx, last_tx;
 790         struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
 791         struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
 792         struct nv_skb_map *tx_skb;
 793
 794         union ring_type tx_ring;
 795         u32 tx_flags;
 796         int tx_ring_size;
 797         int tx_limit;
 798         u32 tx_pkts_in_progress;
 799         struct nv_skb_map *tx_change_owner;
 800         struct nv_skb_map *tx_end_flip;
 801         int tx_stop;
 802
 803         /* vlan fields */
 804         struct vlan_group *vlangrp;
 805
 806         /* msi/msi-x fields */
 807         u32 msi_flags;
 808         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
 809
 810         /* flow control */
 811         u32 pause_flags;
 812
 813         /* power saved state */
 814         u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
 815 };
 816
 817 /*
 818  * Maximum number of loops until we assume that a bit in the irq mask
 819  * is stuck. Overridable with module param.
 820  */
 821 static int max_interrupt_work = 15;
 822
 823 /*
 824  * Optimization can be either throuput mode or cpu mode
 825  *
 826  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 827  * CPU Mode: Interrupts are controlled by a timer.
 828  */
 829 enum {
 830         NV_OPTIMIZATION_MODE_THROUGHPUT,
 831         NV_OPTIMIZATION_MODE_CPU
 832 };
 833 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
 834
 835 /*
 836  * Poll interval for timer irq
 837  *
 838  * This interval determines how frequent an interrupt is generated.
 839  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 840  * Min = 0, and Max = 65535
 841  */
 842 static int poll_interval = -1;
 843
 844 /*
 845  * MSI interrupts
 846  */
 847 enum {
 848         NV_MSI_INT_DISABLED,
 849         NV_MSI_INT_ENABLED
 850 };
 851 static int msi = NV_MSI_INT_ENABLED;
 852
 853 /*
 854  * MSIX interrupts
 855  */
 856 enum {
 857         NV_MSIX_INT_DISABLED,
 858         NV_MSIX_INT_ENABLED
 859 };
 860 static int msix = NV_MSIX_INT_DISABLED;
 861
 862 /*
 863  * DMA 64bit
 864  */
 865 enum {
 866         NV_DMA_64BIT_DISABLED,
 867         NV_DMA_64BIT_ENABLED
 868 };
 869 static int dma_64bit = NV_DMA_64BIT_ENABLED;
 870
 871 /*
 872  * Crossover Detection
 873  * Realtek 8201 phy + some OEM boards do not work properly.
 874  */
 875 enum {
 876         NV_CROSSOVER_DETECTION_DISABLED,
 877         NV_CROSSOVER_DETECTION_ENABLED
 878 };
 879 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
 880
 881 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 882 {
 883         return netdev_priv(dev);
 884 }
 885
 886 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 887 {
 888         return ((struct fe_priv *)netdev_priv(dev))->base;
 889 }
 890
 891 static inline void pci_push(u8 __iomem *base)
 892 {
 893         /* force out pending posted writes */
 894         readl(base);
 895 }
 896
 897 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 898 {
 899         return le32_to_cpu(prd->flaglen)
 900                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 901 }
 902
 903 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 904 {
 905         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
 906 }
 907
 908 static bool nv_optimized(struct fe_priv *np)
 909 {
 910         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 911                 return false;
 912         return true;
 913 }
 914
 915 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 916                                 int delay, int delaymax, const char *msg)
 917 {
 918         u8 __iomem *base = get_hwbase(dev);
 919
 920         pci_push(base);
 921         do {
 922                 udelay(delay);
 923                 delaymax -= delay;
 924                 if (delaymax < 0) {
 925                         if (msg)
 926                                 printk(msg);
 927                         return 1;
 928                 }
 929         } while ((readl(base + offset) & mask) != target);
 930         return 0;
 931 }
 932
 933 #define NV_SETUP_RX_RING 0x01
 934 #define NV_SETUP_TX_RING 0x02
 935
 936 static inline u32 dma_low(dma_addr_t addr)
 937 {
 938         return addr;
 939 }
 940
 941 static inline u32 dma_high(dma_addr_t addr)
 942 {
 943         return addr>>31>>1;     /* 0 if 32bit, shift down by 32 if 64bit */
 944 }
 945
 946 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
 947 {
 948         struct fe_priv *np = get_nvpriv(dev);
 949         u8 __iomem *base = get_hwbase(dev);
 950
 951         if (!nv_optimized(np)) {
 952                 if (rxtx_flags & NV_SETUP_RX_RING) {
 953                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
 954                 }
 955                 if (rxtx_flags & NV_SETUP_TX_RING) {
 956                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
 957                 }
 958         } else {
 959                 if (rxtx_flags & NV_SETUP_RX_RING) {
 960                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
 961                         writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
 962                 }
 963                 if (rxtx_flags & NV_SETUP_TX_RING) {
 964                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
 965                         writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
 966                 }
 967         }
 968 }
 969
 970 static void free_rings(struct net_device *dev)
 971 {
 972         struct fe_priv *np = get_nvpriv(dev);
 973
 974         if (!nv_optimized(np)) {
 975                 if (np->rx_ring.orig)
 976                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
 977                                             np->rx_ring.orig, np->ring_addr);
 978         } else {
 979                 if (np->rx_ring.ex)
 980                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
 981                                             np->rx_ring.ex, np->ring_addr);
 982         }
 983         if (np->rx_skb)
 984                 kfree(np->rx_skb);
 985         if (np->tx_skb)
 986                 kfree(np->tx_skb);
 987 }
 988
 989 static int using_multi_irqs(struct net_device *dev)
 990 {
 991         struct fe_priv *np = get_nvpriv(dev);
 992
 993         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
 994             ((np->msi_flags & NV_MSI_X_ENABLED) &&
 995              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
 996                 return 0;
 997         else
 998                 return 1;
 999 }
1000
1001 static void nv_enable_irq(struct net_device *dev)
1002 {
1003         struct fe_priv *np = get_nvpriv(dev);
1004
1005         if (!using_multi_irqs(dev)) {
1006                 if (np->msi_flags & NV_MSI_X_ENABLED)
1007                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1008                 else
1009                         enable_irq(np->pci_dev->irq);
1010         } else {
1011                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1012                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1013                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1014         }
1015 }
1016
1017 static void nv_disable_irq(struct net_device *dev)
1018 {
1019         struct fe_priv *np = get_nvpriv(dev);
1020
1021         if (!using_multi_irqs(dev)) {
1022                 if (np->msi_flags & NV_MSI_X_ENABLED)
1023                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1024                 else
1025                         disable_irq(np->pci_dev->irq);
1026         } else {
1027                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1028                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1029                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1030         }
1031 }
1032
1033 /* In MSIX mode, a write to irqmask behaves as XOR */
1034 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1035 {
1036         u8 __iomem *base = get_hwbase(dev);
1037
1038         writel(mask, base + NvRegIrqMask);
1039 }
1040
1041 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1042 {
1043         struct fe_priv *np = get_nvpriv(dev);
1044         u8 __iomem *base = get_hwbase(dev);
1045
1046         if (np->msi_flags & NV_MSI_X_ENABLED) {
1047                 writel(mask, base + NvRegIrqMask);
1048         } else {
1049                 if (np->msi_flags & NV_MSI_ENABLED)
1050                         writel(0, base + NvRegMSIIrqMask);
1051                 writel(0, base + NvRegIrqMask);
1052         }
1053 }
1054
1055 #define MII_READ        (-1)
1056 /* mii_rw: read/write a register on the PHY.
1057  *
1058  * Caller must guarantee serialization
1059  */
1060 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1061 {
1062         u8 __iomem *base = get_hwbase(dev);
1063         u32 reg;
1064         int retval;
1065
1066         writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1067
1068         reg = readl(base + NvRegMIIControl);
1069         if (reg & NVREG_MIICTL_INUSE) {
1070                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1071                 udelay(NV_MIIBUSY_DELAY);
1072         }
1073
1074         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1075         if (value != MII_READ) {
1076                 writel(value, base + NvRegMIIData);
1077                 reg |= NVREG_MIICTL_WRITE;
1078         }
1079         writel(reg, base + NvRegMIIControl);
1080
1081         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1082                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1083                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1084                                 dev->name, miireg, addr);
1085                 retval = -1;
1086         } else if (value != MII_READ) {
1087                 /* it was a write operation - fewer failures are detectable */
1088                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1089                                 dev->name, value, miireg, addr);
1090                 retval = 0;
1091         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1092                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1093                                 dev->name, miireg, addr);
1094                 retval = -1;
1095         } else {
1096                 retval = readl(base + NvRegMIIData);
1097                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1098                                 dev->name, miireg, addr, retval);
1099         }
1100
1101         return retval;
1102 }
1103
1104 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1105 {
1106         struct fe_priv *np = netdev_priv(dev);
1107         u32 miicontrol;
1108         unsigned int tries = 0;
1109
1110         miicontrol = BMCR_RESET | bmcr_setup;
1111         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1112                 return -1;
1113         }
1114
1115         /* wait for 500ms */
1116         msleep(500);
1117
1118         /* must wait till reset is deasserted */
1119         while (miicontrol & BMCR_RESET) {
1120                 msleep(10);
1121                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1122                 /* FIXME: 100 tries seem excessive */
1123                 if (tries++ > 100)
1124                         return -1;
1125         }
1126         return 0;
1127 }
1128
1129 static int phy_init(struct net_device *dev)
1130 {
1131         struct fe_priv *np = get_nvpriv(dev);
1132         u8 __iomem *base = get_hwbase(dev);
1133         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1134
1135         /* phy errata for E3016 phy */
1136         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1137                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1138                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1139                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1140                         printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1141                         return PHY_ERROR;
1142                 }
1143         }
1144         if (np->phy_oui == PHY_OUI_REALTEK) {
1145                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1146                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1147                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1148                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1149                                 return PHY_ERROR;
1150                         }
1151                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1152                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1153                                 return PHY_ERROR;
1154                         }
1155                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1156                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1157                                 return PHY_ERROR;
1158                         }
1159                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1160                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1161                                 return PHY_ERROR;
1162                         }
1163                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1164                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1165                                 return PHY_ERROR;
1166                         }
1167                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1168                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1169                                 return PHY_ERROR;
1170                         }
1171                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1172                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1173                                 return PHY_ERROR;
1174                         }
1175                 }
1176                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1177                     np->phy_rev == PHY_REV_REALTEK_8211C) {
1178                         u32 powerstate = readl(base + NvRegPowerState2);
1179
1180                         /* need to perform hw phy reset */
1181                         powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1182                         writel(powerstate, base + NvRegPowerState2);
1183                         msleep(25);
1184
1185                         powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1186                         writel(powerstate, base + NvRegPowerState2);
1187                         msleep(25);
1188
1189                         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1190                         reg |= PHY_REALTEK_INIT9;
1191                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) {
1192                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1193                                 return PHY_ERROR;
1194                         }
1195                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) {
1196                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1197                                 return PHY_ERROR;
1198                         }
1199                         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1200                         if (!(reg & PHY_REALTEK_INIT11)) {
1201                                 reg |= PHY_REALTEK_INIT11;
1202                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) {
1203                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1204                                         return PHY_ERROR;
1205                                 }
1206                         }
1207                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1208                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1209                                 return PHY_ERROR;
1210                         }
1211                 }
1212                 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1213                         if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
1214                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
1215                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
1216                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
1217                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
1218                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
1219                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
1220                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) {
1221                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1222                                 phy_reserved |= PHY_REALTEK_INIT7;
1223                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1224                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1225                                         return PHY_ERROR;
1226                                 }
1227                         }
1228                 }
1229         }
1230
1231         /* set advertise register */
1232         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1233         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1234         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1235                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1236                 return PHY_ERROR;
1237         }
1238
1239         /* get phy interface type */
1240         phyinterface = readl(base + NvRegPhyInterface);
1241
1242         /* see if gigabit phy */
1243         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1244         if (mii_status & PHY_GIGABIT) {
1245                 np->gigabit = PHY_GIGABIT;
1246                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1247                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1248                 if (phyinterface & PHY_RGMII)
1249                         mii_control_1000 |= ADVERTISE_1000FULL;
1250                 else
1251                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1252
1253                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1254                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1255                         return PHY_ERROR;
1256                 }
1257         }
1258         else
1259                 np->gigabit = 0;
1260
1261         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1262         mii_control |= BMCR_ANENABLE;
1263
1264         if (np->phy_oui == PHY_OUI_REALTEK &&
1265             np->phy_model == PHY_MODEL_REALTEK_8211 &&
1266             np->phy_rev == PHY_REV_REALTEK_8211C) {
1267                 /* start autoneg since we already performed hw reset above */
1268                 mii_control |= BMCR_ANRESTART;
1269                 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1270                         printk(KERN_INFO "%s: phy init failed\n", pci_name(np->pci_dev));
1271                         return PHY_ERROR;
1272                 }
1273         } else {
1274                 /* reset the phy
1275                  * (certain phys need bmcr to be setup with reset)
1276                  */
1277                 if (phy_reset(dev, mii_control)) {
1278                         printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1279                         return PHY_ERROR;
1280                 }
1281         }
1282
1283         /* phy vendor specific configuration */
1284         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1285                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1286                 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1287                 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1288                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1289                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1290                         return PHY_ERROR;
1291                 }
1292                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1293                 phy_reserved |= PHY_CICADA_INIT5;
1294                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1295                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1296                         return PHY_ERROR;
1297                 }
1298         }
1299         if (np->phy_oui == PHY_OUI_CICADA) {
1300                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1301                 phy_reserved |= PHY_CICADA_INIT6;
1302                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1303                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1304                         return PHY_ERROR;
1305                 }
1306         }
1307         if (np->phy_oui == PHY_OUI_VITESSE) {
1308                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1309                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1310                         return PHY_ERROR;
1311                 }
1312                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1313                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1314                         return PHY_ERROR;
1315                 }
1316                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1317                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1318                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1319                         return PHY_ERROR;
1320                 }
1321                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1322                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1323                 phy_reserved |= PHY_VITESSE_INIT3;
1324                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1325                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1326                         return PHY_ERROR;
1327                 }
1328                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1329                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1330                         return PHY_ERROR;
1331                 }
1332                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1333                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1334                         return PHY_ERROR;
1335                 }
1336                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1337                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1338                 phy_reserved |= PHY_VITESSE_INIT3;
1339                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1340                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1341                         return PHY_ERROR;
1342                 }
1343                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1344                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1345                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1346                         return PHY_ERROR;
1347                 }
1348                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1349                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1350                         return PHY_ERROR;
1351                 }
1352                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1353                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1354                         return PHY_ERROR;
1355                 }
1356                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1357                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1358                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1359                         return PHY_ERROR;
1360                 }
1361                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1362                 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1363                 phy_reserved |= PHY_VITESSE_INIT8;
1364                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1365                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1366                         return PHY_ERROR;
1367                 }
1368                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1369                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1370                         return PHY_ERROR;
1371                 }
1372                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1373                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1374                         return PHY_ERROR;
1375                 }
1376         }
1377         if (np->phy_oui == PHY_OUI_REALTEK) {
1378                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1379                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1380                         /* reset could have cleared these out, set them back */
1381                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1382                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1383                                 return PHY_ERROR;
1384                         }
1385                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1386                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1387                                 return PHY_ERROR;
1388                         }
1389                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1390                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1391                                 return PHY_ERROR;
1392                         }
1393                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1394                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1395                                 return PHY_ERROR;
1396                         }
1397                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1398                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1399                                 return PHY_ERROR;
1400                         }
1401                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1402                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1403                                 return PHY_ERROR;
1404                         }
1405                         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1406                                 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1407                                 return PHY_ERROR;
1408                         }
1409                 }
1410                 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1411                         if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
1412                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
1413                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
1414                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
1415                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
1416                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
1417                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
1418                             np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) {
1419                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1420                                 phy_reserved |= PHY_REALTEK_INIT7;
1421                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1422                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1423                                         return PHY_ERROR;
1424                                 }
1425                         }
1426                         if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1427                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1428                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1429                                         return PHY_ERROR;
1430                                 }
1431                                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
1432                                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1433                                 phy_reserved |= PHY_REALTEK_INIT3;
1434                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) {
1435                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1436                                         return PHY_ERROR;
1437                                 }
1438                                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1439                                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1440                                         return PHY_ERROR;
1441                                 }
1442                         }
1443                 }
1444         }
1445
1446         /* some phys clear out pause advertisment on reset, set it back */
1447         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1448
1449         /* restart auto negotiation, power down phy */
1450         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1451         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE | BMCR_PDOWN);
1452         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1453                 return PHY_ERROR;
1454         }
1455
1456         return 0;
1457 }
1458
1459 static void nv_start_rx(struct net_device *dev)
1460 {
1461         struct fe_priv *np = netdev_priv(dev);
1462         u8 __iomem *base = get_hwbase(dev);
1463         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1464
1465         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1466         /* Already running? Stop it. */
1467         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1468                 rx_ctrl &= ~NVREG_RCVCTL_START;
1469                 writel(rx_ctrl, base + NvRegReceiverControl);
1470                 pci_push(base);
1471         }
1472         writel(np->linkspeed, base + NvRegLinkSpeed);
1473         pci_push(base);
1474         rx_ctrl |= NVREG_RCVCTL_START;
1475         if (np->mac_in_use)
1476                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1477         writel(rx_ctrl, base + NvRegReceiverControl);
1478         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1479                                 dev->name, np->duplex, np->linkspeed);
1480         pci_push(base);
1481 }
1482
1483 static void nv_stop_rx(struct net_device *dev)
1484 {
1485         struct fe_priv *np = netdev_priv(dev);
1486         u8 __iomem *base = get_hwbase(dev);
1487         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1488
1489         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1490         if (!np->mac_in_use)
1491                 rx_ctrl &= ~NVREG_RCVCTL_START;
1492         else
1493                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1494         writel(rx_ctrl, base + NvRegReceiverControl);
1495         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1496                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1497                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1498
1499         udelay(NV_RXSTOP_DELAY2);
1500         if (!np->mac_in_use)
1501                 writel(0, base + NvRegLinkSpeed);
1502 }
1503
1504 static void nv_start_tx(struct net_device *dev)
1505 {
1506         struct fe_priv *np = netdev_priv(dev);
1507         u8 __iomem *base = get_hwbase(dev);
1508         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1509
1510         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1511         tx_ctrl |= NVREG_XMITCTL_START;
1512         if (np->mac_in_use)
1513                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1514         writel(tx_ctrl, base + NvRegTransmitterControl);
1515         pci_push(base);
1516 }
1517
1518 static void nv_stop_tx(struct net_device *dev)
1519 {
1520         struct fe_priv *np = netdev_priv(dev);
1521         u8 __iomem *base = get_hwbase(dev);
1522         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1523
1524         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1525         if (!np->mac_in_use)
1526                 tx_ctrl &= ~NVREG_XMITCTL_START;
1527         else
1528                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1529         writel(tx_ctrl, base + NvRegTransmitterControl);
1530         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1531                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1532                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1533
1534         udelay(NV_TXSTOP_DELAY2);
1535         if (!np->mac_in_use)
1536                 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1537                        base + NvRegTransmitPoll);
1538 }
1539
1540 static void nv_start_rxtx(struct net_device *dev)
1541 {
1542         nv_start_rx(dev);
1543         nv_start_tx(dev);
1544 }
1545
1546 static void nv_stop_rxtx(struct net_device *dev)
1547 {
1548         nv_stop_rx(dev);
1549         nv_stop_tx(dev);
1550 }
1551
1552 static void nv_txrx_reset(struct net_device *dev)
1553 {
1554         struct fe_priv *np = netdev_priv(dev);
1555         u8 __iomem *base = get_hwbase(dev);
1556
1557         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1558         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1559         pci_push(base);
1560         udelay(NV_TXRX_RESET_DELAY);
1561         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1562         pci_push(base);
1563 }
1564
1565 static void nv_mac_reset(struct net_device *dev)
1566 {
1567         struct fe_priv *np = netdev_priv(dev);
1568         u8 __iomem *base = get_hwbase(dev);
1569         u32 temp1, temp2, temp3;
1570
1571         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1572
1573         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1574         pci_push(base);
1575
1576         /* save registers since they will be cleared on reset */
1577         temp1 = readl(base + NvRegMacAddrA);
1578         temp2 = readl(base + NvRegMacAddrB);
1579         temp3 = readl(base + NvRegTransmitPoll);
1580
1581         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1582         pci_push(base);
1583         udelay(NV_MAC_RESET_DELAY);
1584         writel(0, base + NvRegMacReset);
1585         pci_push(base);
1586         udelay(NV_MAC_RESET_DELAY);
1587
1588         /* restore saved registers */
1589         writel(temp1, base + NvRegMacAddrA);
1590         writel(temp2, base + NvRegMacAddrB);
1591         writel(temp3, base + NvRegTransmitPoll);
1592
1593         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1594         pci_push(base);
1595 }
1596
1597 static void nv_get_hw_stats(struct net_device *dev)
1598 {
1599         struct fe_priv *np = netdev_priv(dev);
1600         u8 __iomem *base = get_hwbase(dev);
1601
1602         np->estats.tx_bytes += readl(base + NvRegTxCnt);
1603         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1604         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1605         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1606         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1607         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1608         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1609         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1610         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1611         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1612         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1613         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1614         np->estats.rx_runt += readl(base + NvRegRxRunt);
1615         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1616         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1617         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1618         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1619         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1620         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1621         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1622         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1623         np->estats.rx_packets =
1624                 np->estats.rx_unicast +
1625                 np->estats.rx_multicast +
1626                 np->estats.rx_broadcast;
1627         np->estats.rx_errors_total =
1628                 np->estats.rx_crc_errors +
1629                 np->estats.rx_over_errors +
1630                 np->estats.rx_frame_error +
1631                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1632                 np->estats.rx_late_collision +
1633                 np->estats.rx_runt +
1634                 np->estats.rx_frame_too_long;
1635         np->estats.tx_errors_total =
1636                 np->estats.tx_late_collision +
1637                 np->estats.tx_fifo_errors +
1638                 np->estats.tx_carrier_errors +
1639                 np->estats.tx_excess_deferral +
1640                 np->estats.tx_retry_error;
1641
1642         if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1643                 np->estats.tx_deferral += readl(base + NvRegTxDef);
1644                 np->estats.tx_packets += readl(base + NvRegTxFrame);
1645                 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1646                 np->estats.tx_pause += readl(base + NvRegTxPause);
1647                 np->estats.rx_pause += readl(base + NvRegRxPause);
1648                 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1649         }
1650
1651         if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1652                 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1653                 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1654                 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1655         }
1656 }
1657
1658 /*
1659  * nv_get_stats: dev->get_stats function
1660  * Get latest stats value from the nic.
1661  * Called with read_lock(&dev_base_lock) held for read -
1662  * only synchronized against unregister_netdevice.
1663  */
1664 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1665 {
1666         struct fe_priv *np = netdev_priv(dev);
1667
1668         /* If the nic supports hw counters then retrieve latest values */
1669         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
1670                 nv_get_hw_stats(dev);
1671
1672                 /* copy to net_device stats */
1673                 dev->stats.tx_bytes = np->estats.tx_bytes;
1674                 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1675                 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1676                 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1677                 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1678                 dev->stats.rx_errors = np->estats.rx_errors_total;
1679                 dev->stats.tx_errors = np->estats.tx_errors_total;
1680         }
1681
1682         return &dev->stats;
1683 }
1684
1685 /*
1686  * nv_alloc_rx: fill rx ring entries.
1687  * Return 1 if the allocations for the skbs failed and the
1688  * rx engine is without Available descriptors
1689  */
1690 static int nv_alloc_rx(struct net_device *dev)
1691 {
1692         struct fe_priv *np = netdev_priv(dev);
1693         struct ring_desc* less_rx;
1694
1695         less_rx = np->get_rx.orig;
1696         if (less_rx-- == np->first_rx.orig)
1697                 less_rx = np->last_rx.orig;
1698
1699         while (np->put_rx.orig != less_rx) {
1700                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1701                 if (skb) {
1702                         np->put_rx_ctx->skb = skb;
1703                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1704                                                              skb->data,
1705                                                              skb_tailroom(skb),
1706                                                              PCI_DMA_FROMDEVICE);
1707                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1708                         np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1709                         wmb();
1710                         np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1711                         if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1712                                 np->put_rx.orig = np->first_rx.orig;
1713                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1714                                 np->put_rx_ctx = np->first_rx_ctx;
1715                 } else {
1716                         return 1;
1717                 }
1718         }
1719         return 0;
1720 }
1721
1722 static int nv_alloc_rx_optimized(struct net_device *dev)
1723 {
1724         struct fe_priv *np = netdev_priv(dev);
1725         struct ring_desc_ex* less_rx;
1726
1727         less_rx = np->get_rx.ex;
1728         if (less_rx-- == np->first_rx.ex)
1729                 less_rx = np->last_rx.ex;
1730
1731         while (np->put_rx.ex != less_rx) {
1732                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1733                 if (skb) {
1734                         np->put_rx_ctx->skb = skb;
1735                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1736                                                              skb->data,
1737                                                              skb_tailroom(skb),
1738                                                              PCI_DMA_FROMDEVICE);
1739                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1740                         np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1741                         np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1742                         wmb();
1743                         np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1744                         if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1745                                 np->put_rx.ex = np->first_rx.ex;
1746                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1747                                 np->put_rx_ctx = np->first_rx_ctx;
1748                 } else {
1749                         return 1;
1750                 }
1751         }
1752         return 0;
1753 }
1754
1755 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1756 #ifdef CONFIG_FORCEDETH_NAPI
1757 static void nv_do_rx_refill(unsigned long data)
1758 {
1759         struct net_device *dev = (struct net_device *) data;
1760         struct fe_priv *np = netdev_priv(dev);
1761
1762         /* Just reschedule NAPI rx processing */
1763         netif_rx_schedule(dev, &np->napi);
1764 }
1765 #else
1766 static void nv_do_rx_refill(unsigned long data)
1767 {
1768         struct net_device *dev = (struct net_device *) data;
1769         struct fe_priv *np = netdev_priv(dev);
1770         int retcode;
1771
1772         if (!using_multi_irqs(dev)) {
1773                 if (np->msi_flags & NV_MSI_X_ENABLED)
1774                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1775                 else
1776                         disable_irq(np->pci_dev->irq);
1777         } else {
1778                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1779         }
1780         if (!nv_optimized(np))
1781                 retcode = nv_alloc_rx(dev);
1782         else
1783                 retcode = nv_alloc_rx_optimized(dev);
1784         if (retcode) {
1785                 spin_lock_irq(&np->lock);
1786                 if (!np->in_shutdown)
1787                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1788                 spin_unlock_irq(&np->lock);
1789         }
1790         if (!using_multi_irqs(dev)) {
1791                 if (np->msi_flags & NV_MSI_X_ENABLED)
1792                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1793                 else
1794                         enable_irq(np->pci_dev->irq);
1795         } else {
1796                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1797         }
1798 }
1799 #endif
1800
1801 static void nv_init_rx(struct net_device *dev)
1802 {
1803         struct fe_priv *np = netdev_priv(dev);
1804         int i;
1805
1806         np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1807
1808         if (!nv_optimized(np))
1809                 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1810         else
1811                 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1812         np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1813         np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1814
1815         for (i = 0; i < np->rx_ring_size; i++) {
1816                 if (!nv_optimized(np)) {
1817                         np->rx_ring.orig[i].flaglen = 0;
1818                         np->rx_ring.orig[i].buf = 0;
1819                 } else {
1820                         np->rx_ring.ex[i].flaglen = 0;
1821                         np->rx_ring.ex[i].txvlan = 0;
1822                         np->rx_ring.ex[i].bufhigh = 0;
1823                         np->rx_ring.ex[i].buflow = 0;
1824                 }
1825                 np->rx_skb[i].skb = NULL;
1826                 np->rx_skb[i].dma = 0;
1827         }
1828 }
1829
1830 static void nv_init_tx(struct net_device *dev)
1831 {
1832         struct fe_priv *np = netdev_priv(dev);
1833         int i;
1834
1835         np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1836
1837         if (!nv_optimized(np))
1838                 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1839         else
1840                 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1841         np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1842         np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1843         np->tx_pkts_in_progress = 0;
1844         np->tx_change_owner = NULL;
1845         np->tx_end_flip = NULL;
1846
1847         for (i = 0; i < np->tx_ring_size; i++) {
1848                 if (!nv_optimized(np)) {
1849                         np->tx_ring.orig[i].flaglen = 0;
1850                         np->tx_ring.orig[i].buf = 0;
1851                 } else {
1852                         np->tx_ring.ex[i].flaglen = 0;
1853                         np->tx_ring.ex[i].txvlan = 0;
1854                         np->tx_ring.ex[i].bufhigh = 0;
1855                         np->tx_ring.ex[i].buflow = 0;
1856                 }
1857                 np->tx_skb[i].skb = NULL;
1858                 np->tx_skb[i].dma = 0;
1859                 np->tx_skb[i].dma_len = 0;
1860                 np->tx_skb[i].first_tx_desc = NULL;
1861                 np->tx_skb[i].next_tx_ctx = NULL;
1862         }
1863 }
1864
1865 static int nv_init_ring(struct net_device *dev)
1866 {
1867         struct fe_priv *np = netdev_priv(dev);
1868
1869         nv_init_tx(dev);
1870         nv_init_rx(dev);
1871
1872         if (!nv_optimized(np))
1873                 return nv_alloc_rx(dev);
1874         else
1875                 return nv_alloc_rx_optimized(dev);
1876 }
1877
1878 static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb)
1879 {
1880         struct fe_priv *np = netdev_priv(dev);
1881
1882         if (tx_skb->dma) {
1883                 pci_unmap_page(np->pci_dev, tx_skb->dma,
1884                                tx_skb->dma_len,
1885                                PCI_DMA_TODEVICE);
1886                 tx_skb->dma = 0;
1887         }
1888         if (tx_skb->skb) {
1889                 dev_kfree_skb_any(tx_skb->skb);
1890                 tx_skb->skb = NULL;
1891                 return 1;
1892         } else {
1893                 return 0;
1894         }
1895 }
1896
1897 static void nv_drain_tx(struct net_device *dev)
1898 {
1899         struct fe_priv *np = netdev_priv(dev);
1900         unsigned int i;
1901
1902         for (i = 0; i < np->tx_ring_size; i++) {
1903                 if (!nv_optimized(np)) {
1904                         np->tx_ring.orig[i].flaglen = 0;
1905                         np->tx_ring.orig[i].buf = 0;
1906                 } else {
1907                         np->tx_ring.ex[i].flaglen = 0;
1908                         np->tx_ring.ex[i].txvlan = 0;
1909                         np->tx_ring.ex[i].bufhigh = 0;
1910                         np->tx_ring.ex[i].buflow = 0;
1911                 }
1912                 if (nv_release_txskb(dev, &np->tx_skb[i]))
1913                         dev->stats.tx_dropped++;
1914                 np->tx_skb[i].dma = 0;
1915                 np->tx_skb[i].dma_len = 0;
1916                 np->tx_skb[i].first_tx_desc = NULL;
1917                 np->tx_skb[i].next_tx_ctx = NULL;
1918         }
1919         np->tx_pkts_in_progress = 0;
1920         np->tx_change_owner = NULL;
1921         np->tx_end_flip = NULL;
1922 }
1923
1924 static void nv_drain_rx(struct net_device *dev)
1925 {
1926         struct fe_priv *np = netdev_priv(dev);
1927         int i;
1928
1929         for (i = 0; i < np->rx_ring_size; i++) {
1930                 if (!nv_optimized(np)) {
1931                         np->rx_ring.orig[i].flaglen = 0;
1932                         np->rx_ring.orig[i].buf = 0;
1933                 } else {
1934                         np->rx_ring.ex[i].flaglen = 0;
1935                         np->rx_ring.ex[i].txvlan = 0;
1936                         np->rx_ring.ex[i].bufhigh = 0;
1937                         np->rx_ring.ex[i].buflow = 0;
1938                 }
1939                 wmb();
1940                 if (np->rx_skb[i].skb) {
1941                         pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1942                                          (skb_end_pointer(np->rx_skb[i].skb) -
1943                                           np->rx_skb[i].skb->data),
1944                                          PCI_DMA_FROMDEVICE);
1945                         dev_kfree_skb(np->rx_skb[i].skb);
1946                         np->rx_skb[i].skb = NULL;
1947                 }
1948         }
1949 }
1950
1951 static void nv_drain_rxtx(struct net_device *dev)
1952 {
1953         nv_drain_tx(dev);
1954         nv_drain_rx(dev);
1955 }
1956
1957 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1958 {
1959         return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1960 }
1961
1962 static void nv_legacybackoff_reseed(struct net_device *dev)
1963 {
1964         u8 __iomem *base = get_hwbase(dev);
1965         u32 reg;
1966         u32 low;
1967         int tx_status = 0;
1968
1969         reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
1970         get_random_bytes(&low, sizeof(low));
1971         reg |= low & NVREG_SLOTTIME_MASK;
1972
1973         /* Need to stop tx before change takes effect.
1974          * Caller has already gained np->lock.
1975          */
1976         tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
1977         if (tx_status)
1978                 nv_stop_tx(dev);
1979         nv_stop_rx(dev);
1980         writel(reg, base + NvRegSlotTime);
1981         if (tx_status)
1982                 nv_start_tx(dev);
1983         nv_start_rx(dev);
1984 }
1985
1986 /* Gear Backoff Seeds */
1987 #define BACKOFF_SEEDSET_ROWS    8
1988 #define BACKOFF_SEEDSET_LFSRS   15
1989
1990 /* Known Good seed sets */
1991 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
1992     {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
1993     {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
1994     {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
1995     {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
1996     {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
1997     {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
1998     {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800,  84},
1999     {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}};
2000
2001 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2002     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2003     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2004     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2005     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2006     {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2007     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2008     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2009     {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}};
2010
2011 static void nv_gear_backoff_reseed(struct net_device *dev)
2012 {
2013         u8 __iomem *base = get_hwbase(dev);
2014         u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2015         u32 temp, seedset, combinedSeed;
2016         int i;
2017
2018         /* Setup seed for free running LFSR */
2019         /* We are going to read the time stamp counter 3 times
2020            and swizzle bits around to increase randomness */
2021         get_random_bytes(&miniseed1, sizeof(miniseed1));
2022         miniseed1 &= 0x0fff;
2023         if (miniseed1 == 0)
2024                 miniseed1 = 0xabc;
2025
2026         get_random_bytes(&miniseed2, sizeof(miniseed2));
2027         miniseed2 &= 0x0fff;
2028         if (miniseed2 == 0)
2029                 miniseed2 = 0xabc;
2030         miniseed2_reversed =
2031                 ((miniseed2 & 0xF00) >> 8) |
2032                  (miniseed2 & 0x0F0) |
2033                  ((miniseed2 & 0x00F) << 8);
2034
2035         get_random_bytes(&miniseed3, sizeof(miniseed3));
2036         miniseed3 &= 0x0fff;
2037         if (miniseed3 == 0)
2038                 miniseed3 = 0xabc;
2039         miniseed3_reversed =
2040                 ((miniseed3 & 0xF00) >> 8) |
2041                  (miniseed3 & 0x0F0) |
2042                  ((miniseed3 & 0x00F) << 8);
2043
2044         combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2045                        (miniseed2 ^ miniseed3_reversed);
2046
2047         /* Seeds can not be zero */
2048         if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2049                 combinedSeed |= 0x08;
2050         if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2051                 combinedSeed |= 0x8000;
2052
2053         /* No need to disable tx here */
2054         temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2055         temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2056         temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2057         writel(temp,base + NvRegBackOffControl);
2058
2059         /* Setup seeds for all gear LFSRs. */
2060         get_random_bytes(&seedset, sizeof(seedset));
2061         seedset = seedset % BACKOFF_SEEDSET_ROWS;
2062         for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++)
2063         {
2064                 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2065                 temp |= main_seedset[seedset][i-1] & 0x3ff;
2066                 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2067                 writel(temp, base + NvRegBackOffControl);
2068         }
2069 }
2070
2071 /*
2072  * nv_start_xmit: dev->hard_start_xmit function
2073  * Called with netif_tx_lock held.
2074  */
2075 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2076 {
2077         struct fe_priv *np = netdev_priv(dev);
2078         u32 tx_flags = 0;
2079         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2080         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2081         unsigned int i;
2082         u32 offset = 0;
2083         u32 bcnt;
2084         u32 size = skb->len-skb->data_len;
2085         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2086         u32 empty_slots;
2087         struct ring_desc* put_tx;
2088         struct ring_desc* start_tx;
2089         struct ring_desc* prev_tx;
2090         struct nv_skb_map* prev_tx_ctx;
2091         unsigned long flags;
2092
2093         /* add fragments to entries count */
2094         for (i = 0; i < fragments; i++) {
2095                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2096                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2097         }
2098
2099         empty_slots = nv_get_empty_tx_slots(np);
2100         if (unlikely(empty_slots <= entries)) {
2101                 spin_lock_irqsave(&np->lock, flags);
2102                 netif_stop_queue(dev);
2103                 np->tx_stop = 1;
2104                 spin_unlock_irqrestore(&np->lock, flags);
2105                 return NETDEV_TX_BUSY;
2106         }
2107
2108         start_tx = put_tx = np->put_tx.orig;
2109
2110         /* setup the header buffer */
2111         do {
2112                 prev_tx = put_tx;
2113                 prev_tx_ctx = np->put_tx_ctx;
2114                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2115                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2116                                                 PCI_DMA_TODEVICE);
2117                 np->put_tx_ctx->dma_len = bcnt;
2118                 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2119                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2120
2121                 tx_flags = np->tx_flags;
2122                 offset += bcnt;
2123                 size -= bcnt;
2124                 if (unlikely(put_tx++ == np->last_tx.orig))
2125                         put_tx = np->first_tx.orig;
2126                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2127                         np->put_tx_ctx = np->first_tx_ctx;
2128         } while (size);
2129
2130         /* setup the fragments */
2131         for (i = 0; i < fragments; i++) {
2132                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2133                 u32 size = frag->size;
2134                 offset = 0;
2135
2136                 do {
2137                         prev_tx = put_tx;
2138                         prev_tx_ctx = np->put_tx_ctx;
2139                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2140                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2141                                                            PCI_DMA_TODEVICE);
2142                         np->put_tx_ctx->dma_len = bcnt;
2143                         put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2144                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2145
2146                         offset += bcnt;
2147                         size -= bcnt;
2148                         if (unlikely(put_tx++ == np->last_tx.orig))
2149                                 put_tx = np->first_tx.orig;
2150                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2151                                 np->put_tx_ctx = np->first_tx_ctx;
2152                 } while (size);
2153         }
2154
2155         /* set last fragment flag  */
2156         prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2157
2158         /* save skb in this slot's context area */
2159         prev_tx_ctx->skb = skb;
2160
2161         if (skb_is_gso(skb))
2162                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2163         else
2164                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2165                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2166
2167         spin_lock_irqsave(&np->lock, flags);
2168
2169         /* set tx flags */
2170         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2171         np->put_tx.orig = put_tx;
2172
2173         spin_unlock_irqrestore(&np->lock, flags);
2174
2175         dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
2176                 dev->name, entries, tx_flags_extra);
2177         {
2178                 int j;
2179                 for (j=0; j<64; j++) {
2180                         if ((j%16) == 0)
2181                                 dprintk("\n%03x:", j);
2182                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2183                 }
2184                 dprintk("\n");
2185         }
2186
2187         dev->trans_start = jiffies;
2188         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2189         return NETDEV_TX_OK;
2190 }
2191
2192 static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
2193 {
2194         struct fe_priv *np = netdev_priv(dev);
2195         u32 tx_flags = 0;
2196         u32 tx_flags_extra;
2197         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2198         unsigned int i;
2199         u32 offset = 0;
2200         u32 bcnt;
2201         u32 size = skb->len-skb->data_len;
2202         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2203         u32 empty_slots;
2204         struct ring_desc_ex* put_tx;
2205         struct ring_desc_ex* start_tx;
2206         struct ring_desc_ex* prev_tx;
2207         struct nv_skb_map* prev_tx_ctx;
2208         struct nv_skb_map* start_tx_ctx;
2209         unsigned long flags;
2210
2211         /* add fragments to entries count */
2212         for (i = 0; i < fragments; i++) {
2213                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2214                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2215         }
2216
2217         empty_slots = nv_get_empty_tx_slots(np);
2218         if (unlikely(empty_slots <= entries)) {
2219                 spin_lock_irqsave(&np->lock, flags);
2220                 netif_stop_queue(dev);
2221                 np->tx_stop = 1;
2222                 spin_unlock_irqrestore(&np->lock, flags);
2223                 return NETDEV_TX_BUSY;
2224         }
2225
2226         start_tx = put_tx = np->put_tx.ex;
2227         start_tx_ctx = np->put_tx_ctx;
2228
2229         /* setup the header buffer */
2230         do {
2231                 prev_tx = put_tx;
2232                 prev_tx_ctx = np->put_tx_ctx;
2233                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2234                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2235                                                 PCI_DMA_TODEVICE);
2236                 np->put_tx_ctx->dma_len = bcnt;
2237                 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2238                 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2239                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2240
2241                 tx_flags = NV_TX2_VALID;
2242                 offset += bcnt;
2243                 size -= bcnt;
2244                 if (unlikely(put_tx++ == np->last_tx.ex))
2245                         put_tx = np->first_tx.ex;
2246                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2247                         np->put_tx_ctx = np->first_tx_ctx;
2248         } while (size);
2249
2250         /* setup the fragments */
2251         for (i = 0; i < fragments; i++) {
2252                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2253                 u32 size = frag->size;
2254                 offset = 0;
2255
2256                 do {
2257                         prev_tx = put_tx;
2258                         prev_tx_ctx = np->put_tx_ctx;
2259                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2260                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2261                                                            PCI_DMA_TODEVICE);
2262                         np->put_tx_ctx->dma_len = bcnt;
2263                         put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2264                         put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2265                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2266
2267                         offset += bcnt;
2268                         size -= bcnt;
2269                         if (unlikely(put_tx++ == np->last_tx.ex))
2270                                 put_tx = np->first_tx.ex;
2271                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2272                                 np->put_tx_ctx = np->first_tx_ctx;
2273                 } while (size);
2274         }
2275
2276         /* set last fragment flag  */
2277         prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2278
2279         /* save skb in this slot's context area */
2280         prev_tx_ctx->skb = skb;
2281
2282         if (skb_is_gso(skb))
2283                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2284         else
2285                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2286                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2287
2288         /* vlan tag */
2289         if (likely(!np->vlangrp)) {
2290                 start_tx->txvlan = 0;
2291         } else {
2292                 if (vlan_tx_tag_present(skb))
2293                         start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
2294                 else
2295                         start_tx->txvlan = 0;
2296         }
2297
2298         spin_lock_irqsave(&np->lock, flags);
2299
2300         if (np->tx_limit) {
2301                 /* Limit the number of outstanding tx. Setup all fragments, but
2302                  * do not set the VALID bit on the first descriptor. Save a pointer
2303                  * to that descriptor and also for next skb_map element.
2304                  */
2305
2306                 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2307                         if (!np->tx_change_owner)
2308                                 np->tx_change_owner = start_tx_ctx;
2309
2310                         /* remove VALID bit */
2311                         tx_flags &= ~NV_TX2_VALID;
2312                         start_tx_ctx->first_tx_desc = start_tx;
2313                         start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2314                         np->tx_end_flip = np->put_tx_ctx;
2315                 } else {
2316                         np->tx_pkts_in_progress++;
2317                 }
2318         }
2319
2320         /* set tx flags */
2321         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2322         np->put_tx.ex = put_tx;
2323
2324         spin_unlock_irqrestore(&np->lock, flags);
2325
2326         dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2327                 dev->name, entries, tx_flags_extra);
2328         {
2329                 int j;
2330                 for (j=0; j<64; j++) {
2331                         if ((j%16) == 0)
2332                                 dprintk("\n%03x:", j);
2333                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2334                 }
2335                 dprintk("\n");
2336         }
2337
2338         dev->trans_start = jiffies;
2339         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2340         return NETDEV_TX_OK;
2341 }
2342
2343 static inline void nv_tx_flip_ownership(struct net_device *dev)
2344 {
2345         struct fe_priv *np = netdev_priv(dev);
2346
2347         np->tx_pkts_in_progress--;
2348         if (np->tx_change_owner) {
2349                 np->tx_change_owner->first_tx_desc->flaglen |=
2350                         cpu_to_le32(NV_TX2_VALID);
2351                 np->tx_pkts_in_progress++;
2352
2353                 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2354                 if (np->tx_change_owner == np->tx_end_flip)
2355                         np->tx_change_owner = NULL;
2356
2357                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2358         }
2359 }
2360
2361 /*
2362  * nv_tx_done: check for completed packets, release the skbs.
2363  *
2364  * Caller must own np->lock.
2365  */
2366 static void nv_tx_done(struct net_device *dev)
2367 {
2368         struct fe_priv *np = netdev_priv(dev);
2369         u32 flags;
2370         struct ring_desc* orig_get_tx = np->get_tx.orig;
2371
2372         while ((np->get_tx.orig != np->put_tx.orig) &&
2373                !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID)) {
2374
2375                 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
2376                                         dev->name, flags);
2377
2378                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2379                                np->get_tx_ctx->dma_len,
2380                                PCI_DMA_TODEVICE);
2381                 np->get_tx_ctx->dma = 0;
2382
2383                 if (np->desc_ver == DESC_VER_1) {
2384                         if (flags & NV_TX_LASTPACKET) {
2385                                 if (flags & NV_TX_ERROR) {
2386                                         if (flags & NV_TX_UNDERFLOW)
2387                                                 dev->stats.tx_fifo_errors++;
2388                                         if (flags & NV_TX_CARRIERLOST)
2389                                                 dev->stats.tx_carrier_errors++;
2390                                         if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2391                                                 nv_legacybackoff_reseed(dev);
2392                                         dev->stats.tx_errors++;
2393                                 } else {
2394                                         dev->stats.tx_packets++;
2395                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2396                                 }
2397                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2398                                 np->get_tx_ctx->skb = NULL;
2399                         }
2400                 } else {
2401                         if (flags & NV_TX2_LASTPACKET) {
2402                                 if (flags & NV_TX2_ERROR) {
2403                                         if (flags & NV_TX2_UNDERFLOW)
2404                                                 dev->stats.tx_fifo_errors++;
2405                                         if (flags & NV_TX2_CARRIERLOST)
2406                                                 dev->stats.tx_carrier_errors++;
2407                                         if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2408                                                 nv_legacybackoff_reseed(dev);
2409                                         dev->stats.tx_errors++;
2410                                 } else {
2411                                         dev->stats.tx_packets++;
2412                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2413                                 }
2414                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2415                                 np->get_tx_ctx->skb = NULL;
2416                         }
2417                 }
2418                 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2419                         np->get_tx.orig = np->first_tx.orig;
2420                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2421                         np->get_tx_ctx = np->first_tx_ctx;
2422         }
2423         if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2424                 np->tx_stop = 0;
2425                 netif_wake_queue(dev);
2426         }
2427 }
2428
2429 static void nv_tx_done_optimized(struct net_device *dev, int limit)
2430 {
2431         struct fe_priv *np = netdev_priv(dev);
2432         u32 flags;
2433         struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
2434
2435         while ((np->get_tx.ex != np->put_tx.ex) &&
2436                !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) &&
2437                (limit-- > 0)) {
2438
2439                 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
2440                                         dev->name, flags);
2441
2442                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2443                                np->get_tx_ctx->dma_len,
2444                                PCI_DMA_TODEVICE);
2445                 np->get_tx_ctx->dma = 0;
2446
2447                 if (flags & NV_TX2_LASTPACKET) {
2448                         if (!(flags & NV_TX2_ERROR))
2449                                 dev->stats.tx_packets++;
2450                         else {
2451                                 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2452                                         if (np->driver_data & DEV_HAS_GEAR_MODE)
2453                                                 nv_gear_backoff_reseed(dev);
2454                                         else
2455                                                 nv_legacybackoff_reseed(dev);
2456                                 }
2457                         }
2458
2459                         dev_kfree_skb_any(np->get_tx_ctx->skb);
2460                         np->get_tx_ctx->skb = NULL;
2461
2462                         if (np->tx_limit) {
2463                                 nv_tx_flip_ownership(dev);
2464                         }
2465                 }
2466                 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2467                         np->get_tx.ex = np->first_tx.ex;
2468                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2469                         np->get_tx_ctx = np->first_tx_ctx;
2470         }
2471         if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2472                 np->tx_stop = 0;
2473                 netif_wake_queue(dev);
2474         }
2475 }
2476
2477 /*
2478  * nv_tx_timeout: dev->tx_timeout function
2479  * Called with netif_tx_lock held.
2480  */
2481 static void nv_tx_timeout(struct net_device *dev)
2482 {
2483         struct fe_priv *np = netdev_priv(dev);
2484         u8 __iomem *base = get_hwbase(dev);
2485         u32 status;
2486
2487         if (np->msi_flags & NV_MSI_X_ENABLED)
2488                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2489         else
2490                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2491
2492         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
2493
2494         {
2495                 int i;
2496
2497                 printk(KERN_INFO "%s: Ring at %lx\n",
2498                        dev->name, (unsigned long)np->ring_addr);
2499                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
2500                 for (i=0;i<=np->register_size;i+= 32) {
2501                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2502                                         i,
2503                                         readl(base + i + 0), readl(base + i + 4),
2504                                         readl(base + i + 8), readl(base + i + 12),
2505                                         readl(base + i + 16), readl(base + i + 20),
2506                                         readl(base + i + 24), readl(base + i + 28));
2507                 }
2508                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
2509                 for (i=0;i<np->tx_ring_size;i+= 4) {
2510                         if (!nv_optimized(np)) {
2511                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2512                                        i,
2513                                        le32_to_cpu(np->tx_ring.orig[i].buf),
2514                                        le32_to_cpu(np->tx_ring.orig[i].flaglen),
2515                                        le32_to_cpu(np->tx_ring.orig[i+1].buf),
2516                                        le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2517                                        le32_to_cpu(np->tx_ring.orig[i+2].buf),
2518                                        le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2519                                        le32_to_cpu(np->tx_ring.orig[i+3].buf),
2520                                        le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2521                         } else {
2522                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2523                                        i,
2524                                        le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2525                                        le32_to_cpu(np->tx_ring.ex[i].buflow),
2526                                        le32_to_cpu(np->tx_ring.ex[i].flaglen),
2527                                        le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2528                                        le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2529                                        le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2530                                        le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2531                                        le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2532                                        le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2533                                        le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2534                                        le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2535                                        le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2536                         }
2537                 }
2538         }
2539
2540         spin_lock_irq(&np->lock);
2541
2542         /* 1) stop tx engine */
2543         nv_stop_tx(dev);
2544
2545         /* 2) check that the packets were not sent already: */
2546         if (!nv_optimized(np))
2547                 nv_tx_done(dev);
2548         else
2549                 nv_tx_done_optimized(dev, np->tx_ring_size);
2550
2551         /* 3) if there are dead entries: clear everything */
2552         if (np->get_tx_ctx != np->put_tx_ctx) {
2553                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
2554                 nv_drain_tx(dev);
2555                 nv_init_tx(dev);
2556                 setup_hw_rings(dev, NV_SETUP_TX_RING);
2557         }
2558
2559         netif_wake_queue(dev);
2560
2561         /* 4) restart tx engine */
2562         nv_start_tx(dev);
2563         spin_unlock_irq(&np->lock);
2564 }
2565
2566 /*
2567  * Called when the nic notices a mismatch between the actual data len on the
2568  * wire and the len indicated in the 802 header
2569  */
2570 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2571 {
2572         int hdrlen;     /* length of the 802 header */
2573         int protolen;   /* length as stored in the proto field */
2574
2575         /* 1) calculate len according to header */
2576         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2577                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2578                 hdrlen = VLAN_HLEN;
2579         } else {
2580                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2581                 hdrlen = ETH_HLEN;
2582         }
2583         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2584                                 dev->name, datalen, protolen, hdrlen);
2585         if (protolen > ETH_DATA_LEN)
2586                 return datalen; /* Value in proto field not a len, no checks possible */
2587
2588         protolen += hdrlen;
2589         /* consistency checks: */
2590         if (datalen > ETH_ZLEN) {
2591                 if (datalen >= protolen) {
2592                         /* more data on wire than in 802 header, trim of
2593                          * additional data.
2594                          */
2595                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2596                                         dev->name, protolen);
2597                         return protolen;
2598                 } else {
2599                         /* less data on wire than mentioned in header.
2600                          * Discard the packet.
2601                          */
2602                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2603                                         dev->name);
2604                         return -1;
2605                 }
2606         } else {
2607                 /* short packet. Accept only if 802 values are also short */
2608                 if (protolen > ETH_ZLEN) {
2609                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2610                                         dev->name);
2611                         return -1;
2612                 }
2613                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2614                                 dev->name, datalen);
2615                 return datalen;
2616         }
2617 }
2618
2619 static int nv_rx_process(struct net_device *dev, int limit)
2620 {
2621         struct fe_priv *np = netdev_priv(dev);
2622         u32 flags;
2623         int rx_work = 0;
2624         struct sk_buff *skb;
2625         int len;
2626
2627         while((np->get_rx.orig != np->put_rx.orig) &&
2628               !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2629                 (rx_work < limit)) {
2630
2631                 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2632                                         dev->name, flags);
2633
2634                 /*
2635                  * the packet is for us - immediately tear down the pci mapping.
2636                  * TODO: check if a prefetch of the first cacheline improves
2637                  * the performance.
2638                  */
2639                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2640                                 np->get_rx_ctx->dma_len,
2641                                 PCI_DMA_FROMDEVICE);
2642                 skb = np->get_rx_ctx->skb;
2643                 np->get_rx_ctx->skb = NULL;
2644
2645                 {
2646                         int j;
2647                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2648                         for (j=0; j<64; j++) {
2649                                 if ((j%16) == 0)
2650                                         dprintk("\n%03x:", j);
2651                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2652                         }
2653                         dprintk("\n");
2654                 }
2655                 /* look at what we actually got: */
2656                 if (np->desc_ver == DESC_VER_1) {
2657                         if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2658                                 len = flags & LEN_MASK_V1;
2659                                 if (unlikely(flags & NV_RX_ERROR)) {
2660                                         if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2661                                                 len = nv_getlen(dev, skb->data, len);
2662                                                 if (len < 0) {
2663                                                         dev->stats.rx_errors++;
2664                                                         dev_kfree_skb(skb);
2665                                                         goto next_pkt;
2666                                                 }
2667                                         }
2668                                         /* framing errors are soft errors */
2669                                         else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2670                                                 if (flags & NV_RX_SUBSTRACT1) {
2671                                                         len--;
2672                                                 }
2673                                         }
2674                                         /* the rest are hard errors */
2675                                         else {
2676                                                 if (flags & NV_RX_MISSEDFRAME)
2677                                                         dev->stats.rx_missed_errors++;
2678                                                 if (flags & NV_RX_CRCERR)
2679                                                         dev->stats.rx_crc_errors++;
2680                                                 if (flags & NV_RX_OVERFLOW)
2681                                                         dev->stats.rx_over_errors++;
2682                                                 dev->stats.rx_errors++;
2683                                                 dev_kfree_skb(skb);
2684                                                 goto next_pkt;
2685                                         }
2686                                 }
2687                         } else {
2688                                 dev_kfree_skb(skb);
2689                                 goto next_pkt;
2690                         }
2691                 } else {
2692                         if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2693                                 len = flags & LEN_MASK_V2;
2694                                 if (unlikely(flags & NV_RX2_ERROR)) {
2695                                         if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2696                                                 len = nv_getlen(dev, skb->data, len);
2697                                                 if (len < 0) {
2698                                                         dev->stats.rx_errors++;
2699                                                         dev_kfree_skb(skb);
2700                                                         goto next_pkt;
2701                                                 }
2702                                         }
2703                                         /* framing errors are soft errors */
2704                                         else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2705                                                 if (flags & NV_RX2_SUBSTRACT1) {
2706                                                         len--;
2707                                                 }
2708                                         }
2709                                         /* the rest are hard errors */
2710                                         else {
2711                                                 if (flags & NV_RX2_CRCERR)
2712                                                         dev->stats.rx_crc_errors++;
2713                                                 if (flags & NV_RX2_OVERFLOW)
2714                                                         dev->stats.rx_over_errors++;
2715                                                 dev->stats.rx_errors++;
2716                                                 dev_kfree_skb(skb);
2717                                                 goto next_pkt;
2718                                         }
2719                                 }
2720                                 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2721                                     ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2722                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2723                         } else {
2724                                 dev_kfree_skb(skb);
2725                                 goto next_pkt;
2726                         }
2727                 }
2728                 /* got a valid packet - forward it to the network core */
2729                 skb_put(skb, len);
2730                 skb->protocol = eth_type_trans(skb, dev);
2731                 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2732                                         dev->name, len, skb->protocol);
2733 #ifdef CONFIG_FORCEDETH_NAPI
2734                 netif_receive_skb(skb);
2735 #else
2736                 netif_rx(skb);
2737 #endif
2738                 dev->stats.rx_packets++;
2739                 dev->stats.rx_bytes += len;
2740 next_pkt:
2741                 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2742                         np->get_rx.orig = np->first_rx.orig;
2743                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2744                         np->get_rx_ctx = np->first_rx_ctx;
2745
2746                 rx_work++;
2747         }
2748
2749         return rx_work;
2750 }
2751
2752 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2753 {
2754         struct fe_priv *np = netdev_priv(dev);
2755         u32 flags;
2756         u32 vlanflags = 0;
2757         int rx_work = 0;
2758         struct sk_buff *skb;
2759         int len;
2760
2761         while((np->get_rx.ex != np->put_rx.ex) &&
2762               !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2763               (rx_work < limit)) {
2764
2765                 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2766                                         dev->name, flags);
2767
2768                 /*
2769                  * the packet is for us - immediately tear down the pci mapping.
2770                  * TODO: check if a prefetch of the first cacheline improves
2771                  * the performance.
2772                  */
2773                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2774                                 np->get_rx_ctx->dma_len,
2775                                 PCI_DMA_FROMDEVICE);
2776                 skb = np->get_rx_ctx->skb;
2777                 np->get_rx_ctx->skb = NULL;
2778
2779                 {
2780                         int j;
2781                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2782                         for (j=0; j<64; j++) {
2783                                 if ((j%16) == 0)
2784                                         dprintk("\n%03x:", j);
2785                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2786                         }
2787                         dprintk("\n");
2788                 }
2789                 /* look at what we actually got: */
2790                 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2791                         len = flags & LEN_MASK_V2;
2792                         if (unlikely(flags & NV_RX2_ERROR)) {
2793                                 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2794                                         len = nv_getlen(dev, skb->data, len);
2795                                         if (len < 0) {
2796                                                 dev_kfree_skb(skb);
2797                                                 goto next_pkt;
2798                                         }
2799                                 }
2800                                 /* framing errors are soft errors */
2801                                 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2802                                         if (flags & NV_RX2_SUBSTRACT1) {
2803                                                 len--;
2804                                         }
2805                                 }
2806                                 /* the rest are hard errors */
2807                                 else {
2808                                         dev_kfree_skb(skb);
2809                                         goto next_pkt;
2810                                 }
2811                         }
2812
2813                         if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2814                             ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2815                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2816
2817                         /* got a valid packet - forward it to the network core */
2818                         skb_put(skb, len);
2819                         skb->protocol = eth_type_trans(skb, dev);
2820                         prefetch(skb->data);
2821
2822                         dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2823                                 dev->name, len, skb->protocol);
2824
2825                         if (likely(!np->vlangrp)) {
2826 #ifdef CONFIG_FORCEDETH_NAPI
2827                                 netif_receive_skb(skb);
2828 #else
2829                                 netif_rx(skb);
2830 #endif
2831                         } else {
2832                                 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2833                                 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2834 #ifdef CONFIG_FORCEDETH_NAPI
2835                                         vlan_hwaccel_receive_skb(skb, np->vlangrp,
2836                                                                  vlanflags & NV_RX3_VLAN_TAG_MASK);
2837 #else
2838                                         vlan_hwaccel_rx(skb, np->vlangrp,
2839                                                         vlanflags & NV_RX3_VLAN_TAG_MASK);
2840 #endif
2841                                 } else {
2842 #ifdef CONFIG_FORCEDETH_NAPI
2843                                         netif_receive_skb(skb);
2844 #else
2845                                         netif_rx(skb);
2846 #endif
2847                                 }
2848                         }
2849
2850                         dev->stats.rx_packets++;
2851                         dev->stats.rx_bytes += len;
2852                 } else {
2853                         dev_kfree_skb(skb);
2854                 }
2855 next_pkt:
2856                 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2857                         np->get_rx.ex = np->first_rx.ex;
2858                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2859                         np->get_rx_ctx = np->first_rx_ctx;
2860
2861                 rx_work++;
2862         }
2863
2864         return rx_work;
2865 }
2866
2867 static void set_bufsize(struct net_device *dev)
2868 {
2869         struct fe_priv *np = netdev_priv(dev);
2870
2871         if (dev->mtu <= ETH_DATA_LEN)
2872                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2873         else
2874                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2875 }
2876
2877 /*
2878  * nv_change_mtu: dev->change_mtu function
2879  * Called with dev_base_lock held for read.
2880  */
2881 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2882 {
2883         struct fe_priv *np = netdev_priv(dev);
2884         int old_mtu;
2885
2886         if (new_mtu < 64 || new_mtu > np->pkt_limit)
2887                 return -EINVAL;
2888
2889         old_mtu = dev->mtu;
2890         dev->mtu = new_mtu;
2891
2892         /* return early if the buffer sizes will not change */
2893         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2894                 return 0;
2895         if (old_mtu == new_mtu)
2896                 return 0;
2897
2898         /* synchronized against open : rtnl_lock() held by caller */
2899         if (netif_running(dev)) {
2900                 u8 __iomem *base = get_hwbase(dev);
2901                 /*
2902                  * It seems that the nic preloads valid ring entries into an
2903                  * internal buffer. The procedure for flushing everything is
2904                  * guessed, there is probably a simpler approach.
2905                  * Changing the MTU is a rare event, it shouldn't matter.
2906                  */
2907                 nv_disable_irq(dev);
2908                 netif_tx_lock_bh(dev);
2909                 netif_addr_lock(dev);
2910                 spin_lock(&np->lock);
2911                 /* stop engines */
2912                 nv_stop_rxtx(dev);
2913                 nv_txrx_reset(dev);
2914                 /* drain rx queue */
2915                 nv_drain_rxtx(dev);
2916                 /* reinit driver view of the rx queue */
2917                 set_bufsize(dev);
2918                 if (nv_init_ring(dev)) {
2919                         if (!np->in_shutdown)
2920                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2921                 }
2922                 /* reinit nic view of the rx queue */
2923                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2924                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2925                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2926                         base + NvRegRingSizes);
2927                 pci_push(base);
2928                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2929                 pci_push(base);
2930
2931                 /* restart rx engine */
2932                 nv_start_rxtx(dev);
2933                 spin_unlock(&np->lock);
2934                 netif_addr_unlock(dev);
2935                 netif_tx_unlock_bh(dev);
2936                 nv_enable_irq(dev);
2937         }
2938         return 0;
2939 }
2940
2941 static void nv_copy_mac_to_hw(struct net_device *dev)
2942 {
2943         u8 __iomem *base = get_hwbase(dev);
2944         u32 mac[2];
2945
2946         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2947                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2948         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2949
2950         writel(mac[0], base + NvRegMacAddrA);
2951         writel(mac[1], base + NvRegMacAddrB);
2952 }
2953
2954 /*
2955  * nv_set_mac_address: dev->set_mac_address function
2956  * Called with rtnl_lock() held.
2957  */
2958 static int nv_set_mac_address(struct net_device *dev, void *addr)
2959 {
2960         struct fe_priv *np = netdev_priv(dev);
2961         struct sockaddr *macaddr = (struct sockaddr*)addr;
2962
2963         if (!is_valid_ether_addr(macaddr->sa_data))
2964                 return -EADDRNOTAVAIL;
2965
2966         /* synchronized against open : rtnl_lock() held by caller */
2967         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2968
2969         if (netif_running(dev)) {
2970                 netif_tx_lock_bh(dev);
2971                 netif_addr_lock(dev);
2972                 spin_lock_irq(&np->lock);
2973
2974                 /* stop rx engine */
2975                 nv_stop_rx(dev);
2976
2977                 /* set mac address */
2978                 nv_copy_mac_to_hw(dev);
2979
2980                 /* restart rx engine */
2981                 nv_start_rx(dev);
2982                 spin_unlock_irq(&np->lock);
2983                 netif_addr_unlock(dev);
2984                 netif_tx_unlock_bh(dev);
2985         } else {
2986                 nv_copy_mac_to_hw(dev);
2987         }
2988         return 0;
2989 }
2990
2991 /*
2992  * nv_set_multicast: dev->set_multicast function
2993  * Called with netif_tx_lock held.
2994  */
2995 static void nv_set_multicast(struct net_device *dev)
2996 {
2997         struct fe_priv *np = netdev_priv(dev);
2998         u8 __iomem *base = get_hwbase(dev);
2999         u32 addr[2];
3000         u32 mask[2];
3001         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
3002
3003         memset(addr, 0, sizeof(addr));
3004         memset(mask, 0, sizeof(mask));
3005
3006         if (dev->flags & IFF_PROMISC) {
3007                 pff |= NVREG_PFF_PROMISC;
3008         } else {
3009                 pff |= NVREG_PFF_MYADDR;
3010
3011                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
3012                         u32 alwaysOff[2];
3013                         u32 alwaysOn[2];
3014
3015                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
3016                         if (dev->flags & IFF_ALLMULTI) {
3017                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
3018                         } else {
3019                                 struct dev_mc_list *walk;
3020
3021                                 walk = dev->mc_list;
3022                                 while (walk != NULL) {
3023                                         u32 a, b;
3024                                         a = le32_to_cpu(*(__le32 *) walk->dmi_addr);
3025                                         b = le16_to_cpu(*(__le16 *) (&walk->dmi_addr[4]));
3026                                         alwaysOn[0] &= a;
3027                                         alwaysOff[0] &= ~a;
3028                                         alwaysOn[1] &= b;
3029                                         alwaysOff[1] &= ~b;
3030                                         walk = walk->next;
3031                                 }
3032                         }
3033                         addr[0] = alwaysOn[0];
3034                         addr[1] = alwaysOn[1];
3035                         mask[0] = alwaysOn[0] | alwaysOff[0];
3036                         mask[1] = alwaysOn[1] | alwaysOff[1];
3037                 } else {
3038                         mask[0] = NVREG_MCASTMASKA_NONE;
3039                         mask[1] = NVREG_MCASTMASKB_NONE;
3040                 }
3041         }
3042         addr[0] |= NVREG_MCASTADDRA_FORCE;
3043         pff |= NVREG_PFF_ALWAYS;
3044         spin_lock_irq(&np->lock);
3045         nv_stop_rx(dev);
3046         writel(addr[0], base + NvRegMulticastAddrA);
3047         writel(addr[1], base + NvRegMulticastAddrB);
3048         writel(mask[0], base + NvRegMulticastMaskA);
3049         writel(mask[1], base + NvRegMulticastMaskB);
3050         writel(pff, base + NvRegPacketFilterFlags);
3051         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
3052                 dev->name);
3053         nv_start_rx(dev);
3054         spin_unlock_irq(&np->lock);
3055 }
3056
3057 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
3058 {
3059         struct fe_priv *np = netdev_priv(dev);
3060         u8 __iomem *base = get_hwbase(dev);
3061
3062         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3063
3064         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3065                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3066                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3067                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3068                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3069                 } else {
3070                         writel(pff, base + NvRegPacketFilterFlags);
3071                 }
3072         }
3073         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3074                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3075                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3076                         u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3077                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3078                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3079                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3080                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3081                                 /* limit the number of tx pause frames to a default of 8 */
3082                                 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3083                         }
3084                         writel(pause_enable,  base + NvRegTxPauseFrame);
3085                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3086                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3087                 } else {
3088                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
3089                         writel(regmisc, base + NvRegMisc1);
3090                 }
3091         }
3092 }
3093
3094 /**
3095  * nv_update_linkspeed: Setup the MAC according to the link partner
3096  * @dev: Network device to be configured
3097  *
3098  * The function queries the PHY and checks if there is a link partner.
3099  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3100  * set to 10 MBit HD.
3101  *
3102  * The function returns 0 if there is no link partner and 1 if there is
3103  * a good link partner.
3104  */
3105 static int nv_update_linkspeed(struct net_device *dev)
3106 {
3107         struct fe_priv *np = netdev_priv(dev);
3108         u8 __iomem *base = get_hwbase(dev);
3109         int adv = 0;
3110         int lpa = 0;
3111         int adv_lpa, adv_pause, lpa_pause;
3112         int newls = np->linkspeed;
3113         int newdup = np->duplex;
3114         int mii_status;
3115         int retval = 0;
3116         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3117         u32 txrxFlags = 0;
3118         u32 phy_exp;
3119
3120         /* BMSR_LSTATUS is latched, read it twice:
3121          * we want the current value.
3122          */
3123         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3124         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3125
3126         if (!(mii_status & BMSR_LSTATUS)) {
3127                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
3128                                 dev->name);
3129                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3130                 newdup = 0;
3131                 retval = 0;
3132                 goto set_speed;
3133         }
3134
3135         if (np->autoneg == 0) {
3136                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
3137                                 dev->name, np->fixed_mode);
3138                 if (np->fixed_mode & LPA_100FULL) {
3139                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3140                         newdup = 1;
3141                 } else if (np->fixed_mode & LPA_100HALF) {
3142                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3143                         newdup = 0;
3144                 } else if (np->fixed_mode & LPA_10FULL) {
3145                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3146                         newdup = 1;
3147                 } else {
3148                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3149                         newdup = 0;
3150                 }
3151                 retval = 1;
3152                 goto set_speed;
3153         }
3154         /* check auto negotiation is complete */
3155         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3156                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3157                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3158                 newdup = 0;
3159                 retval = 0;
3160                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
3161                 goto set_speed;
3162         }
3163
3164         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3165         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3166         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
3167                                 dev->name, adv, lpa);
3168
3169         retval = 1;
3170         if (np->gigabit == PHY_GIGABIT) {
3171                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3172                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3173
3174                 if ((control_1000 & ADVERTISE_1000FULL) &&
3175                         (status_1000 & LPA_1000FULL)) {
3176                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
3177                                 dev->name);
3178                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3179                         newdup = 1;
3180                         goto set_speed;
3181                 }
3182         }
3183
3184         /* FIXME: handle parallel detection properly */
3185         adv_lpa = lpa & adv;
3186         if (adv_lpa & LPA_100FULL) {
3187                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3188                 newdup = 1;
3189         } else if (adv_lpa & LPA_100HALF) {
3190                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3191                 newdup = 0;
3192         } else if (adv_lpa & LPA_10FULL) {
3193                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3194                 newdup = 1;
3195         } else if (adv_lpa & LPA_10HALF) {
3196                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3197                 newdup = 0;
3198         } else {
3199                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
3200                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3201                 newdup = 0;
3202         }
3203
3204 set_speed:
3205         if (np->duplex == newdup && np->linkspeed == newls)
3206                 return retval;
3207
3208         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
3209                         dev->name, np->linkspeed, np->duplex, newls, newdup);
3210
3211         np->duplex = newdup;
3212         np->linkspeed = newls;
3213
3214         /* The transmitter and receiver must be restarted for safe update */
3215         if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3216                 txrxFlags |= NV_RESTART_TX;
3217                 nv_stop_tx(dev);
3218         }
3219         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3220                 txrxFlags |= NV_RESTART_RX;
3221                 nv_stop_rx(dev);
3222         }
3223
3224         if (np->gigabit == PHY_GIGABIT) {
3225                 phyreg = readl(base + NvRegSlotTime);
3226                 phyreg &= ~(0x3FF00);
3227                 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3228                     ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3229                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
3230                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3231                         phyreg |= NVREG_SLOTTIME_1000_FULL;
3232                 writel(phyreg, base + NvRegSlotTime);
3233         }
3234
3235         phyreg = readl(base + NvRegPhyInterface);
3236         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3237         if (np->duplex == 0)
3238                 phyreg |= PHY_HALF;
3239         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3240                 phyreg |= PHY_100;
3241         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3242                 phyreg |= PHY_1000;
3243         writel(phyreg, base + NvRegPhyInterface);
3244
3245         phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3246         if (phyreg & PHY_RGMII) {
3247                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3248                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3249                 } else {
3250                         if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3251                                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3252                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3253                                 else
3254                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3255                         } else {
3256                                 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3257                         }
3258                 }
3259         } else {
3260                 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3261                         txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3262                 else
3263                         txreg = NVREG_TX_DEFERRAL_DEFAULT;
3264         }
3265         writel(txreg, base + NvRegTxDeferral);
3266
3267         if (np->desc_ver == DESC_VER_1) {
3268                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3269         } else {
3270                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3271                         txreg = NVREG_TX_WM_DESC2_3_1000;
3272                 else
3273                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3274         }
3275         writel(txreg, base + NvRegTxWatermark);
3276
3277         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
3278                 base + NvRegMisc1);
3279         pci_push(base);
3280         writel(np->linkspeed, base + NvRegLinkSpeed);
3281         pci_push(base);
3282
3283         pause_flags = 0;
3284         /* setup pause frame */
3285         if (np->duplex != 0) {
3286                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3287                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
3288                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
3289
3290                         switch (adv_pause) {
3291                         case ADVERTISE_PAUSE_CAP:
3292                                 if (lpa_pause & LPA_PAUSE_CAP) {
3293                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3294                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3295                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3296                                 }
3297                                 break;
3298                         case ADVERTISE_PAUSE_ASYM:
3299                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
3300                                 {
3301                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3302                                 }
3303                                 break;
3304                         case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
3305                                 if (lpa_pause & LPA_PAUSE_CAP)
3306                                 {
3307                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
3308                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3309                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3310                                 }
3311                                 if (lpa_pause == LPA_PAUSE_ASYM)
3312                                 {
3313                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3314                                 }
3315                                 break;
3316                         }
3317                 } else {
3318                         pause_flags = np->pause_flags;
3319                 }
3320         }
3321         nv_update_pause(dev, pause_flags);
3322
3323         if (txrxFlags & NV_RESTART_TX)
3324                 nv_start_tx(dev);
3325         if (txrxFlags & NV_RESTART_RX)
3326                 nv_start_rx(dev);
3327
3328         return retval;
3329 }
3330
3331 static void nv_linkchange(struct net_device *dev)
3332 {
3333         if (nv_update_linkspeed(dev)) {
3334                 if (!netif_carrier_ok(dev)) {
3335                         netif_carrier_on(dev);
3336                         printk(KERN_INFO "%s: link up.\n", dev->name);
3337                         nv_start_rx(dev);
3338                 }
3339         } else {
3340                 if (netif_carrier_ok(dev)) {
3341                         netif_carrier_off(dev);
3342                         printk(KERN_INFO "%s: link down.\n", dev->name);
3343                         nv_stop_rx(dev);
3344                 }
3345         }
3346 }
3347
3348 static void nv_link_irq(struct net_device *dev)
3349 {
3350         u8 __iomem *base = get_hwbase(dev);
3351         u32 miistat;
3352
3353         miistat = readl(base + NvRegMIIStatus);
3354         writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3355         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
3356
3357         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3358                 nv_linkchange(dev);
3359         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
3360 }
3361
3362 static void nv_msi_workaround(struct fe_priv *np)
3363 {
3364
3365         /* Need to toggle the msi irq mask within the ethernet device,
3366          * otherwise, future interrupts will not be detected.
3367          */
3368         if (np->msi_flags & NV_MSI_ENABLED) {
3369                 u8 __iomem *base = np->base;
3370
3371                 writel(0, base + NvRegMSIIrqMask);
3372                 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3373         }
3374 }
3375
3376 static irqreturn_t nv_nic_irq(int foo, void *data)
3377 {
3378         struct net_device *dev = (struct net_device *) data;
3379         struct fe_priv *np = netdev_priv(dev);
3380         u8 __iomem *base = get_hwbase(dev);
3381         u32 events;
3382         int i;
3383
3384         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
3385
3386         for (i=0; ; i++) {
3387                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3388                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3389                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3390                 } else {
3391                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3392                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3393                 }
3394                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3395                 if (!(events & np->irqmask))
3396                         break;
3397
3398                 nv_msi_workaround(np);
3399
3400                 spin_lock(&np->lock);
3401                 nv_tx_done(dev);
3402                 spin_unlock(&np->lock);
3403
3404 #ifdef CONFIG_FORCEDETH_NAPI
3405                 if (events & NVREG_IRQ_RX_ALL) {
3406                         netif_rx_schedule(dev, &np->napi);
3407
3408                         /* Disable furthur receive irq's */
3409                         spin_lock(&np->lock);
3410                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
3411
3412                         if (np->msi_flags & NV_MSI_X_ENABLED)
3413                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3414                         else
3415                                 writel(np->irqmask, base + NvRegIrqMask);
3416                         spin_unlock(&np->lock);
3417                 }
3418 #else
3419                 if (nv_rx_process(dev, RX_WORK_PER_LOOP)) {
3420                         if (unlikely(nv_alloc_rx(dev))) {
3421                                 spin_lock(&np->lock);
3422                                 if (!np->in_shutdown)
3423                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3424                                 spin_unlock(&np->lock);
3425                         }
3426                 }
3427 #endif
3428                 if (unlikely(events & NVREG_IRQ_LINK)) {
3429                         spin_lock(&np->lock);
3430                         nv_link_irq(dev);
3431                         spin_unlock(&np->lock);
3432                 }
3433                 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3434                         spin_lock(&np->lock);
3435                         nv_linkchange(dev);
3436                         spin_unlock(&np->lock);
3437                         np->link_timeout = jiffies + LINK_TIMEOUT;
3438                 }
3439                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3440                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3441                                                 dev->name, events);
3442                 }
3443                 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
3444                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3445                                                 dev->name, events);
3446                 }
3447                 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3448                         spin_lock(&np->lock);
3449                         /* disable interrupts on the nic */
3450                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3451                                 writel(0, base + NvRegIrqMask);
3452                         else
3453                                 writel(np->irqmask, base + NvRegIrqMask);
3454                         pci_push(base);
3455
3456                         if (!np->in_shutdown) {
3457                                 np->nic_poll_irq = np->irqmask;
3458                                 np->recover_error = 1;
3459                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3460                         }
3461                         spin_unlock(&np->lock);
3462                         break;
3463                 }
3464                 if (unlikely(i > max_interrupt_work)) {
3465                         spin_lock(&np->lock);
3466                         /* disable interrupts on the nic */
3467                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3468                                 writel(0, base + NvRegIrqMask);
3469                         else
3470                                 writel(np->irqmask, base + NvRegIrqMask);
3471                         pci_push(base);
3472
3473                         if (!np->in_shutdown) {
3474                                 np->nic_poll_irq = np->irqmask;
3475                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3476                         }
3477                         spin_unlock(&np->lock);
3478                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
3479                         break;
3480                 }
3481
3482         }
3483         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
3484
3485         return IRQ_RETVAL(i);
3486 }
3487
3488 /**
3489  * All _optimized functions are used to help increase performance
3490  * (reduce CPU and increase throughput). They use descripter version 3,
3491  * compiler directives, and reduce memory accesses.
3492  */
3493 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3494 {
3495         struct net_device *dev = (struct net_device *) data;
3496         struct fe_priv *np = netdev_priv(dev);
3497         u8 __iomem *base = get_hwbase(dev);
3498         u32 events;
3499         int i;
3500
3501         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
3502
3503         for (i=0; ; i++) {
3504                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3505                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3506                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3507                 } else {
3508                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3509                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3510                 }
3511                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3512                 if (!(events & np->irqmask))
3513                         break;
3514
3515                 nv_msi_workaround(np);
3516
3517                 spin_lock(&np->lock);
3518                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3519                 spin_unlock(&np->lock);
3520
3521 #ifdef CONFIG_FORCEDETH_NAPI
3522                 if (events & NVREG_IRQ_RX_ALL) {
3523                         netif_rx_schedule(dev, &np->napi);
3524
3525                         /* Disable furthur receive irq's */
3526                         spin_lock(&np->lock);
3527                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
3528
3529                         if (np->msi_flags & NV_MSI_X_ENABLED)
3530                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3531                         else
3532                                 writel(np->irqmask, base + NvRegIrqMask);
3533                         spin_unlock(&np->lock);
3534                 }
3535 #else
3536                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3537                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3538                                 spin_lock(&np->lock);
3539                                 if (!np->in_shutdown)
3540                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3541                                 spin_unlock(&np->lock);
3542                         }
3543                 }
3544 #endif
3545                 if (unlikely(events & NVREG_IRQ_LINK)) {
3546                         spin_lock(&np->lock);
3547                         nv_link_irq(dev);
3548                         spin_unlock(&np->lock);
3549                 }
3550                 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3551                         spin_lock(&np->lock);
3552                         nv_linkchange(dev);
3553                         spin_unlock(&np->lock);
3554                         np->link_timeout = jiffies + LINK_TIMEOUT;
3555                 }
3556                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3557                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3558                                                 dev->name, events);
3559                 }
3560                 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
3561                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3562                                                 dev->name, events);
3563                 }
3564                 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3565                         spin_lock(&np->lock);
3566                         /* disable interrupts on the nic */
3567                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3568                                 writel(0, base + NvRegIrqMask);
3569                         else
3570                                 writel(np->irqmask, base + NvRegIrqMask);
3571                         pci_push(base);
3572
3573                         if (!np->in_shutdown) {
3574                                 np->nic_poll_irq = np->irqmask;
3575                                 np->recover_error = 1;
3576                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3577                         }
3578                         spin_unlock(&np->lock);
3579                         break;
3580                 }
3581
3582                 if (unlikely(i > max_interrupt_work)) {
3583                         spin_lock(&np->lock);
3584                         /* disable interrupts on the nic */
3585                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3586                                 writel(0, base + NvRegIrqMask);
3587                         else
3588                                 writel(np->irqmask, base + NvRegIrqMask);
3589                         pci_push(base);
3590
3591                         if (!np->in_shutdown) {
3592                                 np->nic_poll_irq = np->irqmask;
3593                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3594                         }
3595                         spin_unlock(&np->lock);
3596                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
3597                         break;
3598                 }
3599
3600         }
3601         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3602
3603         return IRQ_RETVAL(i);
3604 }
3605
3606 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3607 {
3608         struct net_device *dev = (struct net_device *) data;
3609         struct fe_priv *np = netdev_priv(dev);
3610         u8 __iomem *base = get_hwbase(dev);
3611         u32 events;
3612         int i;
3613         unsigned long flags;
3614
3615         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3616
3617         for (i=0; ; i++) {
3618                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3619                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3620                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3621                 if (!(events & np->irqmask))
3622                         break;
3623
3624                 spin_lock_irqsave(&np->lock, flags);
3625                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3626                 spin_unlock_irqrestore(&np->lock, flags);
3627
3628                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3629                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3630                                                 dev->name, events);
3631                 }
3632                 if (unlikely(i > max_interrupt_work)) {
3633                         spin_lock_irqsave(&np->lock, flags);
3634                         /* disable interrupts on the nic */
3635                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3636                         pci_push(base);
3637
3638                         if (!np->in_shutdown) {
3639                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3640                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3641                         }
3642                         spin_unlock_irqrestore(&np->lock, flags);
3643                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
3644                         break;
3645                 }
3646
3647         }
3648         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3649
3650         return IRQ_RETVAL(i);
3651 }
3652
3653 #ifdef CONFIG_FORCEDETH_NAPI
3654 static int nv_napi_poll(struct napi_struct *napi, int budget)
3655 {
3656         struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3657         struct net_device *dev = np->dev;
3658         u8 __iomem *base = get_hwbase(dev);
3659         unsigned long flags;
3660         int pkts, retcode;
3661
3662         if (!nv_optimized(np)) {
3663                 pkts = nv_rx_process(dev, budget);
3664                 retcode = nv_alloc_rx(dev);
3665         } else {
3666                 pkts = nv_rx_process_optimized(dev, budget);
3667                 retcode = nv_alloc_rx_optimized(dev);
3668         }
3669
3670         if (retcode) {
3671                 spin_lock_irqsave(&np->lock, flags);
3672                 if (!np->in_shutdown)
3673                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3674                 spin_unlock_irqrestore(&np->lock, flags);
3675         }
3676
3677         if (pkts < budget) {
3678                 /* re-enable receive interrupts */
3679                 spin_lock_irqsave(&np->lock, flags);
3680
3681                 __netif_rx_complete(dev, napi);
3682
3683                 np->irqmask |= NVREG_IRQ_RX_ALL;
3684                 if (np->msi_flags & NV_MSI_X_ENABLED)
3685                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3686                 else
3687                         writel(np->irqmask, base + NvRegIrqMask);
3688
3689                 spin_unlock_irqrestore(&np->lock, flags);
3690         }
3691         return pkts;
3692 }
3693 #endif
3694
3695 #ifdef CONFIG_FORCEDETH_NAPI
3696 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3697 {
3698         struct net_device *dev = (struct net_device *) data;
3699         struct fe_priv *np = netdev_priv(dev);
3700         u8 __iomem *base = get_hwbase(dev);
3701         u32 events;
3702
3703         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3704         writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3705
3706         if (events) {
3707                 netif_rx_schedule(dev, &np->napi);
3708                 /* disable receive interrupts on the nic */
3709                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3710                 pci_push(base);
3711         }
3712         return IRQ_HANDLED;
3713 }
3714 #else
3715 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3716 {
3717         struct net_device *dev = (struct net_device *) data;
3718         struct fe_priv *np = netdev_priv(dev);
3719         u8 __iomem *base = get_hwbase(dev);
3720         u32 events;
3721         int i;
3722         unsigned long flags;
3723
3724         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3725
3726         for (i=0; ; i++) {
3727                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3728                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3729                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3730                 if (!(events & np->irqmask))
3731                         break;
3732
3733                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3734                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3735                                 spin_lock_irqsave(&np->lock, flags);
3736                                 if (!np->in_shutdown)
3737                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3738                                 spin_unlock_irqrestore(&np->lock, flags);
3739                         }
3740                 }
3741
3742                 if (unlikely(i > max_interrupt_work)) {
3743                         spin_lock_irqsave(&np->lock, flags);
3744                         /* disable interrupts on the nic */
3745                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3746                         pci_push(base);
3747
3748                         if (!np->in_shutdown) {
3749                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3750                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3751                         }
3752                         spin_unlock_irqrestore(&np->lock, flags);
3753                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
3754                         break;
3755                 }
3756         }
3757         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3758
3759         return IRQ_RETVAL(i);
3760 }
3761 #endif
3762
3763 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3764 {
3765         struct net_device *dev = (struct net_device *) data;
3766         struct fe_priv *np = netdev_priv(dev);
3767         u8 __iomem *base = get_hwbase(dev);
3768         u32 events;
3769         int i;
3770         unsigned long flags;
3771
3772         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3773
3774         for (i=0; ; i++) {
3775                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3776                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3777                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3778                 if (!(events & np->irqmask))
3779                         break;
3780
3781                 /* check tx in case we reached max loop limit in tx isr */
3782                 spin_lock_irqsave(&np->lock, flags);
3783                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3784                 spin_unlock_irqrestore(&np->lock, flags);
3785
3786                 if (events & NVREG_IRQ_LINK) {
3787                         spin_lock_irqsave(&np->lock, flags);
3788                         nv_link_irq(dev);
3789                         spin_unlock_irqrestore(&np->lock, flags);
3790                 }
3791                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3792                         spin_lock_irqsave(&np->lock, flags);
3793                         nv_linkchange(dev);
3794                         spin_unlock_irqrestore(&np->lock, flags);
3795                         np->link_timeout = jiffies + LINK_TIMEOUT;
3796                 }
3797                 if (events & NVREG_IRQ_RECOVER_ERROR) {
3798                         spin_lock_irq(&np->lock);
3799                         /* disable interrupts on the nic */
3800                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3801                         pci_push(base);
3802
3803                         if (!np->in_shutdown) {
3804                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3805                                 np->recover_error = 1;
3806                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3807                         }
3808                         spin_unlock_irq(&np->lock);
3809                         break;
3810                 }
3811                 if (events & (NVREG_IRQ_UNKNOWN)) {
3812                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3813                                                 dev->name, events);
3814                 }
3815                 if (unlikely(i > max_interrupt_work)) {
3816                         spin_lock_irqsave(&np->lock, flags);
3817                         /* disable interrupts on the nic */
3818                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3819                         pci_push(base);
3820
3821                         if (!np->in_shutdown) {
3822                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3823                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3824                         }
3825                         spin_unlock_irqrestore(&np->lock, flags);
3826                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
3827                         break;
3828                 }
3829
3830         }
3831         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3832
3833         return IRQ_RETVAL(i);
3834 }
3835
3836 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3837 {
3838         struct net_device *dev = (struct net_device *) data;
3839         struct fe_priv *np = netdev_priv(dev);
3840         u8 __iomem *base = get_hwbase(dev);
3841         u32 events;
3842
3843         dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3844
3845         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3846                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3847                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3848         } else {
3849                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3850                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3851         }
3852         pci_push(base);
3853         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3854         if (!(events & NVREG_IRQ_TIMER))
3855                 return IRQ_RETVAL(0);
3856
3857         nv_msi_workaround(np);
3858
3859         spin_lock(&np->lock);
3860         np->intr_test = 1;
3861         spin_unlock(&np->lock);
3862
3863         dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3864
3865         return IRQ_RETVAL(1);
3866 }
3867
3868 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3869 {
3870         u8 __iomem *base = get_hwbase(dev);
3871         int i;
3872         u32 msixmap = 0;
3873
3874         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3875          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3876          * the remaining 8 interrupts.
3877          */
3878         for (i = 0; i < 8; i++) {
3879                 if ((irqmask >> i) & 0x1) {
3880                         msixmap |= vector << (i << 2);
3881                 }
3882         }
3883         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3884
3885         msixmap = 0;
3886         for (i = 0; i < 8; i++) {
3887                 if ((irqmask >> (i + 8)) & 0x1) {
3888                         msixmap |= vector << (i << 2);
3889                 }
3890         }
3891         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3892 }
3893
3894 static int nv_request_irq(struct net_device *dev, int intr_test)
3895 {
3896         struct fe_priv *np = get_nvpriv(dev);
3897         u8 __iomem *base = get_hwbase(dev);
3898         int ret = 1;
3899         int i;
3900         irqreturn_t (*handler)(int foo, void *data);
3901
3902         if (intr_test) {
3903                 handler = nv_nic_irq_test;
3904         } else {
3905                 if (nv_optimized(np))
3906                         handler = nv_nic_irq_optimized;
3907                 else
3908                         handler = nv_nic_irq;
3909         }
3910
3911         if (np->msi_flags & NV_MSI_X_CAPABLE) {
3912                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3913                         np->msi_x_entry[i].entry = i;
3914                 }
3915                 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
3916                         np->msi_flags |= NV_MSI_X_ENABLED;
3917                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3918                                 /* Request irq for rx handling */
3919                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
3920                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
3921                                         pci_disable_msix(np->pci_dev);
3922                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3923                                         goto out_err;
3924                                 }
3925                                 /* Request irq for tx handling */
3926                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
3927                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
3928                                         pci_disable_msix(np->pci_dev);
3929                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3930                                         goto out_free_rx;
3931                                 }
3932                                 /* Request irq for link and timer handling */
3933                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
3934                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
3935                                         pci_disable_msix(np->pci_dev);
3936                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3937                                         goto out_free_tx;
3938                                 }
3939                                 /* map interrupts to their respective vector */
3940                                 writel(0, base + NvRegMSIXMap0);
3941                                 writel(0, base + NvRegMSIXMap1);
3942                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3943                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3944                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3945                         } else {
3946                                 /* Request irq for all interrupts */
3947                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3948                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3949                                         pci_disable_msix(np->pci_dev);
3950                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3951                                         goto out_err;
3952                                 }
3953
3954                                 /* map interrupts to vector 0 */
3955                                 writel(0, base + NvRegMSIXMap0);
3956                                 writel(0, base + NvRegMSIXMap1);
3957                         }
3958                 }
3959         }
3960         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3961                 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
3962                         np->msi_flags |= NV_MSI_ENABLED;
3963                         dev->irq = np->pci_dev->irq;
3964                         if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3965                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3966                                 pci_disable_msi(np->pci_dev);
3967                                 np->msi_flags &= ~NV_MSI_ENABLED;
3968                                 dev->irq = np->pci_dev->irq;
3969                                 goto out_err;
3970                         }
3971
3972                         /* map interrupts to vector 0 */
3973                         writel(0, base + NvRegMSIMap0);
3974                         writel(0, base + NvRegMSIMap1);
3975                         /* enable msi vector 0 */
3976                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3977                 }
3978         }
3979         if (ret != 0) {
3980                 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3981                         goto out_err;
3982
3983         }
3984
3985         return 0;
3986 out_free_tx:
3987         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3988 out_free_rx:
3989         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3990 out_err:
3991         return 1;
3992 }
3993
3994 static void nv_free_irq(struct net_device *dev)
3995 {
3996         struct fe_priv *np = get_nvpriv(dev);
3997         int i;
3998
3999         if (np->msi_flags & NV_MSI_X_ENABLED) {
4000                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
4001                         free_irq(np->msi_x_entry[i].vector, dev);
4002                 }
4003                 pci_disable_msix(np->pci_dev);
4004                 np->msi_flags &= ~NV_MSI_X_ENABLED;
4005         } else {
4006                 free_irq(np->pci_dev->irq, dev);
4007                 if (np->msi_flags & NV_MSI_ENABLED) {
4008                         pci_disable_msi(np->pci_dev);
4009                         np->msi_flags &= ~NV_MSI_ENABLED;
4010                 }
4011         }
4012 }
4013
4014 static void nv_do_nic_poll(unsigned long data)
4015 {
4016         struct net_device *dev = (struct net_device *) data;
4017         struct fe_priv *np = netdev_priv(dev);
4018         u8 __iomem *base = get_hwbase(dev);
4019         u32 mask = 0;
4020
4021         /*
4022          * First disable irq(s) and then
4023          * reenable interrupts on the nic, we have to do this before calling
4024          * nv_nic_irq because that may decide to do otherwise
4025          */
4026
4027         if (!using_multi_irqs(dev)) {
4028                 if (np->msi_flags & NV_MSI_X_ENABLED)
4029                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4030                 else
4031                         disable_irq_lockdep(np->pci_dev->irq);
4032                 mask = np->irqmask;
4033         } else {
4034                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4035                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4036                         mask |= NVREG_IRQ_RX_ALL;
4037                 }
4038                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4039                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4040                         mask |= NVREG_IRQ_TX_ALL;
4041                 }
4042                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4043                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4044                         mask |= NVREG_IRQ_OTHER;
4045                 }
4046         }
4047         np->nic_poll_irq = 0;
4048
4049         /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
4050
4051         if (np->recover_error) {
4052                 np->recover_error = 0;
4053                 printk(KERN_INFO "forcedeth: MAC in recoverable error state\n");
4054                 if (netif_running(dev)) {
4055                         netif_tx_lock_bh(dev);
4056                         netif_addr_lock(dev);
4057                         spin_lock(&np->lock);
4058                         /* stop engines */
4059                         nv_stop_rxtx(dev);
4060                         nv_txrx_reset(dev);
4061                         /* drain rx queue */
4062                         nv_drain_rxtx(dev);
4063                         /* reinit driver view of the rx queue */
4064                         set_bufsize(dev);
4065                         if (nv_init_ring(dev)) {
4066                                 if (!np->in_shutdown)
4067                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4068                         }
4069                         /* reinit nic view of the rx queue */
4070                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4071                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4072                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4073                                 base + NvRegRingSizes);
4074                         pci_push(base);
4075                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4076                         pci_push(base);
4077
4078                         /* restart rx engine */
4079                         nv_start_rxtx(dev);
4080                         spin_unlock(&np->lock);
4081                         netif_addr_unlock(dev);
4082                         netif_tx_unlock_bh(dev);
4083                 }
4084         }
4085
4086
4087         writel(mask, base + NvRegIrqMask);
4088         pci_push(base);
4089
4090         if (!using_multi_irqs(dev)) {
4091                 if (nv_optimized(np))
4092                         nv_nic_irq_optimized(0, dev);
4093                 else
4094                         nv_nic_irq(0, dev);
4095                 if (np->msi_flags & NV_MSI_X_ENABLED)
4096                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4097                 else
4098                         enable_irq_lockdep(np->pci_dev->irq);
4099         } else {
4100                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4101                         nv_nic_irq_rx(0, dev);
4102                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4103                 }
4104                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4105                         nv_nic_irq_tx(0, dev);
4106                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4107                 }
4108                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4109                         nv_nic_irq_other(0, dev);
4110                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4111                 }
4112         }
4113 }
4114
4115 #ifdef CONFIG_NET_POLL_CONTROLLER
4116 static void nv_poll_controller(struct net_device *dev)
4117 {
4118         nv_do_nic_poll((unsigned long) dev);
4119 }
4120 #endif
4121
4122 static void nv_do_stats_poll(unsigned long data)
4123 {
4124         struct net_device *dev = (struct net_device *) data;
4125         struct fe_priv *np = netdev_priv(dev);
4126
4127         nv_get_hw_stats(dev);
4128
4129         if (!np->in_shutdown)
4130                 mod_timer(&np->stats_poll,
4131                         round_jiffies(jiffies + STATS_INTERVAL));
4132 }
4133
4134 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4135 {
4136         struct fe_priv *np = netdev_priv(dev);
4137         strcpy(info->driver, DRV_NAME);
4138         strcpy(info->version, FORCEDETH_VERSION);
4139         strcpy(info->bus_info, pci_name(np->pci_dev));
4140 }
4141
4142 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4143 {
4144         struct fe_priv *np = netdev_priv(dev);
4145         wolinfo->supported = WAKE_MAGIC;
4146
4147         spin_lock_irq(&np->lock);
4148         if (np->wolenabled)
4149                 wolinfo->wolopts = WAKE_MAGIC;
4150         spin_unlock_irq(&np->lock);
4151 }
4152
4153 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4154 {
4155         struct fe_priv *np = netdev_priv(dev);
4156         u8 __iomem *base = get_hwbase(dev);
4157         u32 flags = 0;
4158
4159         if (wolinfo->wolopts == 0) {
4160                 np->wolenabled = 0;
4161         } else if (wolinfo->wolopts & WAKE_MAGIC) {
4162                 np->wolenabled = 1;
4163                 flags = NVREG_WAKEUPFLAGS_ENABLE;
4164         }
4165         if (netif_running(dev)) {
4166                 spin_lock_irq(&np->lock);
4167                 writel(flags, base + NvRegWakeUpFlags);
4168                 spin_unlock_irq(&np->lock);
4169         }
4170         return 0;
4171 }
4172
4173 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4174 {
4175         struct fe_priv *np = netdev_priv(dev);
4176         int adv;
4177
4178         spin_lock_irq(&np->lock);
4179         ecmd->port = PORT_MII;
4180         if (!netif_running(dev)) {
4181                 /* We do not track link speed / duplex setting if the
4182                  * interface is disabled. Force a link check */
4183                 if (nv_update_linkspeed(dev)) {
4184                         if (!netif_carrier_ok(dev))
4185                                 netif_carrier_on(dev);
4186                 } else {
4187                         if (netif_carrier_ok(dev))
4188                                 netif_carrier_off(dev);
4189                 }
4190         }
4191
4192         if (netif_carrier_ok(dev)) {
4193                 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
4194                 case NVREG_LINKSPEED_10:
4195                         ecmd->speed = SPEED_10;
4196                         break;
4197                 case NVREG_LINKSPEED_100:
4198                         ecmd->speed = SPEED_100;
4199                         break;
4200                 case NVREG_LINKSPEED_1000:
4201                         ecmd->speed = SPEED_1000;
4202                         break;
4203                 }
4204                 ecmd->duplex = DUPLEX_HALF;
4205                 if (np->duplex)
4206                         ecmd->duplex = DUPLEX_FULL;
4207         } else {
4208                 ecmd->speed = -1;
4209                 ecmd->duplex = -1;
4210         }
4211
4212         ecmd->autoneg = np->autoneg;
4213
4214         ecmd->advertising = ADVERTISED_MII;
4215         if (np->autoneg) {
4216                 ecmd->advertising |= ADVERTISED_Autoneg;
4217                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4218                 if (adv & ADVERTISE_10HALF)
4219                         ecmd->advertising |= ADVERTISED_10baseT_Half;
4220                 if (adv & ADVERTISE_10FULL)
4221                         ecmd->advertising |= ADVERTISED_10baseT_Full;
4222                 if (adv & ADVERTISE_100HALF)
4223                         ecmd->advertising |= ADVERTISED_100baseT_Half;
4224                 if (adv & ADVERTISE_100FULL)
4225                         ecmd->advertising |= ADVERTISED_100baseT_Full;
4226                 if (np->gigabit == PHY_GIGABIT) {
4227                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4228                         if (adv & ADVERTISE_1000FULL)
4229                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4230                 }
4231         }
4232         ecmd->supported = (SUPPORTED_Autoneg |
4233                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4234                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4235                 SUPPORTED_MII);
4236         if (np->gigabit == PHY_GIGABIT)
4237                 ecmd->supported |= SUPPORTED_1000baseT_Full;
4238
4239         ecmd->phy_address = np->phyaddr;
4240         ecmd->transceiver = XCVR_EXTERNAL;
4241
4242         /* ignore maxtxpkt, maxrxpkt for now */
4243         spin_unlock_irq(&np->lock);
4244         return 0;
4245 }
4246
4247 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4248 {
4249         struct fe_priv *np = netdev_priv(dev);
4250
4251         if (ecmd->port != PORT_MII)
4252                 return -EINVAL;
4253         if (ecmd->transceiver != XCVR_EXTERNAL)
4254                 return -EINVAL;
4255         if (ecmd->phy_address != np->phyaddr) {
4256                 /* TODO: support switching between multiple phys. Should be
4257                  * trivial, but not enabled due to lack of test hardware. */
4258                 return -EINVAL;
4259         }
4260         if (ecmd->autoneg == AUTONEG_ENABLE) {
4261                 u32 mask;
4262
4263                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4264                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4265                 if (np->gigabit == PHY_GIGABIT)
4266                         mask |= ADVERTISED_1000baseT_Full;
4267
4268                 if ((ecmd->advertising & mask) == 0)
4269                         return -EINVAL;
4270
4271         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4272                 /* Note: autonegotiation disable, speed 1000 intentionally
4273                  * forbidden - noone should need that. */
4274
4275                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
4276                         return -EINVAL;
4277                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4278                         return -EINVAL;
4279         } else {
4280                 return -EINVAL;
4281         }
4282
4283         netif_carrier_off(dev);
4284         if (netif_running(dev)) {
4285                 unsigned long flags;
4286
4287                 nv_disable_irq(dev);
4288                 netif_tx_lock_bh(dev);
4289                 netif_addr_lock(dev);
4290                 /* with plain spinlock lockdep complains */
4291                 spin_lock_irqsave(&np->lock, flags);
4292                 /* stop engines */
4293                 /* FIXME:
4294                  * this can take some time, and interrupts are disabled
4295                  * due to spin_lock_irqsave, but let's hope no daemon
4296                  * is going to change the settings very often...
4297                  * Worst case:
4298                  * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4299                  * + some minor delays, which is up to a second approximately
4300                  */
4301                 nv_stop_rxtx(dev);
4302                 spin_unlock_irqrestore(&np->lock, flags);
4303                 netif_addr_unlock(dev);
4304                 netif_tx_unlock_bh(dev);
4305         }
4306
4307         if (ecmd->autoneg == AUTONEG_ENABLE) {
4308                 int adv, bmcr;
4309
4310                 np->autoneg = 1;
4311
4312                 /* advertise only what has been requested */
4313                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4314                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4315                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4316                         adv |= ADVERTISE_10HALF;
4317                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4318                         adv |= ADVERTISE_10FULL;
4319                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4320                         adv |= ADVERTISE_100HALF;
4321                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4322                         adv |= ADVERTISE_100FULL;
4323                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
4324                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4325                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4326                         adv |=  ADVERTISE_PAUSE_ASYM;
4327                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4328
4329                 if (np->gigabit == PHY_GIGABIT) {
4330                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4331                         adv &= ~ADVERTISE_1000FULL;
4332                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4333                                 adv |= ADVERTISE_1000FULL;
4334                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4335                 }
4336
4337                 if (netif_running(dev))
4338                         printk(KERN_INFO "%s: link down.\n", dev->name);
4339                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4340                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4341                         bmcr |= BMCR_ANENABLE;
4342                         /* reset the phy in order for settings to stick,
4343                          * and cause autoneg to start */
4344                         if (phy_reset(dev, bmcr)) {
4345                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4346                                 return -EINVAL;
4347                         }
4348                 } else {
4349                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4350                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4351                 }
4352         } else {
4353                 int adv, bmcr;
4354
4355                 np->autoneg = 0;
4356
4357                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4358                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4359                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4360                         adv |= ADVERTISE_10HALF;
4361                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4362                         adv |= ADVERTISE_10FULL;
4363                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4364                         adv |= ADVERTISE_100HALF;
4365                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4366                         adv |= ADVERTISE_100FULL;
4367                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4368                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
4369                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4370                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4371                 }
4372                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4373                         adv |=  ADVERTISE_PAUSE_ASYM;
4374                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4375                 }
4376                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4377                 np->fixed_mode = adv;
4378
4379                 if (np->gigabit == PHY_GIGABIT) {
4380                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4381                         adv &= ~ADVERTISE_1000FULL;
4382                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4383                 }
4384
4385                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4386                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4387                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4388                         bmcr |= BMCR_FULLDPLX;
4389                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4390                         bmcr |= BMCR_SPEED100;
4391                 if (np->phy_oui == PHY_OUI_MARVELL) {
4392                         /* reset the phy in order for forced mode settings to stick */
4393                         if (phy_reset(dev, bmcr)) {
4394                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4395                                 return -EINVAL;
4396                         }
4397                 } else {
4398                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4399                         if (netif_running(dev)) {
4400                                 /* Wait a bit and then reconfigure the nic. */
4401                                 udelay(10);
4402                                 nv_linkchange(dev);
4403                         }
4404                 }
4405         }
4406
4407         if (netif_running(dev)) {
4408                 nv_start_rxtx(dev);
4409                 nv_enable_irq(dev);
4410         }
4411
4412         return 0;
4413 }
4414
4415 #define FORCEDETH_REGS_VER      1
4416
4417 static int nv_get_regs_len(struct net_device *dev)
4418 {
4419         struct fe_priv *np = netdev_priv(dev);
4420         return np->register_size;
4421 }
4422
4423 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4424 {
4425         struct fe_priv *np = netdev_priv(dev);
4426         u8 __iomem *base = get_hwbase(dev);
4427         u32 *rbuf = buf;
4428         int i;
4429
4430         regs->version = FORCEDETH_REGS_VER;
4431         spin_lock_irq(&np->lock);
4432         for (i = 0;i <= np->register_size/sizeof(u32); i++)
4433                 rbuf[i] = readl(base + i*sizeof(u32));
4434         spin_unlock_irq(&np->lock);
4435 }
4436
4437 static int nv_nway_reset(struct net_device *dev)
4438 {
4439         struct fe_priv *np = netdev_priv(dev);
4440         int ret;
4441
4442         if (np->autoneg) {
4443                 int bmcr;
4444
4445                 netif_carrier_off(dev);
4446                 if (netif_running(dev)) {
4447                         nv_disable_irq(dev);
4448                         netif_tx_lock_bh(dev);
4449                         netif_addr_lock(dev);
4450                         spin_lock(&np->lock);
4451                         /* stop engines */
4452                         nv_stop_rxtx(dev);
4453                         spin_unlock(&np->lock);
4454                         netif_addr_unlock(dev);
4455                         netif_tx_unlock_bh(dev);
4456                         printk(KERN_INFO "%s: link down.\n", dev->name);
4457                 }
4458
4459                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4460                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4461                         bmcr |= BMCR_ANENABLE;
4462                         /* reset the phy in order for settings to stick*/
4463                         if (phy_reset(dev, bmcr)) {
4464                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4465                                 return -EINVAL;
4466                         }
4467                 } else {
4468                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4469                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4470                 }
4471
4472                 if (netif_running(dev)) {
4473                         nv_start_rxtx(dev);
4474                         nv_enable_irq(dev);
4475                 }
4476                 ret = 0;
4477         } else {
4478                 ret = -EINVAL;
4479         }
4480
4481         return ret;
4482 }
4483
4484 static int nv_set_tso(struct net_device *dev, u32 value)
4485 {
4486         struct fe_priv *np = netdev_priv(dev);
4487
4488         if ((np->driver_data & DEV_HAS_CHECKSUM))
4489                 return ethtool_op_set_tso(dev, value);
4490         else
4491                 return -EOPNOTSUPP;
4492 }
4493
4494 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4495 {
4496         struct fe_priv *np = netdev_priv(dev);
4497
4498         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4499         ring->rx_mini_max_pending = 0;
4500         ring->rx_jumbo_max_pending = 0;
4501         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4502
4503         ring->rx_pending = np->rx_ring_size;
4504         ring->rx_mini_pending = 0;
4505         ring->rx_jumbo_pending = 0;
4506         ring->tx_pending = np->tx_ring_size;
4507 }
4508
4509 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4510 {
4511         struct fe_priv *np = netdev_priv(dev);
4512         u8 __iomem *base = get_hwbase(dev);
4513         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4514         dma_addr_t ring_addr;
4515
4516         if (ring->rx_pending < RX_RING_MIN ||
4517             ring->tx_pending < TX_RING_MIN ||
4518             ring->rx_mini_pending != 0 ||
4519             ring->rx_jumbo_pending != 0 ||
4520             (np->desc_ver == DESC_VER_1 &&
4521              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4522               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4523             (np->desc_ver != DESC_VER_1 &&
4524              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4525               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4526                 return -EINVAL;
4527         }
4528
4529         /* allocate new rings */
4530         if (!nv_optimized(np)) {
4531                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4532                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4533                                             &ring_addr);
4534         } else {
4535                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4536                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4537                                             &ring_addr);
4538         }
4539         rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4540         tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4541         if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4542                 /* fall back to old rings */
4543                 if (!nv_optimized(np)) {
4544                         if (rxtx_ring)
4545                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4546                                                     rxtx_ring, ring_addr);
4547                 } else {
4548                         if (rxtx_ring)
4549                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4550                                                     rxtx_ring, ring_addr);
4551                 }
4552                 if (rx_skbuff)
4553                         kfree(rx_skbuff);
4554                 if (tx_skbuff)
4555                         kfree(tx_skbuff);
4556                 goto exit;
4557         }
4558
4559         if (netif_running(dev)) {
4560                 nv_disable_irq(dev);
4561                 netif_tx_lock_bh(dev);
4562                 netif_addr_lock(dev);
4563                 spin_lock(&np->lock);
4564                 /* stop engines */
4565                 nv_stop_rxtx(dev);
4566                 nv_txrx_reset(dev);
4567                 /* drain queues */
4568                 nv_drain_rxtx(dev);
4569                 /* delete queues */
4570                 free_rings(dev);
4571         }
4572
4573         /* set new values */
4574         np->rx_ring_size = ring->rx_pending;
4575         np->tx_ring_size = ring->tx_pending;
4576
4577         if (!nv_optimized(np)) {
4578                 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
4579                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4580         } else {
4581                 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
4582                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4583         }
4584         np->rx_skb = (struct nv_skb_map*)rx_skbuff;
4585         np->tx_skb = (struct nv_skb_map*)tx_skbuff;
4586         np->ring_addr = ring_addr;
4587
4588         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4589         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4590
4591         if (netif_running(dev)) {
4592                 /* reinit driver view of the queues */
4593                 set_bufsize(dev);
4594                 if (nv_init_ring(dev)) {
4595                         if (!np->in_shutdown)
4596                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4597                 }
4598
4599                 /* reinit nic view of the queues */
4600                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4601                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4602                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4603                         base + NvRegRingSizes);
4604                 pci_push(base);
4605                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4606                 pci_push(base);
4607
4608                 /* restart engines */
4609                 nv_start_rxtx(dev);
4610                 spin_unlock(&np->lock);
4611                 netif_addr_unlock(dev);
4612                 netif_tx_unlock_bh(dev);
4613                 nv_enable_irq(dev);
4614         }
4615         return 0;
4616 exit:
4617         return -ENOMEM;
4618 }
4619
4620 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4621 {
4622         struct fe_priv *np = netdev_priv(dev);
4623
4624         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4625         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4626         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4627 }
4628
4629 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4630 {
4631         struct fe_priv *np = netdev_priv(dev);
4632         int adv, bmcr;
4633
4634         if ((!np->autoneg && np->duplex == 0) ||
4635             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4636                 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4637                        dev->name);
4638                 return -EINVAL;
4639         }
4640         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4641                 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4642                 return -EINVAL;
4643         }
4644
4645         netif_carrier_off(dev);
4646         if (netif_running(dev)) {
4647                 nv_disable_irq(dev);
4648                 netif_tx_lock_bh(dev);
4649                 netif_addr_lock(dev);
4650                 spin_lock(&np->lock);
4651                 /* stop engines */
4652                 nv_stop_rxtx(dev);
4653                 spin_unlock(&np->lock);
4654                 netif_addr_unlock(dev);
4655                 netif_tx_unlock_bh(dev);
4656         }
4657
4658         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4659         if (pause->rx_pause)
4660                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4661         if (pause->tx_pause)
4662                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4663
4664         if (np->autoneg && pause->autoneg) {
4665                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4666
4667                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4668                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4669                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4670                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4671                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4672                         adv |=  ADVERTISE_PAUSE_ASYM;
4673                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4674
4675                 if (netif_running(dev))
4676                         printk(KERN_INFO "%s: link down.\n", dev->name);
4677                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4678                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4679                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4680         } else {
4681                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4682                 if (pause->rx_pause)
4683                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4684                 if (pause->tx_pause)
4685                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4686
4687                 if (!netif_running(dev))
4688                         nv_update_linkspeed(dev);
4689                 else
4690                         nv_update_pause(dev, np->pause_flags);
4691         }
4692
4693         if (netif_running(dev)) {
4694                 nv_start_rxtx(dev);
4695                 nv_enable_irq(dev);
4696         }
4697         return 0;
4698 }
4699
4700 static u32 nv_get_rx_csum(struct net_device *dev)
4701 {
4702         struct fe_priv *np = netdev_priv(dev);
4703         return (np->rx_csum) != 0;
4704 }
4705
4706 static int nv_set_rx_csum(struct net_device *dev, u32 data)
4707 {
4708         struct fe_priv *np = netdev_priv(dev);
4709         u8 __iomem *base = get_hwbase(dev);
4710         int retcode = 0;
4711
4712         if (np->driver_data & DEV_HAS_CHECKSUM) {
4713                 if (data) {
4714                         np->rx_csum = 1;
4715                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4716                 } else {
4717                         np->rx_csum = 0;
4718                         /* vlan is dependent on rx checksum offload */
4719                         if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4720                                 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4721                 }
4722                 if (netif_running(dev)) {
4723                         spin_lock_irq(&np->lock);
4724                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4725                         spin_unlock_irq(&np->lock);
4726                 }
4727         } else {
4728                 return -EINVAL;
4729         }
4730
4731         return retcode;
4732 }
4733
4734 static int nv_set_tx_csum(struct net_device *dev, u32 data)
4735 {
4736         struct fe_priv *np = netdev_priv(dev);
4737
4738         if (np->driver_data & DEV_HAS_CHECKSUM)
4739                 return ethtool_op_set_tx_hw_csum(dev, data);
4740         else
4741                 return -EOPNOTSUPP;
4742 }
4743
4744 static int nv_set_sg(struct net_device *dev, u32 data)
4745 {
4746         struct fe_priv *np = netdev_priv(dev);
4747
4748         if (np->driver_data & DEV_HAS_CHECKSUM)
4749                 return ethtool_op_set_sg(dev, data);
4750         else
4751                 return -EOPNOTSUPP;
4752 }
4753
4754 static int nv_get_sset_count(struct net_device *dev, int sset)
4755 {
4756         struct fe_priv *np = netdev_priv(dev);
4757
4758         switch (sset) {
4759         case ETH_SS_TEST:
4760                 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4761                         return NV_TEST_COUNT_EXTENDED;
4762                 else
4763                         return NV_TEST_COUNT_BASE;
4764         case ETH_SS_STATS:
4765                 if (np->driver_data & DEV_HAS_STATISTICS_V1)
4766                         return NV_DEV_STATISTICS_V1_COUNT;
4767                 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4768                         return NV_DEV_STATISTICS_V2_COUNT;
4769                 else if (np->driver_data & DEV_HAS_STATISTICS_V3)
4770                         return NV_DEV_STATISTICS_V3_COUNT;
4771                 else
4772                         return 0;
4773         default:
4774                 return -EOPNOTSUPP;
4775         }
4776 }
4777
4778 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4779 {
4780         struct fe_priv *np = netdev_priv(dev);
4781
4782         /* update stats */
4783         nv_do_stats_poll((unsigned long)dev);
4784
4785         memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4786 }
4787
4788 static int nv_link_test(struct net_device *dev)
4789 {
4790         struct fe_priv *np = netdev_priv(dev);
4791         int mii_status;
4792
4793         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4794         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4795
4796         /* check phy link status */
4797         if (!(mii_status & BMSR_LSTATUS))
4798                 return 0;
4799         else
4800                 return 1;
4801 }
4802
4803 static int nv_register_test(struct net_device *dev)
4804 {
4805         u8 __iomem *base = get_hwbase(dev);
4806         int i = 0;
4807         u32 orig_read, new_read;
4808
4809         do {
4810                 orig_read = readl(base + nv_registers_test[i].reg);
4811
4812                 /* xor with mask to toggle bits */
4813                 orig_read ^= nv_registers_test[i].mask;
4814
4815                 writel(orig_read, base + nv_registers_test[i].reg);
4816
4817                 new_read = readl(base + nv_registers_test[i].reg);
4818
4819                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4820                         return 0;
4821
4822                 /* restore original value */
4823                 orig_read ^= nv_registers_test[i].mask;
4824                 writel(orig_read, base + nv_registers_test[i].reg);
4825
4826         } while (nv_registers_test[++i].reg != 0);
4827
4828         return 1;
4829 }
4830
4831 static int nv_interrupt_test(struct net_device *dev)
4832 {
4833         struct fe_priv *np = netdev_priv(dev);
4834         u8 __iomem *base = get_hwbase(dev);
4835         int ret = 1;
4836         int testcnt;
4837         u32 save_msi_flags, save_poll_interval = 0;
4838
4839         if (netif_running(dev)) {
4840                 /* free current irq */
4841                 nv_free_irq(dev);
4842                 save_poll_interval = readl(base+NvRegPollingInterval);
4843         }
4844
4845         /* flag to test interrupt handler */
4846         np->intr_test = 0;
4847
4848         /* setup test irq */
4849         save_msi_flags = np->msi_flags;
4850         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4851         np->msi_flags |= 0x001; /* setup 1 vector */
4852         if (nv_request_irq(dev, 1))
4853                 return 0;
4854
4855         /* setup timer interrupt */
4856         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4857         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4858
4859         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4860
4861         /* wait for at least one interrupt */
4862         msleep(100);
4863
4864         spin_lock_irq(&np->lock);
4865
4866         /* flag should be set within ISR */
4867         testcnt = np->intr_test;
4868         if (!testcnt)
4869                 ret = 2;
4870
4871         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4872         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4873                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4874         else
4875                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4876
4877         spin_unlock_irq(&np->lock);
4878
4879         nv_free_irq(dev);
4880
4881         np->msi_flags = save_msi_flags;
4882
4883         if (netif_running(dev)) {
4884                 writel(save_poll_interval, base + NvRegPollingInterval);
4885                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4886                 /* restore original irq */
4887                 if (nv_request_irq(dev, 0))
4888                         return 0;
4889         }
4890
4891         return ret;
4892 }
4893
4894 static int nv_loopback_test(struct net_device *dev)
4895 {
4896         struct fe_priv *np = netdev_priv(dev);
4897         u8 __iomem *base = get_hwbase(dev);
4898         struct sk_buff *tx_skb, *rx_skb;
4899         dma_addr_t test_dma_addr;
4900         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4901         u32 flags;
4902         int len, i, pkt_len;
4903         u8 *pkt_data;
4904         u32 filter_flags = 0;
4905         u32 misc1_flags = 0;
4906         int ret = 1;
4907
4908         if (netif_running(dev)) {
4909                 nv_disable_irq(dev);
4910                 filter_flags = readl(base + NvRegPacketFilterFlags);
4911                 misc1_flags = readl(base + NvRegMisc1);
4912         } else {
4913                 nv_txrx_reset(dev);
4914         }
4915
4916         /* reinit driver view of the rx queue */
4917         set_bufsize(dev);
4918         nv_init_ring(dev);
4919
4920         /* setup hardware for loopback */
4921         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4922         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4923
4924         /* reinit nic view of the rx queue */
4925         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4926         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4927         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4928                 base + NvRegRingSizes);
4929         pci_push(base);
4930
4931         /* restart rx engine */
4932         nv_start_rxtx(dev);
4933
4934         /* setup packet for tx */
4935         pkt_len = ETH_DATA_LEN;
4936         tx_skb = dev_alloc_skb(pkt_len);
4937         if (!tx_skb) {
4938                 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
4939                          " of %s\n", dev->name);
4940                 ret = 0;
4941                 goto out;
4942         }
4943         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4944                                        skb_tailroom(tx_skb),
4945                                        PCI_DMA_FROMDEVICE);
4946         pkt_data = skb_put(tx_skb, pkt_len);
4947         for (i = 0; i < pkt_len; i++)
4948                 pkt_data[i] = (u8)(i & 0xff);
4949
4950         if (!nv_optimized(np)) {
4951                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4952                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4953         } else {
4954                 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
4955                 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
4956                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4957         }
4958         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4959         pci_push(get_hwbase(dev));
4960
4961         msleep(500);
4962
4963         /* check for rx of the packet */
4964         if (!nv_optimized(np)) {
4965                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4966                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4967
4968         } else {
4969                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4970                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4971         }
4972
4973         if (flags & NV_RX_AVAIL) {
4974                 ret = 0;
4975         } else if (np->desc_ver == DESC_VER_1) {
4976                 if (flags & NV_RX_ERROR)
4977                         ret = 0;
4978         } else {
4979                 if (flags & NV_RX2_ERROR) {
4980                         ret = 0;
4981                 }
4982         }
4983
4984         if (ret) {
4985                 if (len != pkt_len) {
4986                         ret = 0;
4987                         dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
4988                                 dev->name, len, pkt_len);
4989                 } else {
4990                         rx_skb = np->rx_skb[0].skb;
4991                         for (i = 0; i < pkt_len; i++) {
4992                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4993                                         ret = 0;
4994                                         dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
4995                                                 dev->name, i);
4996                                         break;
4997                                 }
4998                         }
4999                 }
5000         } else {
5001                 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
5002         }
5003
5004         pci_unmap_page(np->pci_dev, test_dma_addr,
5005                        (skb_end_pointer(tx_skb) - tx_skb->data),
5006                        PCI_DMA_TODEVICE);
5007         dev_kfree_skb_any(tx_skb);
5008  out:
5009         /* stop engines */
5010         nv_stop_rxtx(dev);
5011         nv_txrx_reset(dev);
5012         /* drain rx queue */
5013         nv_drain_rxtx(dev);
5014
5015         if (netif_running(dev)) {
5016                 writel(misc1_flags, base + NvRegMisc1);
5017                 writel(filter_flags, base + NvRegPacketFilterFlags);
5018                 nv_enable_irq(dev);
5019         }
5020
5021         return ret;
5022 }
5023
5024 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
5025 {
5026         struct fe_priv *np = netdev_priv(dev);
5027         u8 __iomem *base = get_hwbase(dev);
5028         int result;
5029         memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
5030
5031         if (!nv_link_test(dev)) {
5032                 test->flags |= ETH_TEST_FL_FAILED;
5033                 buffer[0] = 1;
5034         }
5035
5036         if (test->flags & ETH_TEST_FL_OFFLINE) {
5037                 if (netif_running(dev)) {
5038                         netif_stop_queue(dev);
5039 #ifdef CONFIG_FORCEDETH_NAPI
5040                         napi_disable(&np->napi);
5041 #endif
5042                         netif_tx_lock_bh(dev);
5043                         netif_addr_lock(dev);
5044                         spin_lock_irq(&np->lock);
5045                         nv_disable_hw_interrupts(dev, np->irqmask);
5046                         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
5047                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5048                         } else {
5049                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5050                         }
5051                         /* stop engines */
5052                         nv_stop_rxtx(dev);
5053                         nv_txrx_reset(dev);
5054                         /* drain rx queue */
5055                         nv_drain_rxtx(dev);
5056                         spin_unlock_irq(&np->lock);
5057                         netif_addr_unlock(dev);
5058                         netif_tx_unlock_bh(dev);
5059                 }
5060
5061                 if (!nv_register_test(dev)) {
5062                         test->flags |= ETH_TEST_FL_FAILED;
5063                         buffer[1] = 1;
5064                 }
5065
5066                 result = nv_interrupt_test(dev);
5067                 if (result != 1) {
5068                         test->flags |= ETH_TEST_FL_FAILED;
5069                         buffer[2] = 1;
5070                 }
5071                 if (result == 0) {
5072                         /* bail out */
5073                         return;
5074                 }
5075
5076                 if (!nv_loopback_test(dev)) {
5077                         test->flags |= ETH_TEST_FL_FAILED;
5078                         buffer[3] = 1;
5079                 }
5080
5081                 if (netif_running(dev)) {
5082                         /* reinit driver view of the rx queue */
5083                         set_bufsize(dev);
5084                         if (nv_init_ring(dev)) {
5085                                 if (!np->in_shutdown)
5086                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5087                         }
5088                         /* reinit nic view of the rx queue */
5089                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5090                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5091                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5092                                 base + NvRegRingSizes);
5093                         pci_push(base);
5094                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5095                         pci_push(base);
5096                         /* restart rx engine */
5097                         nv_start_rxtx(dev);
5098                         netif_start_queue(dev);
5099 #ifdef CONFIG_FORCEDETH_NAPI
5100                         napi_enable(&np->napi);
5101 #endif
5102                         nv_enable_hw_interrupts(dev, np->irqmask);
5103                 }
5104         }
5105 }
5106
5107 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
5108 {
5109         switch (stringset) {
5110         case ETH_SS_STATS:
5111                 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
5112                 break;
5113         case ETH_SS_TEST:
5114                 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
5115                 break;
5116         }
5117 }
5118
5119 static const struct ethtool_ops ops = {
5120         .get_drvinfo = nv_get_drvinfo,
5121         .get_link = ethtool_op_get_link,
5122         .get_wol = nv_get_wol,
5123         .set_wol = nv_set_wol,
5124         .get_settings = nv_get_settings,
5125         .set_settings = nv_set_settings,
5126         .get_regs_len = nv_get_regs_len,
5127         .get_regs = nv_get_regs,
5128         .nway_reset = nv_nway_reset,
5129         .set_tso = nv_set_tso,
5130         .get_ringparam = nv_get_ringparam,
5131         .set_ringparam = nv_set_ringparam,
5132         .get_pauseparam = nv_get_pauseparam,
5133         .set_pauseparam = nv_set_pauseparam,
5134         .get_rx_csum = nv_get_rx_csum,
5135         .set_rx_csum = nv_set_rx_csum,
5136         .set_tx_csum = nv_set_tx_csum,
5137         .set_sg = nv_set_sg,
5138         .get_strings = nv_get_strings,
5139         .get_ethtool_stats = nv_get_ethtool_stats,
5140         .get_sset_count = nv_get_sset_count,
5141         .self_test = nv_self_test,
5142 };
5143
5144 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
5145 {
5146         struct fe_priv *np = get_nvpriv(dev);
5147
5148         spin_lock_irq(&np->lock);
5149
5150         /* save vlan group */
5151         np->vlangrp = grp;
5152
5153         if (grp) {
5154                 /* enable vlan on MAC */
5155                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
5156         } else {
5157                 /* disable vlan on MAC */
5158                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
5159                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
5160         }
5161
5162         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5163
5164         spin_unlock_irq(&np->lock);
5165 }
5166
5167 /* The mgmt unit and driver use a semaphore to access the phy during init */
5168 static int nv_mgmt_acquire_sema(struct net_device *dev)
5169 {
5170         u8 __iomem *base = get_hwbase(dev);
5171         int i;
5172         u32 tx_ctrl, mgmt_sema;
5173
5174         for (i = 0; i < 10; i++) {
5175                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5176                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5177                         break;
5178                 msleep(500);
5179         }
5180
5181         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5182                 return 0;
5183
5184         for (i = 0; i < 2; i++) {
5185                 tx_ctrl = readl(base + NvRegTransmitterControl);
5186                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5187                 writel(tx_ctrl, base + NvRegTransmitterControl);
5188
5189                 /* verify that semaphore was acquired */
5190                 tx_ctrl = readl(base + NvRegTransmitterControl);
5191                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
5192                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE))
5193                         return 1;
5194                 else
5195                         udelay(50);
5196         }
5197
5198         return 0;
5199 }
5200
5201 static int nv_open(struct net_device *dev)
5202 {
5203         struct fe_priv *np = netdev_priv(dev);
5204         u8 __iomem *base = get_hwbase(dev);
5205         int ret = 1;
5206         int oom, i;
5207         u32 low;
5208
5209         dprintk(KERN_DEBUG "nv_open: begin\n");
5210
5211         /* power up phy */
5212         mii_rw(dev, np->phyaddr, MII_BMCR,
5213                mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5214
5215         /* erase previous misconfiguration */
5216         if (np->driver_data & DEV_HAS_POWER_CNTRL)
5217                 nv_mac_reset(dev);
5218         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5219         writel(0, base + NvRegMulticastAddrB);
5220         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5221         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5222         writel(0, base + NvRegPacketFilterFlags);
5223
5224         writel(0, base + NvRegTransmitterControl);
5225         writel(0, base + NvRegReceiverControl);
5226
5227         writel(0, base + NvRegAdapterControl);
5228
5229         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5230                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
5231
5232         /* initialize descriptor rings */
5233         set_bufsize(dev);
5234         oom = nv_init_ring(dev);
5235
5236         writel(0, base + NvRegLinkSpeed);
5237         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5238         nv_txrx_reset(dev);
5239         writel(0, base + NvRegUnknownSetupReg6);
5240
5241         np->in_shutdown = 0;
5242
5243         /* give hw rings */
5244         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5245         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5246                 base + NvRegRingSizes);
5247
5248         writel(np->linkspeed, base + NvRegLinkSpeed);
5249         if (np->desc_ver == DESC_VER_1)
5250                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5251         else
5252                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5253         writel(np->txrxctl_bits, base + NvRegTxRxControl);
5254         writel(np->vlanctl_bits, base + NvRegVlanControl);
5255         pci_push(base);
5256         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5257         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5258                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
5259                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
5260
5261         writel(0, base + NvRegMIIMask);
5262         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5263         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5264
5265         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5266         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5267         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5268         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5269
5270         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5271
5272         get_random_bytes(&low, sizeof(low));
5273         low &= NVREG_SLOTTIME_MASK;
5274         if (np->desc_ver == DESC_VER_1) {
5275                 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5276         } else {
5277                 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5278                         /* setup legacy backoff */
5279                         writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5280                 } else {
5281                         writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5282                         nv_gear_backoff_reseed(dev);
5283                 }
5284         }
5285         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5286         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5287         if (poll_interval == -1) {
5288                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5289                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5290                 else
5291                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5292         }
5293         else
5294                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5295         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5296         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5297                         base + NvRegAdapterControl);
5298         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5299         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5300         if (np->wolenabled)
5301                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5302
5303         i = readl(base + NvRegPowerState);
5304         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
5305                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5306
5307         pci_push(base);
5308         udelay(10);
5309         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5310
5311         nv_disable_hw_interrupts(dev, np->irqmask);
5312         pci_push(base);
5313         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5314         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5315         pci_push(base);
5316
5317         if (nv_request_irq(dev, 0)) {
5318                 goto out_drain;
5319         }
5320
5321         /* ask for interrupts */
5322         nv_enable_hw_interrupts(dev, np->irqmask);
5323
5324         spin_lock_irq(&np->lock);
5325         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5326         writel(0, base + NvRegMulticastAddrB);
5327         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5328         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5329         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5330         /* One manual link speed update: Interrupts are enabled, future link
5331          * speed changes cause interrupts and are handled by nv_link_irq().
5332          */
5333         {
5334                 u32 miistat;
5335                 miistat = readl(base + NvRegMIIStatus);
5336                 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5337                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
5338         }
5339         /* set linkspeed to invalid value, thus force nv_update_linkspeed
5340          * to init hw */
5341         np->linkspeed = 0;
5342         ret = nv_update_linkspeed(dev);
5343         nv_start_rxtx(dev);
5344         netif_start_queue(dev);
5345 #ifdef CONFIG_FORCEDETH_NAPI
5346         napi_enable(&np->napi);
5347 #endif
5348
5349         if (ret) {
5350                 netif_carrier_on(dev);
5351         } else {
5352                 printk(KERN_INFO "%s: no link during initialization.\n", dev->name);
5353                 netif_carrier_off(dev);
5354         }
5355         if (oom)
5356                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5357
5358         /* start statistics timer */
5359         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5360                 mod_timer(&np->stats_poll,
5361                         round_jiffies(jiffies + STATS_INTERVAL));
5362
5363         spin_unlock_irq(&np->lock);
5364
5365         return 0;
5366 out_drain:
5367         nv_drain_rxtx(dev);
5368         return ret;
5369 }
5370
5371 static int nv_close(struct net_device *dev)
5372 {
5373         struct fe_priv *np = netdev_priv(dev);
5374         u8 __iomem *base;
5375
5376         spin_lock_irq(&np->lock);
5377         np->in_shutdown = 1;
5378         spin_unlock_irq(&np->lock);
5379 #ifdef CONFIG_FORCEDETH_NAPI
5380         napi_disable(&np->napi);
5381 #endif
5382         synchronize_irq(np->pci_dev->irq);
5383
5384         del_timer_sync(&np->oom_kick);
5385         del_timer_sync(&np->nic_poll);
5386         del_timer_sync(&np->stats_poll);
5387
5388         netif_stop_queue(dev);
5389         spin_lock_irq(&np->lock);
5390         nv_stop_rxtx(dev);
5391         nv_txrx_reset(dev);
5392
5393         /* disable interrupts on the nic or we will lock up */
5394         base = get_hwbase(dev);
5395         nv_disable_hw_interrupts(dev, np->irqmask);
5396         pci_push(base);
5397         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
5398
5399         spin_unlock_irq(&np->lock);
5400
5401         nv_free_irq(dev);
5402
5403         nv_drain_rxtx(dev);
5404
5405         if (np->wolenabled) {
5406                 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5407                 nv_start_rx(dev);
5408         } else {
5409                 /* power down phy */
5410                 mii_rw(dev, np->phyaddr, MII_BMCR,
5411                        mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5412         }
5413
5414         /* FIXME: power down nic */
5415
5416         return 0;
5417 }
5418
5419 static const struct net_device_ops nv_netdev_ops = {
5420         .ndo_open               = nv_open,
5421         .ndo_stop               = nv_close,
5422         .ndo_get_stats          = nv_get_stats,
5423         .ndo_start_xmit         = nv_start_xmit,
5424         .ndo_tx_timeout         = nv_tx_timeout,
5425         .ndo_change_mtu         = nv_change_mtu,
5426         .ndo_validate_addr      = eth_validate_addr,
5427         .ndo_set_mac_address    = nv_set_mac_address,
5428         .ndo_set_multicast_list = nv_set_multicast,
5429         .ndo_vlan_rx_register   = nv_vlan_rx_register,
5430 #ifdef CONFIG_NET_POLL_CONTROLLER
5431         .ndo_poll_controller    = nv_poll_controller,
5432 #endif
5433 };
5434
5435 static const struct net_device_ops nv_netdev_ops_optimized = {
5436         .ndo_open               = nv_open,
5437         .ndo_stop               = nv_close,
5438         .ndo_get_stats          = nv_get_stats,
5439         .ndo_start_xmit         = nv_start_xmit_optimized,
5440         .ndo_tx_timeout         = nv_tx_timeout,
5441         .ndo_change_mtu         = nv_change_mtu,
5442         .ndo_validate_addr      = eth_validate_addr,
5443         .ndo_set_mac_address    = nv_set_mac_address,
5444         .ndo_set_multicast_list = nv_set_multicast,
5445         .ndo_vlan_rx_register   = nv_vlan_rx_register,
5446 #ifdef CONFIG_NET_POLL_CONTROLLER
5447         .ndo_poll_controller    = nv_poll_controller,
5448 #endif
5449 };
5450
5451 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5452 {
5453         struct net_device *dev;
5454         struct fe_priv *np;
5455         unsigned long addr;
5456         u8 __iomem *base;
5457         int err, i;
5458         u32 powerstate, txreg;
5459         u32 phystate_orig = 0, phystate;
5460         int phyinitialized = 0;
5461         static int printed_version;
5462
5463         if (!printed_version++)
5464                 printk(KERN_INFO "%s: Reverse Engineered nForce ethernet"
5465                        " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION);
5466
5467         dev = alloc_etherdev(sizeof(struct fe_priv));
5468         err = -ENOMEM;
5469         if (!dev)
5470                 goto out;
5471
5472         np = netdev_priv(dev);
5473         np->dev = dev;
5474         np->pci_dev = pci_dev;
5475         spin_lock_init(&np->lock);
5476         SET_NETDEV_DEV(dev, &pci_dev->dev);
5477
5478         init_timer(&np->oom_kick);
5479         np->oom_kick.data = (unsigned long) dev;
5480         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
5481         init_timer(&np->nic_poll);
5482         np->nic_poll.data = (unsigned long) dev;
5483         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
5484         init_timer(&np->stats_poll);
5485         np->stats_poll.data = (unsigned long) dev;
5486         np->stats_poll.function = &nv_do_stats_poll;    /* timer handler */
5487
5488         err = pci_enable_device(pci_dev);
5489         if (err)
5490                 goto out_free;
5491
5492         pci_set_master(pci_dev);
5493
5494         err = pci_request_regions(pci_dev, DRV_NAME);
5495         if (err < 0)
5496                 goto out_disable;
5497
5498         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5499                 np->register_size = NV_PCI_REGSZ_VER3;
5500         else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5501                 np->register_size = NV_PCI_REGSZ_VER2;
5502         else
5503                 np->register_size = NV_PCI_REGSZ_VER1;
5504
5505         err = -EINVAL;
5506         addr = 0;
5507         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5508                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
5509                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
5510                                 pci_resource_len(pci_dev, i),
5511                                 pci_resource_flags(pci_dev, i));
5512                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5513                                 pci_resource_len(pci_dev, i) >= np->register_size) {
5514                         addr = pci_resource_start(pci_dev, i);
5515                         break;
5516                 }
5517         }
5518         if (i == DEVICE_COUNT_RESOURCE) {
5519                 dev_printk(KERN_INFO, &pci_dev->dev,
5520                            "Couldn't find register window\n");
5521                 goto out_relreg;
5522         }
5523
5524         /* copy of driver data */
5525         np->driver_data = id->driver_data;
5526         /* copy of device id */
5527         np->device_id = id->device;
5528
5529         /* handle different descriptor versions */
5530         if (id->driver_data & DEV_HAS_HIGH_DMA) {
5531                 /* packet format 3: supports 40-bit addressing */
5532                 np->desc_ver = DESC_VER_3;
5533                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5534                 if (dma_64bit) {
5535                         if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK))
5536                                 dev_printk(KERN_INFO, &pci_dev->dev,
5537                                         "64-bit DMA failed, using 32-bit addressing\n");
5538                         else
5539                                 dev->features |= NETIF_F_HIGHDMA;
5540                         if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
5541                                 dev_printk(KERN_INFO, &pci_dev->dev,
5542                                         "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5543                         }
5544                 }
5545         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5546                 /* packet format 2: supports jumbo frames */
5547                 np->desc_ver = DESC_VER_2;
5548                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5549         } else {
5550                 /* original packet format */
5551                 np->desc_ver = DESC_VER_1;
5552                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5553         }
5554
5555         np->pkt_limit = NV_PKTLIMIT_1;
5556         if (id->driver_data & DEV_HAS_LARGEDESC)
5557                 np->pkt_limit = NV_PKTLIMIT_2;
5558
5559         if (id->driver_data & DEV_HAS_CHECKSUM) {
5560                 np->rx_csum = 1;
5561                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5562                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
5563                 dev->features |= NETIF_F_TSO;
5564         }
5565
5566         np->vlanctl_bits = 0;
5567         if (id->driver_data & DEV_HAS_VLAN) {
5568                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5569                 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5570         }
5571
5572         np->msi_flags = 0;
5573         if ((id->driver_data & DEV_HAS_MSI) && msi) {
5574                 np->msi_flags |= NV_MSI_CAPABLE;
5575         }
5576         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5577                 np->msi_flags |= NV_MSI_X_CAPABLE;
5578         }
5579
5580         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5581         if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5582             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5583             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5584                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5585         }
5586
5587
5588         err = -ENOMEM;
5589         np->base = ioremap(addr, np->register_size);
5590         if (!np->base)
5591                 goto out_relreg;
5592         dev->base_addr = (unsigned long)np->base;
5593
5594         dev->irq = pci_dev->irq;
5595
5596         np->rx_ring_size = RX_RING_DEFAULT;
5597         np->tx_ring_size = TX_RING_DEFAULT;
5598
5599         if (!nv_optimized(np)) {
5600                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5601                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5602                                         &np->ring_addr);
5603                 if (!np->rx_ring.orig)
5604                         goto out_unmap;
5605                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5606         } else {
5607                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5608                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5609                                         &np->ring_addr);
5610                 if (!np->rx_ring.ex)
5611                         goto out_unmap;
5612                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5613         }
5614         np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5615         np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5616         if (!np->rx_skb || !np->tx_skb)
5617                 goto out_freering;
5618
5619         if (!nv_optimized(np))
5620                 dev->netdev_ops = &nv_netdev_ops;
5621         else
5622                 dev->netdev_ops = &nv_netdev_ops_optimized;
5623
5624 #ifdef CONFIG_FORCEDETH_NAPI
5625         netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5626 #endif
5627         SET_ETHTOOL_OPS(dev, &ops);
5628         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5629
5630         pci_set_drvdata(pci_dev, dev);
5631
5632         /* read the mac address */
5633         base = get_hwbase(dev);
5634         np->orig_mac[0] = readl(base + NvRegMacAddrA);
5635         np->orig_mac[1] = readl(base + NvRegMacAddrB);
5636
5637         /* check the workaround bit for correct mac address order */
5638         txreg = readl(base + NvRegTransmitPoll);
5639         if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5640                 /* mac address is already in correct order */
5641                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5642                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5643                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5644                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5645                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5646                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5647         } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5648                 /* mac address is already in correct order */
5649                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5650                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5651                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5652                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5653                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5654                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5655                 /*
5656                  * Set orig mac address back to the reversed version.
5657                  * This flag will be cleared during low power transition.
5658                  * Therefore, we should always put back the reversed address.
5659                  */
5660                 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5661                         (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5662                 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
5663         } else {
5664                 /* need to reverse mac address to correct order */
5665                 dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
5666                 dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
5667                 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5668                 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5669                 dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
5670                 dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
5671                 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5672                 printk(KERN_DEBUG "nv_probe: set workaround bit for reversed mac addr\n");
5673         }
5674         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5675
5676         if (!is_valid_ether_addr(dev->perm_addr)) {
5677                 /*
5678                  * Bad mac address. At least one bios sets the mac address
5679                  * to 01:23:45:67:89:ab
5680                  */
5681                 dev_printk(KERN_ERR, &pci_dev->dev,
5682                         "Invalid Mac address detected: %pM\n",
5683                         dev->dev_addr);
5684                 dev_printk(KERN_ERR, &pci_dev->dev,
5685                         "Please complain to your hardware vendor. Switching to a random MAC.\n");
5686                 dev->dev_addr[0] = 0x00;
5687                 dev->dev_addr[1] = 0x00;
5688                 dev->dev_addr[2] = 0x6c;
5689                 get_random_bytes(&dev->dev_addr[3], 3);
5690         }
5691
5692         dprintk(KERN_DEBUG "%s: MAC Address %pM\n",
5693                 pci_name(pci_dev), dev->dev_addr);
5694
5695         /* set mac address */
5696         nv_copy_mac_to_hw(dev);
5697
5698         /* Workaround current PCI init glitch:  wakeup bits aren't
5699          * being set from PCI PM capability.
5700          */
5701         device_init_wakeup(&pci_dev->dev, 1);
5702
5703         /* disable WOL */
5704         writel(0, base + NvRegWakeUpFlags);
5705         np->wolenabled = 0;
5706
5707         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5708
5709                 /* take phy and nic out of low power mode */
5710                 powerstate = readl(base + NvRegPowerState2);
5711                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5712                 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
5713                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
5714                     pci_dev->revision >= 0xA3)
5715                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5716                 writel(powerstate, base + NvRegPowerState2);
5717         }
5718
5719         if (np->desc_ver == DESC_VER_1) {
5720                 np->tx_flags = NV_TX_VALID;
5721         } else {
5722                 np->tx_flags = NV_TX2_VALID;
5723         }
5724         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
5725                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5726                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5727                         np->msi_flags |= 0x0003;
5728         } else {
5729                 np->irqmask = NVREG_IRQMASK_CPU;
5730                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5731                         np->msi_flags |= 0x0001;
5732         }
5733
5734         if (id->driver_data & DEV_NEED_TIMERIRQ)
5735                 np->irqmask |= NVREG_IRQ_TIMER;
5736         if (id->driver_data & DEV_NEED_LINKTIMER) {
5737                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
5738                 np->need_linktimer = 1;
5739                 np->link_timeout = jiffies + LINK_TIMEOUT;
5740         } else {
5741                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
5742                 np->need_linktimer = 0;
5743         }
5744
5745         /* Limit the number of tx's outstanding for hw bug */
5746         if (id->driver_data & DEV_NEED_TX_LIMIT) {
5747                 np->tx_limit = 1;
5748                 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
5749                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
5750                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
5751                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
5752                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
5753                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
5754                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
5755                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_39) &&
5756                     pci_dev->revision >= 0xA2)
5757                         np->tx_limit = 0;
5758         }
5759
5760         /* clear phy state and temporarily halt phy interrupts */
5761         writel(0, base + NvRegMIIMask);
5762         phystate = readl(base + NvRegAdapterControl);
5763         if (phystate & NVREG_ADAPTCTL_RUNNING) {
5764                 phystate_orig = 1;
5765                 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5766                 writel(phystate, base + NvRegAdapterControl);
5767         }
5768         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5769
5770         if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5771                 /* management unit running on the mac? */
5772                 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) {
5773                         np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST;
5774                         dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n", pci_name(pci_dev), np->mac_in_use);
5775                         if (nv_mgmt_acquire_sema(dev)) {
5776                                 /* management unit setup the phy already? */
5777                                 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5778                                     NVREG_XMITCTL_SYNC_PHY_INIT) {
5779                                         /* phy is inited by mgmt unit */
5780                                         phyinitialized = 1;
5781                                         dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n", pci_name(pci_dev));
5782                                 } else {
5783                                         /* we need to init the phy */
5784                                 }
5785                         }
5786                 }
5787         }
5788
5789         /* find a suitable phy */
5790         for (i = 1; i <= 32; i++) {
5791                 int id1, id2;
5792                 int phyaddr = i & 0x1F;
5793
5794                 spin_lock_irq(&np->lock);
5795                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5796                 spin_unlock_irq(&np->lock);
5797                 if (id1 < 0 || id1 == 0xffff)
5798                         continue;
5799                 spin_lock_irq(&np->lock);
5800                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5801                 spin_unlock_irq(&np->lock);
5802                 if (id2 < 0 || id2 == 0xffff)
5803                         continue;
5804
5805                 np->phy_model = id2 & PHYID2_MODEL_MASK;
5806                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5807                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5808                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
5809                         pci_name(pci_dev), id1, id2, phyaddr);
5810                 np->phyaddr = phyaddr;
5811                 np->phy_oui = id1 | id2;
5812
5813                 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5814                 if (np->phy_oui == PHY_OUI_REALTEK2)
5815                         np->phy_oui = PHY_OUI_REALTEK;
5816                 /* Setup phy revision for Realtek */
5817                 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5818                         np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5819
5820                 break;
5821         }
5822         if (i == 33) {
5823                 dev_printk(KERN_INFO, &pci_dev->dev,
5824                         "open: Could not find a valid PHY.\n");
5825                 goto out_error;
5826         }
5827
5828         if (!phyinitialized) {
5829                 /* reset it */
5830                 phy_init(dev);
5831         } else {
5832                 /* see if it is a gigabit phy */
5833                 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5834                 if (mii_status & PHY_GIGABIT) {
5835                         np->gigabit = PHY_GIGABIT;
5836                 }
5837         }
5838
5839         /* set default link speed settings */
5840         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5841         np->duplex = 0;
5842         np->autoneg = 1;
5843
5844         err = register_netdev(dev);
5845         if (err) {
5846                 dev_printk(KERN_INFO, &pci_dev->dev,
5847                            "unable to register netdev: %d\n", err);
5848                 goto out_error;
5849         }
5850
5851         dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, "
5852                    "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
5853                    dev->name,
5854                    np->phy_oui,
5855                    np->phyaddr,
5856                    dev->dev_addr[0],
5857                    dev->dev_addr[1],
5858                    dev->dev_addr[2],
5859                    dev->dev_addr[3],
5860                    dev->dev_addr[4],
5861                    dev->dev_addr[5]);
5862
5863         dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5864                    dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
5865                    dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
5866                         "csum " : "",
5867                    dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
5868                         "vlan " : "",
5869                    id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5870                    id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5871                    id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5872                    np->gigabit == PHY_GIGABIT ? "gbit " : "",
5873                    np->need_linktimer ? "lnktim " : "",
5874                    np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5875                    np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5876                    np->desc_ver);
5877
5878         return 0;
5879
5880 out_error:
5881         if (phystate_orig)
5882                 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
5883         pci_set_drvdata(pci_dev, NULL);
5884 out_freering:
5885         free_rings(dev);
5886 out_unmap:
5887         iounmap(get_hwbase(dev));
5888 out_relreg:
5889         pci_release_regions(pci_dev);
5890 out_disable:
5891         pci_disable_device(pci_dev);
5892 out_free:
5893         free_netdev(dev);
5894 out:
5895         return err;
5896 }
5897
5898 static void nv_restore_phy(struct net_device *dev)
5899 {
5900         struct fe_priv *np = netdev_priv(dev);
5901         u16 phy_reserved, mii_control;
5902
5903         if (np->phy_oui == PHY_OUI_REALTEK &&
5904             np->phy_model == PHY_MODEL_REALTEK_8201 &&
5905             phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
5906                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
5907                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
5908                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
5909                 phy_reserved |= PHY_REALTEK_INIT8;
5910                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
5911                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
5912
5913                 /* restart auto negotiation */
5914                 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
5915                 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
5916                 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
5917         }
5918 }
5919
5920 static void nv_restore_mac_addr(struct pci_dev *pci_dev)
5921 {
5922         struct net_device *dev = pci_get_drvdata(pci_dev);
5923         struct fe_priv *np = netdev_priv(dev);
5924         u8 __iomem *base = get_hwbase(dev);
5925
5926         /* special op: write back the misordered MAC address - otherwise
5927          * the next nv_probe would see a wrong address.
5928          */
5929         writel(np->orig_mac[0], base + NvRegMacAddrA);
5930         writel(np->orig_mac[1], base + NvRegMacAddrB);
5931         writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
5932                base + NvRegTransmitPoll);
5933 }
5934
5935 static void __devexit nv_remove(struct pci_dev *pci_dev)
5936 {
5937         struct net_device *dev = pci_get_drvdata(pci_dev);
5938
5939         unregister_netdev(dev);
5940
5941         nv_restore_mac_addr(pci_dev);
5942
5943         /* restore any phy related changes */
5944         nv_restore_phy(dev);
5945
5946         /* free all structures */
5947         free_rings(dev);
5948         iounmap(get_hwbase(dev));
5949         pci_release_regions(pci_dev);
5950         pci_disable_device(pci_dev);
5951         free_netdev(dev);
5952         pci_set_drvdata(pci_dev, NULL);
5953 }
5954
5955 #ifdef CONFIG_PM
5956 static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
5957 {
5958         struct net_device *dev = pci_get_drvdata(pdev);
5959         struct fe_priv *np = netdev_priv(dev);
5960         u8 __iomem *base = get_hwbase(dev);
5961         int i;
5962
5963         if (netif_running(dev)) {
5964                 // Gross.
5965                 nv_close(dev);
5966         }
5967         netif_device_detach(dev);
5968
5969         /* save non-pci configuration space */
5970         for (i = 0;i <= np->register_size/sizeof(u32); i++)
5971                 np->saved_config_space[i] = readl(base + i*sizeof(u32));
5972
5973         pci_save_state(pdev);
5974         pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
5975         pci_disable_device(pdev);
5976         pci_set_power_state(pdev, pci_choose_state(pdev, state));
5977         return 0;
5978 }
5979
5980 static int nv_resume(struct pci_dev *pdev)
5981 {
5982         struct net_device *dev = pci_get_drvdata(pdev);
5983         struct fe_priv *np = netdev_priv(dev);
5984         u8 __iomem *base = get_hwbase(dev);
5985         int i, rc = 0;
5986
5987         pci_set_power_state(pdev, PCI_D0);
5988         pci_restore_state(pdev);
5989         /* ack any pending wake events, disable PME */
5990         pci_enable_wake(pdev, PCI_D0, 0);
5991
5992         /* restore non-pci configuration space */
5993         for (i = 0;i <= np->register_size/sizeof(u32); i++)
5994                 writel(np->saved_config_space[i], base+i*sizeof(u32));
5995
5996         netif_device_attach(dev);
5997         if (netif_running(dev)) {
5998                 rc = nv_open(dev);
5999                 nv_set_multicast(dev);
6000         }
6001         return rc;
6002 }
6003
6004 static void nv_shutdown(struct pci_dev *pdev)
6005 {
6006         struct net_device *dev = pci_get_drvdata(pdev);
6007         struct fe_priv *np = netdev_priv(dev);
6008
6009         if (netif_running(dev))
6010                 nv_close(dev);
6011
6012         nv_restore_mac_addr(pdev);
6013
6014         pci_disable_device(pdev);
6015         if (system_state == SYSTEM_POWER_OFF) {
6016                 if (pci_enable_wake(pdev, PCI_D3cold, np->wolenabled))
6017                         pci_enable_wake(pdev, PCI_D3hot, np->wolenabled);
6018                 pci_set_power_state(pdev, PCI_D3hot);
6019         }
6020 }
6021 #else
6022 #define nv_suspend NULL
6023 #define nv_shutdown NULL
6024 #define nv_resume NULL
6025 #endif /* CONFIG_PM */
6026
6027 static struct pci_device_id pci_tbl[] = {
6028         {       /* nForce Ethernet Controller */
6029                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
6030                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6031         },
6032         {       /* nForce2 Ethernet Controller */
6033                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
6034                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6035         },
6036         {       /* nForce3 Ethernet Controller */
6037                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
6038                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6039         },
6040         {       /* nForce3 Ethernet Controller */
6041                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
6042                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6043         },
6044         {       /* nForce3 Ethernet Controller */
6045                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
6046                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6047         },
6048         {       /* nForce3 Ethernet Controller */
6049                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
6050                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6051         },
6052         {       /* nForce3 Ethernet Controller */
6053                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
6054                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6055         },
6056         {       /* CK804 Ethernet Controller */
6057                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
6058                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6059         },
6060         {       /* CK804 Ethernet Controller */
6061                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
6062                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6063         },
6064         {       /* MCP04 Ethernet Controller */
6065                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
6066                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6067         },
6068         {       /* MCP04 Ethernet Controller */
6069                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
6070                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6071         },
6072         {       /* MCP51 Ethernet Controller */
6073                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
6074                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
6075         },
6076         {       /* MCP51 Ethernet Controller */
6077                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
6078                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
6079         },
6080         {       /* MCP55 Ethernet Controller */
6081                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
6082                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT,
6083         },
6084         {       /* MCP55 Ethernet Controller */
6085                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
6086                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT,
6087         },
6088         {       /* MCP61 Ethernet Controller */
6089                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
6090                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
6091         },
6092         {       /* MCP61 Ethernet Controller */
6093                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
6094                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
6095         },
6096         {       /* MCP61 Ethernet Controller */
6097                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
6098                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
6099         },
6100         {       /* MCP61 Ethernet Controller */
6101                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
6102                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
6103         },
6104         {       /* MCP65 Ethernet Controller */
6105                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
6106                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6107         },
6108         {       /* MCP65 Ethernet Controller */
6109                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
6110                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6111         },
6112         {       /* MCP65 Ethernet Controller */
6113                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
6114                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6115         },
6116         {       /* MCP65 Ethernet Controller */
6117                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
6118                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6119         },
6120         {       /* MCP67 Ethernet Controller */
6121                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24),
6122                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
6123         },
6124         {       /* MCP67 Ethernet Controller */
6125                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25),
6126                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
6127         },
6128         {       /* MCP67 Ethernet Controller */
6129                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26),
6130                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
6131         },
6132         {       /* MCP67 Ethernet Controller */
6133                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27),
6134                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
6135         },
6136         {       /* MCP73 Ethernet Controller */
6137                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_28),
6138                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
6139         },
6140         {       /* MCP73 Ethernet Controller */
6141                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_29),
6142                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
6143         },
6144         {       /* MCP73 Ethernet Controller */
6145                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_30),
6146                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
6147         },
6148         {       /* MCP73 Ethernet Controller */
6149                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_31),
6150                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
6151         },
6152         {       /* MCP77 Ethernet Controller */
6153                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_32),
6154                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6155         },
6156         {       /* MCP77 Ethernet Controller */
6157                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_33),
6158                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6159         },
6160         {       /* MCP77 Ethernet Controller */
6161                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_34),
6162                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6163         },
6164         {       /* MCP77 Ethernet Controller */
6165                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_35),
6166                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6167         },
6168         {       /* MCP79 Ethernet Controller */
6169                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36),
6170                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6171         },
6172         {       /* MCP79 Ethernet Controller */
6173                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37),
6174                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6175         },
6176         {       /* MCP79 Ethernet Controller */
6177                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38),
6178                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6179         },
6180         {       /* MCP79 Ethernet Controller */
6181                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39),
6182                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
6183         },
6184         {0,},
6185 };
6186
6187 static struct pci_driver driver = {
6188         .name           = DRV_NAME,
6189         .id_table       = pci_tbl,
6190         .probe          = nv_probe,
6191         .remove         = __devexit_p(nv_remove),
6192         .suspend        = nv_suspend,
6193         .resume         = nv_resume,
6194         .shutdown       = nv_shutdown,
6195 };
6196
6197 static int __init init_nic(void)
6198 {
6199         return pci_register_driver(&driver);
6200 }
6201
6202 static void __exit exit_nic(void)
6203 {
6204         pci_unregister_driver(&driver);
6205 }
6206
6207 module_param(max_interrupt_work, int, 0);
6208 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
6209 module_param(optimization_mode, int, 0);
6210 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
6211 module_param(poll_interval, int, 0);
6212 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6213 module_param(msi, int, 0);
6214 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6215 module_param(msix, int, 0);
6216 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6217 module_param(dma_64bit, int, 0);
6218 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6219 module_param(phy_cross, int, 0);
6220 MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6221
6222 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6223 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6224 MODULE_LICENSE("GPL");
6225
6226 MODULE_DEVICE_TABLE(pci, pci_tbl);
6227
6228 module_init(init_nic);
6229 module_exit(exit_nic);