git.oblomov.eu Git - linux-2.6/blob - arch/powerpc/boot/dts/mpc834x_mds.dts

   1 /*
   2  * MPC8349E MDS Device Tree Source
   3  *
   4  * Copyright 2005, 2006 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 / {
  15         model = "MPC8349EMDS";
  16         compatible = "MPC8349EMDS", "MPC834xMDS", "MPC83xxMDS";
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         aliases {
  21                 ethernet0 = &enet0;
  22                 ethernet1 = &enet1;
  23                 serial0 = &serial0;
  24                 serial1 = &serial1;
  25                 pci0 = &pci0;
  26                 pci1 = &pci1;
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 PowerPC,8349@0 {
  34                         device_type = "cpu";
  35                         reg = <0x0>;
  36                         d-cache-line-size = <32>;
  37                         i-cache-line-size = <32>;
  38                         d-cache-size = <32768>;
  39                         i-cache-size = <32768>;
  40                         timebase-frequency = <0>;       // from bootloader
  41                         bus-frequency = <0>;            // from bootloader
  42                         clock-frequency = <0>;          // from bootloader
  43                 };
  44         };
  45
  46         memory {
  47                 device_type = "memory";
  48                 reg = <0x00000000 0x10000000>;  // 256MB at 0
  49         };
  50
  51         bcsr@e2400000 {
  52                 compatible = "fsl,mpc8349mds-bcsr";
  53                 reg = <0xe2400000 0x8000>;
  54         };
  55
  56         soc8349@e0000000 {
  57                 #address-cells = <1>;
  58                 #size-cells = <1>;
  59                 device_type = "soc";
  60                 compatible = "simple-bus";
  61                 ranges = <0x0 0xe0000000 0x00100000>;
  62                 reg = <0xe0000000 0x00000200>;
  63                 bus-frequency = <0>;
  64
  65                 wdt@200 {
  66                         device_type = "watchdog";
  67                         compatible = "mpc83xx_wdt";
  68                         reg = <0x200 0x100>;
  69                 };
  70
  71                 i2c@3000 {
  72                         #address-cells = <1>;
  73                         #size-cells = <0>;
  74                         cell-index = <0>;
  75                         compatible = "fsl-i2c";
  76                         reg = <0x3000 0x100>;
  77                         interrupts = <14 0x8>;
  78                         interrupt-parent = <&ipic>;
  79                         dfsrr;
  80
  81                         rtc@68 {
  82                                 compatible = "dallas,ds1374";
  83                                 reg = <0x68>;
  84                         };
  85                 };
  86
  87                 i2c@3100 {
  88                         #address-cells = <1>;
  89                         #size-cells = <0>;
  90                         cell-index = <1>;
  91                         compatible = "fsl-i2c";
  92                         reg = <0x3100 0x100>;
  93                         interrupts = <15 0x8>;
  94                         interrupt-parent = <&ipic>;
  95                         dfsrr;
  96                 };
  97
  98                 spi@7000 {
  99                         cell-index = <0>;
 100                         compatible = "fsl,spi";
 101                         reg = <0x7000 0x1000>;
 102                         interrupts = <16 0x8>;
 103                         interrupt-parent = <&ipic>;
 104                         mode = "cpu";
 105                 };
 106
 107                 dma@82a8 {
 108                         #address-cells = <1>;
 109                         #size-cells = <1>;
 110                         compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
 111                         reg = <0x82a8 4>;
 112                         ranges = <0 0x8100 0x1a8>;
 113                         interrupt-parent = <&ipic>;
 114                         interrupts = <71 8>;
 115                         cell-index = <0>;
 116                         dma-channel@0 {
 117                                 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
 118                                 reg = <0 0x80>;
 119                                 cell-index = <0>;
 120                                 interrupt-parent = <&ipic>;
 121                                 interrupts = <71 8>;
 122                         };
 123                         dma-channel@80 {
 124                                 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
 125                                 reg = <0x80 0x80>;
 126                                 cell-index = <1>;
 127                                 interrupt-parent = <&ipic>;
 128                                 interrupts = <71 8>;
 129                         };
 130                         dma-channel@100 {
 131                                 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
 132                                 reg = <0x100 0x80>;
 133                                 cell-index = <2>;
 134                                 interrupt-parent = <&ipic>;
 135                                 interrupts = <71 8>;
 136                         };
 137                         dma-channel@180 {
 138                                 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
 139                                 reg = <0x180 0x28>;
 140                                 cell-index = <3>;
 141                                 interrupt-parent = <&ipic>;
 142                                 interrupts = <71 8>;
 143                         };
 144                 };
 145
 146                 /* phy type (ULPI or SERIAL) are only types supported for MPH */
 147                 /* port = 0 or 1 */
 148                 usb@22000 {
 149                         compatible = "fsl-usb2-mph";
 150                         reg = <0x22000 0x1000>;
 151                         #address-cells = <1>;
 152                         #size-cells = <0>;
 153                         interrupt-parent = <&ipic>;
 154                         interrupts = <39 0x8>;
 155                         phy_type = "ulpi";
 156                         port1;
 157                 };
 158                 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
 159                 usb@23000 {
 160                         compatible = "fsl-usb2-dr";
 161                         reg = <0x23000 0x1000>;
 162                         #address-cells = <1>;
 163                         #size-cells = <0>;
 164                         interrupt-parent = <&ipic>;
 165                         interrupts = <38 0x8>;
 166                         dr_mode = "otg";
 167                         phy_type = "ulpi";
 168                 };
 169
 170                 mdio@24520 {
 171                         #address-cells = <1>;
 172                         #size-cells = <0>;
 173                         compatible = "fsl,gianfar-mdio";
 174                         reg = <0x24520 0x20>;
 175
 176                         phy0: ethernet-phy@0 {
 177                                 interrupt-parent = <&ipic>;
 178                                 interrupts = <17 0x8>;
 179                                 reg = <0x0>;
 180                                 device_type = "ethernet-phy";
 181                         };
 182                         phy1: ethernet-phy@1 {
 183                                 interrupt-parent = <&ipic>;
 184                                 interrupts = <18 0x8>;
 185                                 reg = <0x1>;
 186                                 device_type = "ethernet-phy";
 187                         };
 188                 };
 189
 190                 enet0: ethernet@24000 {
 191                         cell-index = <0>;
 192                         device_type = "network";
 193                         model = "TSEC";
 194                         compatible = "gianfar";
 195                         reg = <0x24000 0x1000>;
 196                         local-mac-address = [ 00 00 00 00 00 00 ];
 197                         interrupts = <32 0x8 33 0x8 34 0x8>;
 198                         interrupt-parent = <&ipic>;
 199                         phy-handle = <&phy0>;
 200                         linux,network-index = <0>;
 201                 };
 202
 203                 enet1: ethernet@25000 {
 204                         cell-index = <1>;
 205                         device_type = "network";
 206                         model = "TSEC";
 207                         compatible = "gianfar";
 208                         reg = <0x25000 0x1000>;
 209                         local-mac-address = [ 00 00 00 00 00 00 ];
 210                         interrupts = <35 0x8 36 0x8 37 0x8>;
 211                         interrupt-parent = <&ipic>;
 212                         phy-handle = <&phy1>;
 213                         linux,network-index = <1>;
 214                 };
 215
 216                 serial0: serial@4500 {
 217                         cell-index = <0>;
 218                         device_type = "serial";
 219                         compatible = "ns16550";
 220                         reg = <0x4500 0x100>;
 221                         clock-frequency = <0>;
 222                         interrupts = <9 0x8>;
 223                         interrupt-parent = <&ipic>;
 224                 };
 225
 226                 serial1: serial@4600 {
 227                         cell-index = <1>;
 228                         device_type = "serial";
 229                         compatible = "ns16550";
 230                         reg = <0x4600 0x100>;
 231                         clock-frequency = <0>;
 232                         interrupts = <10 0x8>;
 233                         interrupt-parent = <&ipic>;
 234                 };
 235
 236                 crypto@30000 {
 237                         compatible = "fsl,sec2.0";
 238                         reg = <0x30000 0x10000>;
 239                         interrupts = <11 0x8>;
 240                         interrupt-parent = <&ipic>;
 241                         fsl,num-channels = <4>;
 242                         fsl,channel-fifo-len = <24>;
 243                         fsl,exec-units-mask = <0x7e>;
 244                         fsl,descriptor-types-mask = <0x01010ebf>;
 245                 };
 246
 247                 /* IPIC
 248                  * interrupts cell = <intr #, sense>
 249                  * sense values match linux IORESOURCE_IRQ_* defines:
 250                  * sense == 8: Level, low assertion
 251                  * sense == 2: Edge, high-to-low change
 252                  */
 253                 ipic: pic@700 {
 254                         interrupt-controller;
 255                         #address-cells = <0>;
 256                         #interrupt-cells = <2>;
 257                         reg = <0x700 0x100>;
 258                         device_type = "ipic";
 259                 };
 260         };
 261
 262         pci0: pci@e0008500 {
 263                 cell-index = <1>;
 264                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 265                 interrupt-map = <
 266
 267                                 /* IDSEL 0x11 */
 268                                  0x8800 0x0 0x0 0x1 &ipic 20 0x8
 269                                  0x8800 0x0 0x0 0x2 &ipic 21 0x8
 270                                  0x8800 0x0 0x0 0x3 &ipic 22 0x8
 271                                  0x8800 0x0 0x0 0x4 &ipic 23 0x8
 272
 273                                 /* IDSEL 0x12 */
 274                                  0x9000 0x0 0x0 0x1 &ipic 22 0x8
 275                                  0x9000 0x0 0x0 0x2 &ipic 23 0x8
 276                                  0x9000 0x0 0x0 0x3 &ipic 20 0x8
 277                                  0x9000 0x0 0x0 0x4 &ipic 21 0x8
 278
 279                                 /* IDSEL 0x13 */
 280                                  0x9800 0x0 0x0 0x1 &ipic 23 0x8
 281                                  0x9800 0x0 0x0 0x2 &ipic 20 0x8
 282                                  0x9800 0x0 0x0 0x3 &ipic 21 0x8
 283                                  0x9800 0x0 0x0 0x4 &ipic 22 0x8
 284
 285                                 /* IDSEL 0x15 */
 286                                  0xa800 0x0 0x0 0x1 &ipic 20 0x8
 287                                  0xa800 0x0 0x0 0x2 &ipic 21 0x8
 288                                  0xa800 0x0 0x0 0x3 &ipic 22 0x8
 289                                  0xa800 0x0 0x0 0x4 &ipic 23 0x8
 290
 291                                 /* IDSEL 0x16 */
 292                                  0xb000 0x0 0x0 0x1 &ipic 23 0x8
 293                                  0xb000 0x0 0x0 0x2 &ipic 20 0x8
 294                                  0xb000 0x0 0x0 0x3 &ipic 21 0x8
 295                                  0xb000 0x0 0x0 0x4 &ipic 22 0x8
 296
 297                                 /* IDSEL 0x17 */
 298                                  0xb800 0x0 0x0 0x1 &ipic 22 0x8
 299                                  0xb800 0x0 0x0 0x2 &ipic 23 0x8
 300                                  0xb800 0x0 0x0 0x3 &ipic 20 0x8
 301                                  0xb800 0x0 0x0 0x4 &ipic 21 0x8
 302
 303                                 /* IDSEL 0x18 */
 304                                  0xc000 0x0 0x0 0x1 &ipic 21 0x8
 305                                  0xc000 0x0 0x0 0x2 &ipic 22 0x8
 306                                  0xc000 0x0 0x0 0x3 &ipic 23 0x8
 307                                  0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
 308                 interrupt-parent = <&ipic>;
 309                 interrupts = <66 0x8>;
 310                 bus-range = <0 0>;
 311                 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
 312                           0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
 313                           0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
 314                 clock-frequency = <66666666>;
 315                 #interrupt-cells = <1>;
 316                 #size-cells = <2>;
 317                 #address-cells = <3>;
 318                 reg = <0xe0008500 0x100         /* internal registers */
 319                        0xe0008300 0x8>;         /* config space access registers */
 320                 compatible = "fsl,mpc8349-pci";
 321                 device_type = "pci";
 322         };
 323
 324         pci1: pci@e0008600 {
 325                 cell-index = <2>;
 326                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 327                 interrupt-map = <
 328
 329                                 /* IDSEL 0x11 */
 330                                  0x8800 0x0 0x0 0x1 &ipic 20 0x8
 331                                  0x8800 0x0 0x0 0x2 &ipic 21 0x8
 332                                  0x8800 0x0 0x0 0x3 &ipic 22 0x8
 333                                  0x8800 0x0 0x0 0x4 &ipic 23 0x8
 334
 335                                 /* IDSEL 0x12 */
 336                                  0x9000 0x0 0x0 0x1 &ipic 22 0x8
 337                                  0x9000 0x0 0x0 0x2 &ipic 23 0x8
 338                                  0x9000 0x0 0x0 0x3 &ipic 20 0x8
 339                                  0x9000 0x0 0x0 0x4 &ipic 21 0x8
 340
 341                                 /* IDSEL 0x13 */
 342                                  0x9800 0x0 0x0 0x1 &ipic 23 0x8
 343                                  0x9800 0x0 0x0 0x2 &ipic 20 0x8
 344                                  0x9800 0x0 0x0 0x3 &ipic 21 0x8
 345                                  0x9800 0x0 0x0 0x4 &ipic 22 0x8
 346
 347                                 /* IDSEL 0x15 */
 348                                  0xa800 0x0 0x0 0x1 &ipic 20 0x8
 349                                  0xa800 0x0 0x0 0x2 &ipic 21 0x8
 350                                  0xa800 0x0 0x0 0x3 &ipic 22 0x8
 351                                  0xa800 0x0 0x0 0x4 &ipic 23 0x8
 352
 353                                 /* IDSEL 0x16 */
 354                                  0xb000 0x0 0x0 0x1 &ipic 23 0x8
 355                                  0xb000 0x0 0x0 0x2 &ipic 20 0x8
 356                                  0xb000 0x0 0x0 0x3 &ipic 21 0x8
 357                                  0xb000 0x0 0x0 0x4 &ipic 22 0x8
 358
 359                                 /* IDSEL 0x17 */
 360                                  0xb800 0x0 0x0 0x1 &ipic 22 0x8
 361                                  0xb800 0x0 0x0 0x2 &ipic 23 0x8
 362                                  0xb800 0x0 0x0 0x3 &ipic 20 0x8
 363                                  0xb800 0x0 0x0 0x4 &ipic 21 0x8
 364
 365                                 /* IDSEL 0x18 */
 366                                  0xc000 0x0 0x0 0x1 &ipic 21 0x8
 367                                  0xc000 0x0 0x0 0x2 &ipic 22 0x8
 368                                  0xc000 0x0 0x0 0x3 &ipic 23 0x8
 369                                  0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
 370                 interrupt-parent = <&ipic>;
 371                 interrupts = <67 0x8>;
 372                 bus-range = <0 0>;
 373                 ranges = <0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
 374                           0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
 375                           0x01000000 0x0 0x00000000 0xe2100000 0x0 0x00100000>;
 376                 clock-frequency = <66666666>;
 377                 #interrupt-cells = <1>;
 378                 #size-cells = <2>;
 379                 #address-cells = <3>;
 380                 reg = <0xe0008600 0x100         /* internal registers */
 381                        0xe0008380 0x8>;         /* config space access registers */
 382                 compatible = "fsl,mpc8349-pci";
 383                 device_type = "pci";
 384         };
 385 };