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   1 /*
   2  * Performance counter support for PPC970-family processors.
   3  *
   4  * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11 #include <linux/string.h>
  12 #include <linux/perf_counter.h>
  13 #include <linux/string.h>
  14 #include <asm/reg.h>
  15 #include <asm/cputable.h>
  16
  17 /*
  18  * Bits in event code for PPC970
  19  */
  20 #define PM_PMC_SH       12      /* PMC number (1-based) for direct events */
  21 #define PM_PMC_MSK      0xf
  22 #define PM_UNIT_SH      8       /* TTMMUX number and setting - unit select */
  23 #define PM_UNIT_MSK     0xf
  24 #define PM_SPCSEL_SH    6
  25 #define PM_SPCSEL_MSK   3
  26 #define PM_BYTE_SH      4       /* Byte number of event bus to use */
  27 #define PM_BYTE_MSK     3
  28 #define PM_PMCSEL_MSK   0xf
  29
  30 /* Values in PM_UNIT field */
  31 #define PM_NONE         0
  32 #define PM_FPU          1
  33 #define PM_VPU          2
  34 #define PM_ISU          3
  35 #define PM_IFU          4
  36 #define PM_IDU          5
  37 #define PM_STS          6
  38 #define PM_LSU0         7
  39 #define PM_LSU1U        8
  40 #define PM_LSU1L        9
  41 #define PM_LASTUNIT     9
  42
  43 /*
  44  * Bits in MMCR0 for PPC970
  45  */
  46 #define MMCR0_PMC1SEL_SH        8
  47 #define MMCR0_PMC2SEL_SH        1
  48 #define MMCR_PMCSEL_MSK         0x1f
  49
  50 /*
  51  * Bits in MMCR1 for PPC970
  52  */
  53 #define MMCR1_TTM0SEL_SH        62
  54 #define MMCR1_TTM1SEL_SH        59
  55 #define MMCR1_TTM3SEL_SH        53
  56 #define MMCR1_TTMSEL_MSK        3
  57 #define MMCR1_TD_CP_DBG0SEL_SH  50
  58 #define MMCR1_TD_CP_DBG1SEL_SH  48
  59 #define MMCR1_TD_CP_DBG2SEL_SH  46
  60 #define MMCR1_TD_CP_DBG3SEL_SH  44
  61 #define MMCR1_PMC1_ADDER_SEL_SH 39
  62 #define MMCR1_PMC2_ADDER_SEL_SH 38
  63 #define MMCR1_PMC6_ADDER_SEL_SH 37
  64 #define MMCR1_PMC5_ADDER_SEL_SH 36
  65 #define MMCR1_PMC8_ADDER_SEL_SH 35
  66 #define MMCR1_PMC7_ADDER_SEL_SH 34
  67 #define MMCR1_PMC3_ADDER_SEL_SH 33
  68 #define MMCR1_PMC4_ADDER_SEL_SH 32
  69 #define MMCR1_PMC3SEL_SH        27
  70 #define MMCR1_PMC4SEL_SH        22
  71 #define MMCR1_PMC5SEL_SH        17
  72 #define MMCR1_PMC6SEL_SH        12
  73 #define MMCR1_PMC7SEL_SH        7
  74 #define MMCR1_PMC8SEL_SH        2
  75
  76 static short mmcr1_adder_bits[8] = {
  77         MMCR1_PMC1_ADDER_SEL_SH,
  78         MMCR1_PMC2_ADDER_SEL_SH,
  79         MMCR1_PMC3_ADDER_SEL_SH,
  80         MMCR1_PMC4_ADDER_SEL_SH,
  81         MMCR1_PMC5_ADDER_SEL_SH,
  82         MMCR1_PMC6_ADDER_SEL_SH,
  83         MMCR1_PMC7_ADDER_SEL_SH,
  84         MMCR1_PMC8_ADDER_SEL_SH
  85 };
  86
  87 /*
  88  * Bits in MMCRA
  89  */
  90
  91 /*
  92  * Layout of constraint bits:
  93  * 6666555555555544444444443333333333222222222211111111110000000000
  94  * 3210987654321098765432109876543210987654321098765432109876543210
  95  *               <><><>[  >[  >[  ><  ><  ><  ><  ><><><><><><><><>
  96  *               SPT0T1 UC  PS1 PS2 B0  B1  B2  B3 P1P2P3P4P5P6P7P8
  97  *
  98  * SP - SPCSEL constraint
  99  *     48-49: SPCSEL value 0x3_0000_0000_0000
 100  *
 101  * T0 - TTM0 constraint
 102  *     46-47: TTM0SEL value (0=FPU, 2=IFU, 3=VPU) 0xC000_0000_0000
 103  *
 104  * T1 - TTM1 constraint
 105  *     44-45: TTM1SEL value (0=IDU, 3=STS) 0x3000_0000_0000
 106  *
 107  * UC - unit constraint: can't have all three of FPU|IFU|VPU, ISU, IDU|STS
 108  *     43: UC3 error 0x0800_0000_0000
 109  *     42: FPU|IFU|VPU events needed 0x0400_0000_0000
 110  *     41: ISU events needed 0x0200_0000_0000
 111  *     40: IDU|STS events needed 0x0100_0000_0000
 112  *
 113  * PS1
 114  *     39: PS1 error 0x0080_0000_0000
 115  *     36-38: count of events needing PMC1/2/5/6 0x0070_0000_0000
 116  *
 117  * PS2
 118  *     35: PS2 error 0x0008_0000_0000
 119  *     32-34: count of events needing PMC3/4/7/8 0x0007_0000_0000
 120  *
 121  * B0
 122  *     28-31: Byte 0 event source 0xf000_0000
 123  *            Encoding as for the event code
 124  *
 125  * B1, B2, B3
 126  *     24-27, 20-23, 16-19: Byte 1, 2, 3 event sources
 127  *
 128  * P1
 129  *     15: P1 error 0x8000
 130  *     14-15: Count of events needing PMC1
 131  *
 132  * P2..P8
 133  *     0-13: Count of events needing PMC2..PMC8
 134  */
 135
 136 static unsigned char direct_marked_event[8] = {
 137         (1<<2) | (1<<3),        /* PMC1: PM_MRK_GRP_DISP, PM_MRK_ST_CMPL */
 138         (1<<3) | (1<<5),        /* PMC2: PM_THRESH_TIMEO, PM_MRK_BRU_FIN */
 139         (1<<3) | (1<<5),        /* PMC3: PM_MRK_ST_CMPL_INT, PM_MRK_VMX_FIN */
 140         (1<<4) | (1<<5),        /* PMC4: PM_MRK_GRP_CMPL, PM_MRK_CRU_FIN */
 141         (1<<4) | (1<<5),        /* PMC5: PM_GRP_MRK, PM_MRK_GRP_TIMEO */
 142         (1<<3) | (1<<4) | (1<<5),
 143                 /* PMC6: PM_MRK_ST_STS, PM_MRK_FXU_FIN, PM_MRK_GRP_ISSUED */
 144         (1<<4) | (1<<5),        /* PMC7: PM_MRK_FPU_FIN, PM_MRK_INST_FIN */
 145         (1<<4)                  /* PMC8: PM_MRK_LSU_FIN */
 146 };
 147
 148 /*
 149  * Returns 1 if event counts things relating to marked instructions
 150  * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
 151  */
 152 static int p970_marked_instr_event(u64 event)
 153 {
 154         int pmc, psel, unit, byte, bit;
 155         unsigned int mask;
 156
 157         pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
 158         psel = event & PM_PMCSEL_MSK;
 159         if (pmc) {
 160                 if (direct_marked_event[pmc - 1] & (1 << psel))
 161                         return 1;
 162                 if (psel == 0)          /* add events */
 163                         bit = (pmc <= 4)? pmc - 1: 8 - pmc;
 164                 else if (psel == 7 || psel == 13)       /* decode events */
 165                         bit = 4;
 166                 else
 167                         return 0;
 168         } else
 169                 bit = psel;
 170
 171         byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
 172         unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
 173         mask = 0;
 174         switch (unit) {
 175         case PM_VPU:
 176                 mask = 0x4c;            /* byte 0 bits 2,3,6 */
 177         case PM_LSU0:
 178                 /* byte 2 bits 0,2,3,4,6; all of byte 1 */
 179                 mask = 0x085dff00;
 180         case PM_LSU1L:
 181                 mask = 0x50 << 24;      /* byte 3 bits 4,6 */
 182                 break;
 183         }
 184         return (mask >> (byte * 8 + bit)) & 1;
 185 }
 186
 187 /* Masks and values for using events from the various units */
 188 static unsigned long unit_cons[PM_LASTUNIT+1][2] = {
 189         [PM_FPU] =   { 0xc80000000000ull, 0x040000000000ull },
 190         [PM_VPU] =   { 0xc80000000000ull, 0xc40000000000ull },
 191         [PM_ISU] =   { 0x080000000000ull, 0x020000000000ull },
 192         [PM_IFU] =   { 0xc80000000000ull, 0x840000000000ull },
 193         [PM_IDU] =   { 0x380000000000ull, 0x010000000000ull },
 194         [PM_STS] =   { 0x380000000000ull, 0x310000000000ull },
 195 };
 196
 197 static int p970_get_constraint(u64 event, unsigned long *maskp,
 198                                unsigned long *valp)
 199 {
 200         int pmc, byte, unit, sh, spcsel;
 201         unsigned long mask = 0, value = 0;
 202         int grp = -1;
 203
 204         pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
 205         if (pmc) {
 206                 if (pmc > 8)
 207                         return -1;
 208                 sh = (pmc - 1) * 2;
 209                 mask |= 2 << sh;
 210                 value |= 1 << sh;
 211                 grp = ((pmc - 1) >> 1) & 1;
 212         }
 213         unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
 214         if (unit) {
 215                 if (unit > PM_LASTUNIT)
 216                         return -1;
 217                 mask |= unit_cons[unit][0];
 218                 value |= unit_cons[unit][1];
 219                 byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
 220                 /*
 221                  * Bus events on bytes 0 and 2 can be counted
 222                  * on PMC1/2/5/6; bytes 1 and 3 on PMC3/4/7/8.
 223                  */
 224                 if (!pmc)
 225                         grp = byte & 1;
 226                 /* Set byte lane select field */
 227                 mask  |= 0xfULL << (28 - 4 * byte);
 228                 value |= (unsigned long)unit << (28 - 4 * byte);
 229         }
 230         if (grp == 0) {
 231                 /* increment PMC1/2/5/6 field */
 232                 mask  |= 0x8000000000ull;
 233                 value |= 0x1000000000ull;
 234         } else if (grp == 1) {
 235                 /* increment PMC3/4/7/8 field */
 236                 mask  |= 0x800000000ull;
 237                 value |= 0x100000000ull;
 238         }
 239         spcsel = (event >> PM_SPCSEL_SH) & PM_SPCSEL_MSK;
 240         if (spcsel) {
 241                 mask  |= 3ull << 48;
 242                 value |= (unsigned long)spcsel << 48;
 243         }
 244         *maskp = mask;
 245         *valp = value;
 246         return 0;
 247 }
 248
 249 static int p970_get_alternatives(u64 event, unsigned int flags, u64 alt[])
 250 {
 251         alt[0] = event;
 252
 253         /* 2 alternatives for LSU empty */
 254         if (event == 0x2002 || event == 0x3002) {
 255                 alt[1] = event ^ 0x1000;
 256                 return 2;
 257         }
 258
 259         return 1;
 260 }
 261
 262 static int p970_compute_mmcr(u64 event[], int n_ev,
 263                              unsigned int hwc[], unsigned long mmcr[])
 264 {
 265         unsigned long mmcr0 = 0, mmcr1 = 0, mmcra = 0;
 266         unsigned int pmc, unit, byte, psel;
 267         unsigned int ttm, grp;
 268         unsigned int pmc_inuse = 0;
 269         unsigned int pmc_grp_use[2];
 270         unsigned char busbyte[4];
 271         unsigned char unituse[16];
 272         unsigned char unitmap[] = { 0, 0<<3, 3<<3, 1<<3, 2<<3, 0|4, 3|4 };
 273         unsigned char ttmuse[2];
 274         unsigned char pmcsel[8];
 275         int i;
 276         int spcsel;
 277
 278         if (n_ev > 8)
 279                 return -1;
 280
 281         /* First pass to count resource use */
 282         pmc_grp_use[0] = pmc_grp_use[1] = 0;
 283         memset(busbyte, 0, sizeof(busbyte));
 284         memset(unituse, 0, sizeof(unituse));
 285         for (i = 0; i < n_ev; ++i) {
 286                 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
 287                 if (pmc) {
 288                         if (pmc_inuse & (1 << (pmc - 1)))
 289                                 return -1;
 290                         pmc_inuse |= 1 << (pmc - 1);
 291                         /* count 1/2/5/6 vs 3/4/7/8 use */
 292                         ++pmc_grp_use[((pmc - 1) >> 1) & 1];
 293                 }
 294                 unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
 295                 byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
 296                 if (unit) {
 297                         if (unit > PM_LASTUNIT)
 298                                 return -1;
 299                         if (!pmc)
 300                                 ++pmc_grp_use[byte & 1];
 301                         if (busbyte[byte] && busbyte[byte] != unit)
 302                                 return -1;
 303                         busbyte[byte] = unit;
 304                         unituse[unit] = 1;
 305                 }
 306         }
 307         if (pmc_grp_use[0] > 4 || pmc_grp_use[1] > 4)
 308                 return -1;
 309
 310         /*
 311          * Assign resources and set multiplexer selects.
 312          *
 313          * PM_ISU can go either on TTM0 or TTM1, but that's the only
 314          * choice we have to deal with.
 315          */
 316         if (unituse[PM_ISU] &
 317             (unituse[PM_FPU] | unituse[PM_IFU] | unituse[PM_VPU]))
 318                 unitmap[PM_ISU] = 2 | 4;        /* move ISU to TTM1 */
 319         /* Set TTM[01]SEL fields. */
 320         ttmuse[0] = ttmuse[1] = 0;
 321         for (i = PM_FPU; i <= PM_STS; ++i) {
 322                 if (!unituse[i])
 323                         continue;
 324                 ttm = unitmap[i];
 325                 ++ttmuse[(ttm >> 2) & 1];
 326                 mmcr1 |= (unsigned long)(ttm & ~4) << MMCR1_TTM1SEL_SH;
 327         }
 328         /* Check only one unit per TTMx */
 329         if (ttmuse[0] > 1 || ttmuse[1] > 1)
 330                 return -1;
 331
 332         /* Set byte lane select fields and TTM3SEL. */
 333         for (byte = 0; byte < 4; ++byte) {
 334                 unit = busbyte[byte];
 335                 if (!unit)
 336                         continue;
 337                 if (unit <= PM_STS)
 338                         ttm = (unitmap[unit] >> 2) & 1;
 339                 else if (unit == PM_LSU0)
 340                         ttm = 2;
 341                 else {
 342                         ttm = 3;
 343                         if (unit == PM_LSU1L && byte >= 2)
 344                                 mmcr1 |= 1ull << (MMCR1_TTM3SEL_SH + 3 - byte);
 345                 }
 346                 mmcr1 |= (unsigned long)ttm
 347                         << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);
 348         }
 349
 350         /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */
 351         memset(pmcsel, 0x8, sizeof(pmcsel));    /* 8 means don't count */
 352         for (i = 0; i < n_ev; ++i) {
 353                 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
 354                 unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
 355                 byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
 356                 psel = event[i] & PM_PMCSEL_MSK;
 357                 if (!pmc) {
 358                         /* Bus event or any-PMC direct event */
 359                         if (unit)
 360                                 psel |= 0x10 | ((byte & 2) << 2);
 361                         else
 362                                 psel |= 8;
 363                         for (pmc = 0; pmc < 8; ++pmc) {
 364                                 if (pmc_inuse & (1 << pmc))
 365                                         continue;
 366                                 grp = (pmc >> 1) & 1;
 367                                 if (unit) {
 368                                         if (grp == (byte & 1))
 369                                                 break;
 370                                 } else if (pmc_grp_use[grp] < 4) {
 371                                         ++pmc_grp_use[grp];
 372                                         break;
 373                                 }
 374                         }
 375                         pmc_inuse |= 1 << pmc;
 376                 } else {
 377                         /* Direct event */
 378                         --pmc;
 379                         if (psel == 0 && (byte & 2))
 380                                 /* add events on higher-numbered bus */
 381                                 mmcr1 |= 1ull << mmcr1_adder_bits[pmc];
 382                 }
 383                 pmcsel[pmc] = psel;
 384                 hwc[i] = pmc;
 385                 spcsel = (event[i] >> PM_SPCSEL_SH) & PM_SPCSEL_MSK;
 386                 mmcr1 |= spcsel;
 387                 if (p970_marked_instr_event(event[i]))
 388                         mmcra |= MMCRA_SAMPLE_ENABLE;
 389         }
 390         for (pmc = 0; pmc < 2; ++pmc)
 391                 mmcr0 |= pmcsel[pmc] << (MMCR0_PMC1SEL_SH - 7 * pmc);
 392         for (; pmc < 8; ++pmc)
 393                 mmcr1 |= (unsigned long)pmcsel[pmc]
 394                         << (MMCR1_PMC3SEL_SH - 5 * (pmc - 2));
 395         if (pmc_inuse & 1)
 396                 mmcr0 |= MMCR0_PMC1CE;
 397         if (pmc_inuse & 0xfe)
 398                 mmcr0 |= MMCR0_PMCjCE;
 399
 400         mmcra |= 0x2000;        /* mark only one IOP per PPC instruction */
 401
 402         /* Return MMCRx values */
 403         mmcr[0] = mmcr0;
 404         mmcr[1] = mmcr1;
 405         mmcr[2] = mmcra;
 406         return 0;
 407 }
 408
 409 static void p970_disable_pmc(unsigned int pmc, unsigned long mmcr[])
 410 {
 411         int shift, i;
 412
 413         if (pmc <= 1) {
 414                 shift = MMCR0_PMC1SEL_SH - 7 * pmc;
 415                 i = 0;
 416         } else {
 417                 shift = MMCR1_PMC3SEL_SH - 5 * (pmc - 2);
 418                 i = 1;
 419         }
 420         /*
 421          * Setting the PMCxSEL field to 0x08 disables PMC x.
 422          */
 423         mmcr[i] = (mmcr[i] & ~(0x1fUL << shift)) | (0x08UL << shift);
 424 }
 425
 426 static int ppc970_generic_events[] = {
 427         [PERF_COUNT_HW_CPU_CYCLES]              = 7,
 428         [PERF_COUNT_HW_INSTRUCTIONS]            = 1,
 429         [PERF_COUNT_HW_CACHE_REFERENCES]        = 0x8810, /* PM_LD_REF_L1 */
 430         [PERF_COUNT_HW_CACHE_MISSES]            = 0x3810, /* PM_LD_MISS_L1 */
 431         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = 0x431,  /* PM_BR_ISSUED */
 432         [PERF_COUNT_HW_BRANCH_MISSES]           = 0x327,  /* PM_GRP_BR_MPRED */
 433 };
 434
 435 #define C(x)    PERF_COUNT_HW_CACHE_##x
 436
 437 /*
 438  * Table of generalized cache-related events.
 439  * 0 means not supported, -1 means nonsensical, other values
 440  * are event codes.
 441  */
 442 static int ppc970_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
 443         [C(L1D)] = {            /*      RESULT_ACCESS   RESULT_MISS */
 444                 [C(OP_READ)] = {        0x8810,         0x3810  },
 445                 [C(OP_WRITE)] = {       0x7810,         0x813   },
 446                 [C(OP_PREFETCH)] = {    0x731,          0       },
 447         },
 448         [C(L1I)] = {            /*      RESULT_ACCESS   RESULT_MISS */
 449                 [C(OP_READ)] = {        0,              0       },
 450                 [C(OP_WRITE)] = {       -1,             -1      },
 451                 [C(OP_PREFETCH)] = {    0,              0       },
 452         },
 453         [C(LL)] = {             /*      RESULT_ACCESS   RESULT_MISS */
 454                 [C(OP_READ)] = {        0,              0       },
 455                 [C(OP_WRITE)] = {       0,              0       },
 456                 [C(OP_PREFETCH)] = {    0x733,          0       },
 457         },
 458         [C(DTLB)] = {           /*      RESULT_ACCESS   RESULT_MISS */
 459                 [C(OP_READ)] = {        0,              0x704   },
 460                 [C(OP_WRITE)] = {       -1,             -1      },
 461                 [C(OP_PREFETCH)] = {    -1,             -1      },
 462         },
 463         [C(ITLB)] = {           /*      RESULT_ACCESS   RESULT_MISS */
 464                 [C(OP_READ)] = {        0,              0x700   },
 465                 [C(OP_WRITE)] = {       -1,             -1      },
 466                 [C(OP_PREFETCH)] = {    -1,             -1      },
 467         },
 468         [C(BPU)] = {            /*      RESULT_ACCESS   RESULT_MISS */
 469                 [C(OP_READ)] = {        0x431,          0x327   },
 470                 [C(OP_WRITE)] = {       -1,             -1      },
 471                 [C(OP_PREFETCH)] = {    -1,             -1      },
 472         },
 473 };
 474
 475 static struct power_pmu ppc970_pmu = {
 476         .name                   = "PPC970/FX/MP",
 477         .n_counter              = 8,
 478         .max_alternatives       = 2,
 479         .add_fields             = 0x001100005555ull,
 480         .test_adder             = 0x013300000000ull,
 481         .compute_mmcr           = p970_compute_mmcr,
 482         .get_constraint         = p970_get_constraint,
 483         .get_alternatives       = p970_get_alternatives,
 484         .disable_pmc            = p970_disable_pmc,
 485         .n_generic              = ARRAY_SIZE(ppc970_generic_events),
 486         .generic_events         = ppc970_generic_events,
 487         .cache_events           = &ppc970_cache_events,
 488 };
 489
 490 static int init_ppc970_pmu(void)
 491 {
 492         if (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/970")
 493             && strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/970MP"))
 494                 return -ENODEV;
 495
 496         return register_power_pmu(&ppc970_pmu);
 497 }
 498
 499 arch_initcall(init_ppc970_pmu);