2 #ifndef _ASM_POWERPC_IRQ_H
3 #define _ASM_POWERPC_IRQ_H
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 #include <linux/threads.h>
13 #include <linux/list.h>
14 #include <linux/radix-tree.h>
16 #include <asm/types.h>
17 #include <asm/atomic.h>
20 #define get_irq_desc(irq) (&irq_desc[(irq)])
22 /* Define a way to iterate across irqs. */
23 #define for_each_irq(i) \
24 for ((i) = 0; (i) < NR_IRQS; ++(i))
26 extern atomic_t ppc_n_lost_interrupts;
28 #ifdef CONFIG_PPC_MERGE
30 /* This number is used when no interrupt has been assigned */
33 /* This is a special irq number to return from get_irq() to tell that
34 * no interrupt happened _and_ ignore it (don't count it as bad). Some
35 * platforms like iSeries rely on that.
37 #define NO_IRQ_IGNORE ((unsigned int)-1)
39 /* Total number of virq in the platform (make it a CONFIG_* option ? */
42 /* Number of irqs reserved for the legacy controller */
43 #define NUM_ISA_INTERRUPTS 16
45 /* This type is the placeholder for a hardware interrupt number. It has to
46 * be big enough to enclose whatever representation is used by a given
49 typedef unsigned long irq_hw_number_t;
51 /* Interrupt controller "host" data structure. This could be defined as a
52 * irq domain controller. That is, it handles the mapping between hardware
53 * and virtual interrupt numbers for a given interrupt domain. The host
54 * structure is generally created by the PIC code for a given PIC instance
55 * (though a host can cover more than one PIC if they have a flat number
56 * model). It's the host callbacks that are responsible for setting the
57 * irq_chip on a given irq_desc after it's been mapped.
59 * The host code and data structures are fairly agnostic to the fact that
60 * we use an open firmware device-tree. We do have references to struct
61 * device_node in two places: in irq_find_host() to find the host matching
62 * a given interrupt controller node, and of course as an argument to its
63 * counterpart host->ops->match() callback. However, those are treated as
64 * generic pointers by the core and the fact that it's actually a device-node
65 * pointer is purely a convention between callers and implementation. This
66 * code could thus be used on other architectures by replacing those two
67 * by some sort of arch-specific void * "token" used to identify interrupt
71 struct radix_tree_root;
73 /* Functions below are provided by the host and called whenever a new mapping
74 * is created or an old mapping is disposed. The host can then proceed to
75 * whatever internal data structures management is required. It also needs
76 * to setup the irq_desc when returning from map().
79 /* Match an interrupt controller device node to a host, returns
82 int (*match)(struct irq_host *h, struct device_node *node);
84 /* Create or update a mapping between a virtual irq number and a hw
85 * irq number. This is called only once for a given mapping.
87 int (*map)(struct irq_host *h, unsigned int virq, irq_hw_number_t hw);
89 /* Dispose of such a mapping */
90 void (*unmap)(struct irq_host *h, unsigned int virq);
92 /* Update of such a mapping */
93 void (*remap)(struct irq_host *h, unsigned int virq, irq_hw_number_t hw);
95 /* Translate device-tree interrupt specifier from raw format coming
96 * from the firmware to a irq_hw_number_t (interrupt line number) and
97 * type (sense) that can be passed to set_irq_type(). In the absence
98 * of this callback, irq_create_of_mapping() and irq_of_parse_and_map()
99 * will return the hw number in the first cell and IRQ_TYPE_NONE for
100 * the type (which amount to keeping whatever default value the
101 * interrupt controller has for that line)
103 int (*xlate)(struct irq_host *h, struct device_node *ctrler,
104 u32 *intspec, unsigned int intsize,
105 irq_hw_number_t *out_hwirq, unsigned int *out_type);
109 struct list_head link;
111 /* type of reverse mapping technique */
112 unsigned int revmap_type;
113 #define IRQ_HOST_MAP_LEGACY 0 /* legacy 8259, gets irqs 1..15 */
114 #define IRQ_HOST_MAP_NOMAP 1 /* no fast reverse mapping */
115 #define IRQ_HOST_MAP_LINEAR 2 /* linear map of interrupts */
116 #define IRQ_HOST_MAP_TREE 3 /* radix tree */
120 unsigned int *revmap;
122 struct radix_tree_root tree;
124 struct irq_host_ops *ops;
126 irq_hw_number_t inval_irq;
128 /* Optional device node pointer */
129 struct device_node *of_node;
132 /* The main irq map itself is an array of NR_IRQ entries containing the
133 * associate host and irq number. An entry with a host of NULL is free.
134 * An entry can be allocated if it's free, the allocator always then sets
135 * hwirq first to the host's invalid irq number and then fills ops.
137 struct irq_map_entry {
138 irq_hw_number_t hwirq;
139 struct irq_host *host;
142 extern struct irq_map_entry irq_map[NR_IRQS];
144 extern irq_hw_number_t virq_to_hw(unsigned int virq);
147 * irq_alloc_host - Allocate a new irq_host data structure
148 * @of_node: optional device-tree node of the interrupt controller
149 * @revmap_type: type of reverse mapping to use
150 * @revmap_arg: for IRQ_HOST_MAP_LINEAR linear only: size of the map
151 * @ops: map/unmap host callbacks
152 * @inval_irq: provide a hw number in that host space that is always invalid
154 * Allocates and initialize and irq_host structure. Note that in the case of
155 * IRQ_HOST_MAP_LEGACY, the map() callback will be called before this returns
156 * for all legacy interrupts except 0 (which is always the invalid irq for
157 * a legacy controller). For a IRQ_HOST_MAP_LINEAR, the map is allocated by
158 * this call as well. For a IRQ_HOST_MAP_TREE, the radix tree will be allocated
159 * later during boot automatically (the reverse mapping will use the slow path
160 * until that happens).
162 extern struct irq_host *irq_alloc_host(struct device_node *of_node,
163 unsigned int revmap_type,
164 unsigned int revmap_arg,
165 struct irq_host_ops *ops,
166 irq_hw_number_t inval_irq);
170 * irq_find_host - Locates a host for a given device node
171 * @node: device-tree node of the interrupt controller
173 extern struct irq_host *irq_find_host(struct device_node *node);
177 * irq_set_default_host - Set a "default" host
178 * @host: default host pointer
180 * For convenience, it's possible to set a "default" host that will be used
181 * whenever NULL is passed to irq_create_mapping(). It makes life easier for
182 * platforms that want to manipulate a few hard coded interrupt numbers that
183 * aren't properly represented in the device-tree.
185 extern void irq_set_default_host(struct irq_host *host);
189 * irq_set_virq_count - Set the maximum number of virt irqs
190 * @count: number of linux virtual irqs, capped with NR_IRQS
192 * This is mainly for use by platforms like iSeries who want to program
193 * the virtual irq number in the controller to avoid the reverse mapping
195 extern void irq_set_virq_count(unsigned int count);
199 * irq_create_mapping - Map a hardware interrupt into linux virq space
200 * @host: host owning this hardware interrupt or NULL for default host
201 * @hwirq: hardware irq number in that host space
203 * Only one mapping per hardware interrupt is permitted. Returns a linux
205 * If the sense/trigger is to be specified, set_irq_type() should be called
206 * on the number returned from that call.
208 extern unsigned int irq_create_mapping(struct irq_host *host,
209 irq_hw_number_t hwirq);
213 * irq_dispose_mapping - Unmap an interrupt
214 * @virq: linux virq number of the interrupt to unmap
216 extern void irq_dispose_mapping(unsigned int virq);
219 * irq_find_mapping - Find a linux virq from an hw irq number.
220 * @host: host owning this hardware interrupt
221 * @hwirq: hardware irq number in that host space
223 * This is a slow path, for use by generic code. It's expected that an
224 * irq controller implementation directly calls the appropriate low level
227 extern unsigned int irq_find_mapping(struct irq_host *host,
228 irq_hw_number_t hwirq);
231 * irq_create_direct_mapping - Allocate a virq for direct mapping
232 * @host: host to allocate the virq for or NULL for default host
234 * This routine is used for irq controllers which can choose the hardware
235 * interrupt numbers they generate. In such a case it's simplest to use
236 * the linux virq as the hardware interrupt number.
238 extern unsigned int irq_create_direct_mapping(struct irq_host *host);
241 * irq_radix_revmap - Find a linux virq from a hw irq number.
242 * @host: host owning this hardware interrupt
243 * @hwirq: hardware irq number in that host space
245 * This is a fast path, for use by irq controller code that uses radix tree
248 extern unsigned int irq_radix_revmap(struct irq_host *host,
249 irq_hw_number_t hwirq);
252 * irq_linear_revmap - Find a linux virq from a hw irq number.
253 * @host: host owning this hardware interrupt
254 * @hwirq: hardware irq number in that host space
256 * This is a fast path, for use by irq controller code that uses linear
257 * revmaps. It does fallback to the slow path if the revmap doesn't exist
258 * yet and will create the revmap entry with appropriate locking
261 extern unsigned int irq_linear_revmap(struct irq_host *host,
262 irq_hw_number_t hwirq);
267 * irq_alloc_virt - Allocate virtual irq numbers
268 * @host: host owning these new virtual irqs
269 * @count: number of consecutive numbers to allocate
270 * @hint: pass a hint number, the allocator will try to use a 1:1 mapping
272 * This is a low level function that is used internally by irq_create_mapping()
273 * and that can be used by some irq controllers implementations for things
274 * like allocating ranges of numbers for MSIs. The revmaps are left untouched.
276 extern unsigned int irq_alloc_virt(struct irq_host *host,
281 * irq_free_virt - Free virtual irq numbers
282 * @virq: virtual irq number of the first interrupt to free
283 * @count: number of interrupts to free
285 * This function is the opposite of irq_alloc_virt. It will not clear reverse
286 * maps, this should be done previously by unmap'ing the interrupt. In fact,
287 * all interrupts covered by the range being freed should have been unmapped
288 * prior to calling this.
290 extern void irq_free_virt(unsigned int virq, unsigned int count);
293 /* -- OF helpers -- */
295 /* irq_create_of_mapping - Map a hardware interrupt into linux virq space
296 * @controller: Device node of the interrupt controller
297 * @inspec: Interrupt specifier from the device-tree
298 * @intsize: Size of the interrupt specifier from the device-tree
300 * This function is identical to irq_create_mapping except that it takes
301 * as input informations straight from the device-tree (typically the results
302 * of the of_irq_map_*() functions.
304 extern unsigned int irq_create_of_mapping(struct device_node *controller,
305 u32 *intspec, unsigned int intsize);
308 /* irq_of_parse_and_map - Parse nad Map an interrupt into linux virq space
309 * @device: Device node of the device whose interrupt is to be mapped
310 * @index: Index of the interrupt to map
312 * This function is a wrapper that chains of_irq_map_one() and
313 * irq_create_of_mapping() to make things easier to callers
315 extern unsigned int irq_of_parse_and_map(struct device_node *dev, int index);
317 /* -- End OF helpers -- */
320 * irq_early_init - Init irq remapping subsystem
322 extern void irq_early_init(void);
324 static __inline__ int irq_canonicalize(int irq)
330 #else /* CONFIG_PPC_MERGE */
332 /* This number is used when no interrupt has been assigned */
334 #define NO_IRQ_IGNORE (-2)
338 * These constants are used for passing information about interrupt
339 * signal polarity and level/edge sensing to the low-level PIC chip
342 #define IRQ_SENSE_MASK 0x1
343 #define IRQ_SENSE_LEVEL 0x1 /* interrupt on active level */
344 #define IRQ_SENSE_EDGE 0x0 /* interrupt triggered by edge */
346 #define IRQ_POLARITY_MASK 0x2
347 #define IRQ_POLARITY_POSITIVE 0x2 /* high level or low->high edge */
348 #define IRQ_POLARITY_NEGATIVE 0x0 /* low level or high->low edge */
351 #if defined(CONFIG_40x)
352 #include <asm/ibm4xx.h>
354 #ifndef NR_BOARD_IRQS
355 #define NR_BOARD_IRQS 0
358 #ifndef UIC_WIDTH /* Number of interrupts per device */
362 #ifndef NR_UICS /* number of UIC devices */
366 #if defined (CONFIG_403)
368 * The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has
369 * 32 possible interrupts, a majority of which are not implemented on
370 * all cores. There are six configurable, external interrupt pins and
371 * there are eight internal interrupts for the on-chip serial port
372 * (SPU), DMA controller, and JTAG controller.
376 #define NR_AIC_IRQS 32
377 #define NR_IRQS (NR_AIC_IRQS + NR_BOARD_IRQS)
379 #elif !defined (CONFIG_403)
382 * The PowerPC 405 cores' Universal Interrupt Controller (UIC) has 32
383 * possible interrupts as well. There are seven, configurable external
384 * interrupt pins and there are 17 internal interrupts for the on-chip
385 * serial port, DMA controller, on-chip Ethernet controller, PCI, etc.
390 #define NR_UIC_IRQS UIC_WIDTH
391 #define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
394 #elif defined(CONFIG_44x)
395 #include <asm/ibm44x.h>
397 #define NR_UIC_IRQS 32
398 #define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
400 #elif defined(CONFIG_8xx)
402 /* Now include the board configuration specific associations.
404 #include <asm/mpc8xx.h>
406 /* The MPC8xx cores have 16 possible interrupts. There are eight
407 * possible level sensitive interrupts assigned and generated internally
408 * from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer.
409 * There are eight external interrupts (IRQs) that can be configured
410 * as either level or edge sensitive.
412 * On some implementations, there is also the possibility of an 8259
413 * through the PCI and PCI-ISA bridges.
415 * We are "flattening" the interrupt vectors of the cascaded CPM
416 * and 8259 interrupt controllers so that we can uniquely identify
417 * any interrupt source with a single integer.
419 #define NR_SIU_INTS 16
420 #define NR_CPM_INTS 32
422 #define NR_8259_INTS 0
425 #define SIU_IRQ_OFFSET 0
426 #define CPM_IRQ_OFFSET (SIU_IRQ_OFFSET + NR_SIU_INTS)
427 #define I8259_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS)
429 #define NR_IRQS (NR_SIU_INTS + NR_CPM_INTS + NR_8259_INTS)
431 /* These values must be zero-based and map 1:1 with the SIU configuration.
432 * They are used throughout the 8xx I/O subsystem to generate
433 * interrupt masks, flags, and other control patterns. This is why the
434 * current kernel assumption of the 8259 as the base controller is such
435 * a pain in the butt.
437 #define SIU_IRQ0 (0) /* Highest priority */
438 #define SIU_LEVEL0 (1)
440 #define SIU_LEVEL1 (3)
442 #define SIU_LEVEL2 (5)
444 #define SIU_LEVEL3 (7)
446 #define SIU_LEVEL4 (9)
447 #define SIU_IRQ5 (10)
448 #define SIU_LEVEL5 (11)
449 #define SIU_IRQ6 (12)
450 #define SIU_LEVEL6 (13)
451 #define SIU_IRQ7 (14)
452 #define SIU_LEVEL7 (15)
454 #define MPC8xx_INT_FEC1 SIU_LEVEL1
455 #define MPC8xx_INT_FEC2 SIU_LEVEL3
457 #define MPC8xx_INT_SCC1 (CPM_IRQ_OFFSET + CPMVEC_SCC1)
458 #define MPC8xx_INT_SCC2 (CPM_IRQ_OFFSET + CPMVEC_SCC2)
459 #define MPC8xx_INT_SCC3 (CPM_IRQ_OFFSET + CPMVEC_SCC3)
460 #define MPC8xx_INT_SCC4 (CPM_IRQ_OFFSET + CPMVEC_SCC4)
461 #define MPC8xx_INT_SMC1 (CPM_IRQ_OFFSET + CPMVEC_SMC1)
462 #define MPC8xx_INT_SMC2 (CPM_IRQ_OFFSET + CPMVEC_SMC2)
464 /* The internal interrupts we can configure as we see fit.
465 * My personal preference is CPM at level 2, which puts it above the
466 * MBX PCI/ISA/IDE interrupts.
468 #ifndef PIT_INTERRUPT
469 #define PIT_INTERRUPT SIU_LEVEL0
471 #ifndef CPM_INTERRUPT
472 #define CPM_INTERRUPT SIU_LEVEL2
474 #ifndef PCMCIA_INTERRUPT
475 #define PCMCIA_INTERRUPT SIU_LEVEL6
477 #ifndef DEC_INTERRUPT
478 #define DEC_INTERRUPT SIU_LEVEL7
481 /* Some internal interrupt registers use an 8-bit mask for the interrupt
482 * level instead of a number.
484 #define mk_int_int_mask(IL) (1 << (7 - (IL/2)))
486 #elif defined(CONFIG_PPC_86xx)
487 #include <asm/mpc86xx.h>
489 #define NR_EPIC_INTS 48
491 #define NR_8259_INTS 16 /*ULI 1575 can route 12 interrupts */
493 #define NUM_8259_INTERRUPTS NR_8259_INTS
496 #define I8259_OFFSET 0
501 /* Internal IRQs on MPC86xx OpenPIC */
503 #ifndef MPC86xx_OPENPIC_IRQ_OFFSET
504 #define MPC86xx_OPENPIC_IRQ_OFFSET NR_8259_INTS
507 /* The 48 internal sources */
508 #define MPC86xx_IRQ_NULL ( 0 + MPC86xx_OPENPIC_IRQ_OFFSET)
509 #define MPC86xx_IRQ_MCM ( 1 + MPC86xx_OPENPIC_IRQ_OFFSET)
510 #define MPC86xx_IRQ_DDR ( 2 + MPC86xx_OPENPIC_IRQ_OFFSET)
511 #define MPC86xx_IRQ_LBC ( 3 + MPC86xx_OPENPIC_IRQ_OFFSET)
512 #define MPC86xx_IRQ_DMA0 ( 4 + MPC86xx_OPENPIC_IRQ_OFFSET)
513 #define MPC86xx_IRQ_DMA1 ( 5 + MPC86xx_OPENPIC_IRQ_OFFSET)
514 #define MPC86xx_IRQ_DMA2 ( 6 + MPC86xx_OPENPIC_IRQ_OFFSET)
515 #define MPC86xx_IRQ_DMA3 ( 7 + MPC86xx_OPENPIC_IRQ_OFFSET)
518 #define MPC86xx_IRQ_UART2 (12 + MPC86xx_OPENPIC_IRQ_OFFSET)
519 #define MPC86xx_IRQ_TSEC1_TX (13 + MPC86xx_OPENPIC_IRQ_OFFSET)
520 #define MPC86xx_IRQ_TSEC1_RX (14 + MPC86xx_OPENPIC_IRQ_OFFSET)
521 #define MPC86xx_IRQ_TSEC3_TX (15 + MPC86xx_OPENPIC_IRQ_OFFSET)
522 #define MPC86xx_IRQ_TSEC3_RX (16 + MPC86xx_OPENPIC_IRQ_OFFSET)
523 #define MPC86xx_IRQ_TSEC3_ERROR (17 + MPC86xx_OPENPIC_IRQ_OFFSET)
524 #define MPC86xx_IRQ_TSEC1_ERROR (18 + MPC86xx_OPENPIC_IRQ_OFFSET)
525 #define MPC86xx_IRQ_TSEC2_TX (19 + MPC86xx_OPENPIC_IRQ_OFFSET)
526 #define MPC86xx_IRQ_TSEC2_RX (20 + MPC86xx_OPENPIC_IRQ_OFFSET)
527 #define MPC86xx_IRQ_TSEC4_TX (21 + MPC86xx_OPENPIC_IRQ_OFFSET)
528 #define MPC86xx_IRQ_TSEC4_RX (22 + MPC86xx_OPENPIC_IRQ_OFFSET)
529 #define MPC86xx_IRQ_TSEC4_ERROR (23 + MPC86xx_OPENPIC_IRQ_OFFSET)
530 #define MPC86xx_IRQ_TSEC2_ERROR (24 + MPC86xx_OPENPIC_IRQ_OFFSET)
532 #define MPC86xx_IRQ_UART1 (26 + MPC86xx_OPENPIC_IRQ_OFFSET)
533 #define MPC86xx_IRQ_IIC (27 + MPC86xx_OPENPIC_IRQ_OFFSET)
534 #define MPC86xx_IRQ_PERFMON (28 + MPC86xx_OPENPIC_IRQ_OFFSET)
536 #define MPC86xx_IRQ_SRIO_ERROR (32 + MPC86xx_OPENPIC_IRQ_OFFSET)
537 #define MPC86xx_IRQ_SRIO_OUT_BELL (33 + MPC86xx_OPENPIC_IRQ_OFFSET)
538 #define MPC86xx_IRQ_SRIO_IN_BELL (34 + MPC86xx_OPENPIC_IRQ_OFFSET)
540 #define MPC86xx_IRQ_SRIO_OUT_MSG1 (37 + MPC86xx_OPENPIC_IRQ_OFFSET)
541 #define MPC86xx_IRQ_SRIO_IN_MSG1 (38 + MPC86xx_OPENPIC_IRQ_OFFSET)
542 #define MPC86xx_IRQ_SRIO_OUT_MSG2 (39 + MPC86xx_OPENPIC_IRQ_OFFSET)
543 #define MPC86xx_IRQ_SRIO_IN_MSG2 (40 + MPC86xx_OPENPIC_IRQ_OFFSET)
545 /* The 12 external interrupt lines */
546 #define MPC86xx_IRQ_EXT_BASE 48
547 #define MPC86xx_IRQ_EXT0 (0 + MPC86xx_IRQ_EXT_BASE \
548 + MPC86xx_OPENPIC_IRQ_OFFSET)
549 #define MPC86xx_IRQ_EXT1 (1 + MPC86xx_IRQ_EXT_BASE \
550 + MPC86xx_OPENPIC_IRQ_OFFSET)
551 #define MPC86xx_IRQ_EXT2 (2 + MPC86xx_IRQ_EXT_BASE \
552 + MPC86xx_OPENPIC_IRQ_OFFSET)
553 #define MPC86xx_IRQ_EXT3 (3 + MPC86xx_IRQ_EXT_BASE \
554 + MPC86xx_OPENPIC_IRQ_OFFSET)
555 #define MPC86xx_IRQ_EXT4 (4 + MPC86xx_IRQ_EXT_BASE \
556 + MPC86xx_OPENPIC_IRQ_OFFSET)
557 #define MPC86xx_IRQ_EXT5 (5 + MPC86xx_IRQ_EXT_BASE \
558 + MPC86xx_OPENPIC_IRQ_OFFSET)
559 #define MPC86xx_IRQ_EXT6 (6 + MPC86xx_IRQ_EXT_BASE \
560 + MPC86xx_OPENPIC_IRQ_OFFSET)
561 #define MPC86xx_IRQ_EXT7 (7 + MPC86xx_IRQ_EXT_BASE \
562 + MPC86xx_OPENPIC_IRQ_OFFSET)
563 #define MPC86xx_IRQ_EXT8 (8 + MPC86xx_IRQ_EXT_BASE \
564 + MPC86xx_OPENPIC_IRQ_OFFSET)
565 #define MPC86xx_IRQ_EXT9 (9 + MPC86xx_IRQ_EXT_BASE \
566 + MPC86xx_OPENPIC_IRQ_OFFSET)
567 #define MPC86xx_IRQ_EXT10 (10 + MPC86xx_IRQ_EXT_BASE \
568 + MPC86xx_OPENPIC_IRQ_OFFSET)
569 #define MPC86xx_IRQ_EXT11 (11 + MPC86xx_IRQ_EXT_BASE \
570 + MPC86xx_OPENPIC_IRQ_OFFSET)
572 #else /* CONFIG_40x + CONFIG_8xx */
574 * this is the # irq's for all ppc arch's (pmac/chrp/prep)
575 * so it is the max of them all
578 #define __DO_IRQ_CANON 1
582 #define NUM_8259_INTERRUPTS 16
584 #else /* CONFIG_8260 */
586 /* The 8260 has an internal interrupt controller with a maximum of
587 * 64 IRQs. We will use NR_IRQs from above since it is large enough.
588 * Don't be confused by the 8260 documentation where they list an
589 * "interrupt number" and "interrupt vector". We are only interested
590 * in the interrupt vector. There are "reserved" holes where the
591 * vector number increases, but the interrupt number in the table does not.
592 * (Document errata updates have fixed this...make sure you have up to
593 * date processor documentation -- Dan).
596 #ifndef CPM_IRQ_OFFSET
597 #define CPM_IRQ_OFFSET 0
600 #define NR_CPM_INTS 64
602 #define SIU_INT_ERROR ((uint)0x00 + CPM_IRQ_OFFSET)
603 #define SIU_INT_I2C ((uint)0x01 + CPM_IRQ_OFFSET)
604 #define SIU_INT_SPI ((uint)0x02 + CPM_IRQ_OFFSET)
605 #define SIU_INT_RISC ((uint)0x03 + CPM_IRQ_OFFSET)
606 #define SIU_INT_SMC1 ((uint)0x04 + CPM_IRQ_OFFSET)
607 #define SIU_INT_SMC2 ((uint)0x05 + CPM_IRQ_OFFSET)
608 #define SIU_INT_IDMA1 ((uint)0x06 + CPM_IRQ_OFFSET)
609 #define SIU_INT_IDMA2 ((uint)0x07 + CPM_IRQ_OFFSET)
610 #define SIU_INT_IDMA3 ((uint)0x08 + CPM_IRQ_OFFSET)
611 #define SIU_INT_IDMA4 ((uint)0x09 + CPM_IRQ_OFFSET)
612 #define SIU_INT_SDMA ((uint)0x0a + CPM_IRQ_OFFSET)
613 #define SIU_INT_USB ((uint)0x0b + CPM_IRQ_OFFSET)
614 #define SIU_INT_TIMER1 ((uint)0x0c + CPM_IRQ_OFFSET)
615 #define SIU_INT_TIMER2 ((uint)0x0d + CPM_IRQ_OFFSET)
616 #define SIU_INT_TIMER3 ((uint)0x0e + CPM_IRQ_OFFSET)
617 #define SIU_INT_TIMER4 ((uint)0x0f + CPM_IRQ_OFFSET)
618 #define SIU_INT_TMCNT ((uint)0x10 + CPM_IRQ_OFFSET)
619 #define SIU_INT_PIT ((uint)0x11 + CPM_IRQ_OFFSET)
620 #define SIU_INT_PCI ((uint)0x12 + CPM_IRQ_OFFSET)
621 #define SIU_INT_IRQ1 ((uint)0x13 + CPM_IRQ_OFFSET)
622 #define SIU_INT_IRQ2 ((uint)0x14 + CPM_IRQ_OFFSET)
623 #define SIU_INT_IRQ3 ((uint)0x15 + CPM_IRQ_OFFSET)
624 #define SIU_INT_IRQ4 ((uint)0x16 + CPM_IRQ_OFFSET)
625 #define SIU_INT_IRQ5 ((uint)0x17 + CPM_IRQ_OFFSET)
626 #define SIU_INT_IRQ6 ((uint)0x18 + CPM_IRQ_OFFSET)
627 #define SIU_INT_IRQ7 ((uint)0x19 + CPM_IRQ_OFFSET)
628 #define SIU_INT_FCC1 ((uint)0x20 + CPM_IRQ_OFFSET)
629 #define SIU_INT_FCC2 ((uint)0x21 + CPM_IRQ_OFFSET)
630 #define SIU_INT_FCC3 ((uint)0x22 + CPM_IRQ_OFFSET)
631 #define SIU_INT_MCC1 ((uint)0x24 + CPM_IRQ_OFFSET)
632 #define SIU_INT_MCC2 ((uint)0x25 + CPM_IRQ_OFFSET)
633 #define SIU_INT_SCC1 ((uint)0x28 + CPM_IRQ_OFFSET)
634 #define SIU_INT_SCC2 ((uint)0x29 + CPM_IRQ_OFFSET)
635 #define SIU_INT_SCC3 ((uint)0x2a + CPM_IRQ_OFFSET)
636 #define SIU_INT_SCC4 ((uint)0x2b + CPM_IRQ_OFFSET)
637 #define SIU_INT_PC15 ((uint)0x30 + CPM_IRQ_OFFSET)
638 #define SIU_INT_PC14 ((uint)0x31 + CPM_IRQ_OFFSET)
639 #define SIU_INT_PC13 ((uint)0x32 + CPM_IRQ_OFFSET)
640 #define SIU_INT_PC12 ((uint)0x33 + CPM_IRQ_OFFSET)
641 #define SIU_INT_PC11 ((uint)0x34 + CPM_IRQ_OFFSET)
642 #define SIU_INT_PC10 ((uint)0x35 + CPM_IRQ_OFFSET)
643 #define SIU_INT_PC9 ((uint)0x36 + CPM_IRQ_OFFSET)
644 #define SIU_INT_PC8 ((uint)0x37 + CPM_IRQ_OFFSET)
645 #define SIU_INT_PC7 ((uint)0x38 + CPM_IRQ_OFFSET)
646 #define SIU_INT_PC6 ((uint)0x39 + CPM_IRQ_OFFSET)
647 #define SIU_INT_PC5 ((uint)0x3a + CPM_IRQ_OFFSET)
648 #define SIU_INT_PC4 ((uint)0x3b + CPM_IRQ_OFFSET)
649 #define SIU_INT_PC3 ((uint)0x3c + CPM_IRQ_OFFSET)
650 #define SIU_INT_PC2 ((uint)0x3d + CPM_IRQ_OFFSET)
651 #define SIU_INT_PC1 ((uint)0x3e + CPM_IRQ_OFFSET)
652 #define SIU_INT_PC0 ((uint)0x3f + CPM_IRQ_OFFSET)
654 #endif /* CONFIG_8260 */
656 #endif /* Whatever way too big #ifdef */
658 #define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
659 /* pedantic: these are long because they are used with set_bit --RR */
660 extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
663 * Because many systems have two overlapping names spaces for
664 * interrupts (ISA and XICS for example), and the ISA interrupts
665 * have historically not been easy to renumber, we allow ISA
666 * interrupts to take values 0 - 15, and shift up the remaining
667 * interrupts by 0x10.
669 #define NUM_ISA_INTERRUPTS 0x10
670 extern int __irq_offset_value;
672 static inline int irq_offset_up(int irq)
674 return(irq + __irq_offset_value);
677 static inline int irq_offset_down(int irq)
679 return(irq - __irq_offset_value);
682 static inline int irq_offset_value(void)
684 return __irq_offset_value;
687 #ifdef __DO_IRQ_CANON
688 extern int ppc_do_canonicalize_irqs;
690 #define ppc_do_canonicalize_irqs 0
693 static __inline__ int irq_canonicalize(int irq)
695 if (ppc_do_canonicalize_irqs && irq == 2)
699 #endif /* CONFIG_PPC_MERGE */
701 extern int distribute_irqs;
706 #define __ARCH_HAS_DO_SOFTIRQ
708 extern void __do_softirq(void);
710 #ifdef CONFIG_IRQSTACKS
712 * Per-cpu stacks for handling hard and soft interrupts.
714 extern struct thread_info *hardirq_ctx[NR_CPUS];
715 extern struct thread_info *softirq_ctx[NR_CPUS];
717 extern void irq_ctx_init(void);
718 extern void call_do_softirq(struct thread_info *tp);
719 extern int call_handle_irq(int irq, void *p1,
720 struct thread_info *tp, void *func);
722 #define irq_ctx_init()
724 #endif /* CONFIG_IRQSTACKS */
726 extern void do_IRQ(struct pt_regs *regs);
728 #endif /* _ASM_IRQ_H */
729 #endif /* __KERNEL__ */