git.oblomov.eu Git - linux-2.6/blob - drivers/infiniband/hw/mthca/mthca_qp.c

   1 /*
   2  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Cisco Systems. All rights reserved.
   4  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  *
  35  * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
  36  */
  37
  38 #include <linux/init.h>
  39 #include <linux/string.h>
  40 #include <linux/slab.h>
  41
  42 #include <rdma/ib_verbs.h>
  43 #include <rdma/ib_cache.h>
  44 #include <rdma/ib_pack.h>
  45
  46 #include "mthca_dev.h"
  47 #include "mthca_cmd.h"
  48 #include "mthca_memfree.h"
  49 #include "mthca_wqe.h"
  50
  51 enum {
  52         MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
  53         MTHCA_ACK_REQ_FREQ       = 10,
  54         MTHCA_FLIGHT_LIMIT       = 9,
  55         MTHCA_UD_HEADER_SIZE     = 72, /* largest UD header possible */
  56         MTHCA_INLINE_HEADER_SIZE = 4,  /* data segment overhead for inline */
  57         MTHCA_INLINE_CHUNK_SIZE  = 16  /* inline data segment chunk */
  58 };
  59
  60 enum {
  61         MTHCA_QP_STATE_RST  = 0,
  62         MTHCA_QP_STATE_INIT = 1,
  63         MTHCA_QP_STATE_RTR  = 2,
  64         MTHCA_QP_STATE_RTS  = 3,
  65         MTHCA_QP_STATE_SQE  = 4,
  66         MTHCA_QP_STATE_SQD  = 5,
  67         MTHCA_QP_STATE_ERR  = 6,
  68         MTHCA_QP_STATE_DRAINING = 7
  69 };
  70
  71 enum {
  72         MTHCA_QP_ST_RC  = 0x0,
  73         MTHCA_QP_ST_UC  = 0x1,
  74         MTHCA_QP_ST_RD  = 0x2,
  75         MTHCA_QP_ST_UD  = 0x3,
  76         MTHCA_QP_ST_MLX = 0x7
  77 };
  78
  79 enum {
  80         MTHCA_QP_PM_MIGRATED = 0x3,
  81         MTHCA_QP_PM_ARMED    = 0x0,
  82         MTHCA_QP_PM_REARM    = 0x1
  83 };
  84
  85 enum {
  86         /* qp_context flags */
  87         MTHCA_QP_BIT_DE  = 1 <<  8,
  88         /* params1 */
  89         MTHCA_QP_BIT_SRE = 1 << 15,
  90         MTHCA_QP_BIT_SWE = 1 << 14,
  91         MTHCA_QP_BIT_SAE = 1 << 13,
  92         MTHCA_QP_BIT_SIC = 1 <<  4,
  93         MTHCA_QP_BIT_SSC = 1 <<  3,
  94         /* params2 */
  95         MTHCA_QP_BIT_RRE = 1 << 15,
  96         MTHCA_QP_BIT_RWE = 1 << 14,
  97         MTHCA_QP_BIT_RAE = 1 << 13,
  98         MTHCA_QP_BIT_RIC = 1 <<  4,
  99         MTHCA_QP_BIT_RSC = 1 <<  3
 100 };
 101
 102 struct mthca_qp_path {
 103         __be32 port_pkey;
 104         u8     rnr_retry;
 105         u8     g_mylmc;
 106         __be16 rlid;
 107         u8     ackto;
 108         u8     mgid_index;
 109         u8     static_rate;
 110         u8     hop_limit;
 111         __be32 sl_tclass_flowlabel;
 112         u8     rgid[16];
 113 } __attribute__((packed));
 114
 115 struct mthca_qp_context {
 116         __be32 flags;
 117         __be32 tavor_sched_queue; /* Reserved on Arbel */
 118         u8     mtu_msgmax;
 119         u8     rq_size_stride;  /* Reserved on Tavor */
 120         u8     sq_size_stride;  /* Reserved on Tavor */
 121         u8     rlkey_arbel_sched_queue; /* Reserved on Tavor */
 122         __be32 usr_page;
 123         __be32 local_qpn;
 124         __be32 remote_qpn;
 125         u32    reserved1[2];
 126         struct mthca_qp_path pri_path;
 127         struct mthca_qp_path alt_path;
 128         __be32 rdd;
 129         __be32 pd;
 130         __be32 wqe_base;
 131         __be32 wqe_lkey;
 132         __be32 params1;
 133         __be32 reserved2;
 134         __be32 next_send_psn;
 135         __be32 cqn_snd;
 136         __be32 snd_wqe_base_l;  /* Next send WQE on Tavor */
 137         __be32 snd_db_index;    /* (debugging only entries) */
 138         __be32 last_acked_psn;
 139         __be32 ssn;
 140         __be32 params2;
 141         __be32 rnr_nextrecvpsn;
 142         __be32 ra_buff_indx;
 143         __be32 cqn_rcv;
 144         __be32 rcv_wqe_base_l;  /* Next recv WQE on Tavor */
 145         __be32 rcv_db_index;    /* (debugging only entries) */
 146         __be32 qkey;
 147         __be32 srqn;
 148         __be32 rmsn;
 149         __be16 rq_wqe_counter;  /* reserved on Tavor */
 150         __be16 sq_wqe_counter;  /* reserved on Tavor */
 151         u32    reserved3[18];
 152 } __attribute__((packed));
 153
 154 struct mthca_qp_param {
 155         __be32 opt_param_mask;
 156         u32    reserved1;
 157         struct mthca_qp_context context;
 158         u32    reserved2[62];
 159 } __attribute__((packed));
 160
 161 enum {
 162         MTHCA_QP_OPTPAR_ALT_ADDR_PATH     = 1 << 0,
 163         MTHCA_QP_OPTPAR_RRE               = 1 << 1,
 164         MTHCA_QP_OPTPAR_RAE               = 1 << 2,
 165         MTHCA_QP_OPTPAR_RWE               = 1 << 3,
 166         MTHCA_QP_OPTPAR_PKEY_INDEX        = 1 << 4,
 167         MTHCA_QP_OPTPAR_Q_KEY             = 1 << 5,
 168         MTHCA_QP_OPTPAR_RNR_TIMEOUT       = 1 << 6,
 169         MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
 170         MTHCA_QP_OPTPAR_SRA_MAX           = 1 << 8,
 171         MTHCA_QP_OPTPAR_RRA_MAX           = 1 << 9,
 172         MTHCA_QP_OPTPAR_PM_STATE          = 1 << 10,
 173         MTHCA_QP_OPTPAR_PORT_NUM          = 1 << 11,
 174         MTHCA_QP_OPTPAR_RETRY_COUNT       = 1 << 12,
 175         MTHCA_QP_OPTPAR_ALT_RNR_RETRY     = 1 << 13,
 176         MTHCA_QP_OPTPAR_ACK_TIMEOUT       = 1 << 14,
 177         MTHCA_QP_OPTPAR_RNR_RETRY         = 1 << 15,
 178         MTHCA_QP_OPTPAR_SCHED_QUEUE       = 1 << 16
 179 };
 180
 181 static const u8 mthca_opcode[] = {
 182         [IB_WR_SEND]                 = MTHCA_OPCODE_SEND,
 183         [IB_WR_SEND_WITH_IMM]        = MTHCA_OPCODE_SEND_IMM,
 184         [IB_WR_RDMA_WRITE]           = MTHCA_OPCODE_RDMA_WRITE,
 185         [IB_WR_RDMA_WRITE_WITH_IMM]  = MTHCA_OPCODE_RDMA_WRITE_IMM,
 186         [IB_WR_RDMA_READ]            = MTHCA_OPCODE_RDMA_READ,
 187         [IB_WR_ATOMIC_CMP_AND_SWP]   = MTHCA_OPCODE_ATOMIC_CS,
 188         [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
 189 };
 190
 191 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
 192 {
 193         return qp->qpn >= dev->qp_table.sqp_start &&
 194                 qp->qpn <= dev->qp_table.sqp_start + 3;
 195 }
 196
 197 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
 198 {
 199         return qp->qpn >= dev->qp_table.sqp_start &&
 200                 qp->qpn <= dev->qp_table.sqp_start + 1;
 201 }
 202
 203 static void *get_recv_wqe(struct mthca_qp *qp, int n)
 204 {
 205         if (qp->is_direct)
 206                 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
 207         else
 208                 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
 209                         ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
 210 }
 211
 212 static void *get_send_wqe(struct mthca_qp *qp, int n)
 213 {
 214         if (qp->is_direct)
 215                 return qp->queue.direct.buf + qp->send_wqe_offset +
 216                         (n << qp->sq.wqe_shift);
 217         else
 218                 return qp->queue.page_list[(qp->send_wqe_offset +
 219                                             (n << qp->sq.wqe_shift)) >>
 220                                            PAGE_SHIFT].buf +
 221                         ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
 222                          (PAGE_SIZE - 1));
 223 }
 224
 225 static void mthca_wq_init(struct mthca_wq *wq)
 226 {
 227         spin_lock_init(&wq->lock);
 228         wq->next_ind  = 0;
 229         wq->last_comp = wq->max - 1;
 230         wq->head      = 0;
 231         wq->tail      = 0;
 232 }
 233
 234 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
 235                     enum ib_event_type event_type)
 236 {
 237         struct mthca_qp *qp;
 238         struct ib_event event;
 239
 240         spin_lock(&dev->qp_table.lock);
 241         qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
 242         if (qp)
 243                 atomic_inc(&qp->refcount);
 244         spin_unlock(&dev->qp_table.lock);
 245
 246         if (!qp) {
 247                 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn);
 248                 return;
 249         }
 250
 251         event.device      = &dev->ib_dev;
 252         event.event       = event_type;
 253         event.element.qp  = &qp->ibqp;
 254         if (qp->ibqp.event_handler)
 255                 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
 256
 257         if (atomic_dec_and_test(&qp->refcount))
 258                 wake_up(&qp->wait);
 259 }
 260
 261 static int to_mthca_state(enum ib_qp_state ib_state)
 262 {
 263         switch (ib_state) {
 264         case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
 265         case IB_QPS_INIT:  return MTHCA_QP_STATE_INIT;
 266         case IB_QPS_RTR:   return MTHCA_QP_STATE_RTR;
 267         case IB_QPS_RTS:   return MTHCA_QP_STATE_RTS;
 268         case IB_QPS_SQD:   return MTHCA_QP_STATE_SQD;
 269         case IB_QPS_SQE:   return MTHCA_QP_STATE_SQE;
 270         case IB_QPS_ERR:   return MTHCA_QP_STATE_ERR;
 271         default:                return -1;
 272         }
 273 }
 274
 275 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
 276
 277 static int to_mthca_st(int transport)
 278 {
 279         switch (transport) {
 280         case RC:  return MTHCA_QP_ST_RC;
 281         case UC:  return MTHCA_QP_ST_UC;
 282         case UD:  return MTHCA_QP_ST_UD;
 283         case RD:  return MTHCA_QP_ST_RD;
 284         case MLX: return MTHCA_QP_ST_MLX;
 285         default:  return -1;
 286         }
 287 }
 288
 289 static const struct {
 290         int trans;
 291         u32 req_param[NUM_TRANS];
 292         u32 opt_param[NUM_TRANS];
 293 } state_table[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = {
 294         [IB_QPS_RESET] = {
 295                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 296                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 297                 [IB_QPS_INIT]  = {
 298                         .trans = MTHCA_TRANS_RST2INIT,
 299                         .req_param = {
 300                                 [UD]  = (IB_QP_PKEY_INDEX |
 301                                          IB_QP_PORT       |
 302                                          IB_QP_QKEY),
 303                                 [UC]  = (IB_QP_PKEY_INDEX |
 304                                          IB_QP_PORT       |
 305                                          IB_QP_ACCESS_FLAGS),
 306                                 [RC]  = (IB_QP_PKEY_INDEX |
 307                                          IB_QP_PORT       |
 308                                          IB_QP_ACCESS_FLAGS),
 309                                 [MLX] = (IB_QP_PKEY_INDEX |
 310                                          IB_QP_QKEY),
 311                         },
 312                         /* bug-for-bug compatibility with VAPI: */
 313                         .opt_param = {
 314                                 [MLX] = IB_QP_PORT
 315                         }
 316                 },
 317         },
 318         [IB_QPS_INIT]  = {
 319                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 320                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 321                 [IB_QPS_INIT]  = {
 322                         .trans = MTHCA_TRANS_INIT2INIT,
 323                         .opt_param = {
 324                                 [UD]  = (IB_QP_PKEY_INDEX |
 325                                          IB_QP_PORT       |
 326                                          IB_QP_QKEY),
 327                                 [UC]  = (IB_QP_PKEY_INDEX |
 328                                          IB_QP_PORT       |
 329                                          IB_QP_ACCESS_FLAGS),
 330                                 [RC]  = (IB_QP_PKEY_INDEX |
 331                                          IB_QP_PORT       |
 332                                          IB_QP_ACCESS_FLAGS),
 333                                 [MLX] = (IB_QP_PKEY_INDEX |
 334                                          IB_QP_QKEY),
 335                         }
 336                 },
 337                 [IB_QPS_RTR]   = {
 338                         .trans = MTHCA_TRANS_INIT2RTR,
 339                         .req_param = {
 340                                 [UC]  = (IB_QP_AV                  |
 341                                          IB_QP_PATH_MTU            |
 342                                          IB_QP_DEST_QPN            |
 343                                          IB_QP_RQ_PSN),
 344                                 [RC]  = (IB_QP_AV                  |
 345                                          IB_QP_PATH_MTU            |
 346                                          IB_QP_DEST_QPN            |
 347                                          IB_QP_RQ_PSN              |
 348                                          IB_QP_MAX_DEST_RD_ATOMIC  |
 349                                          IB_QP_MIN_RNR_TIMER),
 350                         },
 351                         .opt_param = {
 352                                 [UD]  = (IB_QP_PKEY_INDEX |
 353                                          IB_QP_QKEY),
 354                                 [UC]  = (IB_QP_ALT_PATH     |
 355                                          IB_QP_ACCESS_FLAGS |
 356                                          IB_QP_PKEY_INDEX),
 357                                 [RC]  = (IB_QP_ALT_PATH     |
 358                                          IB_QP_ACCESS_FLAGS |
 359                                          IB_QP_PKEY_INDEX),
 360                                 [MLX] = (IB_QP_PKEY_INDEX |
 361                                          IB_QP_QKEY),
 362                         }
 363                 }
 364         },
 365         [IB_QPS_RTR]   = {
 366                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 367                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 368                 [IB_QPS_RTS]   = {
 369                         .trans = MTHCA_TRANS_RTR2RTS,
 370                         .req_param = {
 371                                 [UD]  = IB_QP_SQ_PSN,
 372                                 [UC]  = IB_QP_SQ_PSN,
 373                                 [RC]  = (IB_QP_TIMEOUT           |
 374                                          IB_QP_RETRY_CNT         |
 375                                          IB_QP_RNR_RETRY         |
 376                                          IB_QP_SQ_PSN            |
 377                                          IB_QP_MAX_QP_RD_ATOMIC),
 378                                 [MLX] = IB_QP_SQ_PSN,
 379                         },
 380                         .opt_param = {
 381                                 [UD]  = (IB_QP_CUR_STATE             |
 382                                          IB_QP_QKEY),
 383                                 [UC]  = (IB_QP_CUR_STATE             |
 384                                          IB_QP_ALT_PATH              |
 385                                          IB_QP_ACCESS_FLAGS          |
 386                                          IB_QP_PKEY_INDEX            |
 387                                          IB_QP_PATH_MIG_STATE),
 388                                 [RC]  = (IB_QP_CUR_STATE             |
 389                                          IB_QP_ALT_PATH              |
 390                                          IB_QP_ACCESS_FLAGS          |
 391                                          IB_QP_PKEY_INDEX            |
 392                                          IB_QP_MIN_RNR_TIMER         |
 393                                          IB_QP_PATH_MIG_STATE),
 394                                 [MLX] = (IB_QP_CUR_STATE             |
 395                                          IB_QP_QKEY),
 396                         }
 397                 }
 398         },
 399         [IB_QPS_RTS]   = {
 400                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 401                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 402                 [IB_QPS_RTS]   = {
 403                         .trans = MTHCA_TRANS_RTS2RTS,
 404                         .opt_param = {
 405                                 [UD]  = (IB_QP_CUR_STATE             |
 406                                          IB_QP_QKEY),
 407                                 [UC]  = (IB_QP_ACCESS_FLAGS          |
 408                                          IB_QP_ALT_PATH              |
 409                                          IB_QP_PATH_MIG_STATE),
 410                                 [RC]  = (IB_QP_ACCESS_FLAGS          |
 411                                          IB_QP_ALT_PATH              |
 412                                          IB_QP_PATH_MIG_STATE        |
 413                                          IB_QP_MIN_RNR_TIMER),
 414                                 [MLX] = (IB_QP_CUR_STATE             |
 415                                          IB_QP_QKEY),
 416                         }
 417                 },
 418                 [IB_QPS_SQD]   = {
 419                         .trans = MTHCA_TRANS_RTS2SQD,
 420                 },
 421         },
 422         [IB_QPS_SQD]   = {
 423                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 424                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 425                 [IB_QPS_RTS]   = {
 426                         .trans = MTHCA_TRANS_SQD2RTS,
 427                         .opt_param = {
 428                                 [UD]  = (IB_QP_CUR_STATE             |
 429                                          IB_QP_QKEY),
 430                                 [UC]  = (IB_QP_CUR_STATE             |
 431                                          IB_QP_ALT_PATH              |
 432                                          IB_QP_ACCESS_FLAGS          |
 433                                          IB_QP_PATH_MIG_STATE),
 434                                 [RC]  = (IB_QP_CUR_STATE             |
 435                                          IB_QP_ALT_PATH              |
 436                                          IB_QP_ACCESS_FLAGS          |
 437                                          IB_QP_MIN_RNR_TIMER         |
 438                                          IB_QP_PATH_MIG_STATE),
 439                                 [MLX] = (IB_QP_CUR_STATE             |
 440                                          IB_QP_QKEY),
 441                         }
 442                 },
 443                 [IB_QPS_SQD]   = {
 444                         .trans = MTHCA_TRANS_SQD2SQD,
 445                         .opt_param = {
 446                                 [UD]  = (IB_QP_PKEY_INDEX            |
 447                                          IB_QP_QKEY),
 448                                 [UC]  = (IB_QP_AV                    |
 449                                          IB_QP_CUR_STATE             |
 450                                          IB_QP_ALT_PATH              |
 451                                          IB_QP_ACCESS_FLAGS          |
 452                                          IB_QP_PKEY_INDEX            |
 453                                          IB_QP_PATH_MIG_STATE),
 454                                 [RC]  = (IB_QP_AV                    |
 455                                          IB_QP_TIMEOUT               |
 456                                          IB_QP_RETRY_CNT             |
 457                                          IB_QP_RNR_RETRY             |
 458                                          IB_QP_MAX_QP_RD_ATOMIC      |
 459                                          IB_QP_MAX_DEST_RD_ATOMIC    |
 460                                          IB_QP_CUR_STATE             |
 461                                          IB_QP_ALT_PATH              |
 462                                          IB_QP_ACCESS_FLAGS          |
 463                                          IB_QP_PKEY_INDEX            |
 464                                          IB_QP_MIN_RNR_TIMER         |
 465                                          IB_QP_PATH_MIG_STATE),
 466                                 [MLX] = (IB_QP_PKEY_INDEX            |
 467                                          IB_QP_QKEY),
 468                         }
 469                 }
 470         },
 471         [IB_QPS_SQE]   = {
 472                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 473                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 474                 [IB_QPS_RTS]   = {
 475                         .trans = MTHCA_TRANS_SQERR2RTS,
 476                         .opt_param = {
 477                                 [UD]  = (IB_QP_CUR_STATE             |
 478                                          IB_QP_QKEY),
 479                                 [UC]  = IB_QP_CUR_STATE,
 480                                 [RC]  = (IB_QP_CUR_STATE             |
 481                                          IB_QP_MIN_RNR_TIMER),
 482                                 [MLX] = (IB_QP_CUR_STATE             |
 483                                          IB_QP_QKEY),
 484                         }
 485                 }
 486         },
 487         [IB_QPS_ERR] = {
 488                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 489                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR }
 490         }
 491 };
 492
 493 static void store_attrs(struct mthca_sqp *sqp, struct ib_qp_attr *attr,
 494                         int attr_mask)
 495 {
 496         if (attr_mask & IB_QP_PKEY_INDEX)
 497                 sqp->pkey_index = attr->pkey_index;
 498         if (attr_mask & IB_QP_QKEY)
 499                 sqp->qkey = attr->qkey;
 500         if (attr_mask & IB_QP_SQ_PSN)
 501                 sqp->send_psn = attr->sq_psn;
 502 }
 503
 504 static void init_port(struct mthca_dev *dev, int port)
 505 {
 506         int err;
 507         u8 status;
 508         struct mthca_init_ib_param param;
 509
 510         memset(&param, 0, sizeof param);
 511
 512         param.port_width = dev->limits.port_width_cap;
 513         param.vl_cap     = dev->limits.vl_cap;
 514         param.mtu_cap    = dev->limits.mtu_cap;
 515         param.gid_cap    = dev->limits.gid_table_len;
 516         param.pkey_cap   = dev->limits.pkey_table_len;
 517
 518         err = mthca_INIT_IB(dev, &param, port, &status);
 519         if (err)
 520                 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
 521         if (status)
 522                 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
 523 }
 524
 525 static __be32 get_hw_access_flags(struct mthca_qp *qp, struct ib_qp_attr *attr,
 526                                   int attr_mask)
 527 {
 528         u8 dest_rd_atomic;
 529         u32 access_flags;
 530         u32 hw_access_flags = 0;
 531
 532         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 533                 dest_rd_atomic = attr->max_dest_rd_atomic;
 534         else
 535                 dest_rd_atomic = qp->resp_depth;
 536
 537         if (attr_mask & IB_QP_ACCESS_FLAGS)
 538                 access_flags = attr->qp_access_flags;
 539         else
 540                 access_flags = qp->atomic_rd_en;
 541
 542         if (!dest_rd_atomic)
 543                 access_flags &= IB_ACCESS_REMOTE_WRITE;
 544
 545         if (access_flags & IB_ACCESS_REMOTE_READ)
 546                 hw_access_flags |= MTHCA_QP_BIT_RRE;
 547         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
 548                 hw_access_flags |= MTHCA_QP_BIT_RAE;
 549         if (access_flags & IB_ACCESS_REMOTE_WRITE)
 550                 hw_access_flags |= MTHCA_QP_BIT_RWE;
 551
 552         return cpu_to_be32(hw_access_flags);
 553 }
 554
 555 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask)
 556 {
 557         struct mthca_dev *dev = to_mdev(ibqp->device);
 558         struct mthca_qp *qp = to_mqp(ibqp);
 559         enum ib_qp_state cur_state, new_state;
 560         struct mthca_mailbox *mailbox;
 561         struct mthca_qp_param *qp_param;
 562         struct mthca_qp_context *qp_context;
 563         u32 req_param, opt_param;
 564         u8 status;
 565         int err;
 566
 567         if (attr_mask & IB_QP_CUR_STATE) {
 568                 if (attr->cur_qp_state != IB_QPS_RTR &&
 569                     attr->cur_qp_state != IB_QPS_RTS &&
 570                     attr->cur_qp_state != IB_QPS_SQD &&
 571                     attr->cur_qp_state != IB_QPS_SQE)
 572                         return -EINVAL;
 573                 else
 574                         cur_state = attr->cur_qp_state;
 575         } else {
 576                 spin_lock_irq(&qp->sq.lock);
 577                 spin_lock(&qp->rq.lock);
 578                 cur_state = qp->state;
 579                 spin_unlock(&qp->rq.lock);
 580                 spin_unlock_irq(&qp->sq.lock);
 581         }
 582
 583         if (attr_mask & IB_QP_STATE) {
 584                if (attr->qp_state < 0 || attr->qp_state > IB_QPS_ERR)
 585                         return -EINVAL;
 586                 new_state = attr->qp_state;
 587         } else
 588                 new_state = cur_state;
 589
 590         if (state_table[cur_state][new_state].trans == MTHCA_TRANS_INVALID) {
 591                 mthca_dbg(dev, "Illegal QP transition "
 592                           "%d->%d\n", cur_state, new_state);
 593                 return -EINVAL;
 594         }
 595
 596         req_param = state_table[cur_state][new_state].req_param[qp->transport];
 597         opt_param = state_table[cur_state][new_state].opt_param[qp->transport];
 598
 599         if ((req_param & attr_mask) != req_param) {
 600                 mthca_dbg(dev, "QP transition "
 601                           "%d->%d missing req attr 0x%08x\n",
 602                           cur_state, new_state,
 603                           req_param & ~attr_mask);
 604                 return -EINVAL;
 605         }
 606
 607         if (attr_mask & ~(req_param | opt_param | IB_QP_STATE)) {
 608                 mthca_dbg(dev, "QP transition (transport %d) "
 609                           "%d->%d has extra attr 0x%08x\n",
 610                           qp->transport,
 611                           cur_state, new_state,
 612                           attr_mask & ~(req_param | opt_param |
 613                                                  IB_QP_STATE));
 614                 return -EINVAL;
 615         }
 616
 617         if ((attr_mask & IB_QP_PKEY_INDEX) &&
 618              attr->pkey_index >= dev->limits.pkey_table_len) {
 619                 mthca_dbg(dev, "PKey index (%u) too large. max is %d\n",
 620                           attr->pkey_index,dev->limits.pkey_table_len-1);
 621                 return -EINVAL;
 622         }
 623
 624         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
 625             attr->max_rd_atomic > dev->limits.max_qp_init_rdma) {
 626                 mthca_dbg(dev, "Max rdma_atomic as initiator %u too large (max is %d)\n",
 627                           attr->max_rd_atomic, dev->limits.max_qp_init_rdma);
 628                 return -EINVAL;
 629         }
 630
 631         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
 632             attr->max_dest_rd_atomic > 1 << dev->qp_table.rdb_shift) {
 633                 mthca_dbg(dev, "Max rdma_atomic as responder %u too large (max %d)\n",
 634                           attr->max_dest_rd_atomic, 1 << dev->qp_table.rdb_shift);
 635                 return -EINVAL;
 636         }
 637
 638         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 639         if (IS_ERR(mailbox))
 640                 return PTR_ERR(mailbox);
 641         qp_param = mailbox->buf;
 642         qp_context = &qp_param->context;
 643         memset(qp_param, 0, sizeof *qp_param);
 644
 645         qp_context->flags      = cpu_to_be32((to_mthca_state(new_state) << 28) |
 646                                              (to_mthca_st(qp->transport) << 16));
 647         qp_context->flags     |= cpu_to_be32(MTHCA_QP_BIT_DE);
 648         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 649                 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 650         else {
 651                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
 652                 switch (attr->path_mig_state) {
 653                 case IB_MIG_MIGRATED:
 654                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 655                         break;
 656                 case IB_MIG_REARM:
 657                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
 658                         break;
 659                 case IB_MIG_ARMED:
 660                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
 661                         break;
 662                 }
 663         }
 664
 665         /* leave tavor_sched_queue as 0 */
 666
 667         if (qp->transport == MLX || qp->transport == UD)
 668                 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
 669         else if (attr_mask & IB_QP_PATH_MTU)
 670                 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
 671
 672         if (mthca_is_memfree(dev)) {
 673                 if (qp->rq.max)
 674                         qp_context->rq_size_stride = long_log2(qp->rq.max) << 3;
 675                 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4;
 676
 677                 if (qp->sq.max)
 678                         qp_context->sq_size_stride = long_log2(qp->sq.max) << 3;
 679                 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4;
 680         }
 681
 682         /* leave arbel_sched_queue as 0 */
 683
 684         if (qp->ibqp.uobject)
 685                 qp_context->usr_page =
 686                         cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index);
 687         else
 688                 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
 689         qp_context->local_qpn  = cpu_to_be32(qp->qpn);
 690         if (attr_mask & IB_QP_DEST_QPN) {
 691                 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
 692         }
 693
 694         if (qp->transport == MLX)
 695                 qp_context->pri_path.port_pkey |=
 696                         cpu_to_be32(to_msqp(qp)->port << 24);
 697         else {
 698                 if (attr_mask & IB_QP_PORT) {
 699                         qp_context->pri_path.port_pkey |=
 700                                 cpu_to_be32(attr->port_num << 24);
 701                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
 702                 }
 703         }
 704
 705         if (attr_mask & IB_QP_PKEY_INDEX) {
 706                 qp_context->pri_path.port_pkey |=
 707                         cpu_to_be32(attr->pkey_index);
 708                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
 709         }
 710
 711         if (attr_mask & IB_QP_RNR_RETRY) {
 712                 qp_context->pri_path.rnr_retry = attr->rnr_retry << 5;
 713                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY);
 714         }
 715
 716         if (attr_mask & IB_QP_AV) {
 717                 qp_context->pri_path.g_mylmc     = attr->ah_attr.src_path_bits & 0x7f;
 718                 qp_context->pri_path.rlid        = cpu_to_be16(attr->ah_attr.dlid);
 719                 qp_context->pri_path.static_rate = !!attr->ah_attr.static_rate;
 720                 if (attr->ah_attr.ah_flags & IB_AH_GRH) {
 721                         qp_context->pri_path.g_mylmc |= 1 << 7;
 722                         qp_context->pri_path.mgid_index = attr->ah_attr.grh.sgid_index;
 723                         qp_context->pri_path.hop_limit = attr->ah_attr.grh.hop_limit;
 724                         qp_context->pri_path.sl_tclass_flowlabel =
 725                                 cpu_to_be32((attr->ah_attr.sl << 28)                |
 726                                             (attr->ah_attr.grh.traffic_class << 20) |
 727                                             (attr->ah_attr.grh.flow_label));
 728                         memcpy(qp_context->pri_path.rgid,
 729                                attr->ah_attr.grh.dgid.raw, 16);
 730                 } else {
 731                         qp_context->pri_path.sl_tclass_flowlabel =
 732                                 cpu_to_be32(attr->ah_attr.sl << 28);
 733                 }
 734                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
 735         }
 736
 737         if (attr_mask & IB_QP_TIMEOUT) {
 738                 qp_context->pri_path.ackto = attr->timeout << 3;
 739                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
 740         }
 741
 742         /* XXX alt_path */
 743
 744         /* leave rdd as 0 */
 745         qp_context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
 746         /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
 747         qp_context->wqe_lkey   = cpu_to_be32(qp->mr.ibmr.lkey);
 748         qp_context->params1    = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
 749                                              (MTHCA_FLIGHT_LIMIT << 24) |
 750                                              MTHCA_QP_BIT_SWE);
 751         if (qp->sq_policy == IB_SIGNAL_ALL_WR)
 752                 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
 753         if (attr_mask & IB_QP_RETRY_CNT) {
 754                 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
 755                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
 756         }
 757
 758         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
 759                 if (attr->max_rd_atomic) {
 760                         qp_context->params1 |=
 761                                 cpu_to_be32(MTHCA_QP_BIT_SRE |
 762                                             MTHCA_QP_BIT_SAE);
 763                         qp_context->params1 |=
 764                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
 765                 }
 766                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
 767         }
 768
 769         if (attr_mask & IB_QP_SQ_PSN)
 770                 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
 771         qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
 772
 773         if (mthca_is_memfree(dev)) {
 774                 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
 775                 qp_context->snd_db_index   = cpu_to_be32(qp->sq.db_index);
 776         }
 777
 778         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
 779                 if (attr->max_dest_rd_atomic)
 780                         qp_context->params2 |=
 781                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
 782
 783                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
 784         }
 785
 786         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
 787                 qp_context->params2      |= get_hw_access_flags(qp, attr, attr_mask);
 788                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 789                                                         MTHCA_QP_OPTPAR_RRE |
 790                                                         MTHCA_QP_OPTPAR_RAE);
 791         }
 792
 793         qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
 794
 795         if (ibqp->srq)
 796                 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC);
 797
 798         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
 799                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
 800                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
 801         }
 802         if (attr_mask & IB_QP_RQ_PSN)
 803                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
 804
 805         qp_context->ra_buff_indx =
 806                 cpu_to_be32(dev->qp_table.rdb_base +
 807                             ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
 808                              dev->qp_table.rdb_shift));
 809
 810         qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
 811
 812         if (mthca_is_memfree(dev))
 813                 qp_context->rcv_db_index   = cpu_to_be32(qp->rq.db_index);
 814
 815         if (attr_mask & IB_QP_QKEY) {
 816                 qp_context->qkey = cpu_to_be32(attr->qkey);
 817                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
 818         }
 819
 820         if (ibqp->srq)
 821                 qp_context->srqn = cpu_to_be32(1 << 24 |
 822                                                to_msrq(ibqp->srq)->srqn);
 823
 824         err = mthca_MODIFY_QP(dev, state_table[cur_state][new_state].trans,
 825                               qp->qpn, 0, mailbox, 0, &status);
 826         if (status) {
 827                 mthca_warn(dev, "modify QP %d returned status %02x.\n",
 828                            state_table[cur_state][new_state].trans, status);
 829                 err = -EINVAL;
 830         }
 831
 832         if (!err) {
 833                 qp->state = new_state;
 834                 if (attr_mask & IB_QP_ACCESS_FLAGS)
 835                         qp->atomic_rd_en = attr->qp_access_flags;
 836                 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 837                         qp->resp_depth = attr->max_dest_rd_atomic;
 838         }
 839
 840         mthca_free_mailbox(dev, mailbox);
 841
 842         if (is_sqp(dev, qp))
 843                 store_attrs(to_msqp(qp), attr, attr_mask);
 844
 845         /*
 846          * If we moved QP0 to RTR, bring the IB link up; if we moved
 847          * QP0 to RESET or ERROR, bring the link back down.
 848          */
 849         if (is_qp0(dev, qp)) {
 850                 if (cur_state != IB_QPS_RTR &&
 851                     new_state == IB_QPS_RTR)
 852                         init_port(dev, to_msqp(qp)->port);
 853
 854                 if (cur_state != IB_QPS_RESET &&
 855                     cur_state != IB_QPS_ERR &&
 856                     (new_state == IB_QPS_RESET ||
 857                      new_state == IB_QPS_ERR))
 858                         mthca_CLOSE_IB(dev, to_msqp(qp)->port, &status);
 859         }
 860
 861         /*
 862          * If we moved a kernel QP to RESET, clean up all old CQ
 863          * entries and reinitialize the QP.
 864          */
 865         if (!err && new_state == IB_QPS_RESET && !qp->ibqp.uobject) {
 866                 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn,
 867                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
 868                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
 869                         mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn,
 870                                        qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
 871
 872                 mthca_wq_init(&qp->sq);
 873                 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
 874
 875                 mthca_wq_init(&qp->rq);
 876                 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
 877
 878                 if (mthca_is_memfree(dev)) {
 879                         *qp->sq.db = 0;
 880                         *qp->rq.db = 0;
 881                 }
 882         }
 883
 884         return err;
 885 }
 886
 887 static void mthca_adjust_qp_caps(struct mthca_dev *dev,
 888                                  struct mthca_pd *pd,
 889                                  struct mthca_qp *qp)
 890 {
 891         int max_data_size;
 892
 893         /*
 894          * Calculate the maximum size of WQE s/g segments, excluding
 895          * the next segment and other non-data segments.
 896          */
 897         max_data_size = min(dev->limits.max_desc_sz, 1 << qp->sq.wqe_shift) -
 898                 sizeof (struct mthca_next_seg);
 899
 900         switch (qp->transport) {
 901         case MLX:
 902                 max_data_size -= 2 * sizeof (struct mthca_data_seg);
 903                 break;
 904
 905         case UD:
 906                 if (mthca_is_memfree(dev))
 907                         max_data_size -= sizeof (struct mthca_arbel_ud_seg);
 908                 else
 909                         max_data_size -= sizeof (struct mthca_tavor_ud_seg);
 910                 break;
 911
 912         default:
 913                 max_data_size -= sizeof (struct mthca_raddr_seg);
 914                 break;
 915         }
 916
 917         /* We don't support inline data for kernel QPs (yet). */
 918         if (!pd->ibpd.uobject)
 919                 qp->max_inline_data = 0;
 920         else
 921                 qp->max_inline_data = max_data_size - MTHCA_INLINE_HEADER_SIZE;
 922
 923         qp->sq.max_gs = min_t(int, dev->limits.max_sg,
 924                               max_data_size / sizeof (struct mthca_data_seg));
 925         qp->rq.max_gs = min_t(int, dev->limits.max_sg,
 926                                (min(dev->limits.max_desc_sz, 1 << qp->rq.wqe_shift) -
 927                                 sizeof (struct mthca_next_seg)) /
 928                                sizeof (struct mthca_data_seg));
 929 }
 930
 931 /*
 932  * Allocate and register buffer for WQEs.  qp->rq.max, sq.max,
 933  * rq.max_gs and sq.max_gs must all be assigned.
 934  * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
 935  * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
 936  * queue)
 937  */
 938 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
 939                                struct mthca_pd *pd,
 940                                struct mthca_qp *qp)
 941 {
 942         int size;
 943         int err = -ENOMEM;
 944
 945         size = sizeof (struct mthca_next_seg) +
 946                 qp->rq.max_gs * sizeof (struct mthca_data_seg);
 947
 948         if (size > dev->limits.max_desc_sz)
 949                 return -EINVAL;
 950
 951         for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
 952              qp->rq.wqe_shift++)
 953                 ; /* nothing */
 954
 955         size = qp->sq.max_gs * sizeof (struct mthca_data_seg);
 956         switch (qp->transport) {
 957         case MLX:
 958                 size += 2 * sizeof (struct mthca_data_seg);
 959                 break;
 960
 961         case UD:
 962                 size += mthca_is_memfree(dev) ?
 963                         sizeof (struct mthca_arbel_ud_seg) :
 964                         sizeof (struct mthca_tavor_ud_seg);
 965                 break;
 966
 967         case UC:
 968                 size += sizeof (struct mthca_raddr_seg);
 969                 break;
 970
 971         case RC:
 972                 size += sizeof (struct mthca_raddr_seg);
 973                 /*
 974                  * An atomic op will require an atomic segment, a
 975                  * remote address segment and one scatter entry.
 976                  */
 977                 size = max_t(int, size,
 978                              sizeof (struct mthca_atomic_seg) +
 979                              sizeof (struct mthca_raddr_seg) +
 980                              sizeof (struct mthca_data_seg));
 981                 break;
 982
 983         default:
 984                 break;
 985         }
 986
 987         /* Make sure that we have enough space for a bind request */
 988         size = max_t(int, size, sizeof (struct mthca_bind_seg));
 989
 990         size += sizeof (struct mthca_next_seg);
 991
 992         if (size > dev->limits.max_desc_sz)
 993                 return -EINVAL;
 994
 995         for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
 996              qp->sq.wqe_shift++)
 997                 ; /* nothing */
 998
 999         qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
1000                                     1 << qp->sq.wqe_shift);
1001
1002         /*
1003          * If this is a userspace QP, we don't actually have to
1004          * allocate anything.  All we need is to calculate the WQE
1005          * sizes and the send_wqe_offset, so we're done now.
1006          */
1007         if (pd->ibpd.uobject)
1008                 return 0;
1009
1010         size = PAGE_ALIGN(qp->send_wqe_offset +
1011                           (qp->sq.max << qp->sq.wqe_shift));
1012
1013         qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
1014                            GFP_KERNEL);
1015         if (!qp->wrid)
1016                 goto err_out;
1017
1018         err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
1019                               &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
1020         if (err)
1021                 goto err_out;
1022
1023         return 0;
1024
1025 err_out:
1026         kfree(qp->wrid);
1027         return err;
1028 }
1029
1030 static void mthca_free_wqe_buf(struct mthca_dev *dev,
1031                                struct mthca_qp *qp)
1032 {
1033         mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
1034                                        (qp->sq.max << qp->sq.wqe_shift)),
1035                        &qp->queue, qp->is_direct, &qp->mr);
1036         kfree(qp->wrid);
1037 }
1038
1039 static int mthca_map_memfree(struct mthca_dev *dev,
1040                              struct mthca_qp *qp)
1041 {
1042         int ret;
1043
1044         if (mthca_is_memfree(dev)) {
1045                 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
1046                 if (ret)
1047                         return ret;
1048
1049                 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
1050                 if (ret)
1051                         goto err_qpc;
1052
1053                 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
1054                                       qp->qpn << dev->qp_table.rdb_shift);
1055                 if (ret)
1056                         goto err_eqpc;
1057
1058         }
1059
1060         return 0;
1061
1062 err_eqpc:
1063         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1064
1065 err_qpc:
1066         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1067
1068         return ret;
1069 }
1070
1071 static void mthca_unmap_memfree(struct mthca_dev *dev,
1072                                 struct mthca_qp *qp)
1073 {
1074         mthca_table_put(dev, dev->qp_table.rdb_table,
1075                         qp->qpn << dev->qp_table.rdb_shift);
1076         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1077         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1078 }
1079
1080 static int mthca_alloc_memfree(struct mthca_dev *dev,
1081                                struct mthca_qp *qp)
1082 {
1083         int ret = 0;
1084
1085         if (mthca_is_memfree(dev)) {
1086                 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1087                                                  qp->qpn, &qp->rq.db);
1088                 if (qp->rq.db_index < 0)
1089                         return ret;
1090
1091                 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1092                                                  qp->qpn, &qp->sq.db);
1093                 if (qp->sq.db_index < 0)
1094                         mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1095         }
1096
1097         return ret;
1098 }
1099
1100 static void mthca_free_memfree(struct mthca_dev *dev,
1101                                struct mthca_qp *qp)
1102 {
1103         if (mthca_is_memfree(dev)) {
1104                 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1105                 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1106         }
1107 }
1108
1109 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1110                                  struct mthca_pd *pd,
1111                                  struct mthca_cq *send_cq,
1112                                  struct mthca_cq *recv_cq,
1113                                  enum ib_sig_type send_policy,
1114                                  struct mthca_qp *qp)
1115 {
1116         int ret;
1117         int i;
1118
1119         atomic_set(&qp->refcount, 1);
1120         init_waitqueue_head(&qp->wait);
1121         qp->state        = IB_QPS_RESET;
1122         qp->atomic_rd_en = 0;
1123         qp->resp_depth   = 0;
1124         qp->sq_policy    = send_policy;
1125         mthca_wq_init(&qp->sq);
1126         mthca_wq_init(&qp->rq);
1127
1128         ret = mthca_map_memfree(dev, qp);
1129         if (ret)
1130                 return ret;
1131
1132         ret = mthca_alloc_wqe_buf(dev, pd, qp);
1133         if (ret) {
1134                 mthca_unmap_memfree(dev, qp);
1135                 return ret;
1136         }
1137
1138         mthca_adjust_qp_caps(dev, pd, qp);
1139
1140         /*
1141          * If this is a userspace QP, we're done now.  The doorbells
1142          * will be allocated and buffers will be initialized in
1143          * userspace.
1144          */
1145         if (pd->ibpd.uobject)
1146                 return 0;
1147
1148         ret = mthca_alloc_memfree(dev, qp);
1149         if (ret) {
1150                 mthca_free_wqe_buf(dev, qp);
1151                 mthca_unmap_memfree(dev, qp);
1152                 return ret;
1153         }
1154
1155         if (mthca_is_memfree(dev)) {
1156                 struct mthca_next_seg *next;
1157                 struct mthca_data_seg *scatter;
1158                 int size = (sizeof (struct mthca_next_seg) +
1159                             qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1160
1161                 for (i = 0; i < qp->rq.max; ++i) {
1162                         next = get_recv_wqe(qp, i);
1163                         next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1164                                                    qp->rq.wqe_shift);
1165                         next->ee_nds = cpu_to_be32(size);
1166
1167                         for (scatter = (void *) (next + 1);
1168                              (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1169                              ++scatter)
1170                                 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1171                 }
1172
1173                 for (i = 0; i < qp->sq.max; ++i) {
1174                         next = get_send_wqe(qp, i);
1175                         next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1176                                                     qp->sq.wqe_shift) +
1177                                                    qp->send_wqe_offset);
1178                 }
1179         }
1180
1181         qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
1182         qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
1183
1184         return 0;
1185 }
1186
1187 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1188                              struct mthca_qp *qp)
1189 {
1190         /* Sanity check QP size before proceeding */
1191         if (cap->max_send_wr  > dev->limits.max_wqes ||
1192             cap->max_recv_wr  > dev->limits.max_wqes ||
1193             cap->max_send_sge > dev->limits.max_sg   ||
1194             cap->max_recv_sge > dev->limits.max_sg)
1195                 return -EINVAL;
1196
1197         if (mthca_is_memfree(dev)) {
1198                 qp->rq.max = cap->max_recv_wr ?
1199                         roundup_pow_of_two(cap->max_recv_wr) : 0;
1200                 qp->sq.max = cap->max_send_wr ?
1201                         roundup_pow_of_two(cap->max_send_wr) : 0;
1202         } else {
1203                 qp->rq.max = cap->max_recv_wr;
1204                 qp->sq.max = cap->max_send_wr;
1205         }
1206
1207         qp->rq.max_gs = cap->max_recv_sge;
1208         qp->sq.max_gs = max_t(int, cap->max_send_sge,
1209                               ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1210                                     MTHCA_INLINE_CHUNK_SIZE) /
1211                               sizeof (struct mthca_data_seg));
1212
1213         /*
1214          * For MLX transport we need 2 extra S/G entries:
1215          * one for the header and one for the checksum at the end
1216          */
1217         if ((qp->transport == MLX && qp->sq.max_gs + 2 > dev->limits.max_sg) ||
1218             qp->sq.max_gs > dev->limits.max_sg || qp->rq.max_gs > dev->limits.max_sg)
1219                 return -EINVAL;
1220
1221         return 0;
1222 }
1223
1224 int mthca_alloc_qp(struct mthca_dev *dev,
1225                    struct mthca_pd *pd,
1226                    struct mthca_cq *send_cq,
1227                    struct mthca_cq *recv_cq,
1228                    enum ib_qp_type type,
1229                    enum ib_sig_type send_policy,
1230                    struct ib_qp_cap *cap,
1231                    struct mthca_qp *qp)
1232 {
1233         int err;
1234
1235         err = mthca_set_qp_size(dev, cap, qp);
1236         if (err)
1237                 return err;
1238
1239         switch (type) {
1240         case IB_QPT_RC: qp->transport = RC; break;
1241         case IB_QPT_UC: qp->transport = UC; break;
1242         case IB_QPT_UD: qp->transport = UD; break;
1243         default: return -EINVAL;
1244         }
1245
1246         qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1247         if (qp->qpn == -1)
1248                 return -ENOMEM;
1249
1250         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1251                                     send_policy, qp);
1252         if (err) {
1253                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1254                 return err;
1255         }
1256
1257         spin_lock_irq(&dev->qp_table.lock);
1258         mthca_array_set(&dev->qp_table.qp,
1259                         qp->qpn & (dev->limits.num_qps - 1), qp);
1260         spin_unlock_irq(&dev->qp_table.lock);
1261
1262         return 0;
1263 }
1264
1265 int mthca_alloc_sqp(struct mthca_dev *dev,
1266                     struct mthca_pd *pd,
1267                     struct mthca_cq *send_cq,
1268                     struct mthca_cq *recv_cq,
1269                     enum ib_sig_type send_policy,
1270                     struct ib_qp_cap *cap,
1271                     int qpn,
1272                     int port,
1273                     struct mthca_sqp *sqp)
1274 {
1275         u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1276         int err;
1277
1278         err = mthca_set_qp_size(dev, cap, &sqp->qp);
1279         if (err)
1280                 return err;
1281
1282         sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1283         sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1284                                              &sqp->header_dma, GFP_KERNEL);
1285         if (!sqp->header_buf)
1286                 return -ENOMEM;
1287
1288         spin_lock_irq(&dev->qp_table.lock);
1289         if (mthca_array_get(&dev->qp_table.qp, mqpn))
1290                 err = -EBUSY;
1291         else
1292                 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1293         spin_unlock_irq(&dev->qp_table.lock);
1294
1295         if (err)
1296                 goto err_out;
1297
1298         sqp->port = port;
1299         sqp->qp.qpn       = mqpn;
1300         sqp->qp.transport = MLX;
1301
1302         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1303                                     send_policy, &sqp->qp);
1304         if (err)
1305                 goto err_out_free;
1306
1307         atomic_inc(&pd->sqp_count);
1308
1309         return 0;
1310
1311  err_out_free:
1312         /*
1313          * Lock CQs here, so that CQ polling code can do QP lookup
1314          * without taking a lock.
1315          */
1316         spin_lock_irq(&send_cq->lock);
1317         if (send_cq != recv_cq)
1318                 spin_lock(&recv_cq->lock);
1319
1320         spin_lock(&dev->qp_table.lock);
1321         mthca_array_clear(&dev->qp_table.qp, mqpn);
1322         spin_unlock(&dev->qp_table.lock);
1323
1324         if (send_cq != recv_cq)
1325                 spin_unlock(&recv_cq->lock);
1326         spin_unlock_irq(&send_cq->lock);
1327
1328  err_out:
1329         dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1330                           sqp->header_buf, sqp->header_dma);
1331
1332         return err;
1333 }
1334
1335 void mthca_free_qp(struct mthca_dev *dev,
1336                    struct mthca_qp *qp)
1337 {
1338         u8 status;
1339         struct mthca_cq *send_cq;
1340         struct mthca_cq *recv_cq;
1341
1342         send_cq = to_mcq(qp->ibqp.send_cq);
1343         recv_cq = to_mcq(qp->ibqp.recv_cq);
1344
1345         /*
1346          * Lock CQs here, so that CQ polling code can do QP lookup
1347          * without taking a lock.
1348          */
1349         spin_lock_irq(&send_cq->lock);
1350         if (send_cq != recv_cq)
1351                 spin_lock(&recv_cq->lock);
1352
1353         spin_lock(&dev->qp_table.lock);
1354         mthca_array_clear(&dev->qp_table.qp,
1355                           qp->qpn & (dev->limits.num_qps - 1));
1356         spin_unlock(&dev->qp_table.lock);
1357
1358         if (send_cq != recv_cq)
1359                 spin_unlock(&recv_cq->lock);
1360         spin_unlock_irq(&send_cq->lock);
1361
1362         atomic_dec(&qp->refcount);
1363         wait_event(qp->wait, !atomic_read(&qp->refcount));
1364
1365         if (qp->state != IB_QPS_RESET)
1366                 mthca_MODIFY_QP(dev, MTHCA_TRANS_ANY2RST, qp->qpn, 0, NULL, 0, &status);
1367
1368         /*
1369          * If this is a userspace QP, the buffers, MR, CQs and so on
1370          * will be cleaned up in userspace, so all we have to do is
1371          * unref the mem-free tables and free the QPN in our table.
1372          */
1373         if (!qp->ibqp.uobject) {
1374                 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn,
1375                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1376                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
1377                         mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn,
1378                                        qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1379
1380                 mthca_free_memfree(dev, qp);
1381                 mthca_free_wqe_buf(dev, qp);
1382         }
1383
1384         mthca_unmap_memfree(dev, qp);
1385
1386         if (is_sqp(dev, qp)) {
1387                 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1388                 dma_free_coherent(&dev->pdev->dev,
1389                                   to_msqp(qp)->header_buf_size,
1390                                   to_msqp(qp)->header_buf,
1391                                   to_msqp(qp)->header_dma);
1392         } else
1393                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1394 }
1395
1396 /* Create UD header for an MLX send and build a data segment for it */
1397 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1398                             int ind, struct ib_send_wr *wr,
1399                             struct mthca_mlx_seg *mlx,
1400                             struct mthca_data_seg *data)
1401 {
1402         int header_size;
1403         int err;
1404         u16 pkey;
1405
1406         ib_ud_header_init(256, /* assume a MAD */
1407                           sqp->ud_header.grh_present,
1408                           &sqp->ud_header);
1409
1410         err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1411         if (err)
1412                 return err;
1413         mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1414         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1415                                   (sqp->ud_header.lrh.destination_lid ==
1416                                    IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1417                                   (sqp->ud_header.lrh.service_level << 8));
1418         mlx->rlid = sqp->ud_header.lrh.destination_lid;
1419         mlx->vcrc = 0;
1420
1421         switch (wr->opcode) {
1422         case IB_WR_SEND:
1423                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1424                 sqp->ud_header.immediate_present = 0;
1425                 break;
1426         case IB_WR_SEND_WITH_IMM:
1427                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1428                 sqp->ud_header.immediate_present = 1;
1429                 sqp->ud_header.immediate_data = wr->imm_data;
1430                 break;
1431         default:
1432                 return -EINVAL;
1433         }
1434
1435         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1436         if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1437                 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1438         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1439         if (!sqp->qp.ibqp.qp_num)
1440                 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1441                                    sqp->pkey_index, &pkey);
1442         else
1443                 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1444                                    wr->wr.ud.pkey_index, &pkey);
1445         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1446         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1447         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1448         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1449                                                sqp->qkey : wr->wr.ud.remote_qkey);
1450         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1451
1452         header_size = ib_ud_header_pack(&sqp->ud_header,
1453                                         sqp->header_buf +
1454                                         ind * MTHCA_UD_HEADER_SIZE);
1455
1456         data->byte_count = cpu_to_be32(header_size);
1457         data->lkey       = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1458         data->addr       = cpu_to_be64(sqp->header_dma +
1459                                        ind * MTHCA_UD_HEADER_SIZE);
1460
1461         return 0;
1462 }
1463
1464 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1465                                     struct ib_cq *ib_cq)
1466 {
1467         unsigned cur;
1468         struct mthca_cq *cq;
1469
1470         cur = wq->head - wq->tail;
1471         if (likely(cur + nreq < wq->max))
1472                 return 0;
1473
1474         cq = to_mcq(ib_cq);
1475         spin_lock(&cq->lock);
1476         cur = wq->head - wq->tail;
1477         spin_unlock(&cq->lock);
1478
1479         return cur + nreq >= wq->max;
1480 }
1481
1482 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1483                           struct ib_send_wr **bad_wr)
1484 {
1485         struct mthca_dev *dev = to_mdev(ibqp->device);
1486         struct mthca_qp *qp = to_mqp(ibqp);
1487         void *wqe;
1488         void *prev_wqe;
1489         unsigned long flags;
1490         int err = 0;
1491         int nreq;
1492         int i;
1493         int size;
1494         int size0 = 0;
1495         u32 f0 = 0;
1496         int ind;
1497         u8 op0 = 0;
1498
1499         spin_lock_irqsave(&qp->sq.lock, flags);
1500
1501         /* XXX check that state is OK to post send */
1502
1503         ind = qp->sq.next_ind;
1504
1505         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1506                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1507                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1508                                         " %d max, %d nreq)\n", qp->qpn,
1509                                         qp->sq.head, qp->sq.tail,
1510                                         qp->sq.max, nreq);
1511                         err = -ENOMEM;
1512                         *bad_wr = wr;
1513                         goto out;
1514                 }
1515
1516                 wqe = get_send_wqe(qp, ind);
1517                 prev_wqe = qp->sq.last;
1518                 qp->sq.last = wqe;
1519
1520                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1521                 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1522                 ((struct mthca_next_seg *) wqe)->flags =
1523                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1524                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1525                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1526                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1527                         cpu_to_be32(1);
1528                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1529                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1530                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1531
1532                 wqe += sizeof (struct mthca_next_seg);
1533                 size = sizeof (struct mthca_next_seg) / 16;
1534
1535                 switch (qp->transport) {
1536                 case RC:
1537                         switch (wr->opcode) {
1538                         case IB_WR_ATOMIC_CMP_AND_SWP:
1539                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1540                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1541                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1542                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1543                                         cpu_to_be32(wr->wr.atomic.rkey);
1544                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1545
1546                                 wqe += sizeof (struct mthca_raddr_seg);
1547
1548                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1549                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1550                                                 cpu_to_be64(wr->wr.atomic.swap);
1551                                         ((struct mthca_atomic_seg *) wqe)->compare =
1552                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1553                                 } else {
1554                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1555                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1556                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1557                                 }
1558
1559                                 wqe += sizeof (struct mthca_atomic_seg);
1560                                 size += (sizeof (struct mthca_raddr_seg) +
1561                                          sizeof (struct mthca_atomic_seg)) / 16;
1562                                 break;
1563
1564                         case IB_WR_RDMA_WRITE:
1565                         case IB_WR_RDMA_WRITE_WITH_IMM:
1566                         case IB_WR_RDMA_READ:
1567                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1568                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1569                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1570                                         cpu_to_be32(wr->wr.rdma.rkey);
1571                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1572                                 wqe += sizeof (struct mthca_raddr_seg);
1573                                 size += sizeof (struct mthca_raddr_seg) / 16;
1574                                 break;
1575
1576                         default:
1577                                 /* No extra segments required for sends */
1578                                 break;
1579                         }
1580
1581                         break;
1582
1583                 case UC:
1584                         switch (wr->opcode) {
1585                         case IB_WR_RDMA_WRITE:
1586                         case IB_WR_RDMA_WRITE_WITH_IMM:
1587                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1588                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1589                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1590                                         cpu_to_be32(wr->wr.rdma.rkey);
1591                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1592                                 wqe += sizeof (struct mthca_raddr_seg);
1593                                 size += sizeof (struct mthca_raddr_seg) / 16;
1594                                 break;
1595
1596                         default:
1597                                 /* No extra segments required for sends */
1598                                 break;
1599                         }
1600
1601                         break;
1602
1603                 case UD:
1604                         ((struct mthca_tavor_ud_seg *) wqe)->lkey =
1605                                 cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1606                         ((struct mthca_tavor_ud_seg *) wqe)->av_addr =
1607                                 cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1608                         ((struct mthca_tavor_ud_seg *) wqe)->dqpn =
1609                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1610                         ((struct mthca_tavor_ud_seg *) wqe)->qkey =
1611                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1612
1613                         wqe += sizeof (struct mthca_tavor_ud_seg);
1614                         size += sizeof (struct mthca_tavor_ud_seg) / 16;
1615                         break;
1616
1617                 case MLX:
1618                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1619                                                wqe - sizeof (struct mthca_next_seg),
1620                                                wqe);
1621                         if (err) {
1622                                 *bad_wr = wr;
1623                                 goto out;
1624                         }
1625                         wqe += sizeof (struct mthca_data_seg);
1626                         size += sizeof (struct mthca_data_seg) / 16;
1627                         break;
1628                 }
1629
1630                 if (wr->num_sge > qp->sq.max_gs) {
1631                         mthca_err(dev, "too many gathers\n");
1632                         err = -EINVAL;
1633                         *bad_wr = wr;
1634                         goto out;
1635                 }
1636
1637                 for (i = 0; i < wr->num_sge; ++i) {
1638                         ((struct mthca_data_seg *) wqe)->byte_count =
1639                                 cpu_to_be32(wr->sg_list[i].length);
1640                         ((struct mthca_data_seg *) wqe)->lkey =
1641                                 cpu_to_be32(wr->sg_list[i].lkey);
1642                         ((struct mthca_data_seg *) wqe)->addr =
1643                                 cpu_to_be64(wr->sg_list[i].addr);
1644                         wqe += sizeof (struct mthca_data_seg);
1645                         size += sizeof (struct mthca_data_seg) / 16;
1646                 }
1647
1648                 /* Add one more inline data segment for ICRC */
1649                 if (qp->transport == MLX) {
1650                         ((struct mthca_data_seg *) wqe)->byte_count =
1651                                 cpu_to_be32((1 << 31) | 4);
1652                         ((u32 *) wqe)[1] = 0;
1653                         wqe += sizeof (struct mthca_data_seg);
1654                         size += sizeof (struct mthca_data_seg) / 16;
1655                 }
1656
1657                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1658
1659                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1660                         mthca_err(dev, "opcode invalid\n");
1661                         err = -EINVAL;
1662                         *bad_wr = wr;
1663                         goto out;
1664                 }
1665
1666                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1667                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
1668                                      qp->send_wqe_offset) |
1669                                     mthca_opcode[wr->opcode]);
1670                 wmb();
1671                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1672                         cpu_to_be32((size0 ? 0 : MTHCA_NEXT_DBD) | size);
1673
1674                 if (!size0) {
1675                         size0 = size;
1676                         op0   = mthca_opcode[wr->opcode];
1677                 }
1678
1679                 ++ind;
1680                 if (unlikely(ind >= qp->sq.max))
1681                         ind -= qp->sq.max;
1682         }
1683
1684 out:
1685         if (likely(nreq)) {
1686                 __be32 doorbell[2];
1687
1688                 doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) +
1689                                            qp->send_wqe_offset) | f0 | op0);
1690                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1691
1692                 wmb();
1693
1694                 mthca_write64(doorbell,
1695                               dev->kar + MTHCA_SEND_DOORBELL,
1696                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1697         }
1698
1699         qp->sq.next_ind = ind;
1700         qp->sq.head    += nreq;
1701
1702         spin_unlock_irqrestore(&qp->sq.lock, flags);
1703         return err;
1704 }
1705
1706 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1707                              struct ib_recv_wr **bad_wr)
1708 {
1709         struct mthca_dev *dev = to_mdev(ibqp->device);
1710         struct mthca_qp *qp = to_mqp(ibqp);
1711         __be32 doorbell[2];
1712         unsigned long flags;
1713         int err = 0;
1714         int nreq;
1715         int i;
1716         int size;
1717         int size0 = 0;
1718         int ind;
1719         void *wqe;
1720         void *prev_wqe;
1721
1722         spin_lock_irqsave(&qp->rq.lock, flags);
1723
1724         /* XXX check that state is OK to post receive */
1725
1726         ind = qp->rq.next_ind;
1727
1728         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1729                 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) {
1730                         nreq = 0;
1731
1732                         doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1733                         doorbell[1] = cpu_to_be32(qp->qpn << 8);
1734
1735                         wmb();
1736
1737                         mthca_write64(doorbell,
1738                                       dev->kar + MTHCA_RECEIVE_DOORBELL,
1739                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1740
1741                         qp->rq.head += MTHCA_TAVOR_MAX_WQES_PER_RECV_DB;
1742                         size0 = 0;
1743                 }
1744
1745                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1746                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1747                                         " %d max, %d nreq)\n", qp->qpn,
1748                                         qp->rq.head, qp->rq.tail,
1749                                         qp->rq.max, nreq);
1750                         err = -ENOMEM;
1751                         *bad_wr = wr;
1752                         goto out;
1753                 }
1754
1755                 wqe = get_recv_wqe(qp, ind);
1756                 prev_wqe = qp->rq.last;
1757                 qp->rq.last = wqe;
1758
1759                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1760                 ((struct mthca_next_seg *) wqe)->ee_nds =
1761                         cpu_to_be32(MTHCA_NEXT_DBD);
1762                 ((struct mthca_next_seg *) wqe)->flags = 0;
1763
1764                 wqe += sizeof (struct mthca_next_seg);
1765                 size = sizeof (struct mthca_next_seg) / 16;
1766
1767                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1768                         err = -EINVAL;
1769                         *bad_wr = wr;
1770                         goto out;
1771                 }
1772
1773                 for (i = 0; i < wr->num_sge; ++i) {
1774                         ((struct mthca_data_seg *) wqe)->byte_count =
1775                                 cpu_to_be32(wr->sg_list[i].length);
1776                         ((struct mthca_data_seg *) wqe)->lkey =
1777                                 cpu_to_be32(wr->sg_list[i].lkey);
1778                         ((struct mthca_data_seg *) wqe)->addr =
1779                                 cpu_to_be64(wr->sg_list[i].addr);
1780                         wqe += sizeof (struct mthca_data_seg);
1781                         size += sizeof (struct mthca_data_seg) / 16;
1782                 }
1783
1784                 qp->wrid[ind] = wr->wr_id;
1785
1786                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1787                         cpu_to_be32((ind << qp->rq.wqe_shift) | 1);
1788                 wmb();
1789                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1790                         cpu_to_be32(MTHCA_NEXT_DBD | size);
1791
1792                 if (!size0)
1793                         size0 = size;
1794
1795                 ++ind;
1796                 if (unlikely(ind >= qp->rq.max))
1797                         ind -= qp->rq.max;
1798         }
1799
1800 out:
1801         if (likely(nreq)) {
1802                 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1803                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq);
1804
1805                 wmb();
1806
1807                 mthca_write64(doorbell,
1808                               dev->kar + MTHCA_RECEIVE_DOORBELL,
1809                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1810         }
1811
1812         qp->rq.next_ind = ind;
1813         qp->rq.head    += nreq;
1814
1815         spin_unlock_irqrestore(&qp->rq.lock, flags);
1816         return err;
1817 }
1818
1819 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1820                           struct ib_send_wr **bad_wr)
1821 {
1822         struct mthca_dev *dev = to_mdev(ibqp->device);
1823         struct mthca_qp *qp = to_mqp(ibqp);
1824         __be32 doorbell[2];
1825         void *wqe;
1826         void *prev_wqe;
1827         unsigned long flags;
1828         int err = 0;
1829         int nreq;
1830         int i;
1831         int size;
1832         int size0 = 0;
1833         u32 f0 = 0;
1834         int ind;
1835         u8 op0 = 0;
1836
1837         spin_lock_irqsave(&qp->sq.lock, flags);
1838
1839         /* XXX check that state is OK to post send */
1840
1841         ind = qp->sq.head & (qp->sq.max - 1);
1842
1843         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1844                 if (unlikely(nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB)) {
1845                         nreq = 0;
1846
1847                         doorbell[0] = cpu_to_be32((MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) |
1848                                                   ((qp->sq.head & 0xffff) << 8) |
1849                                                   f0 | op0);
1850                         doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1851
1852                         qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB;
1853                         size0 = 0;
1854
1855                         /*
1856                          * Make sure that descriptors are written before
1857                          * doorbell record.
1858                          */
1859                         wmb();
1860                         *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1861
1862                         /*
1863                          * Make sure doorbell record is written before we
1864                          * write MMIO send doorbell.
1865                          */
1866                         wmb();
1867                         mthca_write64(doorbell,
1868                                       dev->kar + MTHCA_SEND_DOORBELL,
1869                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1870                 }
1871
1872                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1873                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1874                                         " %d max, %d nreq)\n", qp->qpn,
1875                                         qp->sq.head, qp->sq.tail,
1876                                         qp->sq.max, nreq);
1877                         err = -ENOMEM;
1878                         *bad_wr = wr;
1879                         goto out;
1880                 }
1881
1882                 wqe = get_send_wqe(qp, ind);
1883                 prev_wqe = qp->sq.last;
1884                 qp->sq.last = wqe;
1885
1886                 ((struct mthca_next_seg *) wqe)->flags =
1887                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1888                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1889                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1890                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1891                         cpu_to_be32(1);
1892                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1893                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1894                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1895
1896                 wqe += sizeof (struct mthca_next_seg);
1897                 size = sizeof (struct mthca_next_seg) / 16;
1898
1899                 switch (qp->transport) {
1900                 case RC:
1901                         switch (wr->opcode) {
1902                         case IB_WR_ATOMIC_CMP_AND_SWP:
1903                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1904                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1905                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1906                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1907                                         cpu_to_be32(wr->wr.atomic.rkey);
1908                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1909
1910                                 wqe += sizeof (struct mthca_raddr_seg);
1911
1912                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1913                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1914                                                 cpu_to_be64(wr->wr.atomic.swap);
1915                                         ((struct mthca_atomic_seg *) wqe)->compare =
1916                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1917                                 } else {
1918                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1919                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1920                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1921                                 }
1922
1923                                 wqe += sizeof (struct mthca_atomic_seg);
1924                                 size += (sizeof (struct mthca_raddr_seg) +
1925                                          sizeof (struct mthca_atomic_seg)) / 16;
1926                                 break;
1927
1928                         case IB_WR_RDMA_READ:
1929                         case IB_WR_RDMA_WRITE:
1930                         case IB_WR_RDMA_WRITE_WITH_IMM:
1931                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1932                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1933                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1934                                         cpu_to_be32(wr->wr.rdma.rkey);
1935                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1936                                 wqe += sizeof (struct mthca_raddr_seg);
1937                                 size += sizeof (struct mthca_raddr_seg) / 16;
1938                                 break;
1939
1940                         default:
1941                                 /* No extra segments required for sends */
1942                                 break;
1943                         }
1944
1945                         break;
1946
1947                 case UC:
1948                         switch (wr->opcode) {
1949                         case IB_WR_RDMA_WRITE:
1950                         case IB_WR_RDMA_WRITE_WITH_IMM:
1951                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1952                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1953                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1954                                         cpu_to_be32(wr->wr.rdma.rkey);
1955                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1956                                 wqe += sizeof (struct mthca_raddr_seg);
1957                                 size += sizeof (struct mthca_raddr_seg) / 16;
1958                                 break;
1959
1960                         default:
1961                                 /* No extra segments required for sends */
1962                                 break;
1963                         }
1964
1965                         break;
1966
1967                 case UD:
1968                         memcpy(((struct mthca_arbel_ud_seg *) wqe)->av,
1969                                to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE);
1970                         ((struct mthca_arbel_ud_seg *) wqe)->dqpn =
1971                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1972                         ((struct mthca_arbel_ud_seg *) wqe)->qkey =
1973                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1974
1975                         wqe += sizeof (struct mthca_arbel_ud_seg);
1976                         size += sizeof (struct mthca_arbel_ud_seg) / 16;
1977                         break;
1978
1979                 case MLX:
1980                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1981                                                wqe - sizeof (struct mthca_next_seg),
1982                                                wqe);
1983                         if (err) {
1984                                 *bad_wr = wr;
1985                                 goto out;
1986                         }
1987                         wqe += sizeof (struct mthca_data_seg);
1988                         size += sizeof (struct mthca_data_seg) / 16;
1989                         break;
1990                 }
1991
1992                 if (wr->num_sge > qp->sq.max_gs) {
1993                         mthca_err(dev, "too many gathers\n");
1994                         err = -EINVAL;
1995                         *bad_wr = wr;
1996                         goto out;
1997                 }
1998
1999                 for (i = 0; i < wr->num_sge; ++i) {
2000                         ((struct mthca_data_seg *) wqe)->byte_count =
2001                                 cpu_to_be32(wr->sg_list[i].length);
2002                         ((struct mthca_data_seg *) wqe)->lkey =
2003                                 cpu_to_be32(wr->sg_list[i].lkey);
2004                         ((struct mthca_data_seg *) wqe)->addr =
2005                                 cpu_to_be64(wr->sg_list[i].addr);
2006                         wqe += sizeof (struct mthca_data_seg);
2007                         size += sizeof (struct mthca_data_seg) / 16;
2008                 }
2009
2010                 /* Add one more inline data segment for ICRC */
2011                 if (qp->transport == MLX) {
2012                         ((struct mthca_data_seg *) wqe)->byte_count =
2013                                 cpu_to_be32((1 << 31) | 4);
2014                         ((u32 *) wqe)[1] = 0;
2015                         wqe += sizeof (struct mthca_data_seg);
2016                         size += sizeof (struct mthca_data_seg) / 16;
2017                 }
2018
2019                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
2020
2021                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
2022                         mthca_err(dev, "opcode invalid\n");
2023                         err = -EINVAL;
2024                         *bad_wr = wr;
2025                         goto out;
2026                 }
2027
2028                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
2029                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
2030                                      qp->send_wqe_offset) |
2031                                     mthca_opcode[wr->opcode]);
2032                 wmb();
2033                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
2034                         cpu_to_be32(MTHCA_NEXT_DBD | size);
2035
2036                 if (!size0) {
2037                         size0 = size;
2038                         op0   = mthca_opcode[wr->opcode];
2039                 }
2040
2041                 ++ind;
2042                 if (unlikely(ind >= qp->sq.max))
2043                         ind -= qp->sq.max;
2044         }
2045
2046 out:
2047         if (likely(nreq)) {
2048                 doorbell[0] = cpu_to_be32((nreq << 24)                  |
2049                                           ((qp->sq.head & 0xffff) << 8) |
2050                                           f0 | op0);
2051                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
2052
2053                 qp->sq.head += nreq;
2054
2055                 /*
2056                  * Make sure that descriptors are written before
2057                  * doorbell record.
2058                  */
2059                 wmb();
2060                 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
2061
2062                 /*
2063                  * Make sure doorbell record is written before we
2064                  * write MMIO send doorbell.
2065                  */
2066                 wmb();
2067                 mthca_write64(doorbell,
2068                               dev->kar + MTHCA_SEND_DOORBELL,
2069                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
2070         }
2071
2072         spin_unlock_irqrestore(&qp->sq.lock, flags);
2073         return err;
2074 }
2075
2076 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2077                              struct ib_recv_wr **bad_wr)
2078 {
2079         struct mthca_dev *dev = to_mdev(ibqp->device);
2080         struct mthca_qp *qp = to_mqp(ibqp);
2081         unsigned long flags;
2082         int err = 0;
2083         int nreq;
2084         int ind;
2085         int i;
2086         void *wqe;
2087
2088         spin_lock_irqsave(&qp->rq.lock, flags);
2089
2090         /* XXX check that state is OK to post receive */
2091
2092         ind = qp->rq.head & (qp->rq.max - 1);
2093
2094         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2095                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2096                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
2097                                         " %d max, %d nreq)\n", qp->qpn,
2098                                         qp->rq.head, qp->rq.tail,
2099                                         qp->rq.max, nreq);
2100                         err = -ENOMEM;
2101                         *bad_wr = wr;
2102                         goto out;
2103                 }
2104
2105                 wqe = get_recv_wqe(qp, ind);
2106
2107                 ((struct mthca_next_seg *) wqe)->flags = 0;
2108
2109                 wqe += sizeof (struct mthca_next_seg);
2110
2111                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2112                         err = -EINVAL;
2113                         *bad_wr = wr;
2114                         goto out;
2115                 }
2116
2117                 for (i = 0; i < wr->num_sge; ++i) {
2118                         ((struct mthca_data_seg *) wqe)->byte_count =
2119                                 cpu_to_be32(wr->sg_list[i].length);
2120                         ((struct mthca_data_seg *) wqe)->lkey =
2121                                 cpu_to_be32(wr->sg_list[i].lkey);
2122                         ((struct mthca_data_seg *) wqe)->addr =
2123                                 cpu_to_be64(wr->sg_list[i].addr);
2124                         wqe += sizeof (struct mthca_data_seg);
2125                 }
2126
2127                 if (i < qp->rq.max_gs) {
2128                         ((struct mthca_data_seg *) wqe)->byte_count = 0;
2129                         ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
2130                         ((struct mthca_data_seg *) wqe)->addr = 0;
2131                 }
2132
2133                 qp->wrid[ind] = wr->wr_id;
2134
2135                 ++ind;
2136                 if (unlikely(ind >= qp->rq.max))
2137                         ind -= qp->rq.max;
2138         }
2139 out:
2140         if (likely(nreq)) {
2141                 qp->rq.head += nreq;
2142
2143                 /*
2144                  * Make sure that descriptors are written before
2145                  * doorbell record.
2146                  */
2147                 wmb();
2148                 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2149         }
2150
2151         spin_unlock_irqrestore(&qp->rq.lock, flags);
2152         return err;
2153 }
2154
2155 int mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2156                        int index, int *dbd, __be32 *new_wqe)
2157 {
2158         struct mthca_next_seg *next;
2159
2160         /*
2161          * For SRQs, all WQEs generate a CQE, so we're always at the
2162          * end of the doorbell chain.
2163          */
2164         if (qp->ibqp.srq) {
2165                 *new_wqe = 0;
2166                 return 0;
2167         }
2168
2169         if (is_send)
2170                 next = get_send_wqe(qp, index);
2171         else
2172                 next = get_recv_wqe(qp, index);
2173
2174         *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2175         if (next->ee_nds & cpu_to_be32(0x3f))
2176                 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2177                         (next->ee_nds & cpu_to_be32(0x3f));
2178         else
2179                 *new_wqe = 0;
2180
2181         return 0;
2182 }
2183
2184 int __devinit mthca_init_qp_table(struct mthca_dev *dev)
2185 {
2186         int err;
2187         u8 status;
2188         int i;
2189
2190         spin_lock_init(&dev->qp_table.lock);
2191
2192         /*
2193          * We reserve 2 extra QPs per port for the special QPs.  The
2194          * special QP for port 1 has to be even, so round up.
2195          */
2196         dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2197         err = mthca_alloc_init(&dev->qp_table.alloc,
2198                                dev->limits.num_qps,
2199                                (1 << 24) - 1,
2200                                dev->qp_table.sqp_start +
2201                                MTHCA_MAX_PORTS * 2);
2202         if (err)
2203                 return err;
2204
2205         err = mthca_array_init(&dev->qp_table.qp,
2206                                dev->limits.num_qps);
2207         if (err) {
2208                 mthca_alloc_cleanup(&dev->qp_table.alloc);
2209                 return err;
2210         }
2211
2212         for (i = 0; i < 2; ++i) {
2213                 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2214                                             dev->qp_table.sqp_start + i * 2,
2215                                             &status);
2216                 if (err)
2217                         goto err_out;
2218                 if (status) {
2219                         mthca_warn(dev, "CONF_SPECIAL_QP returned "
2220                                    "status %02x, aborting.\n",
2221                                    status);
2222                         err = -EINVAL;
2223                         goto err_out;
2224                 }
2225         }
2226         return 0;
2227
2228  err_out:
2229         for (i = 0; i < 2; ++i)
2230                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2231
2232         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2233         mthca_alloc_cleanup(&dev->qp_table.alloc);
2234
2235         return err;
2236 }
2237
2238 void __devexit mthca_cleanup_qp_table(struct mthca_dev *dev)
2239 {
2240         int i;
2241         u8 status;
2242
2243         for (i = 0; i < 2; ++i)
2244                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2245
2246         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2247         mthca_alloc_cleanup(&dev->qp_table.alloc);
2248 }