Merge ../linus
[linux-2.6] / arch / mips / tx4927 / toshiba_rbtx4927 / toshiba_rbtx4927_irq.c
1 /*
2  * linux/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
3  *
4  * Toshiba RBTX4927 specific interrupt handlers
5  *
6  * Author: MontaVista Software, Inc.
7  *         source@mvista.com
8  *
9  * Copyright 2001-2002 MontaVista Software Inc.
10  *
11  *  This program is free software; you can redistribute it and/or modify it
12  *  under the terms of the GNU General Public License as published by the
13  *  Free Software Foundation; either version 2 of the License, or (at your
14  *  option) any later version.
15  *
16  *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17  *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19  *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21  *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
22  *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23  *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
24  *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
25  *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26  *
27  *  You should have received a copy of the GNU General Public License along
28  *  with this program; if not, write to the Free Software Foundation, Inc.,
29  *  675 Mass Ave, Cambridge, MA 02139, USA.
30  */
31
32
33 /*
34 IRQ  Device
35 00   RBTX4927-ISA/00
36 01   RBTX4927-ISA/01 PS2/Keyboard
37 02   RBTX4927-ISA/02 Cascade RBTX4927-ISA (irqs 8-15)
38 03   RBTX4927-ISA/03
39 04   RBTX4927-ISA/04
40 05   RBTX4927-ISA/05
41 06   RBTX4927-ISA/06
42 07   RBTX4927-ISA/07
43 08   RBTX4927-ISA/08
44 09   RBTX4927-ISA/09
45 10   RBTX4927-ISA/10
46 11   RBTX4927-ISA/11
47 12   RBTX4927-ISA/12 PS2/Mouse (not supported at this time)
48 13   RBTX4927-ISA/13
49 14   RBTX4927-ISA/14 IDE
50 15   RBTX4927-ISA/15
51
52 16   TX4927-CP0/00 Software 0
53 17   TX4927-CP0/01 Software 1
54 18   TX4927-CP0/02 Cascade TX4927-CP0
55 19   TX4927-CP0/03 Multiplexed -- do not use
56 20   TX4927-CP0/04 Multiplexed -- do not use
57 21   TX4927-CP0/05 Multiplexed -- do not use
58 22   TX4927-CP0/06 Multiplexed -- do not use
59 23   TX4927-CP0/07 CPU TIMER
60
61 24   TX4927-PIC/00
62 25   TX4927-PIC/01
63 26   TX4927-PIC/02
64 27   TX4927-PIC/03 Cascade RBTX4927-IOC
65 28   TX4927-PIC/04
66 29   TX4927-PIC/05 RBTX4927 RTL-8019AS ethernet
67 30   TX4927-PIC/06
68 31   TX4927-PIC/07
69 32   TX4927-PIC/08 TX4927 SerialIO Channel 0
70 33   TX4927-PIC/09 TX4927 SerialIO Channel 1
71 34   TX4927-PIC/10
72 35   TX4927-PIC/11
73 36   TX4927-PIC/12
74 37   TX4927-PIC/13
75 38   TX4927-PIC/14
76 39   TX4927-PIC/15
77 40   TX4927-PIC/16 TX4927 PCI PCI-C
78 41   TX4927-PIC/17
79 42   TX4927-PIC/18
80 43   TX4927-PIC/19
81 44   TX4927-PIC/20
82 45   TX4927-PIC/21
83 46   TX4927-PIC/22 TX4927 PCI PCI-ERR
84 47   TX4927-PIC/23 TX4927 PCI PCI-PMA (not used)
85 48   TX4927-PIC/24
86 49   TX4927-PIC/25
87 50   TX4927-PIC/26
88 51   TX4927-PIC/27
89 52   TX4927-PIC/28
90 53   TX4927-PIC/29
91 54   TX4927-PIC/30
92 55   TX4927-PIC/31
93
94 56 RBTX4927-IOC/00 FPCIB0 PCI-D PJ4/A PJ5/B SB/C PJ6/D PJ7/A (SouthBridge/NotUsed)        [RTL-8139=PJ4]
95 57 RBTX4927-IOC/01 FPCIB0 PCI-C PJ4/D PJ5/A SB/B PJ6/C PJ7/D (SouthBridge/NotUsed)        [RTL-8139=PJ5]
96 58 RBTX4927-IOC/02 FPCIB0 PCI-B PJ4/C PJ5/D SB/A PJ6/B PJ7/C (SouthBridge/IDE/pin=1,INTR) [RTL-8139=NotSupported]
97 59 RBTX4927-IOC/03 FPCIB0 PCI-A PJ4/B PJ5/C SB/D PJ6/A PJ7/B (SouthBridge/USB/pin=4)      [RTL-8139=PJ6]
98 60 RBTX4927-IOC/04
99 61 RBTX4927-IOC/05
100 62 RBTX4927-IOC/06
101 63 RBTX4927-IOC/07
102
103 NOTES:
104 SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58
105 SouthBridge/ISA/pin=0 no pci irq used by this device
106 SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR via ISA IRQ14
107 SouthBridge/USB/pin=4 using pci irq SouthBridge/D=PCI-A=#59
108 SouthBridge/PMC/pin=0 no pci irq used by this device
109 SuperIO/PS2/Keyboard, using INTR via ISA IRQ1
110 SuperIO/PS2/Mouse, using INTR via ISA IRQ12 (mouse not currently supported)
111 JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthBridge, JP4, JP5, JP6
112 */
113
114 #include <linux/init.h>
115 #include <linux/kernel.h>
116 #include <linux/types.h>
117 #include <linux/mm.h>
118 #include <linux/swap.h>
119 #include <linux/ioport.h>
120 #include <linux/sched.h>
121 #include <linux/interrupt.h>
122 #include <linux/pci.h>
123 #include <linux/timex.h>
124 #include <asm/bootinfo.h>
125 #include <asm/page.h>
126 #include <asm/io.h>
127 #include <asm/irq.h>
128 #include <asm/pci.h>
129 #include <asm/processor.h>
130 #include <asm/reboot.h>
131 #include <asm/time.h>
132 #include <asm/wbflush.h>
133 #include <linux/bootmem.h>
134 #include <linux/blkdev.h>
135 #ifdef CONFIG_RTC_DS1742
136 #include <linux/ds1742rtc.h>
137 #endif
138 #ifdef CONFIG_TOSHIBA_FPCIB0
139 #include <asm/tx4927/smsc_fdc37m81x.h>
140 #endif
141 #include <asm/tx4927/toshiba_rbtx4927.h>
142
143
144 #undef TOSHIBA_RBTX4927_IRQ_DEBUG
145
146 #ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
147 #define TOSHIBA_RBTX4927_IRQ_NONE        0x00000000
148
149 #define TOSHIBA_RBTX4927_IRQ_INFO          ( 1 <<  0 )
150 #define TOSHIBA_RBTX4927_IRQ_WARN          ( 1 <<  1 )
151 #define TOSHIBA_RBTX4927_IRQ_EROR          ( 1 <<  2 )
152
153 #define TOSHIBA_RBTX4927_IRQ_IOC_INIT      ( 1 << 10 )
154 #define TOSHIBA_RBTX4927_IRQ_IOC_ENABLE    ( 1 << 13 )
155 #define TOSHIBA_RBTX4927_IRQ_IOC_DISABLE   ( 1 << 14 )
156
157 #define TOSHIBA_RBTX4927_IRQ_ISA_INIT      ( 1 << 20 )
158 #define TOSHIBA_RBTX4927_IRQ_ISA_ENABLE    ( 1 << 23 )
159 #define TOSHIBA_RBTX4927_IRQ_ISA_DISABLE   ( 1 << 24 )
160 #define TOSHIBA_RBTX4927_IRQ_ISA_MASK      ( 1 << 25 )
161
162 #define TOSHIBA_RBTX4927_SETUP_ALL         0xffffffff
163 #endif
164
165
166 #ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
167 static const u32 toshiba_rbtx4927_irq_debug_flag =
168     (TOSHIBA_RBTX4927_IRQ_NONE | TOSHIBA_RBTX4927_IRQ_INFO |
169      TOSHIBA_RBTX4927_IRQ_WARN | TOSHIBA_RBTX4927_IRQ_EROR
170 //                                                 | TOSHIBA_RBTX4927_IRQ_IOC_INIT
171 //                                                 | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE
172 //                                                 | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE
173 //                                                 | TOSHIBA_RBTX4927_IRQ_ISA_INIT
174 //                                                 | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE
175 //                                                 | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE
176 //                                                 | TOSHIBA_RBTX4927_IRQ_ISA_MASK
177     );
178 #endif
179
180
181 #ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
182 #define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag,str...) \
183         if ( (toshiba_rbtx4927_irq_debug_flag) & (flag) ) \
184         { \
185            char tmp[100]; \
186            sprintf( tmp, str ); \
187            printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
188         }
189 #else
190 #define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag,str...)
191 #endif
192
193
194
195
196 #define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG   0
197 #define TOSHIBA_RBTX4927_IRQ_IOC_RAW_END   7
198
199 #define TOSHIBA_RBTX4927_IRQ_IOC_BEG  ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG) /* 56 */
200 #define TOSHIBA_RBTX4927_IRQ_IOC_END  ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_END) /* 63 */
201
202
203 #define TOSHIBA_RBTX4927_IRQ_ISA_BEG MI8259_IRQ_ISA_BEG
204 #define TOSHIBA_RBTX4927_IRQ_ISA_END MI8259_IRQ_ISA_END
205 #define TOSHIBA_RBTX4927_IRQ_ISA_MID ((TOSHIBA_RBTX4927_IRQ_ISA_BEG+TOSHIBA_RBTX4927_IRQ_ISA_END+1)/2)
206
207
208 #define TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC TX4927_IRQ_NEST_EXT_ON_PIC
209 #define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC (TOSHIBA_RBTX4927_IRQ_IOC_BEG+2)
210 #define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA (TOSHIBA_RBTX4927_IRQ_ISA_BEG+2)
211
212 extern int tx4927_using_backplane;
213
214 #ifdef CONFIG_TOSHIBA_FPCIB0
215 extern void enable_8259A_irq(unsigned int irq);
216 extern void disable_8259A_irq(unsigned int irq);
217 extern void mask_and_ack_8259A(unsigned int irq);
218 #endif
219
220 static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq);
221 static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq);
222
223 #ifdef CONFIG_TOSHIBA_FPCIB0
224 static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq);
225 static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq);
226 static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq);
227 #endif
228
229 #define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC"
230 static struct irq_chip toshiba_rbtx4927_irq_ioc_type = {
231         .typename = TOSHIBA_RBTX4927_IOC_NAME,
232         .ack = toshiba_rbtx4927_irq_ioc_disable,
233         .mask = toshiba_rbtx4927_irq_ioc_disable,
234         .mask_ack = toshiba_rbtx4927_irq_ioc_disable,
235         .unmask = toshiba_rbtx4927_irq_ioc_enable,
236 };
237 #define TOSHIBA_RBTX4927_IOC_INTR_ENAB 0xbc002000
238 #define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006
239
240
241 #ifdef CONFIG_TOSHIBA_FPCIB0
242 #define TOSHIBA_RBTX4927_ISA_NAME "RBTX4927-ISA"
243 static struct irq_chip toshiba_rbtx4927_irq_isa_type = {
244         .typename = TOSHIBA_RBTX4927_ISA_NAME,
245         .ack = toshiba_rbtx4927_irq_isa_mask_and_ack,
246         .mask = toshiba_rbtx4927_irq_isa_disable,
247         .mask_ack = toshiba_rbtx4927_irq_isa_mask_and_ack,
248         .unmask = toshiba_rbtx4927_irq_isa_enable,
249 };
250 #endif
251
252
253 u32 bit2num(u32 num)
254 {
255         u32 i;
256
257         for (i = 0; i < (sizeof(num) * 8); i++) {
258                 if (num & (1 << i)) {
259                         return (i);
260                 }
261         }
262         return (0);
263 }
264
265 int toshiba_rbtx4927_irq_nested(int sw_irq)
266 {
267         u32 level3;
268         u32 level4;
269         u32 level5;
270
271         level3 = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
272         if (level3) {
273                 sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + bit2num(level3);
274                 if (sw_irq != TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC) {
275                         goto RETURN;
276                 }
277         }
278 #ifdef CONFIG_TOSHIBA_FPCIB0
279         {
280                 if (tx4927_using_backplane) {
281                         outb(0x0A, 0x20);
282                         level4 = inb(0x20) & 0xff;
283                         if (level4) {
284                                 sw_irq =
285                                     TOSHIBA_RBTX4927_IRQ_ISA_BEG +
286                                     bit2num(level4);
287                                 if (sw_irq !=
288                                     TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA) {
289                                         goto RETURN;
290                                 }
291                         }
292
293                         outb(0x0A, 0xA0);
294                         level5 = inb(0xA0) & 0xff;
295                         if (level5) {
296                                 sw_irq =
297                                     TOSHIBA_RBTX4927_IRQ_ISA_MID +
298                                     bit2num(level5);
299                                 goto RETURN;
300                         }
301                 }
302         }
303 #endif
304
305       RETURN:
306         return (sw_irq);
307 }
308
309 //#define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, 0, CPU_MASK_NONE, s, NULL, NULL }
310 #define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, IRQF_SHARED, CPU_MASK_NONE, s, NULL, NULL }
311 static struct irqaction toshiba_rbtx4927_irq_ioc_action =
312 TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_IOC_NAME);
313 #ifdef CONFIG_TOSHIBA_FPCIB0
314 static struct irqaction toshiba_rbtx4927_irq_isa_master =
315 TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_ISA_NAME "/M");
316 static struct irqaction toshiba_rbtx4927_irq_isa_slave =
317 TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_ISA_NAME "/S");
318 #endif
319
320
321 /**********************************************************************************/
322 /* Functions for ioc                                                              */
323 /**********************************************************************************/
324
325
326 static void __init toshiba_rbtx4927_irq_ioc_init(void)
327 {
328         int i;
329
330         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_INIT,
331                                      "beg=%d end=%d\n",
332                                      TOSHIBA_RBTX4927_IRQ_IOC_BEG,
333                                      TOSHIBA_RBTX4927_IRQ_IOC_END);
334
335         for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG;
336              i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++)
337                 set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type,
338                                          handle_level_irq);
339
340         setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC,
341                   &toshiba_rbtx4927_irq_ioc_action);
342 }
343
344 static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq)
345 {
346         volatile unsigned char v;
347
348         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENABLE,
349                                      "irq=%d\n", irq);
350
351         if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
352             || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
353                 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
354                                              "bad irq=%d\n", irq);
355                 panic("\n");
356         }
357
358         v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
359         v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
360         TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v);
361 }
362
363
364 static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)
365 {
366         volatile unsigned char v;
367
368         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_DISABLE,
369                                      "irq=%d\n", irq);
370
371         if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
372             || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
373                 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
374                                              "bad irq=%d\n", irq);
375                 panic("\n");
376         }
377
378         v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
379         v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
380         TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v);
381 }
382
383
384 /**********************************************************************************/
385 /* Functions for isa                                                              */
386 /**********************************************************************************/
387
388
389 #ifdef CONFIG_TOSHIBA_FPCIB0
390 static void __init toshiba_rbtx4927_irq_isa_init(void)
391 {
392         int i;
393
394         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_INIT,
395                                      "beg=%d end=%d\n",
396                                      TOSHIBA_RBTX4927_IRQ_ISA_BEG,
397                                      TOSHIBA_RBTX4927_IRQ_ISA_END);
398
399         for (i = TOSHIBA_RBTX4927_IRQ_ISA_BEG;
400              i <= TOSHIBA_RBTX4927_IRQ_ISA_END; i++)
401                 set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_isa_type,
402                                          handle_level_irq);
403
404         setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC,
405                   &toshiba_rbtx4927_irq_isa_master);
406         setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA,
407                   &toshiba_rbtx4927_irq_isa_slave);
408
409         /* make sure we are looking at IRR (not ISR) */
410         outb(0x0A, 0x20);
411         outb(0x0A, 0xA0);
412 }
413 #endif
414
415
416 #ifdef CONFIG_TOSHIBA_FPCIB0
417 static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq)
418 {
419         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_ENABLE,
420                                      "irq=%d\n", irq);
421
422         if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
423             || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
424                 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
425                                              "bad irq=%d\n", irq);
426                 panic("\n");
427         }
428
429         enable_8259A_irq(irq);
430 }
431 #endif
432
433
434 #ifdef CONFIG_TOSHIBA_FPCIB0
435 static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq)
436 {
437         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_DISABLE,
438                                      "irq=%d\n", irq);
439
440         if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
441             || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
442                 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
443                                              "bad irq=%d\n", irq);
444                 panic("\n");
445         }
446
447         disable_8259A_irq(irq);
448 }
449 #endif
450
451
452 #ifdef CONFIG_TOSHIBA_FPCIB0
453 static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq)
454 {
455         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_MASK,
456                                      "irq=%d\n", irq);
457
458         if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
459             || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
460                 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
461                                              "bad irq=%d\n", irq);
462                 panic("\n");
463         }
464
465         mask_and_ack_8259A(irq);
466 }
467 #endif
468
469
470 void __init arch_init_irq(void)
471 {
472         extern void tx4927_irq_init(void);
473
474         tx4927_irq_init();
475         toshiba_rbtx4927_irq_ioc_init();
476 #ifdef CONFIG_TOSHIBA_FPCIB0
477         {
478                 if (tx4927_using_backplane) {
479                         toshiba_rbtx4927_irq_isa_init();
480                 }
481         }
482 #endif
483
484         wbflush();
485 }
486
487 void toshiba_rbtx4927_irq_dump(char *key)
488 {
489 #ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
490         {
491                 u32 i, j = 0;
492                 for (i = 0; i < NR_IRQS; i++) {
493                         if (strcmp(irq_desc[i].chip->typename, "none")
494                             == 0)
495                                 continue;
496
497                         if ((i >= 1)
498                             && (irq_desc[i - 1].chip->typename ==
499                                 irq_desc[i].chip->typename)) {
500                                 j++;
501                         } else {
502                                 j = 0;
503                         }
504                         TOSHIBA_RBTX4927_IRQ_DPRINTK
505                             (TOSHIBA_RBTX4927_IRQ_INFO,
506                              "%s irq=0x%02x/%3d s=0x%08x h=0x%08x a=0x%08x ah=0x%08x d=%1d n=%s/%02d\n",
507                              key, i, i, irq_desc[i].status,
508                              (u32) irq_desc[i].chip,
509                              (u32) irq_desc[i].action,
510                              (u32) (irq_desc[i].action ? irq_desc[i].
511                                     action->handler : 0),
512                              irq_desc[i].depth,
513                              irq_desc[i].chip->typename, j);
514                 }
515         }
516 #endif
517 }
518
519 void toshiba_rbtx4927_irq_dump_pics(char *s)
520 {
521         u32 level0_m;
522         u32 level0_s;
523         u32 level1_m;
524         u32 level1_s;
525         u32 level2;
526         u32 level2_p;
527         u32 level2_s;
528         u32 level3_m;
529         u32 level3_s;
530         u32 level4_m;
531         u32 level4_s;
532         u32 level5_m;
533         u32 level5_s;
534
535         if (s == NULL)
536                 s = "null";
537
538         level0_m = (read_c0_status() & 0x0000ff00) >> 8;
539         level0_s = (read_c0_cause() & 0x0000ff00) >> 8;
540
541         level1_m = level0_m;
542         level1_s = level0_s & 0x87;
543
544         level2 = TX4927_RD(0xff1ff6a0);
545         level2_p = (((level2 & 0x10000)) ? 0 : 1);
546         level2_s = (((level2 & 0x1f) == 0x1f) ? 0 : (level2 & 0x1f));
547
548         level3_m = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_ENAB) & 0x1f;
549         level3_s = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
550
551         level4_m = inb(0x21);
552         outb(0x0A, 0x20);
553         level4_s = inb(0x20);
554
555         level5_m = inb(0xa1);
556         outb(0x0A, 0xa0);
557         level5_s = inb(0xa0);
558
559         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
560                                      "dump_raw_pic() ");
561         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
562                                      "cp0:m=0x%02x/s=0x%02x ", level0_m,
563                                      level0_s);
564         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
565                                      "cp0:m=0x%02x/s=0x%02x ", level1_m,
566                                      level1_s);
567         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
568                                      "pic:e=0x%02x/s=0x%02x ", level2_p,
569                                      level2_s);
570         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
571                                      "ioc:m=0x%02x/s=0x%02x ", level3_m,
572                                      level3_s);
573         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
574                                      "sbm:m=0x%02x/s=0x%02x ", level4_m,
575                                      level4_s);
576         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
577                                      "sbs:m=0x%02x/s=0x%02x ", level5_m,
578                                      level5_s);
579         TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, "[%s]\n",
580                                      s);
581 }