git.oblomov.eu Git - linux-2.6/blob - arch/ppc/platforms/4xx/ibm440gx.c

   1 /*
   2  * PPC440GX I/O descriptions
   3  *
   4  * Matt Porter <mporter@mvista.com>
   5  * Copyright 2002-2004 MontaVista Software Inc.
   6  *
   7  * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
   8  * Copyright (c) 2003, 2004 Zultys Technologies
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  *
  15  */
  16 #include <linux/init.h>
  17 #include <linux/module.h>
  18 #include <platforms/4xx/ibm440gx.h>
  19 #include <asm/ocp.h>
  20 #include <asm/ppc4xx_pic.h>
  21
  22 static struct ocp_func_emac_data ibm440gx_emac0_def = {
  23         .rgmii_idx      = -1,           /* No RGMII */
  24         .rgmii_mux      = -1,           /* No RGMII */
  25         .zmii_idx       = 0,            /* ZMII device index */
  26         .zmii_mux       = 0,            /* ZMII input of this EMAC */
  27         .mal_idx        = 0,            /* MAL device index */
  28         .mal_rx_chan    = 0,            /* MAL rx channel number */
  29         .mal_tx_chan    = 0,            /* MAL tx channel number */
  30         .wol_irq        = 61,           /* WOL interrupt number */
  31         .mdio_idx       = -1,           /* No shared MDIO */
  32         .tah_idx        = -1,           /* No TAH */
  33 };
  34
  35 static struct ocp_func_emac_data ibm440gx_emac1_def = {
  36         .rgmii_idx      = -1,           /* No RGMII */
  37         .rgmii_mux      = -1,           /* No RGMII */
  38         .zmii_idx       = 0,            /* ZMII device index */
  39         .zmii_mux       = 1,            /* ZMII input of this EMAC */
  40         .mal_idx        = 0,            /* MAL device index */
  41         .mal_rx_chan    = 1,            /* MAL rx channel number */
  42         .mal_tx_chan    = 1,            /* MAL tx channel number */
  43         .wol_irq        = 63,           /* WOL interrupt number */
  44         .mdio_idx       = -1,           /* No shared MDIO */
  45         .tah_idx        = -1,           /* No TAH */
  46 };
  47
  48 static struct ocp_func_emac_data ibm440gx_emac2_def = {
  49         .rgmii_idx      = 0,            /* RGMII device index */
  50         .rgmii_mux      = 0,            /* RGMII input of this EMAC */
  51         .zmii_idx       = 0,            /* ZMII device index */
  52         .zmii_mux       = 2,            /* ZMII input of this EMAC */
  53         .mal_idx        = 0,            /* MAL device index */
  54         .mal_rx_chan    = 2,            /* MAL rx channel number */
  55         .mal_tx_chan    = 2,            /* MAL tx channel number */
  56         .wol_irq        = 65,           /* WOL interrupt number */
  57         .mdio_idx       = -1,           /* No shared MDIO */
  58         .tah_idx        = 0,            /* TAH device index */
  59 };
  60
  61 static struct ocp_func_emac_data ibm440gx_emac3_def = {
  62         .rgmii_idx      = 0,            /* RGMII device index */
  63         .rgmii_mux      = 1,            /* RGMII input of this EMAC */
  64         .zmii_idx       = 0,            /* ZMII device index */
  65         .zmii_mux       = 3,            /* ZMII input of this EMAC */
  66         .mal_idx        = 0,            /* MAL device index */
  67         .mal_rx_chan    = 3,            /* MAL rx channel number */
  68         .mal_tx_chan    = 3,            /* MAL tx channel number */
  69         .wol_irq        = 67,           /* WOL interrupt number */
  70         .mdio_idx       = -1,           /* No shared MDIO */
  71         .tah_idx        = 1,            /* TAH device index */
  72 };
  73 OCP_SYSFS_EMAC_DATA()
  74
  75 static struct ocp_func_mal_data ibm440gx_mal0_def = {
  76         .num_tx_chans   = 4,            /* Number of TX channels */
  77         .num_rx_chans   = 4,            /* Number of RX channels */
  78         .txeob_irq      = 10,           /* TX End Of Buffer IRQ  */
  79         .rxeob_irq      = 11,           /* RX End Of Buffer IRQ  */
  80         .txde_irq       = 33,           /* TX Descriptor Error IRQ */
  81         .rxde_irq       = 34,           /* RX Descriptor Error IRQ */
  82         .serr_irq       = 32,           /* MAL System Error IRQ    */
  83         .dcr_base       = DCRN_MAL_BASE /* MAL0_CFG DCR number */
  84 };
  85 OCP_SYSFS_MAL_DATA()
  86
  87 static struct ocp_func_iic_data ibm440gx_iic0_def = {
  88         .fast_mode      = 0,            /* Use standad mode (100Khz) */
  89 };
  90
  91 static struct ocp_func_iic_data ibm440gx_iic1_def = {
  92         .fast_mode      = 0,            /* Use standad mode (100Khz) */
  93 };
  94 OCP_SYSFS_IIC_DATA()
  95
  96 struct ocp_def core_ocp[] = {
  97         { .vendor       = OCP_VENDOR_IBM,
  98           .function     = OCP_FUNC_OPB,
  99           .index        = 0,
 100           .paddr        = 0x0000000140000000ULL,
 101           .irq          = OCP_IRQ_NA,
 102           .pm           = OCP_CPM_NA,
 103         },
 104         { .vendor       = OCP_VENDOR_IBM,
 105           .function     = OCP_FUNC_16550,
 106           .index        = 0,
 107           .paddr        = PPC440GX_UART0_ADDR,
 108           .irq          = UART0_INT,
 109           .pm           = IBM_CPM_UART0,
 110         },
 111         { .vendor       = OCP_VENDOR_IBM,
 112           .function     = OCP_FUNC_16550,
 113           .index        = 1,
 114           .paddr        = PPC440GX_UART1_ADDR,
 115           .irq          = UART1_INT,
 116           .pm           = IBM_CPM_UART1,
 117         },
 118         { .vendor       = OCP_VENDOR_IBM,
 119           .function     = OCP_FUNC_IIC,
 120           .index        = 0,
 121           .paddr        = 0x0000000140000400ULL,
 122           .irq          = 2,
 123           .pm           = IBM_CPM_IIC0,
 124           .additions    = &ibm440gx_iic0_def,
 125           .show         = &ocp_show_iic_data
 126         },
 127         { .vendor       = OCP_VENDOR_IBM,
 128           .function     = OCP_FUNC_IIC,
 129           .index        = 1,
 130           .paddr        = 0x0000000140000500ULL,
 131           .irq          = 3,
 132           .pm           = IBM_CPM_IIC1,
 133           .additions    = &ibm440gx_iic1_def,
 134           .show         = &ocp_show_iic_data
 135         },
 136         { .vendor       = OCP_VENDOR_IBM,
 137           .function     = OCP_FUNC_GPIO,
 138           .index        = 0,
 139           .paddr        = 0x0000000140000700ULL,
 140           .irq          = OCP_IRQ_NA,
 141           .pm           = IBM_CPM_GPIO0,
 142         },
 143         { .vendor       = OCP_VENDOR_IBM,
 144           .function     = OCP_FUNC_MAL,
 145           .paddr        = OCP_PADDR_NA,
 146           .irq          = OCP_IRQ_NA,
 147           .pm           = OCP_CPM_NA,
 148           .additions    = &ibm440gx_mal0_def,
 149           .show         = &ocp_show_mal_data,
 150         },
 151         { .vendor       = OCP_VENDOR_IBM,
 152           .function     = OCP_FUNC_EMAC,
 153           .index        = 0,
 154           .paddr        = 0x0000000140000800ULL,
 155           .irq          = 60,
 156           .pm           = OCP_CPM_NA,
 157           .additions    = &ibm440gx_emac0_def,
 158           .show         = &ocp_show_emac_data,
 159         },
 160         { .vendor       = OCP_VENDOR_IBM,
 161           .function     = OCP_FUNC_EMAC,
 162           .index        = 1,
 163           .paddr        = 0x0000000140000900ULL,
 164           .irq          = 62,
 165           .pm           = OCP_CPM_NA,
 166           .additions    = &ibm440gx_emac1_def,
 167           .show         = &ocp_show_emac_data,
 168         },
 169         { .vendor       = OCP_VENDOR_IBM,
 170           .function     = OCP_FUNC_EMAC,
 171           .index        = 2,
 172           .paddr        = 0x0000000140000C00ULL,
 173           .irq          = 64,
 174           .pm           = OCP_CPM_NA,
 175           .additions    = &ibm440gx_emac2_def,
 176           .show         = &ocp_show_emac_data,
 177         },
 178         { .vendor       = OCP_VENDOR_IBM,
 179           .function     = OCP_FUNC_EMAC,
 180           .index        = 3,
 181           .paddr        = 0x0000000140000E00ULL,
 182           .irq          = 66,
 183           .pm           = OCP_CPM_NA,
 184           .additions    = &ibm440gx_emac3_def,
 185           .show         = &ocp_show_emac_data,
 186         },
 187         { .vendor       = OCP_VENDOR_IBM,
 188           .function     = OCP_FUNC_RGMII,
 189           .paddr        = 0x0000000140000790ULL,
 190           .irq          = OCP_IRQ_NA,
 191           .pm           = OCP_CPM_NA,
 192         },
 193         { .vendor       = OCP_VENDOR_IBM,
 194           .function     = OCP_FUNC_ZMII,
 195           .paddr        = 0x0000000140000780ULL,
 196           .irq          = OCP_IRQ_NA,
 197           .pm           = OCP_CPM_NA,
 198         },
 199         { .vendor       = OCP_VENDOR_IBM,
 200           .function     = OCP_FUNC_TAH,
 201           .index        = 0,
 202           .paddr        = 0x0000000140000b50ULL,
 203           .irq          = 68,
 204           .pm           = OCP_CPM_NA,
 205         },
 206         { .vendor       = OCP_VENDOR_IBM,
 207           .function     = OCP_FUNC_TAH,
 208           .index        = 1,
 209           .paddr        = 0x0000000140000d50ULL,
 210           .irq          = 69,
 211           .pm           = OCP_CPM_NA,
 212         },
 213         { .vendor       = OCP_VENDOR_INVALID
 214         }
 215 };
 216
 217 /* Polarity and triggering settings for internal interrupt sources */
 218 struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
 219         { .polarity     = 0xfffffe03,
 220           .triggering   = 0x01c00000,
 221           .ext_irq_mask = 0x000001fc,   /* IRQ0 - IRQ6 */
 222         },
 223         { .polarity     = 0xffffc0ff,
 224           .triggering   = 0x00ff8000,
 225           .ext_irq_mask = 0x00003f00,   /* IRQ7 - IRQ12 */
 226         },
 227         { .polarity     = 0xffff83ff,
 228           .triggering   = 0x000f83c0,
 229           .ext_irq_mask = 0x00007c00,   /* IRQ13 - IRQ17 */
 230         },
 231 };