2 * arch/s390/kernel/entry64.S
3 * S390 low-level entry points.
5 * Copyright (C) IBM Corp. 1999,2006
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
7 * Hartmut Penner (hp@de.ibm.com),
8 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
9 * Heiko Carstens <heiko.carstens@de.ibm.com>
12 #include <linux/sys.h>
13 #include <linux/linkage.h>
14 #include <asm/cache.h>
15 #include <asm/lowcore.h>
16 #include <asm/errno.h>
17 #include <asm/ptrace.h>
18 #include <asm/thread_info.h>
19 #include <asm/asm-offsets.h>
20 #include <asm/unistd.h>
24 * Stack layout for the system_call stack entry.
25 * The first few entries are identical to the user_regs_struct.
27 SP_PTREGS = STACK_FRAME_OVERHEAD
28 SP_ARGS = STACK_FRAME_OVERHEAD + __PT_ARGS
29 SP_PSW = STACK_FRAME_OVERHEAD + __PT_PSW
30 SP_R0 = STACK_FRAME_OVERHEAD + __PT_GPRS
31 SP_R1 = STACK_FRAME_OVERHEAD + __PT_GPRS + 8
32 SP_R2 = STACK_FRAME_OVERHEAD + __PT_GPRS + 16
33 SP_R3 = STACK_FRAME_OVERHEAD + __PT_GPRS + 24
34 SP_R4 = STACK_FRAME_OVERHEAD + __PT_GPRS + 32
35 SP_R5 = STACK_FRAME_OVERHEAD + __PT_GPRS + 40
36 SP_R6 = STACK_FRAME_OVERHEAD + __PT_GPRS + 48
37 SP_R7 = STACK_FRAME_OVERHEAD + __PT_GPRS + 56
38 SP_R8 = STACK_FRAME_OVERHEAD + __PT_GPRS + 64
39 SP_R9 = STACK_FRAME_OVERHEAD + __PT_GPRS + 72
40 SP_R10 = STACK_FRAME_OVERHEAD + __PT_GPRS + 80
41 SP_R11 = STACK_FRAME_OVERHEAD + __PT_GPRS + 88
42 SP_R12 = STACK_FRAME_OVERHEAD + __PT_GPRS + 96
43 SP_R13 = STACK_FRAME_OVERHEAD + __PT_GPRS + 104
44 SP_R14 = STACK_FRAME_OVERHEAD + __PT_GPRS + 112
45 SP_R15 = STACK_FRAME_OVERHEAD + __PT_GPRS + 120
46 SP_ORIG_R2 = STACK_FRAME_OVERHEAD + __PT_ORIG_GPR2
47 SP_ILC = STACK_FRAME_OVERHEAD + __PT_ILC
48 SP_TRAP = STACK_FRAME_OVERHEAD + __PT_TRAP
49 SP_SIZE = STACK_FRAME_OVERHEAD + __PT_SIZE
51 STACK_SHIFT = PAGE_SHIFT + THREAD_ORDER
52 STACK_SIZE = 1 << STACK_SHIFT
54 _TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK | _TIF_NEED_RESCHED | \
55 _TIF_MCCK_PENDING | _TIF_RESTART_SVC | _TIF_SINGLE_STEP )
56 _TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK | _TIF_NEED_RESCHED | \
59 #define BASED(name) name-system_call(%r13)
61 #ifdef CONFIG_TRACE_IRQFLAGS
63 brasl %r14,trace_hardirqs_on
67 brasl %r14,trace_hardirqs_off
71 #define TRACE_IRQS_OFF
74 .macro STORE_TIMER lc_offset
75 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
80 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
81 .macro UPDATE_VTIME lc_from,lc_to,lc_sum
90 * Register usage in interrupt handlers:
91 * R9 - pointer to current task structure
92 * R13 - pointer to literal pool
93 * R14 - return register for function calls
94 * R15 - kernel stack pointer
97 .macro SAVE_ALL_BASE savearea
98 stmg %r12,%r15,\savearea
102 .macro SAVE_ALL_SYNC psworg,savearea
104 tm \psworg+1,0x01 # test problem state bit
105 jz 2f # skip stack setup save
106 lg %r15,__LC_KERNEL_STACK # problem state -> load ksp
107 #ifdef CONFIG_CHECK_STACK
109 2: tml %r15,STACK_SIZE - CONFIG_STACK_GUARD
116 .macro SAVE_ALL_ASYNC psworg,savearea
118 tm \psworg+1,0x01 # test problem state bit
119 jnz 1f # from user -> load kernel stack
120 clc \psworg+8(8),BASED(.Lcritical_end)
122 clc \psworg+8(8),BASED(.Lcritical_start)
124 brasl %r14,cleanup_critical
125 tm 1(%r12),0x01 # retest problem state after cleanup
127 0: lg %r14,__LC_ASYNC_STACK # are we already on the async. stack ?
129 srag %r14,%r14,STACK_SHIFT
131 1: lg %r15,__LC_ASYNC_STACK # load async stack
132 #ifdef CONFIG_CHECK_STACK
134 2: tml %r15,STACK_SIZE - CONFIG_STACK_GUARD
141 .macro CREATE_STACK_FRAME psworg,savearea
142 aghi %r15,-SP_SIZE # make room for registers & psw
143 mvc SP_PSW(16,%r15),0(%r12) # move user PSW to stack
145 stg %r2,SP_ORIG_R2(%r15) # store original content of gpr 2
146 icm %r12,12,__LC_SVC_ILC
147 stmg %r0,%r11,SP_R0(%r15) # store gprs %r0-%r11 to kernel stack
149 mvc SP_R12(32,%r15),\savearea # move %r12-%r15 to stack
151 stg %r12,__SF_BACKCHAIN(%r15)
154 .macro RESTORE_ALL psworg,sync
155 mvc \psworg(16),SP_PSW(%r15) # move user PSW to lowcore
157 ni \psworg+1,0xfd # clear wait state bit
159 lmg %r0,%r15,SP_R0(%r15) # load gprs 0-15 of user
160 STORE_TIMER __LC_EXIT_TIMER
161 lpswe \psworg # back to caller
165 * Scheduler resume function, called by switch_to
166 * gpr2 = (task_struct *) prev
167 * gpr3 = (task_struct *) next
173 tm __THREAD_per+4(%r3),0xe8 # is the new process using per ?
174 jz __switch_to_noper # if not we're fine
175 stctg %c9,%c11,__SF_EMPTY(%r15)# We are using per stuff
176 clc __THREAD_per(24,%r3),__SF_EMPTY(%r15)
177 je __switch_to_noper # we got away without bashing TLB's
178 lctlg %c9,%c11,__THREAD_per(%r3) # Nope we didn't
180 lg %r4,__THREAD_info(%r2) # get thread_info of prev
181 tm __TI_flags+7(%r4),_TIF_MCCK_PENDING # machine check pending?
182 jz __switch_to_no_mcck
183 ni __TI_flags+7(%r4),255-_TIF_MCCK_PENDING # clear flag in prev
184 lg %r4,__THREAD_info(%r3) # get thread_info of next
185 oi __TI_flags+7(%r4),_TIF_MCCK_PENDING # set it in next
187 stmg %r6,%r15,__SF_GPRS(%r15)# store __switch_to registers of prev task
188 stg %r15,__THREAD_ksp(%r2) # store kernel stack to prev->tss.ksp
189 lg %r15,__THREAD_ksp(%r3) # load kernel stack from next->tss.ksp
190 lmg %r6,%r15,__SF_GPRS(%r15)# load __switch_to registers of next task
191 stg %r3,__LC_CURRENT # __LC_CURRENT = current task struct
192 lctl %c4,%c4,__TASK_pid(%r3) # load pid to control reg. 4
193 lg %r3,__THREAD_info(%r3) # load thread_info from task struct
194 stg %r3,__LC_THREAD_INFO
196 stg %r3,__LC_KERNEL_STACK # __LC_KERNEL_STACK = new kernel stack
201 * SVC interrupt handler routine. System calls are synchronous events and
202 * are executed with interrupts enabled.
207 STORE_TIMER __LC_SYNC_ENTER_TIMER
209 SAVE_ALL_BASE __LC_SAVE_AREA
210 SAVE_ALL_SYNC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
211 CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA
212 llgh %r7,__LC_SVC_INT_CODE # get svc number from lowcore
213 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
215 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
217 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
219 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
221 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
224 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
225 slag %r7,%r7,2 # *4 and test for svc 0
227 # svc 0: system call number in %r1
228 cl %r1,BASED(.Lnr_syscalls)
230 lgfr %r7,%r1 # clear high word in r1
231 slag %r7,%r7,2 # svc 0: system call number in %r1
233 mvc SP_ARGS(8,%r15),SP_R7(%r15)
235 larl %r10,sys_call_table
237 tm __TI_flags+5(%r9),(_TIF_31BIT>>16) # running in 31 bit mode ?
239 larl %r10,sys_call_table_emu # use 31 bit emulation system calls
242 tm __TI_flags+7(%r9),(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT)
243 lgf %r8,0(%r7,%r10) # load address of system call routine
245 basr %r14,%r8 # call sys_xxxx
246 stg %r2,SP_R2(%r15) # store return value (change R2 on stack)
247 # ATTENTION: check sys_execve_glue before
248 # changing anything here !!
251 tm SP_PSW+1(%r15),0x01 # returning to user ?
253 tm __TI_flags+7(%r9),_TIF_WORK_SVC
254 jnz sysc_work # there is work to do (signals etc.)
256 RESTORE_ALL __LC_RETURN_PSW,1
259 # recheck if there is more work to do
262 tm __TI_flags+7(%r9),_TIF_WORK_SVC
263 jz sysc_leave # there is no work to do
265 # One of the work bits is on. Find out which one.
268 tm __TI_flags+7(%r9),_TIF_MCCK_PENDING
270 tm __TI_flags+7(%r9),_TIF_NEED_RESCHED
272 tm __TI_flags+7(%r9),(_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK)
274 tm __TI_flags+7(%r9),_TIF_RESTART_SVC
276 tm __TI_flags+7(%r9),_TIF_SINGLE_STEP
281 # _TIF_NEED_RESCHED is set, call schedule
284 larl %r14,sysc_work_loop
285 jg schedule # return point is sysc_return
288 # _TIF_MCCK_PENDING is set, call handler
291 larl %r14,sysc_work_loop
292 jg s390_handle_mcck # TIF bit will be cleared by handler
295 # _TIF_SIGPENDING or _TIF_RESTORE_SIGMASK is set, call do_signal
298 ni __TI_flags+7(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP
299 la %r2,SP_PTREGS(%r15) # load pt_regs
300 brasl %r14,do_signal # call do_signal
301 tm __TI_flags+7(%r9),_TIF_RESTART_SVC
303 tm __TI_flags+7(%r9),_TIF_SINGLE_STEP
308 # _TIF_RESTART_SVC is set, set up registers and restart svc
311 ni __TI_flags+7(%r9),255-_TIF_RESTART_SVC # clear TIF_RESTART_SVC
312 lg %r7,SP_R2(%r15) # load new svc number
314 mvc SP_R2(8,%r15),SP_ORIG_R2(%r15) # restore first argument
315 lmg %r2,%r6,SP_R2(%r15) # load svc arguments
316 j sysc_do_restart # restart svc
319 # _TIF_SINGLE_STEP is set, call do_single_step
322 ni __TI_flags+7(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP
323 lhi %r0,__LC_PGM_OLD_PSW
324 sth %r0,SP_TRAP(%r15) # set trap indication to pgm check
325 la %r2,SP_PTREGS(%r15) # address of register-save area
326 larl %r14,sysc_return # load adr. of system return
327 jg do_single_step # branch to do_sigtrap
330 # call syscall_trace before and after system call
331 # special linkage: %r12 contains the return address for trace_svc
334 la %r2,SP_PTREGS(%r15) # load pt_regs
338 brasl %r14,syscall_trace
342 lg %r7,SP_R2(%r15) # strace might have changed the
343 sll %r7,2 # system call
346 lmg %r3,%r6,SP_R3(%r15)
347 lg %r2,SP_ORIG_R2(%r15)
348 basr %r14,%r8 # call sys_xxx
349 stg %r2,SP_R2(%r15) # store return value
351 tm __TI_flags+7(%r9),(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT)
353 la %r2,SP_PTREGS(%r15) # load pt_regs
355 larl %r14,sysc_return # return point is sysc_return
359 # a new process exits the kernel with ret_from_fork
363 lg %r13,__LC_SVC_NEW_PSW+8
364 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
365 tm SP_PSW+1(%r15),0x01 # forking a kernel thread ?
367 stg %r15,SP_R15(%r15) # store stack pointer for new kthread
368 0: brasl %r14,schedule_tail
370 stosm 24(%r15),0x03 # reenable interrupts
374 # clone, fork, vfork, exec and sigreturn need glue,
375 # because they all expect pt_regs as parameter,
376 # but are called with different parameter.
377 # return-address is set up above
380 la %r2,SP_PTREGS(%r15) # load pt_regs
381 jg sys_clone # branch to sys_clone
385 la %r2,SP_PTREGS(%r15) # load pt_regs
386 jg sys32_clone # branch to sys32_clone
390 la %r2,SP_PTREGS(%r15) # load pt_regs
391 jg sys_fork # branch to sys_fork
394 la %r2,SP_PTREGS(%r15) # load pt_regs
395 jg sys_vfork # branch to sys_vfork
398 la %r2,SP_PTREGS(%r15) # load pt_regs
399 lgr %r12,%r14 # save return address
400 brasl %r14,sys_execve # call sys_execve
401 ltgr %r2,%r2 # check if execve failed
402 bnz 0(%r12) # it did fail -> store result in gpr2
403 b 6(%r12) # SKIP STG 2,SP_R2(15) in
404 # system_call/sysc_tracesys
407 la %r2,SP_PTREGS(%r15) # load pt_regs
408 lgr %r12,%r14 # save return address
409 brasl %r14,sys32_execve # call sys32_execve
410 ltgr %r2,%r2 # check if execve failed
411 bnz 0(%r12) # it did fail -> store result in gpr2
412 b 6(%r12) # SKIP STG 2,SP_R2(15) in
413 # system_call/sysc_tracesys
417 la %r2,SP_PTREGS(%r15) # load pt_regs as parameter
418 jg sys_sigreturn # branch to sys_sigreturn
421 sys32_sigreturn_glue:
422 la %r2,SP_PTREGS(%r15) # load pt_regs as parameter
423 jg sys32_sigreturn # branch to sys32_sigreturn
426 sys_rt_sigreturn_glue:
427 la %r2,SP_PTREGS(%r15) # load pt_regs as parameter
428 jg sys_rt_sigreturn # branch to sys_sigreturn
431 sys32_rt_sigreturn_glue:
432 la %r2,SP_PTREGS(%r15) # load pt_regs as parameter
433 jg sys32_rt_sigreturn # branch to sys32_sigreturn
436 sys_sigaltstack_glue:
437 la %r4,SP_PTREGS(%r15) # load pt_regs as parameter
438 jg sys_sigaltstack # branch to sys_sigreturn
441 sys32_sigaltstack_glue:
442 la %r4,SP_PTREGS(%r15) # load pt_regs as parameter
443 jg sys32_sigaltstack_wrapper # branch to sys_sigreturn
447 * Program check handler routine
450 .globl pgm_check_handler
453 * First we need to check for a special case:
454 * Single stepping an instruction that disables the PER event mask will
455 * cause a PER event AFTER the mask has been set. Example: SVC or LPSW.
456 * For a single stepped SVC the program check handler gets control after
457 * the SVC new PSW has been loaded. But we want to execute the SVC first and
458 * then handle the PER event. Therefore we update the SVC old PSW to point
459 * to the pgm_check_handler and branch to the SVC handler after we checked
460 * if we have to load the kernel stack register.
461 * For every other possible cause for PER event without the PER mask set
462 * we just ignore the PER event (FIXME: is there anything we have to do
465 STORE_TIMER __LC_SYNC_ENTER_TIMER
466 SAVE_ALL_BASE __LC_SAVE_AREA
467 tm __LC_PGM_INT_CODE+1,0x80 # check whether we got a per exception
468 jnz pgm_per # got per exception -> special case
469 SAVE_ALL_SYNC __LC_PGM_OLD_PSW,__LC_SAVE_AREA
470 CREATE_STACK_FRAME __LC_PGM_OLD_PSW,__LC_SAVE_AREA
471 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
472 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
474 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
475 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
476 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
479 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
480 lgf %r3,__LC_PGM_ILC # load program interruption code
485 larl %r1,pgm_check_table
486 lg %r1,0(%r8,%r1) # load address of handler routine
487 la %r2,SP_PTREGS(%r15) # address of register-save area
488 larl %r14,sysc_return
489 br %r1 # branch to interrupt-handler
492 # handle per exception
495 tm __LC_PGM_OLD_PSW,0x40 # test if per event recording is on
496 jnz pgm_per_std # ok, normal per event from user space
497 # ok its one of the special cases, now we need to find out which one
498 clc __LC_PGM_OLD_PSW(16),__LC_SVC_NEW_PSW
500 # no interesting special case, ignore PER event
501 lmg %r12,%r15,__LC_SAVE_AREA
502 lpswe __LC_PGM_OLD_PSW
505 # Normal per exception
508 SAVE_ALL_SYNC __LC_PGM_OLD_PSW,__LC_SAVE_AREA
509 CREATE_STACK_FRAME __LC_PGM_OLD_PSW,__LC_SAVE_AREA
510 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
511 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
513 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
514 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
515 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
518 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
519 lg %r1,__TI_task(%r9)
520 tm SP_PSW+1(%r15),0x01 # kernel per event ?
522 mvc __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID
523 mvc __THREAD_per+__PER_address(8,%r1),__LC_PER_ADDRESS
524 mvc __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID
525 oi __TI_flags+7(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP
526 lgf %r3,__LC_PGM_ILC # load program interruption code
528 ngr %r8,%r3 # clear per-event-bit and ilc
533 # it was a single stepped SVC that is causing all the trouble
536 SAVE_ALL_SYNC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
537 CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA
538 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
539 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
541 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
542 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
543 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
546 llgh %r7,__LC_SVC_INT_CODE # get svc number from lowcore
547 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
548 lg %r1,__TI_task(%r9)
549 mvc __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID
550 mvc __THREAD_per+__PER_address(8,%r1),__LC_PER_ADDRESS
551 mvc __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID
552 oi __TI_flags+7(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP
554 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
558 # per was called from kernel, must be kprobes
561 lhi %r0,__LC_PGM_OLD_PSW
562 sth %r0,SP_TRAP(%r15) # set trap indication to pgm check
563 la %r2,SP_PTREGS(%r15) # address of register-save area
564 larl %r14,sysc_leave # load adr. of system ret, no work
565 jg do_single_step # branch to do_single_step
568 * IO interrupt handler routine
570 .globl io_int_handler
572 STORE_TIMER __LC_ASYNC_ENTER_TIMER
574 SAVE_ALL_BASE __LC_SAVE_AREA+32
575 SAVE_ALL_ASYNC __LC_IO_OLD_PSW,__LC_SAVE_AREA+32
576 CREATE_STACK_FRAME __LC_IO_OLD_PSW,__LC_SAVE_AREA+32
577 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
578 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
580 UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
581 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
582 mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
585 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
587 la %r2,SP_PTREGS(%r15) # address of register-save area
588 brasl %r14,do_IRQ # call standard irq handler
592 tm SP_PSW+1(%r15),0x01 # returning to user ?
593 #ifdef CONFIG_PREEMPT
594 jno io_preempt # no -> check for preemptive scheduling
596 jno io_leave # no-> skip resched & signal
598 tm __TI_flags+7(%r9),_TIF_WORK_INT
599 jnz io_work # there is work to do (signals etc.)
601 RESTORE_ALL __LC_RETURN_PSW,0
604 #ifdef CONFIG_PREEMPT
606 icm %r0,15,__TI_precount(%r9)
608 # switch to kernel stack
611 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
612 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
615 tm __TI_flags+7(%r9),_TIF_NEED_RESCHED
618 mvc __TI_precount(4,%r9),0(%r1)
619 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
620 brasl %r14,schedule # call schedule
621 stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts
622 xc __TI_precount(4,%r9),__TI_precount(%r9)
627 # switch to kernel stack, then check TIF bits
630 lg %r1,__LC_KERNEL_STACK
632 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
633 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
636 # One of the work bits is on. Find out which one.
637 # Checked are: _TIF_SIGPENDING, _TIF_RESTORE_SIGPENDING, _TIF_NEED_RESCHED
638 # and _TIF_MCCK_PENDING
641 tm __TI_flags+7(%r9),_TIF_MCCK_PENDING
643 tm __TI_flags+7(%r9),_TIF_NEED_RESCHED
645 tm __TI_flags+7(%r9),(_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK)
650 # _TIF_MCCK_PENDING is set, call handler
653 larl %r14,io_work_loop
654 jg s390_handle_mcck # TIF bit will be cleared by handler
657 # _TIF_NEED_RESCHED is set, call schedule
660 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
661 brasl %r14,schedule # call scheduler
662 stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts
663 tm __TI_flags+7(%r9),_TIF_WORK_INT
664 jz io_leave # there is no work to do
668 # _TIF_SIGPENDING or _TIF_RESTORE_SIGMASK is set, call do_signal
671 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
672 la %r2,SP_PTREGS(%r15) # load pt_regs
673 brasl %r14,do_signal # call do_signal
674 stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts
678 * External interrupt handler routine
680 .globl ext_int_handler
682 STORE_TIMER __LC_ASYNC_ENTER_TIMER
684 SAVE_ALL_BASE __LC_SAVE_AREA+32
685 SAVE_ALL_ASYNC __LC_EXT_OLD_PSW,__LC_SAVE_AREA+32
686 CREATE_STACK_FRAME __LC_EXT_OLD_PSW,__LC_SAVE_AREA+32
687 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
688 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
690 UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
691 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
692 mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
695 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
697 la %r2,SP_PTREGS(%r15) # address of register-save area
698 llgh %r3,__LC_EXT_INT_CODE # get interruption code
706 * Machine check handler routines
708 .globl mcck_int_handler
710 la %r1,4095 # revalidate r1
711 spt __LC_CPU_TIMER_SAVE_AREA-4095(%r1) # revalidate cpu timer
712 lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# revalidate gprs
713 SAVE_ALL_BASE __LC_SAVE_AREA+64
714 la %r12,__LC_MCK_OLD_PSW
715 tm __LC_MCCK_CODE,0x80 # system damage?
716 jo mcck_int_main # yes -> rest of mcck code invalid
717 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
719 mvc __LC_SAVE_AREA+104(8),__LC_ASYNC_ENTER_TIMER
720 mvc __LC_ASYNC_ENTER_TIMER(8),__LC_CPU_TIMER_SAVE_AREA-4095(%r14)
721 tm __LC_MCCK_CODE+5,0x02 # stored cpu timer value valid?
723 la %r14,__LC_SYNC_ENTER_TIMER
724 clc 0(8,%r14),__LC_ASYNC_ENTER_TIMER
726 la %r14,__LC_ASYNC_ENTER_TIMER
727 0: clc 0(8,%r14),__LC_EXIT_TIMER
729 la %r14,__LC_EXIT_TIMER
730 0: clc 0(8,%r14),__LC_LAST_UPDATE_TIMER
732 la %r14,__LC_LAST_UPDATE_TIMER
734 mvc __LC_ASYNC_ENTER_TIMER(8),0(%r14)
737 tm __LC_MCCK_CODE+2,0x09 # mwp + ia of old psw valid?
738 jno mcck_int_main # no -> skip cleanup critical
739 tm __LC_MCK_OLD_PSW+1,0x01 # test problem state bit
740 jnz mcck_int_main # from user -> load kernel stack
741 clc __LC_MCK_OLD_PSW+8(8),BASED(.Lcritical_end)
743 clc __LC_MCK_OLD_PSW+8(8),BASED(.Lcritical_start)
745 brasl %r14,cleanup_critical
747 lg %r14,__LC_PANIC_STACK # are we already on the panic stack?
749 srag %r14,%r14,PAGE_SHIFT
751 lg %r15,__LC_PANIC_STACK # load panic stack
752 0: CREATE_STACK_FRAME __LC_MCK_OLD_PSW,__LC_SAVE_AREA+64
753 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
754 tm __LC_MCCK_CODE+2,0x08 # mwp of old psw valid?
755 jno mcck_no_vtime # no -> no timer update
756 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
758 UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
759 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
760 mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
763 lg %r9,__LC_THREAD_INFO # load pointer to thread_info struct
764 la %r2,SP_PTREGS(%r15) # load pt_regs
765 brasl %r14,s390_do_machine_check
766 tm SP_PSW+1(%r15),0x01 # returning to user ?
768 lg %r1,__LC_KERNEL_STACK # switch to kernel stack
770 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
771 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
773 stosm __SF_EMPTY(%r15),0x04 # turn dat on
774 tm __TI_flags+7(%r9),_TIF_MCCK_PENDING
777 brasl %r14,s390_handle_mcck
780 mvc __LC_RETURN_MCCK_PSW(16),SP_PSW(%r15) # move return PSW
781 ni __LC_RETURN_MCCK_PSW+1,0xfd # clear wait state bit
782 lmg %r0,%r15,SP_R0(%r15) # load gprs 0-15
783 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
784 mvc __LC_ASYNC_ENTER_TIMER(8),__LC_SAVE_AREA+104
785 tm __LC_RETURN_MCCK_PSW+1,0x01 # returning to user ?
790 lpswe __LC_RETURN_MCCK_PSW # back to caller
794 * Restart interruption handler, kick starter for additional CPUs
796 .globl restart_int_handler
798 lg %r15,__LC_SAVE_AREA+120 # load ksp
799 lghi %r10,__LC_CREGS_SAVE_AREA
800 lctlg %c0,%c15,0(%r10) # get new ctl regs
801 lghi %r10,__LC_AREGS_SAVE_AREA
803 lmg %r6,%r15,__SF_GPRS(%r15) # load registers from clone
804 stosm __SF_EMPTY(%r15),0x04 # now we can turn dat on
808 * If we do not run with SMP enabled, let the new CPU crash ...
810 .globl restart_int_handler
814 lpswe restart_crash-restart_base(%r1)
817 .long 0x000a0000,0x00000000,0x00000000,0x00000000
821 #ifdef CONFIG_CHECK_STACK
823 * The synchronous or the asynchronous stack overflowed. We are dead.
824 * No need to properly save the registers, we are going to panic anyway.
825 * Setup a pt_regs so that show_trace can provide a good call trace.
828 lg %r15,__LC_PANIC_STACK # change to panic stack
830 mvc SP_PSW(16,%r15),0(%r12) # move user PSW to stack
831 stmg %r0,%r11,SP_R0(%r15) # store gprs %r0-%r11 to kernel stack
832 la %r1,__LC_SAVE_AREA
833 chi %r12,__LC_SVC_OLD_PSW
835 chi %r12,__LC_PGM_OLD_PSW
837 la %r1,__LC_SAVE_AREA+32
838 0: mvc SP_R12(32,%r15),0(%r1) # move %r12-%r15 to stack
839 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) # clear back chain
840 la %r2,SP_PTREGS(%r15) # load pt_regs
841 jg kernel_stack_overflow
844 cleanup_table_system_call:
845 .quad system_call, sysc_do_svc
846 cleanup_table_sysc_return:
847 .quad sysc_return, sysc_leave
848 cleanup_table_sysc_leave:
849 .quad sysc_leave, sysc_work_loop
850 cleanup_table_sysc_work_loop:
851 .quad sysc_work_loop, sysc_reschedule
852 cleanup_table_io_return:
853 .quad io_return, io_leave
854 cleanup_table_io_leave:
855 .quad io_leave, io_done
856 cleanup_table_io_work_loop:
857 .quad io_work_loop, io_mcck_pending
860 clc 8(8,%r12),BASED(cleanup_table_system_call)
862 clc 8(8,%r12),BASED(cleanup_table_system_call+8)
863 jl cleanup_system_call
865 clc 8(8,%r12),BASED(cleanup_table_sysc_return)
867 clc 8(8,%r12),BASED(cleanup_table_sysc_return+8)
868 jl cleanup_sysc_return
870 clc 8(8,%r12),BASED(cleanup_table_sysc_leave)
872 clc 8(8,%r12),BASED(cleanup_table_sysc_leave+8)
873 jl cleanup_sysc_leave
875 clc 8(8,%r12),BASED(cleanup_table_sysc_work_loop)
877 clc 8(8,%r12),BASED(cleanup_table_sysc_work_loop+8)
878 jl cleanup_sysc_return
880 clc 8(8,%r12),BASED(cleanup_table_io_return)
882 clc 8(8,%r12),BASED(cleanup_table_io_return+8)
885 clc 8(8,%r12),BASED(cleanup_table_io_leave)
887 clc 8(8,%r12),BASED(cleanup_table_io_leave+8)
890 clc 8(8,%r12),BASED(cleanup_table_io_work_loop)
892 clc 8(8,%r12),BASED(cleanup_table_io_work_loop+8)
898 mvc __LC_RETURN_PSW(16),0(%r12)
899 cghi %r12,__LC_MCK_OLD_PSW
901 la %r12,__LC_SAVE_AREA+32
903 0: la %r12,__LC_SAVE_AREA+64
905 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
906 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+8)
908 mvc __LC_SYNC_ENTER_TIMER(8),__LC_ASYNC_ENTER_TIMER
909 0: clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+16)
912 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn)
914 mvc __LC_SAVE_AREA(32),0(%r12)
916 stg %r12,__LC_SAVE_AREA+96 # argh
917 SAVE_ALL_SYNC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
918 CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA
919 lg %r12,__LC_SAVE_AREA+96 # argh
921 llgh %r7,__LC_SVC_INT_CODE
922 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
924 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+24)
926 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
928 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
930 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+32)
932 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
934 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
937 mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_system_call+8)
938 la %r12,__LC_RETURN_PSW
940 cleanup_system_call_insn:
942 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
950 mvc __LC_RETURN_PSW(8),0(%r12)
951 mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_sysc_return)
952 la %r12,__LC_RETURN_PSW
956 clc 8(8,%r12),BASED(cleanup_sysc_leave_insn)
958 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
959 mvc __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER
960 clc 8(8,%r12),BASED(cleanup_sysc_leave_insn+8)
963 mvc __LC_RETURN_PSW(16),SP_PSW(%r15)
964 cghi %r12,__LC_MCK_OLD_PSW
966 mvc __LC_SAVE_AREA+64(32),SP_R12(%r15)
968 0: mvc __LC_SAVE_AREA+32(32),SP_R12(%r15)
969 1: lmg %r0,%r11,SP_R0(%r15)
971 2: la %r12,__LC_RETURN_PSW
973 cleanup_sysc_leave_insn:
974 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
975 .quad sysc_leave + 16
977 .quad sysc_leave + 12
980 mvc __LC_RETURN_PSW(8),0(%r12)
981 mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_io_work_loop)
982 la %r12,__LC_RETURN_PSW
986 clc 8(8,%r12),BASED(cleanup_io_leave_insn)
988 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
989 mvc __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER
990 clc 8(8,%r12),BASED(cleanup_io_leave_insn+8)
993 mvc __LC_RETURN_PSW(16),SP_PSW(%r15)
994 cghi %r12,__LC_MCK_OLD_PSW
996 mvc __LC_SAVE_AREA+64(32),SP_R12(%r15)
998 0: mvc __LC_SAVE_AREA+32(32),SP_R12(%r15)
999 1: lmg %r0,%r11,SP_R0(%r15)
1000 lg %r15,SP_R15(%r15)
1001 2: la %r12,__LC_RETURN_PSW
1003 cleanup_io_leave_insn:
1004 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
1014 .Lc_pactive: .long PREEMPT_ACTIVE
1015 .Lnr_syscalls: .long NR_syscalls
1016 .L0x0130: .short 0x130
1017 .L0x0140: .short 0x140
1018 .L0x0150: .short 0x150
1019 .L0x0160: .short 0x160
1020 .L0x0170: .short 0x170
1022 .quad __critical_start
1024 .quad __critical_end
1026 .section .rodata, "a"
1027 #define SYSCALL(esa,esame,emu) .long esame
1029 #include "syscalls.S"
1032 #ifdef CONFIG_COMPAT
1034 #define SYSCALL(esa,esame,emu) .long emu
1036 #include "syscalls.S"