git.oblomov.eu Git - linux-2.6/blob - drivers/mtd/nand/cafe_nand.c

   1 /*
   2  * cafe_nand.c
   3  *
   4  * Copyright © 2006 Red Hat, Inc.
   5  * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
   6  */
   7
   8 #define DEBUG
   9
  10 #include <linux/device.h>
  11 #undef DEBUG
  12 #include <linux/mtd/mtd.h>
  13 #include <linux/mtd/nand.h>
  14 #include <linux/pci.h>
  15 #include <linux/delay.h>
  16 #include <linux/interrupt.h>
  17 #include <asm/io.h>
  18
  19 #define CAFE_NAND_CTRL1         0x00
  20 #define CAFE_NAND_CTRL2         0x04
  21 #define CAFE_NAND_CTRL3         0x08
  22 #define CAFE_NAND_STATUS        0x0c
  23 #define CAFE_NAND_IRQ           0x10
  24 #define CAFE_NAND_IRQ_MASK      0x14
  25 #define CAFE_NAND_DATA_LEN      0x18
  26 #define CAFE_NAND_ADDR1         0x1c
  27 #define CAFE_NAND_ADDR2         0x20
  28 #define CAFE_NAND_TIMING1       0x24
  29 #define CAFE_NAND_TIMING2       0x28
  30 #define CAFE_NAND_TIMING3       0x2c
  31 #define CAFE_NAND_NONMEM        0x30
  32 #define CAFE_NAND_DMA_CTRL      0x40
  33 #define CAFE_NAND_DMA_ADDR0     0x44
  34 #define CAFE_NAND_DMA_ADDR1     0x48
  35 #define CAFE_NAND_READ_DATA     0x1000
  36 #define CAFE_NAND_WRITE_DATA    0x2000
  37
  38 struct cafe_priv {
  39         struct nand_chip nand;
  40         struct pci_dev *pdev;
  41         void __iomem *mmio;
  42         uint32_t ctl1;
  43         uint32_t ctl2;
  44         int datalen;
  45         int nr_data;
  46         int data_pos;
  47         int page_addr;
  48         dma_addr_t dmaaddr;
  49         unsigned char *dmabuf;
  50
  51 };
  52
  53 static int usedma = 1;
  54 module_param(usedma, int, 0644);
  55
  56 static int skipbbt = 0;
  57 module_param(skipbbt, int, 0644);
  58
  59 static int debug = 0;
  60 module_param(debug, int, 0644);
  61
  62 #define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0)
  63
  64
  65 static int cafe_device_ready(struct mtd_info *mtd)
  66 {
  67         struct cafe_priv *cafe = mtd->priv;
  68         int result = !!(readl(cafe->mmio + CAFE_NAND_STATUS) | 0x40000000);
  69
  70         uint32_t irqs = readl(cafe->mmio + CAFE_NAND_IRQ);
  71         writel(irqs, cafe->mmio+CAFE_NAND_IRQ);
  72         cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n",
  73                 result?"":" not", irqs, readl(cafe->mmio + CAFE_NAND_IRQ),
  74                 readl(cafe->mmio + 0x3008), readl(cafe->mmio + 0x300c));
  75         return result;
  76 }
  77
  78
  79 static void cafe_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
  80 {
  81         struct cafe_priv *cafe = mtd->priv;
  82
  83         if (usedma)
  84                 memcpy(cafe->dmabuf + cafe->datalen, buf, len);
  85         else
  86                 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len);
  87         cafe->datalen += len;
  88
  89         cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n",
  90                 len, cafe->datalen);
  91 }
  92
  93 static void cafe_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  94 {
  95         struct cafe_priv *cafe = mtd->priv;
  96
  97         if (usedma)
  98                 memcpy(buf, cafe->dmabuf + cafe->datalen, len);
  99         else
 100                 memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len);
 101
 102         cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n",
 103                   len, cafe->datalen);
 104         cafe->datalen += len;
 105 }
 106
 107 static uint8_t cafe_read_byte(struct mtd_info *mtd)
 108 {
 109         struct cafe_priv *cafe = mtd->priv;
 110         uint8_t d;
 111
 112         cafe_read_buf(mtd, &d, 1);
 113         cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d);
 114
 115         return d;
 116 }
 117
 118 static void cafe_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
 119                               int column, int page_addr)
 120 {
 121         struct cafe_priv *cafe = mtd->priv;
 122         int adrbytes = 0;
 123         uint32_t ctl1;
 124         uint32_t doneint = 0x80000000;
 125         int i;
 126
 127         cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n",
 128                 command, column, page_addr);
 129
 130         if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) {
 131                 /* Second half of a command we already calculated */
 132                 writel(cafe->ctl2 | 0x100 | command, cafe->mmio + 0x04);
 133                 ctl1 = cafe->ctl1;
 134                 cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n",
 135                           cafe->ctl1, cafe->nr_data);
 136                 goto do_command;
 137         }
 138         /* Reset ECC engine */
 139         writel(0, cafe->mmio + CAFE_NAND_CTRL2);
 140
 141         /* Emulate NAND_CMD_READOOB on large-page chips */
 142         if (mtd->writesize > 512 &&
 143             command == NAND_CMD_READOOB) {
 144                 column += mtd->writesize;
 145                 command = NAND_CMD_READ0;
 146         }
 147
 148         /* FIXME: Do we need to send read command before sending data
 149            for small-page chips, to position the buffer correctly? */
 150
 151         if (column != -1) {
 152                 writel(column, cafe->mmio + 0x1c);
 153                 adrbytes = 2;
 154                 if (page_addr != -1)
 155                         goto write_adr2;
 156         } else if (page_addr != -1) {
 157                 writel(page_addr & 0xffff, cafe->mmio + 0x1c);
 158                 page_addr >>= 16;
 159         write_adr2:
 160                 writel(page_addr, cafe->mmio+0x20);
 161                 adrbytes += 2;
 162                 if (mtd->size > mtd->writesize << 16)
 163                         adrbytes++;
 164         }
 165
 166         cafe->data_pos = cafe->datalen = 0;
 167
 168         /* Set command valid bit */
 169         ctl1 = 0x80000000 | command;
 170
 171         /* Set RD or WR bits as appropriate */
 172         if (command == NAND_CMD_READID || command == NAND_CMD_STATUS) {
 173                 ctl1 |= (1<<26); /* rd */
 174                 /* Always 5 bytes, for now */
 175                 cafe->datalen = 4;
 176                 /* And one address cycle -- even for STATUS, since the controller doesn't work without */
 177                 adrbytes = 1;
 178         } else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 ||
 179                    command == NAND_CMD_READOOB || command == NAND_CMD_RNDOUT) {
 180                 ctl1 |= 1<<26; /* rd */
 181                 /* For now, assume just read to end of page */
 182                 cafe->datalen = mtd->writesize + mtd->oobsize - column;
 183         } else if (command == NAND_CMD_SEQIN)
 184                 ctl1 |= 1<<25; /* wr */
 185
 186         /* Set number of address bytes */
 187         if (adrbytes)
 188                 ctl1 |= ((adrbytes-1)|8) << 27;
 189
 190         if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) {
 191                 /* Ignore the first command of a pair; the hardware
 192                    deals with them both at once, later */
 193                 cafe->ctl1 = ctl1;
 194                 cafe->ctl2 = 0;
 195                 cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n",
 196                           cafe->ctl1, cafe->datalen);
 197                 return;
 198         }
 199         /* RNDOUT and READ0 commands need a following byte */
 200         if (command == NAND_CMD_RNDOUT)
 201                 writel(cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, cafe->mmio + CAFE_NAND_CTRL2);
 202         else if (command == NAND_CMD_READ0 && mtd->writesize > 512)
 203                 writel(cafe->ctl2 | 0x100 | NAND_CMD_READSTART, cafe->mmio + CAFE_NAND_CTRL2);
 204
 205  do_command:
 206         // ECC on read only works if we ...
 207         //      if (cafe->datalen == 2112)
 208         //              cafe->datalen = 2062;
 209         cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n",
 210                 cafe->datalen, ctl1, readl(cafe->mmio+CAFE_NAND_CTRL2));
 211         /* NB: The datasheet lies -- we really should be subtracting 1 here */
 212         writel(cafe->datalen, cafe->mmio + CAFE_NAND_DATA_LEN);
 213         writel(0x90000000, cafe->mmio + CAFE_NAND_IRQ);
 214         if (usedma && (ctl1 & (3<<25))) {
 215                 uint32_t dmactl = 0xc0000000 + cafe->datalen;
 216                 /* If WR or RD bits set, set up DMA */
 217                 if (ctl1 & (1<<26)) {
 218                         /* It's a read */
 219                         dmactl |= (1<<29);
 220                         /* ... so it's done when the DMA is done, not just
 221                            the command. */
 222                         doneint = 0x10000000;
 223                 }
 224                 writel(dmactl, cafe->mmio + 0x40);
 225         }
 226 #if 0
 227         printk("DMA setup is %x, status %x, ctl1 %x\n", readl(cafe->mmio + 0x40), readl(cafe->mmio + 0x0c), readl(cafe->mmio));
 228         printk("DMA setup is %x, status %x, ctl1 %x\n", readl(cafe->mmio + 0x40), readl(cafe->mmio + 0x0c), readl(cafe->mmio));
 229 #endif
 230         cafe->datalen = 0;
 231
 232 #if 0
 233         printk("About to write command %08x\n", ctl1);
 234         for (i=0; i< 0x5c; i+=4)
 235                 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
 236 #endif
 237         writel(ctl1, cafe->mmio + CAFE_NAND_CTRL1);
 238         /* Apply this short delay always to ensure that we do wait tWB in
 239          * any case on any machine. */
 240         ndelay(100);
 241
 242         if (1) {
 243                 int c = 500000;
 244                 uint32_t irqs;
 245
 246                 while (c--) {
 247                         irqs = readl(cafe->mmio + CAFE_NAND_IRQ);
 248                         if (irqs & doneint)
 249                                 break;
 250                         udelay(1);
 251                         if (!(c % 100000))
 252                                 cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs);
 253                         cpu_relax();
 254                 }
 255                 writel(doneint, cafe->mmio + CAFE_NAND_IRQ);
 256                 cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n", command, 50000-c, irqs, readl(cafe->mmio + CAFE_NAND_IRQ));
 257         }
 258
 259
 260         cafe->ctl2 &= ~(1<<8);
 261         cafe->ctl2 &= ~(1<<30);
 262
 263         switch (command) {
 264
 265         case NAND_CMD_CACHEDPROG:
 266         case NAND_CMD_PAGEPROG:
 267         case NAND_CMD_ERASE1:
 268         case NAND_CMD_ERASE2:
 269         case NAND_CMD_SEQIN:
 270         case NAND_CMD_RNDIN:
 271         case NAND_CMD_STATUS:
 272         case NAND_CMD_DEPLETE1:
 273         case NAND_CMD_RNDOUT:
 274         case NAND_CMD_STATUS_ERROR:
 275         case NAND_CMD_STATUS_ERROR0:
 276         case NAND_CMD_STATUS_ERROR1:
 277         case NAND_CMD_STATUS_ERROR2:
 278         case NAND_CMD_STATUS_ERROR3:
 279                 writel(cafe->ctl2, cafe->mmio + CAFE_NAND_CTRL2);
 280                 return;
 281         }
 282         nand_wait_ready(mtd);
 283         writel(cafe->ctl2, cafe->mmio + CAFE_NAND_CTRL2);
 284 }
 285
 286 static void cafe_select_chip(struct mtd_info *mtd, int chipnr)
 287 {
 288         //struct cafe_priv *cafe = mtd->priv;
 289         //      cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr);
 290 }
 291 static int cafe_nand_interrupt(int irq, void *id, struct pt_regs *regs)
 292 {
 293         struct mtd_info *mtd = id;
 294         struct cafe_priv *cafe = mtd->priv;
 295         uint32_t irqs = readl(cafe->mmio + CAFE_NAND_IRQ);
 296         writel(irqs & ~0x90000000, cafe->mmio + CAFE_NAND_IRQ);
 297         if (!irqs)
 298                 return IRQ_NONE;
 299
 300         cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, readl(cafe->mmio + CAFE_NAND_IRQ));
 301         return IRQ_HANDLED;
 302 }
 303
 304 static void cafe_nand_bug(struct mtd_info *mtd)
 305 {
 306         BUG();
 307 }
 308
 309 static int cafe_nand_write_oob(struct mtd_info *mtd,
 310                                struct nand_chip *chip, int page)
 311 {
 312         int status = 0;
 313
 314         WARN_ON(chip->oob_poi != chip->buffers->oobwbuf);
 315
 316         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
 317         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 318         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 319         status = chip->waitfunc(mtd, chip);
 320
 321         return status & NAND_STATUS_FAIL ? -EIO : 0;
 322 }
 323
 324 /* Don't use -- use nand_read_oob_std for now */
 325 static int cafe_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
 326                               int page, int sndcmd)
 327 {
 328         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
 329         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 330         return 1;
 331 }
 332 /**
 333  * cafe_nand_read_page_syndrome - {REPLACABLE] hardware ecc syndrom based page read
 334  * @mtd:        mtd info structure
 335  * @chip:       nand chip info structure
 336  * @buf:        buffer to store read data
 337  *
 338  * The hw generator calculates the error syndrome automatically. Therefor
 339  * we need a special oob layout and handling.
 340  */
 341 static int cafe_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 342                                uint8_t *buf)
 343 {
 344         struct cafe_priv *cafe = mtd->priv;
 345
 346         WARN_ON(chip->oob_poi != chip->buffers->oobrbuf);
 347
 348         cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n", readl(cafe->mmio + 0x3c), readl(cafe->mmio + 0x50));
 349
 350         chip->read_buf(mtd, buf, mtd->writesize);
 351         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 352
 353         return 0;
 354 }
 355
 356 static struct nand_ecclayout cafe_oobinfo_2048 = {
 357         .eccbytes = 14,
 358         .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
 359         .oobfree = {{14, 50}}
 360 };
 361
 362 /* Ick. The BBT code really ought to be able to work this bit out
 363    for itself from the above */
 364 static uint8_t cafe_bbt_pattern[] = {'B', 'b', 't', '0' };
 365 static uint8_t cafe_mirror_pattern[] = {'1', 't', 'b', 'B' };
 366
 367 static struct nand_bbt_descr cafe_bbt_main_descr_2048 = {
 368         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 369                 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 370         .offs = 14,
 371         .len = 4,
 372         .veroffs = 18,
 373         .maxblocks = 4,
 374         .pattern = cafe_bbt_pattern
 375 };
 376
 377 static struct nand_bbt_descr cafe_bbt_mirror_descr_2048 = {
 378         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 379                 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 380         .offs = 14,
 381         .len = 4,
 382         .veroffs = 18,
 383         .maxblocks = 4,
 384         .pattern = cafe_mirror_pattern
 385 };
 386
 387 static struct nand_ecclayout cafe_oobinfo_512 = {
 388         .eccbytes = 14,
 389         .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
 390         .oobfree = {{14, 2}}
 391 };
 392
 393
 394 static void cafe_nand_write_page_lowlevel(struct mtd_info *mtd,
 395                                           struct nand_chip *chip, const uint8_t *buf)
 396 {
 397         struct cafe_priv *cafe = mtd->priv;
 398
 399         WARN_ON(chip->oob_poi != chip->buffers->oobwbuf);
 400
 401         chip->write_buf(mtd, buf, mtd->writesize);
 402         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 403
 404         /* Set up ECC autogeneration */
 405         cafe->ctl2 |= (1<<27) | (1<<30);
 406         if (mtd->writesize == 2048)
 407                 cafe->ctl2 |= (1<<29);
 408 }
 409
 410 static int cafe_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 411                                 const uint8_t *buf, int page, int cached, int raw)
 412 {
 413         int status;
 414
 415         WARN_ON(chip->oob_poi != chip->buffers->oobwbuf);
 416
 417         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
 418
 419         if (unlikely(raw))
 420                 chip->ecc.write_page_raw(mtd, chip, buf);
 421         else
 422                 chip->ecc.write_page(mtd, chip, buf);
 423
 424         /*
 425          * Cached progamming disabled for now, Not sure if its worth the
 426          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
 427          */
 428         cached = 0;
 429
 430         if (!cached || !(chip->options & NAND_CACHEPRG)) {
 431
 432                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 433                 status = chip->waitfunc(mtd, chip);
 434                 /*
 435                  * See if operation failed and additional status checks are
 436                  * available
 437                  */
 438                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
 439                         status = chip->errstat(mtd, chip, FL_WRITING, status,
 440                                                page);
 441
 442                 if (status & NAND_STATUS_FAIL)
 443                         return -EIO;
 444         } else {
 445                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
 446                 status = chip->waitfunc(mtd, chip);
 447         }
 448
 449 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
 450         /* Send command to read back the data */
 451         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
 452
 453         if (chip->verify_buf(mtd, buf, mtd->writesize))
 454                 return -EIO;
 455 #endif
 456         return 0;
 457 }
 458
 459 static int cafe_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 460 {
 461         return 0;
 462 }
 463
 464 static int __devinit cafe_nand_probe(struct pci_dev *pdev,
 465                                      const struct pci_device_id *ent)
 466 {
 467         struct mtd_info *mtd;
 468         struct cafe_priv *cafe;
 469         uint32_t ctrl;
 470         int err = 0;
 471
 472         err = pci_enable_device(pdev);
 473         if (err)
 474                 return err;
 475
 476         pci_set_master(pdev);
 477
 478         mtd = kzalloc(sizeof(*mtd) + sizeof(struct cafe_priv), GFP_KERNEL);
 479         if (!mtd) {
 480                 dev_warn(&pdev->dev, "failed to alloc mtd_info\n");
 481                 return  -ENOMEM;
 482         }
 483         cafe = (void *)(&mtd[1]);
 484
 485         mtd->priv = cafe;
 486         mtd->owner = THIS_MODULE;
 487
 488         cafe->pdev = pdev;
 489         cafe->mmio = pci_iomap(pdev, 0, 0);
 490         if (!cafe->mmio) {
 491                 dev_warn(&pdev->dev, "failed to iomap\n");
 492                 err = -ENOMEM;
 493                 goto out_free_mtd;
 494         }
 495         cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev, 2112 + sizeof(struct nand_buffers),
 496                                           &cafe->dmaaddr, GFP_KERNEL);
 497         if (!cafe->dmabuf) {
 498                 err = -ENOMEM;
 499                 goto out_ior;
 500         }
 501         cafe->nand.buffers = (void *)cafe->dmabuf + 2112;
 502
 503         cafe->nand.cmdfunc = cafe_nand_cmdfunc;
 504         cafe->nand.dev_ready = cafe_device_ready;
 505         cafe->nand.read_byte = cafe_read_byte;
 506         cafe->nand.read_buf = cafe_read_buf;
 507         cafe->nand.write_buf = cafe_write_buf;
 508         cafe->nand.select_chip = cafe_select_chip;
 509
 510         cafe->nand.chip_delay = 0;
 511
 512         /* Enable the following for a flash based bad block table */
 513         cafe->nand.options = NAND_USE_FLASH_BBT | NAND_NO_AUTOINCR | NAND_OWN_BUFFERS;
 514
 515         if (skipbbt) {
 516                 cafe->nand.options |= NAND_SKIP_BBTSCAN;
 517                 cafe->nand.block_bad = cafe_nand_block_bad;
 518         }
 519
 520         /* Timings from Marvell's test code (not verified or calculated by us) */
 521         writel(0xffffffff, cafe->mmio + CAFE_NAND_IRQ_MASK);
 522 #if 1
 523         writel(0x01010a0a, cafe->mmio + CAFE_NAND_TIMING1);
 524         writel(0x24121212, cafe->mmio + CAFE_NAND_TIMING2);
 525         writel(0x11000000, cafe->mmio + CAFE_NAND_TIMING3);
 526 #else
 527         writel(0xffffffff, cafe->mmio + CAFE_NAND_TIMING1);
 528         writel(0xffffffff, cafe->mmio + CAFE_NAND_TIMING2);
 529         writel(0xffffffff, cafe->mmio + CAFE_NAND_TIMING3);
 530 #endif
 531         writel(0xffffffff, cafe->mmio + CAFE_NAND_IRQ_MASK);
 532         err = request_irq(pdev->irq, &cafe_nand_interrupt, SA_SHIRQ, "CAFE NAND", mtd);
 533         if (err) {
 534                 dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq);
 535
 536                 goto out_free_dma;
 537         }
 538 #if 1
 539         /* Disable master reset, enable NAND clock */
 540         ctrl = readl(cafe->mmio + 0x3004);
 541         ctrl &= 0xffffeff0;
 542         ctrl |= 0x00007000;
 543         writel(ctrl | 0x05, cafe->mmio + 0x3004);
 544         writel(ctrl | 0x0a, cafe->mmio + 0x3004);
 545         writel(0, cafe->mmio + 0x40);
 546
 547         writel(0x7006, cafe->mmio + 0x3004);
 548         writel(0x700a, cafe->mmio + 0x3004);
 549
 550         /* Set up DMA address */
 551         writel(cafe->dmaaddr & 0xffffffff, cafe->mmio + 0x44);
 552         if (sizeof(cafe->dmaaddr) > 4)
 553                 writel((cafe->dmaaddr >> 16) >> 16, cafe->mmio + 0x48);
 554         else
 555                 writel(0, cafe->mmio + 0x48);
 556         cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n",
 557                 readl(cafe->mmio+0x44), cafe->dmabuf);
 558
 559         /* Enable NAND IRQ in global IRQ mask register */
 560         writel(0x80000007, cafe->mmio + 0x300c);
 561         cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n",
 562                 readl(cafe->mmio + 0x3004), readl(cafe->mmio + 0x300c));
 563 #endif
 564 #if 1
 565         mtd->writesize=2048;
 566         mtd->oobsize = 0x40;
 567         memset(cafe->dmabuf, 0x5a, 2112);
 568         cafe->nand.cmdfunc(mtd, NAND_CMD_READID, 0, -1);
 569         cafe->nand.read_byte(mtd);
 570         cafe->nand.read_byte(mtd);
 571         cafe->nand.read_byte(mtd);
 572         cafe->nand.read_byte(mtd);
 573         cafe->nand.read_byte(mtd);
 574 #endif
 575 #if 0
 576         cafe->nand.cmdfunc(mtd, NAND_CMD_READ0, 0, 0);
 577         //      nand_wait_ready(mtd);
 578         cafe->nand.read_byte(mtd);
 579         cafe->nand.read_byte(mtd);
 580         cafe->nand.read_byte(mtd);
 581         cafe->nand.read_byte(mtd);
 582 #endif
 583 #if 0
 584         writel(0x84600070, cafe->mmio);
 585         udelay(10);
 586         cafe_dev_dbg(&cafe->pdev->dev, "Status %x\n", readl(cafe->mmio + 0x30));
 587 #endif
 588         /* Scan to find existance of the device */
 589         if (nand_scan_ident(mtd, 1)) {
 590                 err = -ENXIO;
 591                 goto out_irq;
 592         }
 593
 594         cafe->ctl2 = 1<<27; /* Reed-Solomon ECC */
 595         if (mtd->writesize == 2048)
 596                 cafe->ctl2 |= 1<<29; /* 2KiB page size */
 597
 598         /* Set up ECC according to the type of chip we found */
 599         if (mtd->writesize == 512 || mtd->writesize == 2048) {
 600                 cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
 601                 cafe->nand.ecc.size = mtd->writesize;
 602                 cafe->nand.ecc.bytes = 14;
 603                 cafe->nand.ecc.layout = &cafe_oobinfo_2048;
 604                 cafe->nand.bbt_td = &cafe_bbt_main_descr_2048;
 605                 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048;
 606                 cafe->nand.ecc.hwctl  = (void *)cafe_nand_bug;
 607                 cafe->nand.ecc.calculate = (void *)cafe_nand_bug;
 608                 cafe->nand.ecc.correct  = (void *)cafe_nand_bug;
 609                 cafe->nand.write_page = cafe_nand_write_page;
 610                 cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel;
 611                 cafe->nand.ecc.write_oob = cafe_nand_write_oob;
 612                 cafe->nand.ecc.read_page = cafe_nand_read_page;
 613                 cafe->nand.ecc.read_oob = cafe_nand_read_oob;
 614
 615         } else {
 616                 printk(KERN_WARNING "Unexpected NAND flash writesize %d. Using software ECC\n",
 617                        mtd->writesize);
 618                 cafe->nand.ecc.mode = NAND_ECC_NONE;
 619         }
 620
 621         err = nand_scan_tail(mtd);
 622         if (err)
 623                 goto out_irq;
 624
 625         pci_set_drvdata(pdev, mtd);
 626         add_mtd_device(mtd);
 627         goto out;
 628
 629  out_irq:
 630         /* Disable NAND IRQ in global IRQ mask register */
 631         writel(~1 & readl(cafe->mmio + 0x300c), cafe->mmio + 0x300c);
 632         free_irq(pdev->irq, mtd);
 633  out_free_dma:
 634         dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
 635  out_ior:
 636         pci_iounmap(pdev, cafe->mmio);
 637  out_free_mtd:
 638         kfree(mtd);
 639  out:
 640         return err;
 641 }
 642
 643 static void __devexit cafe_nand_remove(struct pci_dev *pdev)
 644 {
 645         struct mtd_info *mtd = pci_get_drvdata(pdev);
 646         struct cafe_priv *cafe = mtd->priv;
 647
 648         del_mtd_device(mtd);
 649         /* Disable NAND IRQ in global IRQ mask register */
 650         writel(~1 & readl(cafe->mmio + 0x300c), cafe->mmio + 0x300c);
 651         free_irq(pdev->irq, mtd);
 652         nand_release(mtd);
 653         pci_iounmap(pdev, cafe->mmio);
 654         dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
 655         kfree(mtd);
 656 }
 657
 658 static struct pci_device_id cafe_nand_tbl[] = {
 659         { 0x11ab, 0x4100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MEMORY_FLASH << 8, 0xFFFF0 }
 660 };
 661
 662 MODULE_DEVICE_TABLE(pci, cafe_nand_tbl);
 663
 664 static struct pci_driver cafe_nand_pci_driver = {
 665         .name = "CAFÉ NAND",
 666         .id_table = cafe_nand_tbl,
 667         .probe = cafe_nand_probe,
 668         .remove = __devexit_p(cafe_nand_remove),
 669 #ifdef CONFIG_PMx
 670         .suspend = cafe_nand_suspend,
 671         .resume = cafe_nand_resume,
 672 #endif
 673 };
 674
 675 static int cafe_nand_init(void)
 676 {
 677         return pci_register_driver(&cafe_nand_pci_driver);
 678 }
 679
 680 static void cafe_nand_exit(void)
 681 {
 682         pci_unregister_driver(&cafe_nand_pci_driver);
 683 }
 684 module_init(cafe_nand_init);
 685 module_exit(cafe_nand_exit);
 686
 687 MODULE_LICENSE("GPL");
 688 MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
 689 MODULE_DESCRIPTION("NAND flash driver for OLPC CAFE chip");
 690
 691 /* Correct ECC for 2048 bytes of 0xff:
 692    41 a0 71 65 54 27 f3 93 ec a9 be ed 0b a1 */
 693
 694 /* dwmw2's B-test board, in case of completely screwing it:
 695 Bad eraseblock 2394 at 0x12b40000
 696 Bad eraseblock 2627 at 0x14860000
 697 Bad eraseblock 3349 at 0x1a2a0000
 698 */