2 * Copyright(c) 2004 - 2007 Intel Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
21 #ifndef _IOAT_REGISTERS_H_
22 #define _IOAT_REGISTERS_H_
24 #define IOAT_PCI_DMACTRL_OFFSET 0x48
25 #define IOAT_PCI_DMACTRL_DMA_EN 0x00000001
26 #define IOAT_PCI_DMACTRL_MSI_EN 0x00000002
28 /* MMIO Device Registers */
29 #define IOAT_CHANCNT_OFFSET 0x00 /* 8-bit */
31 #define IOAT_XFERCAP_OFFSET 0x01 /* 8-bit */
32 #define IOAT_XFERCAP_4KB 12
33 #define IOAT_XFERCAP_8KB 13
34 #define IOAT_XFERCAP_16KB 14
35 #define IOAT_XFERCAP_32KB 15
36 #define IOAT_XFERCAP_32GB 0
38 #define IOAT_GENCTRL_OFFSET 0x02 /* 8-bit */
39 #define IOAT_GENCTRL_DEBUG_EN 0x01
41 #define IOAT_INTRCTRL_OFFSET 0x03 /* 8-bit */
42 #define IOAT_INTRCTRL_MASTER_INT_EN 0x01 /* Master Interrupt Enable */
43 #define IOAT_INTRCTRL_INT_STATUS 0x02 /* ATTNSTATUS -or- Channel Int */
44 #define IOAT_INTRCTRL_INT 0x04 /* INT_STATUS -and- MASTER_INT_EN */
45 #define IOAT_INTRCTRL_MSIX_VECTOR_CONTROL 0x08 /* Enable all MSI-X vectors */
47 #define IOAT_ATTNSTATUS_OFFSET 0x04 /* Each bit is a channel */
49 #define IOAT_VER_OFFSET 0x08 /* 8-bit */
50 #define IOAT_VER_MAJOR_MASK 0xF0
51 #define IOAT_VER_MINOR_MASK 0x0F
52 #define GET_IOAT_VER_MAJOR(x) ((x) & IOAT_VER_MAJOR_MASK)
53 #define GET_IOAT_VER_MINOR(x) ((x) & IOAT_VER_MINOR_MASK)
55 #define IOAT_PERPORTOFFSET_OFFSET 0x0A /* 16-bit */
57 #define IOAT_INTRDELAY_OFFSET 0x0C /* 16-bit */
58 #define IOAT_INTRDELAY_INT_DELAY_MASK 0x3FFF /* Interrupt Delay Time */
59 #define IOAT_INTRDELAY_COALESE_SUPPORT 0x8000 /* Interrupt Coalesing Supported */
61 #define IOAT_DEVICE_STATUS_OFFSET 0x0E /* 16-bit */
62 #define IOAT_DEVICE_STATUS_DEGRADED_MODE 0x0001
65 #define IOAT_CHANNEL_MMIO_SIZE 0x80 /* Each Channel MMIO space is this size */
67 /* DMA Channel Registers */
68 #define IOAT_CHANCTRL_OFFSET 0x00 /* 16-bit Channel Control Register */
69 #define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK 0xF000
70 #define IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100
71 #define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020
72 #define IOAT_CHANCTRL_ERR_INT_EN 0x0010
73 #define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008
74 #define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004
75 #define IOAT_CHANCTRL_INT_DISABLE 0x0001
77 #define IOAT_DMA_COMP_OFFSET 0x02 /* 16-bit DMA channel compatability */
78 #define IOAT_DMA_COMP_V1 0x0001 /* Compatability with DMA version 1 */
80 #define IOAT_CHANSTS_OFFSET 0x04 /* 64-bit Channel Status Register */
81 #define IOAT_CHANSTS_OFFSET_LOW 0x04
82 #define IOAT_CHANSTS_OFFSET_HIGH 0x08
83 #define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR 0xFFFFFFFFFFFFFFC0UL
84 #define IOAT_CHANSTS_SOFT_ERR 0x0000000000000010
85 #define IOAT_CHANSTS_DMA_TRANSFER_STATUS 0x0000000000000007
86 #define IOAT_CHANSTS_DMA_TRANSFER_STATUS_ACTIVE 0x0
87 #define IOAT_CHANSTS_DMA_TRANSFER_STATUS_DONE 0x1
88 #define IOAT_CHANSTS_DMA_TRANSFER_STATUS_SUSPENDED 0x2
89 #define IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED 0x3
91 #define IOAT_CHAINADDR_OFFSET 0x0C /* 64-bit Descriptor Chain Address Register */
92 #define IOAT_CHAINADDR_OFFSET_LOW 0x0C
93 #define IOAT_CHAINADDR_OFFSET_HIGH 0x10
95 #define IOAT_CHANCMD_OFFSET 0x14 /* 8-bit DMA Channel Command Register */
96 #define IOAT_CHANCMD_RESET 0x20
97 #define IOAT_CHANCMD_RESUME 0x10
98 #define IOAT_CHANCMD_ABORT 0x08
99 #define IOAT_CHANCMD_SUSPEND 0x04
100 #define IOAT_CHANCMD_APPEND 0x02
101 #define IOAT_CHANCMD_START 0x01
103 #define IOAT_CHANCMP_OFFSET 0x18 /* 64-bit Channel Completion Address Register */
104 #define IOAT_CHANCMP_OFFSET_LOW 0x18
105 #define IOAT_CHANCMP_OFFSET_HIGH 0x1C
107 #define IOAT_CDAR_OFFSET 0x20 /* 64-bit Current Descriptor Address Register */
108 #define IOAT_CDAR_OFFSET_LOW 0x20
109 #define IOAT_CDAR_OFFSET_HIGH 0x24
111 #define IOAT_CHANERR_OFFSET 0x28 /* 32-bit Channel Error Register */
112 #define IOAT_CHANERR_DMA_TRANSFER_SRC_ADDR_ERR 0x0001
113 #define IOAT_CHANERR_DMA_TRANSFER_DEST_ADDR_ERR 0x0002
114 #define IOAT_CHANERR_NEXT_DESCRIPTOR_ADDR_ERR 0x0004
115 #define IOAT_CHANERR_NEXT_DESCRIPTOR_ALIGNMENT_ERR 0x0008
116 #define IOAT_CHANERR_CHAIN_ADDR_VALUE_ERR 0x0010
117 #define IOAT_CHANERR_CHANCMD_ERR 0x0020
118 #define IOAT_CHANERR_CHIPSET_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0040
119 #define IOAT_CHANERR_DMA_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0080
120 #define IOAT_CHANERR_READ_DATA_ERR 0x0100
121 #define IOAT_CHANERR_WRITE_DATA_ERR 0x0200
122 #define IOAT_CHANERR_DESCRIPTOR_CONTROL_ERR 0x0400
123 #define IOAT_CHANERR_DESCRIPTOR_LENGTH_ERR 0x0800
124 #define IOAT_CHANERR_COMPLETION_ADDR_ERR 0x1000
125 #define IOAT_CHANERR_INT_CONFIGURATION_ERR 0x2000
126 #define IOAT_CHANERR_SOFT_ERR 0x4000
128 #define IOAT_CHANERR_MASK_OFFSET 0x2C /* 32-bit Channel Error Register */
130 #endif /* _IOAT_REGISTERS_H_ */