Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6
[linux-2.6] / arch / sparc64 / kernel / smp.c
1 /* smp.c: Sparc64 SMP support.
2  *
3  * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
4  */
5
6 #include <linux/module.h>
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
9 #include <linux/mm.h>
10 #include <linux/pagemap.h>
11 #include <linux/threads.h>
12 #include <linux/smp.h>
13 #include <linux/smp_lock.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel_stat.h>
16 #include <linux/delay.h>
17 #include <linux/init.h>
18 #include <linux/spinlock.h>
19 #include <linux/fs.h>
20 #include <linux/seq_file.h>
21 #include <linux/cache.h>
22 #include <linux/jiffies.h>
23 #include <linux/profile.h>
24 #include <linux/bootmem.h>
25
26 #include <asm/head.h>
27 #include <asm/ptrace.h>
28 #include <asm/atomic.h>
29 #include <asm/tlbflush.h>
30 #include <asm/mmu_context.h>
31 #include <asm/cpudata.h>
32
33 #include <asm/irq.h>
34 #include <asm/page.h>
35 #include <asm/pgtable.h>
36 #include <asm/oplib.h>
37 #include <asm/uaccess.h>
38 #include <asm/timer.h>
39 #include <asm/starfire.h>
40 #include <asm/tlb.h>
41 #include <asm/sections.h>
42
43 extern void calibrate_delay(void);
44
45 /* Please don't make this stuff initdata!!!  --DaveM */
46 static unsigned char boot_cpu_id;
47
48 cpumask_t cpu_online_map __read_mostly = CPU_MASK_NONE;
49 cpumask_t phys_cpu_present_map __read_mostly = CPU_MASK_NONE;
50 cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly =
51         { [0 ... NR_CPUS-1] = CPU_MASK_NONE };
52 static cpumask_t smp_commenced_mask;
53 static cpumask_t cpu_callout_map;
54
55 void smp_info(struct seq_file *m)
56 {
57         int i;
58         
59         seq_printf(m, "State:\n");
60         for (i = 0; i < NR_CPUS; i++) {
61                 if (cpu_online(i))
62                         seq_printf(m,
63                                    "CPU%d:\t\tonline\n", i);
64         }
65 }
66
67 void smp_bogo(struct seq_file *m)
68 {
69         int i;
70         
71         for (i = 0; i < NR_CPUS; i++)
72                 if (cpu_online(i))
73                         seq_printf(m,
74                                    "Cpu%dBogo\t: %lu.%02lu\n"
75                                    "Cpu%dClkTck\t: %016lx\n",
76                                    i, cpu_data(i).udelay_val / (500000/HZ),
77                                    (cpu_data(i).udelay_val / (5000/HZ)) % 100,
78                                    i, cpu_data(i).clock_tick);
79 }
80
81 void __init smp_store_cpu_info(int id)
82 {
83         int cpu_node, def;
84
85         /* multiplier and counter set by
86            smp_setup_percpu_timer()  */
87         cpu_data(id).udelay_val                 = loops_per_jiffy;
88
89         cpu_find_by_mid(id, &cpu_node);
90         cpu_data(id).clock_tick = prom_getintdefault(cpu_node,
91                                                      "clock-frequency", 0);
92
93         def = ((tlb_type == hypervisor) ? (8 * 1024) : (16 * 1024));
94         cpu_data(id).dcache_size = prom_getintdefault(cpu_node, "dcache-size",
95                                                       def);
96
97         def = 32;
98         cpu_data(id).dcache_line_size =
99                 prom_getintdefault(cpu_node, "dcache-line-size", def);
100
101         def = 16 * 1024;
102         cpu_data(id).icache_size = prom_getintdefault(cpu_node, "icache-size",
103                                                       def);
104
105         def = 32;
106         cpu_data(id).icache_line_size =
107                 prom_getintdefault(cpu_node, "icache-line-size", def);
108
109         def = ((tlb_type == hypervisor) ?
110                (3 * 1024 * 1024) :
111                (4 * 1024 * 1024));
112         cpu_data(id).ecache_size = prom_getintdefault(cpu_node, "ecache-size",
113                                                       def);
114
115         def = 64;
116         cpu_data(id).ecache_line_size =
117                 prom_getintdefault(cpu_node, "ecache-line-size", def);
118
119         printk("CPU[%d]: Caches "
120                "D[sz(%d):line_sz(%d)] "
121                "I[sz(%d):line_sz(%d)] "
122                "E[sz(%d):line_sz(%d)]\n",
123                id,
124                cpu_data(id).dcache_size, cpu_data(id).dcache_line_size,
125                cpu_data(id).icache_size, cpu_data(id).icache_line_size,
126                cpu_data(id).ecache_size, cpu_data(id).ecache_line_size);
127 }
128
129 static void smp_setup_percpu_timer(void);
130
131 static volatile unsigned long callin_flag = 0;
132
133 void __init smp_callin(void)
134 {
135         int cpuid = hard_smp_processor_id();
136
137         __local_per_cpu_offset = __per_cpu_offset(cpuid);
138
139         if (tlb_type == hypervisor)
140                 sun4v_ktsb_register();
141
142         __flush_tlb_all();
143
144         smp_setup_percpu_timer();
145
146         if (cheetah_pcache_forced_on)
147                 cheetah_enable_pcache();
148
149         local_irq_enable();
150
151         calibrate_delay();
152         smp_store_cpu_info(cpuid);
153         callin_flag = 1;
154         __asm__ __volatile__("membar #Sync\n\t"
155                              "flush  %%g6" : : : "memory");
156
157         /* Clear this or we will die instantly when we
158          * schedule back to this idler...
159          */
160         current_thread_info()->new_child = 0;
161
162         /* Attach to the address space of init_task. */
163         atomic_inc(&init_mm.mm_count);
164         current->active_mm = &init_mm;
165
166         while (!cpu_isset(cpuid, smp_commenced_mask))
167                 rmb();
168
169         cpu_set(cpuid, cpu_online_map);
170
171         /* idle thread is expected to have preempt disabled */
172         preempt_disable();
173 }
174
175 void cpu_panic(void)
176 {
177         printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
178         panic("SMP bolixed\n");
179 }
180
181 static unsigned long current_tick_offset __read_mostly;
182
183 /* This tick register synchronization scheme is taken entirely from
184  * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
185  *
186  * The only change I've made is to rework it so that the master
187  * initiates the synchonization instead of the slave. -DaveM
188  */
189
190 #define MASTER  0
191 #define SLAVE   (SMP_CACHE_BYTES/sizeof(unsigned long))
192
193 #define NUM_ROUNDS      64      /* magic value */
194 #define NUM_ITERS       5       /* likewise */
195
196 static DEFINE_SPINLOCK(itc_sync_lock);
197 static unsigned long go[SLAVE + 1];
198
199 #define DEBUG_TICK_SYNC 0
200
201 static inline long get_delta (long *rt, long *master)
202 {
203         unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
204         unsigned long tcenter, t0, t1, tm;
205         unsigned long i;
206
207         for (i = 0; i < NUM_ITERS; i++) {
208                 t0 = tick_ops->get_tick();
209                 go[MASTER] = 1;
210                 membar_storeload();
211                 while (!(tm = go[SLAVE]))
212                         rmb();
213                 go[SLAVE] = 0;
214                 wmb();
215                 t1 = tick_ops->get_tick();
216
217                 if (t1 - t0 < best_t1 - best_t0)
218                         best_t0 = t0, best_t1 = t1, best_tm = tm;
219         }
220
221         *rt = best_t1 - best_t0;
222         *master = best_tm - best_t0;
223
224         /* average best_t0 and best_t1 without overflow: */
225         tcenter = (best_t0/2 + best_t1/2);
226         if (best_t0 % 2 + best_t1 % 2 == 2)
227                 tcenter++;
228         return tcenter - best_tm;
229 }
230
231 void smp_synchronize_tick_client(void)
232 {
233         long i, delta, adj, adjust_latency = 0, done = 0;
234         unsigned long flags, rt, master_time_stamp, bound;
235 #if DEBUG_TICK_SYNC
236         struct {
237                 long rt;        /* roundtrip time */
238                 long master;    /* master's timestamp */
239                 long diff;      /* difference between midpoint and master's timestamp */
240                 long lat;       /* estimate of itc adjustment latency */
241         } t[NUM_ROUNDS];
242 #endif
243
244         go[MASTER] = 1;
245
246         while (go[MASTER])
247                 rmb();
248
249         local_irq_save(flags);
250         {
251                 for (i = 0; i < NUM_ROUNDS; i++) {
252                         delta = get_delta(&rt, &master_time_stamp);
253                         if (delta == 0) {
254                                 done = 1;       /* let's lock on to this... */
255                                 bound = rt;
256                         }
257
258                         if (!done) {
259                                 if (i > 0) {
260                                         adjust_latency += -delta;
261                                         adj = -delta + adjust_latency/4;
262                                 } else
263                                         adj = -delta;
264
265                                 tick_ops->add_tick(adj, current_tick_offset);
266                         }
267 #if DEBUG_TICK_SYNC
268                         t[i].rt = rt;
269                         t[i].master = master_time_stamp;
270                         t[i].diff = delta;
271                         t[i].lat = adjust_latency/4;
272 #endif
273                 }
274         }
275         local_irq_restore(flags);
276
277 #if DEBUG_TICK_SYNC
278         for (i = 0; i < NUM_ROUNDS; i++)
279                 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
280                        t[i].rt, t[i].master, t[i].diff, t[i].lat);
281 #endif
282
283         printk(KERN_INFO "CPU %d: synchronized TICK with master CPU (last diff %ld cycles,"
284                "maxerr %lu cycles)\n", smp_processor_id(), delta, rt);
285 }
286
287 static void smp_start_sync_tick_client(int cpu);
288
289 static void smp_synchronize_one_tick(int cpu)
290 {
291         unsigned long flags, i;
292
293         go[MASTER] = 0;
294
295         smp_start_sync_tick_client(cpu);
296
297         /* wait for client to be ready */
298         while (!go[MASTER])
299                 rmb();
300
301         /* now let the client proceed into his loop */
302         go[MASTER] = 0;
303         membar_storeload();
304
305         spin_lock_irqsave(&itc_sync_lock, flags);
306         {
307                 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
308                         while (!go[MASTER])
309                                 rmb();
310                         go[MASTER] = 0;
311                         wmb();
312                         go[SLAVE] = tick_ops->get_tick();
313                         membar_storeload();
314                 }
315         }
316         spin_unlock_irqrestore(&itc_sync_lock, flags);
317 }
318
319 extern void sun4v_init_mondo_queues(int use_bootmem, int cpu, int alloc, int load);
320
321 extern unsigned long sparc64_cpu_startup;
322
323 /* The OBP cpu startup callback truncates the 3rd arg cookie to
324  * 32-bits (I think) so to be safe we have it read the pointer
325  * contained here so we work on >4GB machines. -DaveM
326  */
327 static struct thread_info *cpu_new_thread = NULL;
328
329 static int __devinit smp_boot_one_cpu(unsigned int cpu)
330 {
331         unsigned long entry =
332                 (unsigned long)(&sparc64_cpu_startup);
333         unsigned long cookie =
334                 (unsigned long)(&cpu_new_thread);
335         struct task_struct *p;
336         int timeout, ret;
337
338         p = fork_idle(cpu);
339         callin_flag = 0;
340         cpu_new_thread = task_thread_info(p);
341         cpu_set(cpu, cpu_callout_map);
342
343         if (tlb_type == hypervisor) {
344                 /* Alloc the mondo queues, cpu will load them.  */
345                 sun4v_init_mondo_queues(0, cpu, 1, 0);
346
347                 prom_startcpu_cpuid(cpu, entry, cookie);
348         } else {
349                 int cpu_node;
350
351                 cpu_find_by_mid(cpu, &cpu_node);
352                 prom_startcpu(cpu_node, entry, cookie);
353         }
354
355         for (timeout = 0; timeout < 5000000; timeout++) {
356                 if (callin_flag)
357                         break;
358                 udelay(100);
359         }
360
361         if (callin_flag) {
362                 ret = 0;
363         } else {
364                 printk("Processor %d is stuck.\n", cpu);
365                 cpu_clear(cpu, cpu_callout_map);
366                 ret = -ENODEV;
367         }
368         cpu_new_thread = NULL;
369
370         return ret;
371 }
372
373 static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
374 {
375         u64 result, target;
376         int stuck, tmp;
377
378         if (this_is_starfire) {
379                 /* map to real upaid */
380                 cpu = (((cpu & 0x3c) << 1) |
381                         ((cpu & 0x40) >> 4) |
382                         (cpu & 0x3));
383         }
384
385         target = (cpu << 14) | 0x70;
386 again:
387         /* Ok, this is the real Spitfire Errata #54.
388          * One must read back from a UDB internal register
389          * after writes to the UDB interrupt dispatch, but
390          * before the membar Sync for that write.
391          * So we use the high UDB control register (ASI 0x7f,
392          * ADDR 0x20) for the dummy read. -DaveM
393          */
394         tmp = 0x40;
395         __asm__ __volatile__(
396         "wrpr   %1, %2, %%pstate\n\t"
397         "stxa   %4, [%0] %3\n\t"
398         "stxa   %5, [%0+%8] %3\n\t"
399         "add    %0, %8, %0\n\t"
400         "stxa   %6, [%0+%8] %3\n\t"
401         "membar #Sync\n\t"
402         "stxa   %%g0, [%7] %3\n\t"
403         "membar #Sync\n\t"
404         "mov    0x20, %%g1\n\t"
405         "ldxa   [%%g1] 0x7f, %%g0\n\t"
406         "membar #Sync"
407         : "=r" (tmp)
408         : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
409           "r" (data0), "r" (data1), "r" (data2), "r" (target),
410           "r" (0x10), "0" (tmp)
411         : "g1");
412
413         /* NOTE: PSTATE_IE is still clear. */
414         stuck = 100000;
415         do {
416                 __asm__ __volatile__("ldxa [%%g0] %1, %0"
417                         : "=r" (result)
418                         : "i" (ASI_INTR_DISPATCH_STAT));
419                 if (result == 0) {
420                         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
421                                              : : "r" (pstate));
422                         return;
423                 }
424                 stuck -= 1;
425                 if (stuck == 0)
426                         break;
427         } while (result & 0x1);
428         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
429                              : : "r" (pstate));
430         if (stuck == 0) {
431                 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
432                        smp_processor_id(), result);
433         } else {
434                 udelay(2);
435                 goto again;
436         }
437 }
438
439 static __inline__ void spitfire_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
440 {
441         u64 pstate;
442         int i;
443
444         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
445         for_each_cpu_mask(i, mask)
446                 spitfire_xcall_helper(data0, data1, data2, pstate, i);
447 }
448
449 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
450  * packet, but we have no use for that.  However we do take advantage of
451  * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
452  */
453 static void cheetah_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
454 {
455         u64 pstate, ver;
456         int nack_busy_id, is_jbus;
457
458         if (cpus_empty(mask))
459                 return;
460
461         /* Unfortunately, someone at Sun had the brilliant idea to make the
462          * busy/nack fields hard-coded by ITID number for this Ultra-III
463          * derivative processor.
464          */
465         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
466         is_jbus = ((ver >> 32) == __JALAPENO_ID ||
467                    (ver >> 32) == __SERRANO_ID);
468
469         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
470
471 retry:
472         __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
473                              : : "r" (pstate), "i" (PSTATE_IE));
474
475         /* Setup the dispatch data registers. */
476         __asm__ __volatile__("stxa      %0, [%3] %6\n\t"
477                              "stxa      %1, [%4] %6\n\t"
478                              "stxa      %2, [%5] %6\n\t"
479                              "membar    #Sync\n\t"
480                              : /* no outputs */
481                              : "r" (data0), "r" (data1), "r" (data2),
482                                "r" (0x40), "r" (0x50), "r" (0x60),
483                                "i" (ASI_INTR_W));
484
485         nack_busy_id = 0;
486         {
487                 int i;
488
489                 for_each_cpu_mask(i, mask) {
490                         u64 target = (i << 14) | 0x70;
491
492                         if (!is_jbus)
493                                 target |= (nack_busy_id << 24);
494                         __asm__ __volatile__(
495                                 "stxa   %%g0, [%0] %1\n\t"
496                                 "membar #Sync\n\t"
497                                 : /* no outputs */
498                                 : "r" (target), "i" (ASI_INTR_W));
499                         nack_busy_id++;
500                 }
501         }
502
503         /* Now, poll for completion. */
504         {
505                 u64 dispatch_stat;
506                 long stuck;
507
508                 stuck = 100000 * nack_busy_id;
509                 do {
510                         __asm__ __volatile__("ldxa      [%%g0] %1, %0"
511                                              : "=r" (dispatch_stat)
512                                              : "i" (ASI_INTR_DISPATCH_STAT));
513                         if (dispatch_stat == 0UL) {
514                                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
515                                                      : : "r" (pstate));
516                                 return;
517                         }
518                         if (!--stuck)
519                                 break;
520                 } while (dispatch_stat & 0x5555555555555555UL);
521
522                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
523                                      : : "r" (pstate));
524
525                 if ((dispatch_stat & ~(0x5555555555555555UL)) == 0) {
526                         /* Busy bits will not clear, continue instead
527                          * of freezing up on this cpu.
528                          */
529                         printk("CPU[%d]: mondo stuckage result[%016lx]\n",
530                                smp_processor_id(), dispatch_stat);
531                 } else {
532                         int i, this_busy_nack = 0;
533
534                         /* Delay some random time with interrupts enabled
535                          * to prevent deadlock.
536                          */
537                         udelay(2 * nack_busy_id);
538
539                         /* Clear out the mask bits for cpus which did not
540                          * NACK us.
541                          */
542                         for_each_cpu_mask(i, mask) {
543                                 u64 check_mask;
544
545                                 if (is_jbus)
546                                         check_mask = (0x2UL << (2*i));
547                                 else
548                                         check_mask = (0x2UL <<
549                                                       this_busy_nack);
550                                 if ((dispatch_stat & check_mask) == 0)
551                                         cpu_clear(i, mask);
552                                 this_busy_nack += 2;
553                         }
554
555                         goto retry;
556                 }
557         }
558 }
559
560 /* Multi-cpu list version.  */
561 static void hypervisor_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
562 {
563         struct trap_per_cpu *tb;
564         u16 *cpu_list;
565         u64 *mondo;
566         cpumask_t error_mask;
567         unsigned long flags, status;
568         int cnt, retries, this_cpu, prev_sent, i;
569
570         /* We have to do this whole thing with interrupts fully disabled.
571          * Otherwise if we send an xcall from interrupt context it will
572          * corrupt both our mondo block and cpu list state.
573          *
574          * One consequence of this is that we cannot use timeout mechanisms
575          * that depend upon interrupts being delivered locally.  So, for
576          * example, we cannot sample jiffies and expect it to advance.
577          *
578          * Fortunately, udelay() uses %stick/%tick so we can use that.
579          */
580         local_irq_save(flags);
581
582         this_cpu = smp_processor_id();
583         tb = &trap_block[this_cpu];
584
585         mondo = __va(tb->cpu_mondo_block_pa);
586         mondo[0] = data0;
587         mondo[1] = data1;
588         mondo[2] = data2;
589         wmb();
590
591         cpu_list = __va(tb->cpu_list_pa);
592
593         /* Setup the initial cpu list.  */
594         cnt = 0;
595         for_each_cpu_mask(i, mask)
596                 cpu_list[cnt++] = i;
597
598         cpus_clear(error_mask);
599         retries = 0;
600         prev_sent = 0;
601         do {
602                 int forward_progress, n_sent;
603
604                 status = sun4v_cpu_mondo_send(cnt,
605                                               tb->cpu_list_pa,
606                                               tb->cpu_mondo_block_pa);
607
608                 /* HV_EOK means all cpus received the xcall, we're done.  */
609                 if (likely(status == HV_EOK))
610                         break;
611
612                 /* First, see if we made any forward progress.
613                  *
614                  * The hypervisor indicates successful sends by setting
615                  * cpu list entries to the value 0xffff.
616                  */
617                 n_sent = 0;
618                 for (i = 0; i < cnt; i++) {
619                         if (likely(cpu_list[i] == 0xffff))
620                                 n_sent++;
621                 }
622
623                 forward_progress = 0;
624                 if (n_sent > prev_sent)
625                         forward_progress = 1;
626
627                 prev_sent = n_sent;
628
629                 /* If we get a HV_ECPUERROR, then one or more of the cpus
630                  * in the list are in error state.  Use the cpu_state()
631                  * hypervisor call to find out which cpus are in error state.
632                  */
633                 if (unlikely(status == HV_ECPUERROR)) {
634                         for (i = 0; i < cnt; i++) {
635                                 long err;
636                                 u16 cpu;
637
638                                 cpu = cpu_list[i];
639                                 if (cpu == 0xffff)
640                                         continue;
641
642                                 err = sun4v_cpu_state(cpu);
643                                 if (err >= 0 &&
644                                     err == HV_CPU_STATE_ERROR) {
645                                         cpu_list[i] = 0xffff;
646                                         cpu_set(cpu, error_mask);
647                                 }
648                         }
649                 } else if (unlikely(status != HV_EWOULDBLOCK))
650                         goto fatal_mondo_error;
651
652                 /* Don't bother rewriting the CPU list, just leave the
653                  * 0xffff and non-0xffff entries in there and the
654                  * hypervisor will do the right thing.
655                  *
656                  * Only advance timeout state if we didn't make any
657                  * forward progress.
658                  */
659                 if (unlikely(!forward_progress)) {
660                         if (unlikely(++retries > 10000))
661                                 goto fatal_mondo_timeout;
662
663                         /* Delay a little bit to let other cpus catch up
664                          * on their cpu mondo queue work.
665                          */
666                         udelay(2 * cnt);
667                 }
668         } while (1);
669
670         local_irq_restore(flags);
671
672         if (unlikely(!cpus_empty(error_mask)))
673                 goto fatal_mondo_cpu_error;
674
675         return;
676
677 fatal_mondo_cpu_error:
678         printk(KERN_CRIT "CPU[%d]: SUN4V mondo cpu error, some target cpus "
679                "were in error state\n",
680                this_cpu);
681         printk(KERN_CRIT "CPU[%d]: Error mask [ ", this_cpu);
682         for_each_cpu_mask(i, error_mask)
683                 printk("%d ", i);
684         printk("]\n");
685         return;
686
687 fatal_mondo_timeout:
688         local_irq_restore(flags);
689         printk(KERN_CRIT "CPU[%d]: SUN4V mondo timeout, no forward "
690                " progress after %d retries.\n",
691                this_cpu, retries);
692         goto dump_cpu_list_and_out;
693
694 fatal_mondo_error:
695         local_irq_restore(flags);
696         printk(KERN_CRIT "CPU[%d]: Unexpected SUN4V mondo error %lu\n",
697                this_cpu, status);
698         printk(KERN_CRIT "CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) "
699                "mondo_block_pa(%lx)\n",
700                this_cpu, cnt, tb->cpu_list_pa, tb->cpu_mondo_block_pa);
701
702 dump_cpu_list_and_out:
703         printk(KERN_CRIT "CPU[%d]: CPU list [ ", this_cpu);
704         for (i = 0; i < cnt; i++)
705                 printk("%u ", cpu_list[i]);
706         printk("]\n");
707 }
708
709 /* Send cross call to all processors mentioned in MASK
710  * except self.
711  */
712 static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, cpumask_t mask)
713 {
714         u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
715         int this_cpu = get_cpu();
716
717         cpus_and(mask, mask, cpu_online_map);
718         cpu_clear(this_cpu, mask);
719
720         if (tlb_type == spitfire)
721                 spitfire_xcall_deliver(data0, data1, data2, mask);
722         else if (tlb_type == cheetah || tlb_type == cheetah_plus)
723                 cheetah_xcall_deliver(data0, data1, data2, mask);
724         else
725                 hypervisor_xcall_deliver(data0, data1, data2, mask);
726         /* NOTE: Caller runs local copy on master. */
727
728         put_cpu();
729 }
730
731 extern unsigned long xcall_sync_tick;
732
733 static void smp_start_sync_tick_client(int cpu)
734 {
735         cpumask_t mask = cpumask_of_cpu(cpu);
736
737         smp_cross_call_masked(&xcall_sync_tick,
738                               0, 0, 0, mask);
739 }
740
741 /* Send cross call to all processors except self. */
742 #define smp_cross_call(func, ctx, data1, data2) \
743         smp_cross_call_masked(func, ctx, data1, data2, cpu_online_map)
744
745 struct call_data_struct {
746         void (*func) (void *info);
747         void *info;
748         atomic_t finished;
749         int wait;
750 };
751
752 static DEFINE_SPINLOCK(call_lock);
753 static struct call_data_struct *call_data;
754
755 extern unsigned long xcall_call_function;
756
757 /*
758  * You must not call this function with disabled interrupts or from a
759  * hardware interrupt handler or from a bottom half handler.
760  */
761 static int smp_call_function_mask(void (*func)(void *info), void *info,
762                                   int nonatomic, int wait, cpumask_t mask)
763 {
764         struct call_data_struct data;
765         int cpus;
766         long timeout;
767
768         /* Can deadlock when called with interrupts disabled */
769         WARN_ON(irqs_disabled());
770
771         data.func = func;
772         data.info = info;
773         atomic_set(&data.finished, 0);
774         data.wait = wait;
775
776         spin_lock(&call_lock);
777
778         cpu_clear(smp_processor_id(), mask);
779         cpus = cpus_weight(mask);
780         if (!cpus)
781                 goto out_unlock;
782
783         call_data = &data;
784
785         smp_cross_call_masked(&xcall_call_function, 0, 0, 0, mask);
786
787         /* 
788          * Wait for other cpus to complete function or at
789          * least snap the call data.
790          */
791         timeout = 1000000;
792         while (atomic_read(&data.finished) != cpus) {
793                 if (--timeout <= 0)
794                         goto out_timeout;
795                 barrier();
796                 udelay(1);
797         }
798
799 out_unlock:
800         spin_unlock(&call_lock);
801
802         return 0;
803
804 out_timeout:
805         spin_unlock(&call_lock);
806         printk("XCALL: Remote cpus not responding, ncpus=%d finished=%d\n",
807                cpus, atomic_read(&data.finished));
808         return 0;
809 }
810
811 int smp_call_function(void (*func)(void *info), void *info,
812                       int nonatomic, int wait)
813 {
814         return smp_call_function_mask(func, info, nonatomic, wait,
815                                       cpu_online_map);
816 }
817
818 void smp_call_function_client(int irq, struct pt_regs *regs)
819 {
820         void (*func) (void *info) = call_data->func;
821         void *info = call_data->info;
822
823         clear_softint(1 << irq);
824         if (call_data->wait) {
825                 /* let initiator proceed only after completion */
826                 func(info);
827                 atomic_inc(&call_data->finished);
828         } else {
829                 /* let initiator proceed after getting data */
830                 atomic_inc(&call_data->finished);
831                 func(info);
832         }
833 }
834
835 static void tsb_sync(void *info)
836 {
837         struct mm_struct *mm = info;
838
839         if (current->active_mm == mm)
840                 tsb_context_switch(mm);
841 }
842
843 void smp_tsb_sync(struct mm_struct *mm)
844 {
845         smp_call_function_mask(tsb_sync, mm, 0, 1, mm->cpu_vm_mask);
846 }
847
848 extern unsigned long xcall_flush_tlb_mm;
849 extern unsigned long xcall_flush_tlb_pending;
850 extern unsigned long xcall_flush_tlb_kernel_range;
851 extern unsigned long xcall_report_regs;
852 extern unsigned long xcall_receive_signal;
853 extern unsigned long xcall_new_mmu_context_version;
854
855 #ifdef DCACHE_ALIASING_POSSIBLE
856 extern unsigned long xcall_flush_dcache_page_cheetah;
857 #endif
858 extern unsigned long xcall_flush_dcache_page_spitfire;
859
860 #ifdef CONFIG_DEBUG_DCFLUSH
861 extern atomic_t dcpage_flushes;
862 extern atomic_t dcpage_flushes_xcall;
863 #endif
864
865 static __inline__ void __local_flush_dcache_page(struct page *page)
866 {
867 #ifdef DCACHE_ALIASING_POSSIBLE
868         __flush_dcache_page(page_address(page),
869                             ((tlb_type == spitfire) &&
870                              page_mapping(page) != NULL));
871 #else
872         if (page_mapping(page) != NULL &&
873             tlb_type == spitfire)
874                 __flush_icache_page(__pa(page_address(page)));
875 #endif
876 }
877
878 void smp_flush_dcache_page_impl(struct page *page, int cpu)
879 {
880         cpumask_t mask = cpumask_of_cpu(cpu);
881         int this_cpu;
882
883         if (tlb_type == hypervisor)
884                 return;
885
886 #ifdef CONFIG_DEBUG_DCFLUSH
887         atomic_inc(&dcpage_flushes);
888 #endif
889
890         this_cpu = get_cpu();
891
892         if (cpu == this_cpu) {
893                 __local_flush_dcache_page(page);
894         } else if (cpu_online(cpu)) {
895                 void *pg_addr = page_address(page);
896                 u64 data0;
897
898                 if (tlb_type == spitfire) {
899                         data0 =
900                                 ((u64)&xcall_flush_dcache_page_spitfire);
901                         if (page_mapping(page) != NULL)
902                                 data0 |= ((u64)1 << 32);
903                         spitfire_xcall_deliver(data0,
904                                                __pa(pg_addr),
905                                                (u64) pg_addr,
906                                                mask);
907                 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
908 #ifdef DCACHE_ALIASING_POSSIBLE
909                         data0 =
910                                 ((u64)&xcall_flush_dcache_page_cheetah);
911                         cheetah_xcall_deliver(data0,
912                                               __pa(pg_addr),
913                                               0, mask);
914 #endif
915                 }
916 #ifdef CONFIG_DEBUG_DCFLUSH
917                 atomic_inc(&dcpage_flushes_xcall);
918 #endif
919         }
920
921         put_cpu();
922 }
923
924 void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
925 {
926         void *pg_addr = page_address(page);
927         cpumask_t mask = cpu_online_map;
928         u64 data0;
929         int this_cpu;
930
931         if (tlb_type == hypervisor)
932                 return;
933
934         this_cpu = get_cpu();
935
936         cpu_clear(this_cpu, mask);
937
938 #ifdef CONFIG_DEBUG_DCFLUSH
939         atomic_inc(&dcpage_flushes);
940 #endif
941         if (cpus_empty(mask))
942                 goto flush_self;
943         if (tlb_type == spitfire) {
944                 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
945                 if (page_mapping(page) != NULL)
946                         data0 |= ((u64)1 << 32);
947                 spitfire_xcall_deliver(data0,
948                                        __pa(pg_addr),
949                                        (u64) pg_addr,
950                                        mask);
951         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
952 #ifdef DCACHE_ALIASING_POSSIBLE
953                 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
954                 cheetah_xcall_deliver(data0,
955                                       __pa(pg_addr),
956                                       0, mask);
957 #endif
958         }
959 #ifdef CONFIG_DEBUG_DCFLUSH
960         atomic_inc(&dcpage_flushes_xcall);
961 #endif
962  flush_self:
963         __local_flush_dcache_page(page);
964
965         put_cpu();
966 }
967
968 static void __smp_receive_signal_mask(cpumask_t mask)
969 {
970         smp_cross_call_masked(&xcall_receive_signal, 0, 0, 0, mask);
971 }
972
973 void smp_receive_signal(int cpu)
974 {
975         cpumask_t mask = cpumask_of_cpu(cpu);
976
977         if (cpu_online(cpu))
978                 __smp_receive_signal_mask(mask);
979 }
980
981 void smp_receive_signal_client(int irq, struct pt_regs *regs)
982 {
983         clear_softint(1 << irq);
984 }
985
986 void smp_new_mmu_context_version_client(int irq, struct pt_regs *regs)
987 {
988         struct mm_struct *mm;
989         unsigned long flags;
990
991         clear_softint(1 << irq);
992
993         /* See if we need to allocate a new TLB context because
994          * the version of the one we are using is now out of date.
995          */
996         mm = current->active_mm;
997         if (unlikely(!mm || (mm == &init_mm)))
998                 return;
999
1000         spin_lock_irqsave(&mm->context.lock, flags);
1001
1002         if (unlikely(!CTX_VALID(mm->context)))
1003                 get_new_mmu_context(mm);
1004
1005         spin_unlock_irqrestore(&mm->context.lock, flags);
1006
1007         load_secondary_context(mm);
1008         __flush_tlb_mm(CTX_HWBITS(mm->context),
1009                        SECONDARY_CONTEXT);
1010 }
1011
1012 void smp_new_mmu_context_version(void)
1013 {
1014         smp_cross_call(&xcall_new_mmu_context_version, 0, 0, 0);
1015 }
1016
1017 void smp_report_regs(void)
1018 {
1019         smp_cross_call(&xcall_report_regs, 0, 0, 0);
1020 }
1021
1022 /* We know that the window frames of the user have been flushed
1023  * to the stack before we get here because all callers of us
1024  * are flush_tlb_*() routines, and these run after flush_cache_*()
1025  * which performs the flushw.
1026  *
1027  * The SMP TLB coherency scheme we use works as follows:
1028  *
1029  * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
1030  *    space has (potentially) executed on, this is the heuristic
1031  *    we use to avoid doing cross calls.
1032  *
1033  *    Also, for flushing from kswapd and also for clones, we
1034  *    use cpu_vm_mask as the list of cpus to make run the TLB.
1035  *
1036  * 2) TLB context numbers are shared globally across all processors
1037  *    in the system, this allows us to play several games to avoid
1038  *    cross calls.
1039  *
1040  *    One invariant is that when a cpu switches to a process, and
1041  *    that processes tsk->active_mm->cpu_vm_mask does not have the
1042  *    current cpu's bit set, that tlb context is flushed locally.
1043  *
1044  *    If the address space is non-shared (ie. mm->count == 1) we avoid
1045  *    cross calls when we want to flush the currently running process's
1046  *    tlb state.  This is done by clearing all cpu bits except the current
1047  *    processor's in current->active_mm->cpu_vm_mask and performing the
1048  *    flush locally only.  This will force any subsequent cpus which run
1049  *    this task to flush the context from the local tlb if the process
1050  *    migrates to another cpu (again).
1051  *
1052  * 3) For shared address spaces (threads) and swapping we bite the
1053  *    bullet for most cases and perform the cross call (but only to
1054  *    the cpus listed in cpu_vm_mask).
1055  *
1056  *    The performance gain from "optimizing" away the cross call for threads is
1057  *    questionable (in theory the big win for threads is the massive sharing of
1058  *    address space state across processors).
1059  */
1060
1061 /* This currently is only used by the hugetlb arch pre-fault
1062  * hook on UltraSPARC-III+ and later when changing the pagesize
1063  * bits of the context register for an address space.
1064  */
1065 void smp_flush_tlb_mm(struct mm_struct *mm)
1066 {
1067         u32 ctx = CTX_HWBITS(mm->context);
1068         int cpu = get_cpu();
1069
1070         if (atomic_read(&mm->mm_users) == 1) {
1071                 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
1072                 goto local_flush_and_out;
1073         }
1074
1075         smp_cross_call_masked(&xcall_flush_tlb_mm,
1076                               ctx, 0, 0,
1077                               mm->cpu_vm_mask);
1078
1079 local_flush_and_out:
1080         __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
1081
1082         put_cpu();
1083 }
1084
1085 void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
1086 {
1087         u32 ctx = CTX_HWBITS(mm->context);
1088         int cpu = get_cpu();
1089
1090         if (mm == current->active_mm && atomic_read(&mm->mm_users) == 1)
1091                 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
1092         else
1093                 smp_cross_call_masked(&xcall_flush_tlb_pending,
1094                                       ctx, nr, (unsigned long) vaddrs,
1095                                       mm->cpu_vm_mask);
1096
1097         __flush_tlb_pending(ctx, nr, vaddrs);
1098
1099         put_cpu();
1100 }
1101
1102 void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
1103 {
1104         start &= PAGE_MASK;
1105         end    = PAGE_ALIGN(end);
1106         if (start != end) {
1107                 smp_cross_call(&xcall_flush_tlb_kernel_range,
1108                                0, start, end);
1109
1110                 __flush_tlb_kernel_range(start, end);
1111         }
1112 }
1113
1114 /* CPU capture. */
1115 /* #define CAPTURE_DEBUG */
1116 extern unsigned long xcall_capture;
1117
1118 static atomic_t smp_capture_depth = ATOMIC_INIT(0);
1119 static atomic_t smp_capture_registry = ATOMIC_INIT(0);
1120 static unsigned long penguins_are_doing_time;
1121
1122 void smp_capture(void)
1123 {
1124         int result = atomic_add_ret(1, &smp_capture_depth);
1125
1126         if (result == 1) {
1127                 int ncpus = num_online_cpus();
1128
1129 #ifdef CAPTURE_DEBUG
1130                 printk("CPU[%d]: Sending penguins to jail...",
1131                        smp_processor_id());
1132 #endif
1133                 penguins_are_doing_time = 1;
1134                 membar_storestore_loadstore();
1135                 atomic_inc(&smp_capture_registry);
1136                 smp_cross_call(&xcall_capture, 0, 0, 0);
1137                 while (atomic_read(&smp_capture_registry) != ncpus)
1138                         rmb();
1139 #ifdef CAPTURE_DEBUG
1140                 printk("done\n");
1141 #endif
1142         }
1143 }
1144
1145 void smp_release(void)
1146 {
1147         if (atomic_dec_and_test(&smp_capture_depth)) {
1148 #ifdef CAPTURE_DEBUG
1149                 printk("CPU[%d]: Giving pardon to "
1150                        "imprisoned penguins\n",
1151                        smp_processor_id());
1152 #endif
1153                 penguins_are_doing_time = 0;
1154                 membar_storeload_storestore();
1155                 atomic_dec(&smp_capture_registry);
1156         }
1157 }
1158
1159 /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they
1160  * can service tlb flush xcalls...
1161  */
1162 extern void prom_world(int);
1163
1164 void smp_penguin_jailcell(int irq, struct pt_regs *regs)
1165 {
1166         clear_softint(1 << irq);
1167
1168         preempt_disable();
1169
1170         __asm__ __volatile__("flushw");
1171         prom_world(1);
1172         atomic_inc(&smp_capture_registry);
1173         membar_storeload_storestore();
1174         while (penguins_are_doing_time)
1175                 rmb();
1176         atomic_dec(&smp_capture_registry);
1177         prom_world(0);
1178
1179         preempt_enable();
1180 }
1181
1182 #define prof_multiplier(__cpu)          cpu_data(__cpu).multiplier
1183 #define prof_counter(__cpu)             cpu_data(__cpu).counter
1184
1185 void smp_percpu_timer_interrupt(struct pt_regs *regs)
1186 {
1187         unsigned long compare, tick, pstate;
1188         int cpu = smp_processor_id();
1189         int user = user_mode(regs);
1190
1191         /*
1192          * Check for level 14 softint.
1193          */
1194         {
1195                 unsigned long tick_mask = tick_ops->softint_mask;
1196
1197                 if (!(get_softint() & tick_mask)) {
1198                         extern void handler_irq(int, struct pt_regs *);
1199
1200                         handler_irq(14, regs);
1201                         return;
1202                 }
1203                 clear_softint(tick_mask);
1204         }
1205
1206         do {
1207                 profile_tick(CPU_PROFILING, regs);
1208                 if (!--prof_counter(cpu)) {
1209                         irq_enter();
1210
1211                         if (cpu == boot_cpu_id) {
1212                                 kstat_this_cpu.irqs[0]++;
1213                                 timer_tick_interrupt(regs);
1214                         }
1215
1216                         update_process_times(user);
1217
1218                         irq_exit();
1219
1220                         prof_counter(cpu) = prof_multiplier(cpu);
1221                 }
1222
1223                 /* Guarantee that the following sequences execute
1224                  * uninterrupted.
1225                  */
1226                 __asm__ __volatile__("rdpr      %%pstate, %0\n\t"
1227                                      "wrpr      %0, %1, %%pstate"
1228                                      : "=r" (pstate)
1229                                      : "i" (PSTATE_IE));
1230
1231                 compare = tick_ops->add_compare(current_tick_offset);
1232                 tick = tick_ops->get_tick();
1233
1234                 /* Restore PSTATE_IE. */
1235                 __asm__ __volatile__("wrpr      %0, 0x0, %%pstate"
1236                                      : /* no outputs */
1237                                      : "r" (pstate));
1238         } while (time_after_eq(tick, compare));
1239 }
1240
1241 static void __init smp_setup_percpu_timer(void)
1242 {
1243         int cpu = smp_processor_id();
1244         unsigned long pstate;
1245
1246         prof_counter(cpu) = prof_multiplier(cpu) = 1;
1247
1248         /* Guarantee that the following sequences execute
1249          * uninterrupted.
1250          */
1251         __asm__ __volatile__("rdpr      %%pstate, %0\n\t"
1252                              "wrpr      %0, %1, %%pstate"
1253                              : "=r" (pstate)
1254                              : "i" (PSTATE_IE));
1255
1256         tick_ops->init_tick(current_tick_offset);
1257
1258         /* Restore PSTATE_IE. */
1259         __asm__ __volatile__("wrpr      %0, 0x0, %%pstate"
1260                              : /* no outputs */
1261                              : "r" (pstate));
1262 }
1263
1264 void __init smp_tick_init(void)
1265 {
1266         boot_cpu_id = hard_smp_processor_id();
1267         current_tick_offset = timer_tick_offset;
1268
1269         cpu_set(boot_cpu_id, cpu_online_map);
1270         prof_counter(boot_cpu_id) = prof_multiplier(boot_cpu_id) = 1;
1271 }
1272
1273 /* /proc/profile writes can call this, don't __init it please. */
1274 static DEFINE_SPINLOCK(prof_setup_lock);
1275
1276 int setup_profiling_timer(unsigned int multiplier)
1277 {
1278         unsigned long flags;
1279         int i;
1280
1281         if ((!multiplier) || (timer_tick_offset / multiplier) < 1000)
1282                 return -EINVAL;
1283
1284         spin_lock_irqsave(&prof_setup_lock, flags);
1285         for (i = 0; i < NR_CPUS; i++)
1286                 prof_multiplier(i) = multiplier;
1287         current_tick_offset = (timer_tick_offset / multiplier);
1288         spin_unlock_irqrestore(&prof_setup_lock, flags);
1289
1290         return 0;
1291 }
1292
1293 /* Constrain the number of cpus to max_cpus.  */
1294 void __init smp_prepare_cpus(unsigned int max_cpus)
1295 {
1296         int i;
1297
1298         if (num_possible_cpus() > max_cpus) {
1299                 int instance, mid;
1300
1301                 instance = 0;
1302                 while (!cpu_find_by_instance(instance, NULL, &mid)) {
1303                         if (mid != boot_cpu_id) {
1304                                 cpu_clear(mid, phys_cpu_present_map);
1305                                 if (num_possible_cpus() <= max_cpus)
1306                                         break;
1307                         }
1308                         instance++;
1309                 }
1310         }
1311
1312         for_each_cpu(i) {
1313                 if (tlb_type == hypervisor) {
1314                         int j;
1315
1316                         /* XXX get this mapping from machine description */
1317                         for_each_cpu(j) {
1318                                 if ((j >> 2) == (i >> 2))
1319                                         cpu_set(j, cpu_sibling_map[i]);
1320                         }
1321                 } else {
1322                         cpu_set(i, cpu_sibling_map[i]);
1323                 }
1324         }
1325
1326         smp_store_cpu_info(boot_cpu_id);
1327 }
1328
1329 /* Set this up early so that things like the scheduler can init
1330  * properly.  We use the same cpu mask for both the present and
1331  * possible cpu map.
1332  */
1333 void __init smp_setup_cpu_possible_map(void)
1334 {
1335         int instance, mid;
1336
1337         instance = 0;
1338         while (!cpu_find_by_instance(instance, NULL, &mid)) {
1339                 if (mid < NR_CPUS)
1340                         cpu_set(mid, phys_cpu_present_map);
1341                 instance++;
1342         }
1343 }
1344
1345 void __devinit smp_prepare_boot_cpu(void)
1346 {
1347         int cpu = hard_smp_processor_id();
1348
1349         if (cpu >= NR_CPUS) {
1350                 prom_printf("Serious problem, boot cpu id >= NR_CPUS\n");
1351                 prom_halt();
1352         }
1353
1354         current_thread_info()->cpu = cpu;
1355         __local_per_cpu_offset = __per_cpu_offset(cpu);
1356
1357         cpu_set(smp_processor_id(), cpu_online_map);
1358         cpu_set(smp_processor_id(), phys_cpu_present_map);
1359 }
1360
1361 int __devinit __cpu_up(unsigned int cpu)
1362 {
1363         int ret = smp_boot_one_cpu(cpu);
1364
1365         if (!ret) {
1366                 cpu_set(cpu, smp_commenced_mask);
1367                 while (!cpu_isset(cpu, cpu_online_map))
1368                         mb();
1369                 if (!cpu_isset(cpu, cpu_online_map)) {
1370                         ret = -ENODEV;
1371                 } else {
1372                         /* On SUN4V, writes to %tick and %stick are
1373                          * not allowed.
1374                          */
1375                         if (tlb_type != hypervisor)
1376                                 smp_synchronize_one_tick(cpu);
1377                 }
1378         }
1379         return ret;
1380 }
1381
1382 void __init smp_cpus_done(unsigned int max_cpus)
1383 {
1384         unsigned long bogosum = 0;
1385         int i;
1386
1387         for (i = 0; i < NR_CPUS; i++) {
1388                 if (cpu_online(i))
1389                         bogosum += cpu_data(i).udelay_val;
1390         }
1391         printk("Total of %ld processors activated "
1392                "(%lu.%02lu BogoMIPS).\n",
1393                (long) num_online_cpus(),
1394                bogosum/(500000/HZ),
1395                (bogosum/(5000/HZ))%100);
1396 }
1397
1398 void smp_send_reschedule(int cpu)
1399 {
1400         smp_receive_signal(cpu);
1401 }
1402
1403 /* This is a nop because we capture all other cpus
1404  * anyways when making the PROM active.
1405  */
1406 void smp_send_stop(void)
1407 {
1408 }
1409
1410 unsigned long __per_cpu_base __read_mostly;
1411 unsigned long __per_cpu_shift __read_mostly;
1412
1413 EXPORT_SYMBOL(__per_cpu_base);
1414 EXPORT_SYMBOL(__per_cpu_shift);
1415
1416 void __init setup_per_cpu_areas(void)
1417 {
1418         unsigned long goal, size, i;
1419         char *ptr;
1420
1421         /* Copy section for each CPU (we discard the original) */
1422         goal = ALIGN(__per_cpu_end - __per_cpu_start, SMP_CACHE_BYTES);
1423 #ifdef CONFIG_MODULES
1424         if (goal < PERCPU_ENOUGH_ROOM)
1425                 goal = PERCPU_ENOUGH_ROOM;
1426 #endif
1427         __per_cpu_shift = 0;
1428         for (size = 1UL; size < goal; size <<= 1UL)
1429                 __per_cpu_shift++;
1430
1431         ptr = alloc_bootmem(size * NR_CPUS);
1432
1433         __per_cpu_base = ptr - __per_cpu_start;
1434
1435         for (i = 0; i < NR_CPUS; i++, ptr += size)
1436                 memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);
1437 }