git.oblomov.eu Git - linux-2.6/blob - drivers/infiniband/hw/ipath/ipath_iba6120.c

   1 /*
   2  * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
   3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33 /*
  34  * This file contains all of the code that is specific to the
  35  * InfiniPath PCIe chip.
  36  */
  37
  38 #include <linux/interrupt.h>
  39 #include <linux/pci.h>
  40 #include <linux/delay.h>
  41
  42
  43 #include "ipath_kernel.h"
  44 #include "ipath_registers.h"
  45
  46 static void ipath_setup_pe_setextled(struct ipath_devdata *, u64, u64);
  47
  48 /*
  49  * This file contains all the chip-specific register information and
  50  * access functions for the QLogic InfiniPath PCI-Express chip.
  51  *
  52  * This lists the InfiniPath registers, in the actual chip layout.
  53  * This structure should never be directly accessed.
  54  */
  55 struct _infinipath_do_not_use_kernel_regs {
  56         unsigned long long Revision;
  57         unsigned long long Control;
  58         unsigned long long PageAlign;
  59         unsigned long long PortCnt;
  60         unsigned long long DebugPortSelect;
  61         unsigned long long Reserved0;
  62         unsigned long long SendRegBase;
  63         unsigned long long UserRegBase;
  64         unsigned long long CounterRegBase;
  65         unsigned long long Scratch;
  66         unsigned long long Reserved1;
  67         unsigned long long Reserved2;
  68         unsigned long long IntBlocked;
  69         unsigned long long IntMask;
  70         unsigned long long IntStatus;
  71         unsigned long long IntClear;
  72         unsigned long long ErrorMask;
  73         unsigned long long ErrorStatus;
  74         unsigned long long ErrorClear;
  75         unsigned long long HwErrMask;
  76         unsigned long long HwErrStatus;
  77         unsigned long long HwErrClear;
  78         unsigned long long HwDiagCtrl;
  79         unsigned long long MDIO;
  80         unsigned long long IBCStatus;
  81         unsigned long long IBCCtrl;
  82         unsigned long long ExtStatus;
  83         unsigned long long ExtCtrl;
  84         unsigned long long GPIOOut;
  85         unsigned long long GPIOMask;
  86         unsigned long long GPIOStatus;
  87         unsigned long long GPIOClear;
  88         unsigned long long RcvCtrl;
  89         unsigned long long RcvBTHQP;
  90         unsigned long long RcvHdrSize;
  91         unsigned long long RcvHdrCnt;
  92         unsigned long long RcvHdrEntSize;
  93         unsigned long long RcvTIDBase;
  94         unsigned long long RcvTIDCnt;
  95         unsigned long long RcvEgrBase;
  96         unsigned long long RcvEgrCnt;
  97         unsigned long long RcvBufBase;
  98         unsigned long long RcvBufSize;
  99         unsigned long long RxIntMemBase;
 100         unsigned long long RxIntMemSize;
 101         unsigned long long RcvPartitionKey;
 102         unsigned long long Reserved3;
 103         unsigned long long RcvPktLEDCnt;
 104         unsigned long long Reserved4[8];
 105         unsigned long long SendCtrl;
 106         unsigned long long SendPIOBufBase;
 107         unsigned long long SendPIOSize;
 108         unsigned long long SendPIOBufCnt;
 109         unsigned long long SendPIOAvailAddr;
 110         unsigned long long TxIntMemBase;
 111         unsigned long long TxIntMemSize;
 112         unsigned long long Reserved5;
 113         unsigned long long PCIeRBufTestReg0;
 114         unsigned long long PCIeRBufTestReg1;
 115         unsigned long long Reserved51[6];
 116         unsigned long long SendBufferError;
 117         unsigned long long SendBufferErrorCONT1;
 118         unsigned long long Reserved6SBE[6];
 119         unsigned long long RcvHdrAddr0;
 120         unsigned long long RcvHdrAddr1;
 121         unsigned long long RcvHdrAddr2;
 122         unsigned long long RcvHdrAddr3;
 123         unsigned long long RcvHdrAddr4;
 124         unsigned long long Reserved7RHA[11];
 125         unsigned long long RcvHdrTailAddr0;
 126         unsigned long long RcvHdrTailAddr1;
 127         unsigned long long RcvHdrTailAddr2;
 128         unsigned long long RcvHdrTailAddr3;
 129         unsigned long long RcvHdrTailAddr4;
 130         unsigned long long Reserved8RHTA[11];
 131         unsigned long long Reserved9SW[8];
 132         unsigned long long SerdesConfig0;
 133         unsigned long long SerdesConfig1;
 134         unsigned long long SerdesStatus;
 135         unsigned long long XGXSConfig;
 136         unsigned long long IBPLLCfg;
 137         unsigned long long Reserved10SW2[3];
 138         unsigned long long PCIEQ0SerdesConfig0;
 139         unsigned long long PCIEQ0SerdesConfig1;
 140         unsigned long long PCIEQ0SerdesStatus;
 141         unsigned long long Reserved11;
 142         unsigned long long PCIEQ1SerdesConfig0;
 143         unsigned long long PCIEQ1SerdesConfig1;
 144         unsigned long long PCIEQ1SerdesStatus;
 145         unsigned long long Reserved12;
 146 };
 147
 148 struct _infinipath_do_not_use_counters {
 149         __u64 LBIntCnt;
 150         __u64 LBFlowStallCnt;
 151         __u64 Reserved1;
 152         __u64 TxUnsupVLErrCnt;
 153         __u64 TxDataPktCnt;
 154         __u64 TxFlowPktCnt;
 155         __u64 TxDwordCnt;
 156         __u64 TxLenErrCnt;
 157         __u64 TxMaxMinLenErrCnt;
 158         __u64 TxUnderrunCnt;
 159         __u64 TxFlowStallCnt;
 160         __u64 TxDroppedPktCnt;
 161         __u64 RxDroppedPktCnt;
 162         __u64 RxDataPktCnt;
 163         __u64 RxFlowPktCnt;
 164         __u64 RxDwordCnt;
 165         __u64 RxLenErrCnt;
 166         __u64 RxMaxMinLenErrCnt;
 167         __u64 RxICRCErrCnt;
 168         __u64 RxVCRCErrCnt;
 169         __u64 RxFlowCtrlErrCnt;
 170         __u64 RxBadFormatCnt;
 171         __u64 RxLinkProblemCnt;
 172         __u64 RxEBPCnt;
 173         __u64 RxLPCRCErrCnt;
 174         __u64 RxBufOvflCnt;
 175         __u64 RxTIDFullErrCnt;
 176         __u64 RxTIDValidErrCnt;
 177         __u64 RxPKeyMismatchCnt;
 178         __u64 RxP0HdrEgrOvflCnt;
 179         __u64 RxP1HdrEgrOvflCnt;
 180         __u64 RxP2HdrEgrOvflCnt;
 181         __u64 RxP3HdrEgrOvflCnt;
 182         __u64 RxP4HdrEgrOvflCnt;
 183         __u64 RxP5HdrEgrOvflCnt;
 184         __u64 RxP6HdrEgrOvflCnt;
 185         __u64 RxP7HdrEgrOvflCnt;
 186         __u64 RxP8HdrEgrOvflCnt;
 187         __u64 Reserved6;
 188         __u64 Reserved7;
 189         __u64 IBStatusChangeCnt;
 190         __u64 IBLinkErrRecoveryCnt;
 191         __u64 IBLinkDownedCnt;
 192         __u64 IBSymbolErrCnt;
 193 };
 194
 195 #define IPATH_KREG_OFFSET(field) (offsetof( \
 196         struct _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
 197 #define IPATH_CREG_OFFSET(field) (offsetof( \
 198         struct _infinipath_do_not_use_counters, field) / sizeof(u64))
 199
 200 static const struct ipath_kregs ipath_pe_kregs = {
 201         .kr_control = IPATH_KREG_OFFSET(Control),
 202         .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
 203         .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
 204         .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
 205         .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
 206         .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
 207         .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
 208         .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
 209         .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
 210         .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
 211         .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
 212         .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
 213         .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
 214         .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
 215         .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
 216         .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
 217         .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
 218         .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
 219         .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
 220         .kr_intclear = IPATH_KREG_OFFSET(IntClear),
 221         .kr_intmask = IPATH_KREG_OFFSET(IntMask),
 222         .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
 223         .kr_mdio = IPATH_KREG_OFFSET(MDIO),
 224         .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
 225         .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
 226         .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
 227         .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
 228         .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
 229         .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
 230         .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
 231         .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
 232         .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
 233         .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
 234         .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
 235         .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
 236         .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
 237         .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
 238         .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
 239         .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
 240         .kr_revision = IPATH_KREG_OFFSET(Revision),
 241         .kr_scratch = IPATH_KREG_OFFSET(Scratch),
 242         .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
 243         .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
 244         .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
 245         .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
 246         .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
 247         .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
 248         .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
 249         .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
 250         .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
 251         .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
 252         .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
 253         .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
 254         .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
 255         .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
 256         .kr_ibpllcfg = IPATH_KREG_OFFSET(IBPLLCfg),
 257
 258         /*
 259          * These should not be used directly via ipath_write_kreg64(),
 260          * use them with ipath_write_kreg64_port(),
 261          */
 262         .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
 263         .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0),
 264
 265         /* The rcvpktled register controls one of the debug port signals, so
 266          * a packet activity LED can be connected to it. */
 267         .kr_rcvpktledcnt = IPATH_KREG_OFFSET(RcvPktLEDCnt),
 268         .kr_pcierbuftestreg0 = IPATH_KREG_OFFSET(PCIeRBufTestReg0),
 269         .kr_pcierbuftestreg1 = IPATH_KREG_OFFSET(PCIeRBufTestReg1),
 270         .kr_pcieq0serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig0),
 271         .kr_pcieq0serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig1),
 272         .kr_pcieq0serdesstatus = IPATH_KREG_OFFSET(PCIEQ0SerdesStatus),
 273         .kr_pcieq1serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig0),
 274         .kr_pcieq1serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig1),
 275         .kr_pcieq1serdesstatus = IPATH_KREG_OFFSET(PCIEQ1SerdesStatus)
 276 };
 277
 278 static const struct ipath_cregs ipath_pe_cregs = {
 279         .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
 280         .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
 281         .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
 282         .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
 283         .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
 284         .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
 285         .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
 286         .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
 287         .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
 288         .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
 289         .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
 290         .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
 291         .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
 292         .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
 293         .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
 294         .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
 295         .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
 296         .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
 297         .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
 298         .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
 299         .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
 300         .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
 301         .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
 302         .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
 303         .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
 304         .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
 305         .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
 306         .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
 307         .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
 308         .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
 309         .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
 310         .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
 311         .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
 312 };
 313
 314 /* kr_intstatus, kr_intclear, kr_intmask bits */
 315 #define INFINIPATH_I_RCVURG_MASK ((1U<<5)-1)
 316 #define INFINIPATH_I_RCVAVAIL_MASK ((1U<<5)-1)
 317
 318 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
 319 #define INFINIPATH_HWE_PCIEMEMPARITYERR_MASK  0x000000000000003fULL
 320 #define INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT 0
 321 #define INFINIPATH_HWE_PCIEPOISONEDTLP      0x0000000010000000ULL
 322 #define INFINIPATH_HWE_PCIECPLTIMEOUT       0x0000000020000000ULL
 323 #define INFINIPATH_HWE_PCIEBUSPARITYXTLH    0x0000000040000000ULL
 324 #define INFINIPATH_HWE_PCIEBUSPARITYXADM    0x0000000080000000ULL
 325 #define INFINIPATH_HWE_PCIEBUSPARITYRADM    0x0000000100000000ULL
 326 #define INFINIPATH_HWE_COREPLL_FBSLIP       0x0080000000000000ULL
 327 #define INFINIPATH_HWE_COREPLL_RFSLIP       0x0100000000000000ULL
 328 #define INFINIPATH_HWE_PCIE1PLLFAILED       0x0400000000000000ULL
 329 #define INFINIPATH_HWE_PCIE0PLLFAILED       0x0800000000000000ULL
 330 #define INFINIPATH_HWE_SERDESPLLFAILED      0x1000000000000000ULL
 331
 332 #define IBA6120_IBCS_LINKTRAININGSTATE_MASK 0xf
 333 #define IBA6120_IBCS_LINKSTATE_SHIFT 4
 334
 335 /* kr_extstatus bits */
 336 #define INFINIPATH_EXTS_FREQSEL 0x2
 337 #define INFINIPATH_EXTS_SERDESSEL 0x4
 338 #define INFINIPATH_EXTS_MEMBIST_ENDTEST     0x0000000000004000
 339 #define INFINIPATH_EXTS_MEMBIST_FOUND       0x0000000000008000
 340
 341 #define _IPATH_GPIO_SDA_NUM 1
 342 #define _IPATH_GPIO_SCL_NUM 0
 343
 344 #define IPATH_GPIO_SDA (1ULL << \
 345         (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
 346 #define IPATH_GPIO_SCL (1ULL << \
 347         (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
 348
 349 #define INFINIPATH_R_INTRAVAIL_SHIFT 16
 350 #define INFINIPATH_R_TAILUPD_SHIFT 31
 351
 352 /* 6120 specific hardware errors... */
 353 static const struct ipath_hwerror_msgs ipath_6120_hwerror_msgs[] = {
 354         INFINIPATH_HWE_MSG(PCIEPOISONEDTLP, "PCIe Poisoned TLP"),
 355         INFINIPATH_HWE_MSG(PCIECPLTIMEOUT, "PCIe completion timeout"),
 356         /*
 357          * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
 358          * parity or memory parity error failures, because most likely we
 359          * won't be able to talk to the core of the chip.  Nonetheless, we
 360          * might see them, if they are in parts of the PCIe core that aren't
 361          * essential.
 362          */
 363         INFINIPATH_HWE_MSG(PCIE1PLLFAILED, "PCIePLL1"),
 364         INFINIPATH_HWE_MSG(PCIE0PLLFAILED, "PCIePLL0"),
 365         INFINIPATH_HWE_MSG(PCIEBUSPARITYXTLH, "PCIe XTLH core parity"),
 366         INFINIPATH_HWE_MSG(PCIEBUSPARITYXADM, "PCIe ADM TX core parity"),
 367         INFINIPATH_HWE_MSG(PCIEBUSPARITYRADM, "PCIe ADM RX core parity"),
 368         INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
 369         INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
 370 };
 371
 372 #define TXE_PIO_PARITY ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF | \
 373                         INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC) \
 374                         << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)
 375
 376 static int ipath_pe_txe_recover(struct ipath_devdata *);
 377 static void ipath_pe_put_tid_2(struct ipath_devdata *, u64 __iomem *,
 378                                u32, unsigned long);
 379
 380 /**
 381  * ipath_pe_handle_hwerrors - display hardware errors.
 382  * @dd: the infinipath device
 383  * @msg: the output buffer
 384  * @msgl: the size of the output buffer
 385  *
 386  * Use same msg buffer as regular errors to avoid excessive stack
 387  * use.  Most hardware errors are catastrophic, but for right now,
 388  * we'll print them and continue.  We reuse the same message buffer as
 389  * ipath_handle_errors() to avoid excessive stack usage.
 390  */
 391 static void ipath_pe_handle_hwerrors(struct ipath_devdata *dd, char *msg,
 392                                      size_t msgl)
 393 {
 394         ipath_err_t hwerrs;
 395         u32 bits, ctrl;
 396         int isfatal = 0;
 397         char bitsmsg[64];
 398         int log_idx;
 399
 400         hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
 401         if (!hwerrs) {
 402                 /*
 403                  * better than printing cofusing messages
 404                  * This seems to be related to clearing the crc error, or
 405                  * the pll error during init.
 406                  */
 407                 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
 408                 return;
 409         } else if (hwerrs == ~0ULL) {
 410                 ipath_dev_err(dd, "Read of hardware error status failed "
 411                               "(all bits set); ignoring\n");
 412                 return;
 413         }
 414         ipath_stats.sps_hwerrs++;
 415
 416         /* Always clear the error status register, except MEMBISTFAIL,
 417          * regardless of whether we continue or stop using the chip.
 418          * We want that set so we know it failed, even across driver reload.
 419          * We'll still ignore it in the hwerrmask.  We do this partly for
 420          * diagnostics, but also for support */
 421         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 422                          hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
 423
 424         hwerrs &= dd->ipath_hwerrmask;
 425
 426         /* We log some errors to EEPROM, check if we have any of those. */
 427         for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx)
 428                 if (hwerrs & dd->ipath_eep_st_masks[log_idx].hwerrs_to_log)
 429                         ipath_inc_eeprom_err(dd, log_idx, 1);
 430
 431         /*
 432          * make sure we get this much out, unless told to be quiet,
 433          * or it's occurred within the last 5 seconds
 434          */
 435         if ((hwerrs & ~(dd->ipath_lasthwerror |
 436                         ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF |
 437                           INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC)
 438                          << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT))) ||
 439             (ipath_debug & __IPATH_VERBDBG))
 440                 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
 441                          "(cleared)\n", (unsigned long long) hwerrs);
 442         dd->ipath_lasthwerror |= hwerrs;
 443
 444         if (hwerrs & ~dd->ipath_hwe_bitsextant)
 445                 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
 446                               "%llx set\n", (unsigned long long)
 447                               (hwerrs & ~dd->ipath_hwe_bitsextant));
 448
 449         ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
 450         if (ctrl & INFINIPATH_C_FREEZEMODE) {
 451                 /*
 452                  * parity errors in send memory are recoverable,
 453                  * just cancel the send (if indicated in * sendbuffererror),
 454                  * count the occurrence, unfreeze (if no other handled
 455                  * hardware error bits are set), and continue. They can
 456                  * occur if a processor speculative read is done to the PIO
 457                  * buffer while we are sending a packet, for example.
 458                  */
 459                 if ((hwerrs & TXE_PIO_PARITY) && ipath_pe_txe_recover(dd))
 460                         hwerrs &= ~TXE_PIO_PARITY;
 461                 if (hwerrs) {
 462                         /*
 463                          * if any set that we aren't ignoring only make the
 464                          * complaint once, in case it's stuck or recurring,
 465                          * and we get here multiple times
 466                          * Force link down, so switch knows, and
 467                          * LEDs are turned off
 468                          */
 469                         if (dd->ipath_flags & IPATH_INITTED) {
 470                                 ipath_set_linkstate(dd, IPATH_IB_LINKDOWN);
 471                                 ipath_setup_pe_setextled(dd,
 472                                         INFINIPATH_IBCS_L_STATE_DOWN,
 473                                         INFINIPATH_IBCS_LT_STATE_DISABLED);
 474                                 ipath_dev_err(dd, "Fatal Hardware Error (freeze "
 475                                               "mode), no longer usable, SN %.16s\n",
 476                                                   dd->ipath_serial);
 477                                 isfatal = 1;
 478                         }
 479                         /*
 480                          * Mark as having had an error for driver, and also
 481                          * for /sys and status word mapped to user programs.
 482                          * This marks unit as not usable, until reset
 483                          */
 484                         *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
 485                         *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
 486                         dd->ipath_flags &= ~IPATH_INITTED;
 487                 } else {
 488                         static u32 freeze_cnt;
 489
 490                         freeze_cnt++;
 491                         ipath_dbg("Clearing freezemode on ignored or recovered "
 492                                   "hardware error (%u)\n", freeze_cnt);
 493                         ipath_clear_freeze(dd);
 494                 }
 495         }
 496
 497         *msg = '\0';
 498
 499         if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
 500                 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]",
 501                         msgl);
 502                 /* ignore from now on, so disable until driver reloaded */
 503                 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
 504                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
 505                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 506                                  dd->ipath_hwerrmask);
 507         }
 508
 509         ipath_format_hwerrors(hwerrs,
 510                               ipath_6120_hwerror_msgs,
 511                               sizeof(ipath_6120_hwerror_msgs)/
 512                               sizeof(ipath_6120_hwerror_msgs[0]),
 513                               msg, msgl);
 514
 515         if (hwerrs & (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK
 516                       << INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT)) {
 517                 bits = (u32) ((hwerrs >>
 518                                INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) &
 519                               INFINIPATH_HWE_PCIEMEMPARITYERR_MASK);
 520                 snprintf(bitsmsg, sizeof bitsmsg,
 521                          "[PCIe Mem Parity Errs %x] ", bits);
 522                 strlcat(msg, bitsmsg, msgl);
 523         }
 524
 525 #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP |        \
 526                          INFINIPATH_HWE_COREPLL_RFSLIP )
 527
 528         if (hwerrs & _IPATH_PLL_FAIL) {
 529                 snprintf(bitsmsg, sizeof bitsmsg,
 530                          "[PLL failed (%llx), InfiniPath hardware unusable]",
 531                          (unsigned long long) hwerrs & _IPATH_PLL_FAIL);
 532                 strlcat(msg, bitsmsg, msgl);
 533                 /* ignore from now on, so disable until driver reloaded */
 534                 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
 535                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 536                                  dd->ipath_hwerrmask);
 537         }
 538
 539         if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
 540                 /*
 541                  * If it occurs, it is left masked since the external
 542                  * interface is unused
 543                  */
 544                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
 545                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 546                                  dd->ipath_hwerrmask);
 547         }
 548
 549         if (*msg)
 550                 ipath_dev_err(dd, "%s hardware error\n", msg);
 551         if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg) {
 552                 /*
 553                  * for /sys status file ; if no trailing } is copied, we'll
 554                  * know it was truncated.
 555                  */
 556                 snprintf(dd->ipath_freezemsg, dd->ipath_freezelen,
 557                          "{%s}", msg);
 558         }
 559 }
 560
 561 /**
 562  * ipath_pe_boardname - fill in the board name
 563  * @dd: the infinipath device
 564  * @name: the output buffer
 565  * @namelen: the size of the output buffer
 566  *
 567  * info is based on the board revision register
 568  */
 569 static int ipath_pe_boardname(struct ipath_devdata *dd, char *name,
 570                               size_t namelen)
 571 {
 572         char *n = NULL;
 573         u8 boardrev = dd->ipath_boardrev;
 574         int ret;
 575
 576         switch (boardrev) {
 577         case 0:
 578                 n = "InfiniPath_Emulation";
 579                 break;
 580         case 1:
 581                 n = "InfiniPath_QLE7140-Bringup";
 582                 break;
 583         case 2:
 584                 n = "InfiniPath_QLE7140";
 585                 break;
 586         case 3:
 587                 n = "InfiniPath_QMI7140";
 588                 break;
 589         case 4:
 590                 n = "InfiniPath_QEM7140";
 591                 break;
 592         case 5:
 593                 n = "InfiniPath_QMH7140";
 594                 break;
 595         case 6:
 596                 n = "InfiniPath_QLE7142";
 597                 break;
 598         default:
 599                 ipath_dev_err(dd,
 600                               "Don't yet know about board with ID %u\n",
 601                               boardrev);
 602                 snprintf(name, namelen, "Unknown_InfiniPath_PCIe_%u",
 603                          boardrev);
 604                 break;
 605         }
 606         if (n)
 607                 snprintf(name, namelen, "%s", n);
 608
 609         if (dd->ipath_majrev != 4 || !dd->ipath_minrev || dd->ipath_minrev>2) {
 610                 ipath_dev_err(dd, "Unsupported InfiniPath hardware revision %u.%u!\n",
 611                               dd->ipath_majrev, dd->ipath_minrev);
 612                 ret = 1;
 613         } else {
 614                 ret = 0;
 615                 if (dd->ipath_minrev >= 2)
 616                         dd->ipath_f_put_tid = ipath_pe_put_tid_2;
 617         }
 618
 619
 620         /*
 621          * set here, not in ipath_init_*_funcs because we have to do
 622          * it after we can read chip registers.
 623          */
 624         dd->ipath_ureg_align =
 625                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign);
 626
 627         return ret;
 628 }
 629
 630 /**
 631  * ipath_pe_init_hwerrors - enable hardware errors
 632  * @dd: the infinipath device
 633  *
 634  * now that we have finished initializing everything that might reasonably
 635  * cause a hardware error, and cleared those errors bits as they occur,
 636  * we can enable hardware errors in the mask (potentially enabling
 637  * freeze mode), and enable hardware errors as errors (along with
 638  * everything else) in errormask
 639  */
 640 static void ipath_pe_init_hwerrors(struct ipath_devdata *dd)
 641 {
 642         ipath_err_t val;
 643         u64 extsval;
 644
 645         extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
 646
 647         if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
 648                 ipath_dev_err(dd, "MemBIST did not complete!\n");
 649         if (extsval & INFINIPATH_EXTS_MEMBIST_FOUND)
 650                 ipath_dbg("MemBIST corrected\n");
 651
 652         val = ~0ULL;    /* barring bugs, all hwerrors become interrupts, */
 653
 654         if (!dd->ipath_boardrev)        // no PLL for Emulator
 655                 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
 656
 657         if (dd->ipath_minrev < 2) {
 658                 /* workaround bug 9460 in internal interface bus parity
 659                  * checking. Fixed (HW bug 9490) in Rev2.
 660                  */
 661                 val &= ~INFINIPATH_HWE_PCIEBUSPARITYRADM;
 662         }
 663         dd->ipath_hwerrmask = val;
 664 }
 665
 666 /**
 667  * ipath_pe_bringup_serdes - bring up the serdes
 668  * @dd: the infinipath device
 669  */
 670 static int ipath_pe_bringup_serdes(struct ipath_devdata *dd)
 671 {
 672         u64 val, config1, prev_val;
 673         int ret = 0;
 674
 675         ipath_dbg("Trying to bringup serdes\n");
 676
 677         if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
 678             INFINIPATH_HWE_SERDESPLLFAILED) {
 679                 ipath_dbg("At start, serdes PLL failed bit set "
 680                           "in hwerrstatus, clearing and continuing\n");
 681                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 682                                  INFINIPATH_HWE_SERDESPLLFAILED);
 683         }
 684
 685         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
 686         config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
 687
 688         ipath_cdbg(VERBOSE, "SerDes status config0=%llx config1=%llx, "
 689                    "xgxsconfig %llx\n", (unsigned long long) val,
 690                    (unsigned long long) config1, (unsigned long long)
 691                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
 692
 693         /*
 694          * Force reset on, also set rxdetect enable.  Must do before reading
 695          * serdesstatus at least for simulation, or some of the bits in
 696          * serdes status will come back as undefined and cause simulation
 697          * failures
 698          */
 699         val |= INFINIPATH_SERDC0_RESET_PLL | INFINIPATH_SERDC0_RXDETECT_EN
 700                 | INFINIPATH_SERDC0_L1PWR_DN;
 701         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
 702         /* be sure chip saw it */
 703         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 704         udelay(5);              /* need pll reset set at least for a bit */
 705         /*
 706          * after PLL is reset, set the per-lane Resets and TxIdle and
 707          * clear the PLL reset and rxdetect (to get falling edge).
 708          * Leave L1PWR bits set (permanently)
 709          */
 710         val &= ~(INFINIPATH_SERDC0_RXDETECT_EN | INFINIPATH_SERDC0_RESET_PLL
 711                  | INFINIPATH_SERDC0_L1PWR_DN);
 712         val |= INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE;
 713         ipath_cdbg(VERBOSE, "Clearing pll reset and setting lane resets "
 714                    "and txidle (%llx)\n", (unsigned long long) val);
 715         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
 716         /* be sure chip saw it */
 717         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 718         /* need PLL reset clear for at least 11 usec before lane
 719          * resets cleared; give it a few more to be sure */
 720         udelay(15);
 721         val &= ~(INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE);
 722
 723         ipath_cdbg(VERBOSE, "Clearing lane resets and txidle "
 724                    "(writing %llx)\n", (unsigned long long) val);
 725         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
 726         /* be sure chip saw it */
 727         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 728
 729         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
 730         prev_val = val;
 731         if (val & INFINIPATH_XGXS_RESET)
 732                 val &= ~INFINIPATH_XGXS_RESET;
 733         if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) &
 734              INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {
 735                 /* need to compensate for Tx inversion in partner */
 736                 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
 737                          INFINIPATH_XGXS_RX_POL_SHIFT);
 738                 val |= dd->ipath_rx_pol_inv <<
 739                         INFINIPATH_XGXS_RX_POL_SHIFT;
 740         }
 741         if (val != prev_val)
 742                 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
 743
 744         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
 745
 746         /* clear current and de-emphasis bits */
 747         config1 &= ~0x0ffffffff00ULL;
 748         /* set current to 20ma */
 749         config1 |= 0x00000000000ULL;
 750         /* set de-emphasis to -5.68dB */
 751         config1 |= 0x0cccc000000ULL;
 752         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
 753
 754         ipath_cdbg(VERBOSE, "done: SerDes status config0=%llx "
 755                    "config1=%llx, sstatus=%llx xgxs=%llx\n",
 756                    (unsigned long long) val, (unsigned long long) config1,
 757                    (unsigned long long)
 758                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
 759                    (unsigned long long)
 760                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
 761
 762         return ret;
 763 }
 764
 765 /**
 766  * ipath_pe_quiet_serdes - set serdes to txidle
 767  * @dd: the infinipath device
 768  * Called when driver is being unloaded
 769  */
 770 static void ipath_pe_quiet_serdes(struct ipath_devdata *dd)
 771 {
 772         u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
 773
 774         val |= INFINIPATH_SERDC0_TXIDLE;
 775         ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
 776                   (unsigned long long) val);
 777         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
 778 }
 779
 780 static int ipath_pe_intconfig(struct ipath_devdata *dd)
 781 {
 782         u32 chiprev;
 783
 784         /*
 785          * If the chip supports added error indication via GPIO pins,
 786          * enable interrupts on those bits so the interrupt routine
 787          * can count the events. Also set flag so interrupt routine
 788          * can know they are expected.
 789          */
 790         chiprev = dd->ipath_revision >> INFINIPATH_R_CHIPREVMINOR_SHIFT;
 791         if ((chiprev & INFINIPATH_R_CHIPREVMINOR_MASK) > 1) {
 792                 /* Rev2+ reports extra errors via internal GPIO pins */
 793                 dd->ipath_flags |= IPATH_GPIO_ERRINTRS;
 794                 dd->ipath_gpio_mask |= IPATH_GPIO_ERRINTR_MASK;
 795                 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_mask,
 796                                  dd->ipath_gpio_mask);
 797         }
 798         return 0;
 799 }
 800
 801 /**
 802  * ipath_setup_pe_setextled - set the state of the two external LEDs
 803  * @dd: the infinipath device
 804  * @lst: the L state
 805  * @ltst: the LT state
 806
 807  * These LEDs indicate the physical and logical state of IB link.
 808  * For this chip (at least with recommended board pinouts), LED1
 809  * is Yellow (logical state) and LED2 is Green (physical state),
 810  *
 811  * Note:  We try to match the Mellanox HCA LED behavior as best
 812  * we can.  Green indicates physical link state is OK (something is
 813  * plugged in, and we can train).
 814  * Amber indicates the link is logically up (ACTIVE).
 815  * Mellanox further blinks the amber LED to indicate data packet
 816  * activity, but we have no hardware support for that, so it would
 817  * require waking up every 10-20 msecs and checking the counters
 818  * on the chip, and then turning the LED off if appropriate.  That's
 819  * visible overhead, so not something we will do.
 820  *
 821  */
 822 static void ipath_setup_pe_setextled(struct ipath_devdata *dd, u64 lst,
 823                                      u64 ltst)
 824 {
 825         u64 extctl;
 826         unsigned long flags = 0;
 827
 828         /* the diags use the LED to indicate diag info, so we leave
 829          * the external LED alone when the diags are running */
 830         if (ipath_diag_inuse)
 831                 return;
 832
 833         /* Allow override of LED display for, e.g. Locating system in rack */
 834         if (dd->ipath_led_override) {
 835                 ltst = (dd->ipath_led_override & IPATH_LED_PHYS)
 836                         ? INFINIPATH_IBCS_LT_STATE_LINKUP
 837                         : INFINIPATH_IBCS_LT_STATE_DISABLED;
 838                 lst = (dd->ipath_led_override & IPATH_LED_LOG)
 839                         ? INFINIPATH_IBCS_L_STATE_ACTIVE
 840                         : INFINIPATH_IBCS_L_STATE_DOWN;
 841         }
 842
 843         spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
 844         extctl = dd->ipath_extctrl & ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
 845                                        INFINIPATH_EXTC_LED2PRIPORT_ON);
 846
 847         if (ltst & INFINIPATH_IBCS_LT_STATE_LINKUP)
 848                 extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
 849         if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
 850                 extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
 851         dd->ipath_extctrl = extctl;
 852         ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
 853         spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
 854 }
 855
 856 /**
 857  * ipath_setup_pe_cleanup - clean up any per-chip chip-specific stuff
 858  * @dd: the infinipath device
 859  *
 860  * This is called during driver unload.
 861  * We do the pci_disable_msi here, not in generic code, because it
 862  * isn't used for the HT chips. If we do end up needing pci_enable_msi
 863  * at some point in the future for HT, we'll move the call back
 864  * into the main init_one code.
 865  */
 866 static void ipath_setup_pe_cleanup(struct ipath_devdata *dd)
 867 {
 868         dd->ipath_msi_lo = 0;   /* just in case unload fails */
 869         pci_disable_msi(dd->pcidev);
 870 }
 871
 872 /**
 873  * ipath_setup_pe_config - setup PCIe config related stuff
 874  * @dd: the infinipath device
 875  * @pdev: the PCI device
 876  *
 877  * The pci_enable_msi() call will fail on systems with MSI quirks
 878  * such as those with AMD8131, even if the device of interest is not
 879  * attached to that device, (in the 2.6.13 - 2.6.15 kernels, at least, fixed
 880  * late in 2.6.16).
 881  * All that can be done is to edit the kernel source to remove the quirk
 882  * check until that is fixed.
 883  * We do not need to call enable_msi() for our HyperTransport chip,
 884  * even though it uses MSI, and we want to avoid the quirk warning, so
 885  * So we call enable_msi only for PCIe.  If we do end up needing
 886  * pci_enable_msi at some point in the future for HT, we'll move the
 887  * call back into the main init_one code.
 888  * We save the msi lo and hi values, so we can restore them after
 889  * chip reset (the kernel PCI infrastructure doesn't yet handle that
 890  * correctly).
 891  */
 892 static int ipath_setup_pe_config(struct ipath_devdata *dd,
 893                                  struct pci_dev *pdev)
 894 {
 895         int pos, ret;
 896
 897         dd->ipath_msi_lo = 0;   /* used as a flag during reset processing */
 898         ret = pci_enable_msi(dd->pcidev);
 899         if (ret)
 900                 ipath_dev_err(dd, "pci_enable_msi failed: %d, "
 901                               "interrupts may not work\n", ret);
 902         /* continue even if it fails, we may still be OK... */
 903         dd->ipath_irq = pdev->irq;
 904
 905         if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
 906                 u16 control;
 907                 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
 908                                       &dd->ipath_msi_lo);
 909                 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
 910                                       &dd->ipath_msi_hi);
 911                 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
 912                                      &control);
 913                 /* now save the data (vector) info */
 914                 pci_read_config_word(dd->pcidev,
 915                                      pos + ((control & PCI_MSI_FLAGS_64BIT)
 916                                             ? 12 : 8),
 917                                      &dd->ipath_msi_data);
 918                 ipath_cdbg(VERBOSE, "Read msi data 0x%x from config offset "
 919                            "0x%x, control=0x%x\n", dd->ipath_msi_data,
 920                            pos + ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
 921                            control);
 922                 /* we save the cachelinesize also, although it doesn't
 923                  * really matter */
 924                 pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
 925                                      &dd->ipath_pci_cacheline);
 926         } else
 927                 ipath_dev_err(dd, "Can't find MSI capability, "
 928                               "can't save MSI settings for reset\n");
 929         if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_EXP))) {
 930                 u16 linkstat;
 931                 pci_read_config_word(dd->pcidev, pos + PCI_EXP_LNKSTA,
 932                                      &linkstat);
 933                 linkstat >>= 4;
 934                 linkstat &= 0x1f;
 935                 if (linkstat != 8)
 936                         ipath_dev_err(dd, "PCIe width %u, "
 937                                       "performance reduced\n", linkstat);
 938         }
 939         else
 940                 ipath_dev_err(dd, "Can't find PCI Express "
 941                               "capability!\n");
 942
 943         dd->ipath_link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
 944         dd->ipath_link_speed_supported = IPATH_IB_SDR;
 945         dd->ipath_link_width_enabled = IB_WIDTH_4X;
 946         dd->ipath_link_speed_enabled = dd->ipath_link_speed_supported;
 947         /* these can't change for this chip, so set once */
 948         dd->ipath_link_width_active = dd->ipath_link_width_enabled;
 949         dd->ipath_link_speed_active = dd->ipath_link_speed_enabled;
 950         return 0;
 951 }
 952
 953 static void ipath_init_pe_variables(struct ipath_devdata *dd)
 954 {
 955         /*
 956          * setup the register offsets, since they are different for each
 957          * chip
 958          */
 959         dd->ipath_kregs = &ipath_pe_kregs;
 960         dd->ipath_cregs = &ipath_pe_cregs;
 961
 962         /*
 963          * bits for selecting i2c direction and values,
 964          * used for I2C serial flash
 965          */
 966         dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
 967         dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
 968         dd->ipath_gpio_sda = IPATH_GPIO_SDA;
 969         dd->ipath_gpio_scl = IPATH_GPIO_SCL;
 970
 971         /*
 972          * Fill in data for field-values that change in newer chips.
 973          * We dynamically specify only the mask for LINKTRAININGSTATE
 974          * and only the shift for LINKSTATE, as they are the only ones
 975          * that change.  Also precalculate the 3 link states of interest
 976          * and the combined mask.
 977          */
 978         dd->ibcs_ls_shift = IBA6120_IBCS_LINKSTATE_SHIFT;
 979         dd->ibcs_lts_mask = IBA6120_IBCS_LINKTRAININGSTATE_MASK;
 980         dd->ibcs_mask = (INFINIPATH_IBCS_LINKSTATE_MASK <<
 981                 dd->ibcs_ls_shift) | dd->ibcs_lts_mask;
 982         dd->ib_init = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
 983                 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
 984                 (INFINIPATH_IBCS_L_STATE_INIT << dd->ibcs_ls_shift);
 985         dd->ib_arm = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
 986                 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
 987                 (INFINIPATH_IBCS_L_STATE_ARM << dd->ibcs_ls_shift);
 988         dd->ib_active = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
 989                 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
 990                 (INFINIPATH_IBCS_L_STATE_ACTIVE << dd->ibcs_ls_shift);
 991
 992         /*
 993          * Fill in data for ibcc field-values that change in newer chips.
 994          * We dynamically specify only the mask for LINKINITCMD
 995          * and only the shift for LINKCMD and MAXPKTLEN, as they are
 996          * the only ones that change.
 997          */
 998         dd->ibcc_lic_mask = INFINIPATH_IBCC_LINKINITCMD_MASK;
 999         dd->ibcc_lc_shift = INFINIPATH_IBCC_LINKCMD_SHIFT;
1000         dd->ibcc_mpl_shift = INFINIPATH_IBCC_MAXPKTLEN_SHIFT;
1001
1002         /* Fill in shifts for RcvCtrl. */
1003         dd->ipath_r_portenable_shift = INFINIPATH_R_PORTENABLE_SHIFT;
1004         dd->ipath_r_intravail_shift = INFINIPATH_R_INTRAVAIL_SHIFT;
1005         dd->ipath_r_tailupd_shift = INFINIPATH_R_TAILUPD_SHIFT;
1006         dd->ipath_r_portcfg_shift = 0; /* Not on IBA6120 */
1007
1008         /* variables for sanity checking interrupt and errors */
1009         dd->ipath_hwe_bitsextant =
1010                 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1011                  INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
1012                 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1013                  INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
1014                 (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK <<
1015                  INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) |
1016                 INFINIPATH_HWE_PCIE1PLLFAILED |
1017                 INFINIPATH_HWE_PCIE0PLLFAILED |
1018                 INFINIPATH_HWE_PCIEPOISONEDTLP |
1019                 INFINIPATH_HWE_PCIECPLTIMEOUT |
1020                 INFINIPATH_HWE_PCIEBUSPARITYXTLH |
1021                 INFINIPATH_HWE_PCIEBUSPARITYXADM |
1022                 INFINIPATH_HWE_PCIEBUSPARITYRADM |
1023                 INFINIPATH_HWE_MEMBISTFAILED |
1024                 INFINIPATH_HWE_COREPLL_FBSLIP |
1025                 INFINIPATH_HWE_COREPLL_RFSLIP |
1026                 INFINIPATH_HWE_SERDESPLLFAILED |
1027                 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
1028                 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
1029         dd->ipath_i_bitsextant =
1030                 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
1031                 (INFINIPATH_I_RCVAVAIL_MASK <<
1032                  INFINIPATH_I_RCVAVAIL_SHIFT) |
1033                 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
1034                 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
1035         dd->ipath_e_bitsextant =
1036                 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
1037                 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
1038                 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
1039                 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
1040                 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
1041                 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
1042                 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
1043                 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
1044                 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
1045                 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
1046                 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
1047                 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
1048                 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
1049                 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
1050                 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
1051                 INFINIPATH_E_HARDWARE;
1052
1053         dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
1054         dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
1055         dd->ipath_i_rcvavail_shift = INFINIPATH_I_RCVAVAIL_SHIFT;
1056         dd->ipath_i_rcvurg_shift = INFINIPATH_I_RCVURG_SHIFT;
1057
1058         /*
1059          * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
1060          * 2 is Some Misc, 3 is reserved for future.
1061          */
1062         dd->ipath_eep_st_masks[0].hwerrs_to_log =
1063                 INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1064                 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT;
1065
1066         /* Ignore errors in PIO/PBC on systems with unordered write-combining */
1067         if (ipath_unordered_wc())
1068                 dd->ipath_eep_st_masks[0].hwerrs_to_log &= ~TXE_PIO_PARITY;
1069
1070         dd->ipath_eep_st_masks[1].hwerrs_to_log =
1071                 INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1072                 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT;
1073
1074         dd->ipath_eep_st_masks[2].errs_to_log =
1075                 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET;
1076
1077
1078         dd->delay_mult = 2; /* SDR, 4X, can't change */
1079 }
1080
1081 /* setup the MSI stuff again after a reset.  I'd like to just call
1082  * pci_enable_msi() and request_irq() again, but when I do that,
1083  * the MSI enable bit doesn't get set in the command word, and
1084  * we switch to to a different interrupt vector, which is confusing,
1085  * so I instead just do it all inline.  Perhaps somehow can tie this
1086  * into the PCIe hotplug support at some point
1087  * Note, because I'm doing it all here, I don't call pci_disable_msi()
1088  * or free_irq() at the start of ipath_setup_pe_reset().
1089  */
1090 static int ipath_reinit_msi(struct ipath_devdata *dd)
1091 {
1092         int pos;
1093         u16 control;
1094         int ret;
1095
1096         if (!dd->ipath_msi_lo) {
1097                 dev_info(&dd->pcidev->dev, "Can't restore MSI config, "
1098                          "initial setup failed?\n");
1099                 ret = 0;
1100                 goto bail;
1101         }
1102
1103         if (!(pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
1104                 ipath_dev_err(dd, "Can't find MSI capability, "
1105                               "can't restore MSI settings\n");
1106                 ret = 0;
1107                 goto bail;
1108         }
1109         ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1110                    dd->ipath_msi_lo, pos + PCI_MSI_ADDRESS_LO);
1111         pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
1112                                dd->ipath_msi_lo);
1113         ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1114                    dd->ipath_msi_hi, pos + PCI_MSI_ADDRESS_HI);
1115         pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
1116                                dd->ipath_msi_hi);
1117         pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);
1118         if (!(control & PCI_MSI_FLAGS_ENABLE)) {
1119                 ipath_cdbg(VERBOSE, "MSI control at off %x was %x, "
1120                            "setting MSI enable (%x)\n", pos + PCI_MSI_FLAGS,
1121                            control, control | PCI_MSI_FLAGS_ENABLE);
1122                 control |= PCI_MSI_FLAGS_ENABLE;
1123                 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
1124                                       control);
1125         }
1126         /* now rewrite the data (vector) info */
1127         pci_write_config_word(dd->pcidev, pos +
1128                               ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
1129                               dd->ipath_msi_data);
1130         /* we restore the cachelinesize also, although it doesn't really
1131          * matter */
1132         pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
1133                               dd->ipath_pci_cacheline);
1134         /* and now set the pci master bit again */
1135         pci_set_master(dd->pcidev);
1136         ret = 1;
1137
1138 bail:
1139         return ret;
1140 }
1141
1142 /* This routine sleeps, so it can only be called from user context, not
1143  * from interrupt context.  If we need interrupt context, we can split
1144  * it into two routines.
1145 */
1146 static int ipath_setup_pe_reset(struct ipath_devdata *dd)
1147 {
1148         u64 val;
1149         int i;
1150         int ret;
1151
1152         /* Use ERROR so it shows up in logs, etc. */
1153         ipath_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->ipath_unit);
1154         /* keep chip from being accessed in a few places */
1155         dd->ipath_flags &= ~(IPATH_INITTED|IPATH_PRESENT);
1156         val = dd->ipath_control | INFINIPATH_C_RESET;
1157         ipath_write_kreg(dd, dd->ipath_kregs->kr_control, val);
1158         mb();
1159
1160         for (i = 1; i <= 5; i++) {
1161                 int r;
1162                 /* allow MBIST, etc. to complete; longer on each retry.
1163                  * We sometimes get machine checks from bus timeout if no
1164                  * response, so for now, make it *really* long.
1165                  */
1166                 msleep(1000 + (1 + i) * 2000);
1167                 if ((r =
1168                      pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
1169                                             dd->ipath_pcibar0)))
1170                         ipath_dev_err(dd, "rewrite of BAR0 failed: %d\n",
1171                                       r);
1172                 if ((r =
1173                      pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
1174                                             dd->ipath_pcibar1)))
1175                         ipath_dev_err(dd, "rewrite of BAR1 failed: %d\n",
1176                                       r);
1177                 /* now re-enable memory access */
1178                 if ((r = pci_enable_device(dd->pcidev)))
1179                         ipath_dev_err(dd, "pci_enable_device failed after "
1180                                       "reset: %d\n", r);
1181                 /* whether it worked or not, mark as present, again */
1182                 dd->ipath_flags |= IPATH_PRESENT;
1183                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
1184                 if (val == dd->ipath_revision) {
1185                         ipath_cdbg(VERBOSE, "Got matching revision "
1186                                    "register %llx on try %d\n",
1187                                    (unsigned long long) val, i);
1188                         ret = ipath_reinit_msi(dd);
1189                         goto bail;
1190                 }
1191                 /* Probably getting -1 back */
1192                 ipath_dbg("Didn't get expected revision register, "
1193                           "got %llx, try %d\n", (unsigned long long) val,
1194                           i + 1);
1195         }
1196         ret = 0; /* failed */
1197
1198 bail:
1199         return ret;
1200 }
1201
1202 /**
1203  * ipath_pe_put_tid - write a TID in chip
1204  * @dd: the infinipath device
1205  * @tidptr: pointer to the expected TID (in chip) to udpate
1206  * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected
1207  * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1208  *
1209  * This exists as a separate routine to allow for special locking etc.
1210  * It's used for both the full cleanup on exit, as well as the normal
1211  * setup and teardown.
1212  */
1213 static void ipath_pe_put_tid(struct ipath_devdata *dd, u64 __iomem *tidptr,
1214                              u32 type, unsigned long pa)
1215 {
1216         u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1217         unsigned long flags = 0; /* keep gcc quiet */
1218
1219         if (pa != dd->ipath_tidinvalid) {
1220                 if (pa & ((1U << 11) - 1)) {
1221                         dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1222                                  "not 4KB aligned!\n", pa);
1223                         return;
1224                 }
1225                 pa >>= 11;
1226                 /* paranoia check */
1227                 if (pa & (7<<29))
1228                         ipath_dev_err(dd,
1229                                       "BUG: Physical page address 0x%lx "
1230                                       "has bits set in 31-29\n", pa);
1231
1232                 if (type == RCVHQ_RCV_TYPE_EAGER)
1233                         pa |= dd->ipath_tidtemplate;
1234                 else /* for now, always full 4KB page */
1235                         pa |= 2 << 29;
1236         }
1237
1238         /*
1239          * Workaround chip bug 9437 by writing the scratch register
1240          * before and after the TID, and with an io write barrier.
1241          * We use a spinlock around the writes, so they can't intermix
1242          * with other TID (eager or expected) writes (the chip bug
1243          * is triggered by back to back TID writes). Unfortunately, this
1244          * call can be done from interrupt level for the port 0 eager TIDs,
1245          * so we have to use irqsave locks.
1246          */
1247         spin_lock_irqsave(&dd->ipath_tid_lock, flags);
1248         ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xfeeddeaf);
1249         if (dd->ipath_kregbase)
1250                 writel(pa, tidp32);
1251         ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xdeadbeef);
1252         mmiowb();
1253         spin_unlock_irqrestore(&dd->ipath_tid_lock, flags);
1254 }
1255 /**
1256  * ipath_pe_put_tid_2 - write a TID in chip, Revision 2 or higher
1257  * @dd: the infinipath device
1258  * @tidptr: pointer to the expected TID (in chip) to udpate
1259  * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected
1260  * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1261  *
1262  * This exists as a separate routine to allow for selection of the
1263  * appropriate "flavor". The static calls in cleanup just use the
1264  * revision-agnostic form, as they are not performance critical.
1265  */
1266 static void ipath_pe_put_tid_2(struct ipath_devdata *dd, u64 __iomem *tidptr,
1267                              u32 type, unsigned long pa)
1268 {
1269         u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1270
1271         if (pa != dd->ipath_tidinvalid) {
1272                 if (pa & ((1U << 11) - 1)) {
1273                         dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1274                                  "not 2KB aligned!\n", pa);
1275                         return;
1276                 }
1277                 pa >>= 11;
1278                 /* paranoia check */
1279                 if (pa & (7<<29))
1280                         ipath_dev_err(dd,
1281                                       "BUG: Physical page address 0x%lx "
1282                                       "has bits set in 31-29\n", pa);
1283
1284                 if (type == RCVHQ_RCV_TYPE_EAGER)
1285                         pa |= dd->ipath_tidtemplate;
1286                 else /* for now, always full 4KB page */
1287                         pa |= 2 << 29;
1288         }
1289         if (dd->ipath_kregbase)
1290                 writel(pa, tidp32);
1291         mmiowb();
1292 }
1293
1294
1295 /**
1296  * ipath_pe_clear_tid - clear all TID entries for a port, expected and eager
1297  * @dd: the infinipath device
1298  * @port: the port
1299  *
1300  * clear all TID entries for a port, expected and eager.
1301  * Used from ipath_close().  On this chip, TIDs are only 32 bits,
1302  * not 64, but they are still on 64 bit boundaries, so tidbase
1303  * is declared as u64 * for the pointer math, even though we write 32 bits
1304  */
1305 static void ipath_pe_clear_tids(struct ipath_devdata *dd, unsigned port)
1306 {
1307         u64 __iomem *tidbase;
1308         unsigned long tidinv;
1309         int i;
1310
1311         if (!dd->ipath_kregbase)
1312                 return;
1313
1314         ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1315
1316         tidinv = dd->ipath_tidinvalid;
1317         tidbase = (u64 __iomem *)
1318                 ((char __iomem *)(dd->ipath_kregbase) +
1319                  dd->ipath_rcvtidbase +
1320                  port * dd->ipath_rcvtidcnt * sizeof(*tidbase));
1321
1322         for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1323                 dd->ipath_f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
1324                                  tidinv);
1325
1326         tidbase = (u64 __iomem *)
1327                 ((char __iomem *)(dd->ipath_kregbase) +
1328                  dd->ipath_rcvegrbase +
1329                  port * dd->ipath_rcvegrcnt * sizeof(*tidbase));
1330
1331         for (i = 0; i < dd->ipath_rcvegrcnt; i++)
1332                 dd->ipath_f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
1333                                  tidinv);
1334 }
1335
1336 /**
1337  * ipath_pe_tidtemplate - setup constants for TID updates
1338  * @dd: the infinipath device
1339  *
1340  * We setup stuff that we use a lot, to avoid calculating each time
1341  */
1342 static void ipath_pe_tidtemplate(struct ipath_devdata *dd)
1343 {
1344         u32 egrsize = dd->ipath_rcvegrbufsize;
1345
1346         /* For now, we always allocate 4KB buffers (at init) so we can
1347          * receive max size packets.  We may want a module parameter to
1348          * specify 2KB or 4KB and/or make be per port instead of per device
1349          * for those who want to reduce memory footprint.  Note that the
1350          * ipath_rcvhdrentsize size must be large enough to hold the largest
1351          * IB header (currently 96 bytes) that we expect to handle (plus of
1352          * course the 2 dwords of RHF).
1353          */
1354         if (egrsize == 2048)
1355                 dd->ipath_tidtemplate = 1U << 29;
1356         else if (egrsize == 4096)
1357                 dd->ipath_tidtemplate = 2U << 29;
1358         else {
1359                 egrsize = 4096;
1360                 dev_info(&dd->pcidev->dev, "BUG: unsupported egrbufsize "
1361                          "%u, using %u\n", dd->ipath_rcvegrbufsize,
1362                          egrsize);
1363                 dd->ipath_tidtemplate = 2U << 29;
1364         }
1365         dd->ipath_tidinvalid = 0;
1366 }
1367
1368 static int ipath_pe_early_init(struct ipath_devdata *dd)
1369 {
1370         dd->ipath_flags |= IPATH_4BYTE_TID;
1371         if (ipath_unordered_wc())
1372                 dd->ipath_flags |= IPATH_PIO_FLUSH_WC;
1373
1374         /*
1375          * For openfabrics, we need to be able to handle an IB header of
1376          * 24 dwords.  HT chip has arbitrary sized receive buffers, so we
1377          * made them the same size as the PIO buffers.  This chip does not
1378          * handle arbitrary size buffers, so we need the header large enough
1379          * to handle largest IB header, but still have room for a 2KB MTU
1380          * standard IB packet.
1381          */
1382         dd->ipath_rcvhdrentsize = 24;
1383         dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1384         dd->ipath_rhf_offset = 0;
1385         dd->ipath_egrtidbase = (u64 __iomem *)
1386                 ((char __iomem *) dd->ipath_kregbase + dd->ipath_rcvegrbase);
1387
1388         /*
1389          * To truly support a 4KB MTU (for usermode), we need to
1390          * bump this to a larger value.  For now, we use them for
1391          * the kernel only.
1392          */
1393         dd->ipath_rcvegrbufsize = 2048;
1394         /*
1395          * the min() check here is currently a nop, but it may not always
1396          * be, depending on just how we do ipath_rcvegrbufsize
1397          */
1398         dd->ipath_ibmaxlen = min(dd->ipath_piosize2k,
1399                                  dd->ipath_rcvegrbufsize +
1400                                  (dd->ipath_rcvhdrentsize << 2));
1401         dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1402
1403         /*
1404          * We can request a receive interrupt for 1 or
1405          * more packets from current offset.  For now, we set this
1406          * up for a single packet.
1407          */
1408         dd->ipath_rhdrhead_intr_off = 1ULL<<32;
1409
1410         ipath_get_eeprom_info(dd);
1411
1412         return 0;
1413 }
1414
1415 int __attribute__((weak)) ipath_unordered_wc(void)
1416 {
1417         return 0;
1418 }
1419
1420 /**
1421  * ipath_init_pe_get_base_info - set chip-specific flags for user code
1422  * @pd: the infinipath port
1423  * @kbase: ipath_base_info pointer
1424  *
1425  * We set the PCIE flag because the lower bandwidth on PCIe vs
1426  * HyperTransport can affect some user packet algorithms.
1427  */
1428 static int ipath_pe_get_base_info(struct ipath_portdata *pd, void *kbase)
1429 {
1430         struct ipath_base_info *kinfo = kbase;
1431         struct ipath_devdata *dd;
1432
1433         if (ipath_unordered_wc()) {
1434                 kinfo->spi_runtime_flags |= IPATH_RUNTIME_FORCE_WC_ORDER;
1435                 ipath_cdbg(PROC, "Intel processor, forcing WC order\n");
1436         }
1437         else
1438                 ipath_cdbg(PROC, "Not Intel processor, WC ordered\n");
1439
1440         if (pd == NULL)
1441                 goto done;
1442
1443         dd = pd->port_dd;
1444
1445 done:
1446         kinfo->spi_runtime_flags |= IPATH_RUNTIME_PCIE |
1447                 IPATH_RUNTIME_FORCE_PIOAVAIL | IPATH_RUNTIME_PIO_REGSWAPPED;
1448         return 0;
1449 }
1450
1451 static void ipath_pe_free_irq(struct ipath_devdata *dd)
1452 {
1453         free_irq(dd->ipath_irq, dd);
1454         dd->ipath_irq = 0;
1455 }
1456
1457
1458 static struct ipath_message_header *
1459 ipath_pe_get_msgheader(struct ipath_devdata *dd, __le32 *rhf_addr)
1460 {
1461         return (struct ipath_message_header *)
1462                 &rhf_addr[sizeof(u64) / sizeof(u32)];
1463 }
1464
1465 static void ipath_pe_config_ports(struct ipath_devdata *dd, ushort cfgports)
1466 {
1467         dd->ipath_portcnt =
1468                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt);
1469         dd->ipath_p0_rcvegrcnt =
1470                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
1471 }
1472
1473 static void ipath_pe_read_counters(struct ipath_devdata *dd,
1474                                    struct infinipath_counters *cntrs)
1475 {
1476         cntrs->LBIntCnt =
1477                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(LBIntCnt));
1478         cntrs->LBFlowStallCnt =
1479                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(LBFlowStallCnt));
1480         cntrs->TxSDmaDescCnt = 0;
1481         cntrs->TxUnsupVLErrCnt =
1482                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxUnsupVLErrCnt));
1483         cntrs->TxDataPktCnt =
1484                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDataPktCnt));
1485         cntrs->TxFlowPktCnt =
1486                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxFlowPktCnt));
1487         cntrs->TxDwordCnt =
1488                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDwordCnt));
1489         cntrs->TxLenErrCnt =
1490                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxLenErrCnt));
1491         cntrs->TxMaxMinLenErrCnt =
1492                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxMaxMinLenErrCnt));
1493         cntrs->TxUnderrunCnt =
1494                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxUnderrunCnt));
1495         cntrs->TxFlowStallCnt =
1496                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxFlowStallCnt));
1497         cntrs->TxDroppedPktCnt =
1498                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDroppedPktCnt));
1499         cntrs->RxDroppedPktCnt =
1500                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDroppedPktCnt));
1501         cntrs->RxDataPktCnt =
1502                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDataPktCnt));
1503         cntrs->RxFlowPktCnt =
1504                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxFlowPktCnt));
1505         cntrs->RxDwordCnt =
1506                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDwordCnt));
1507         cntrs->RxLenErrCnt =
1508                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLenErrCnt));
1509         cntrs->RxMaxMinLenErrCnt =
1510                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxMaxMinLenErrCnt));
1511         cntrs->RxICRCErrCnt =
1512                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxICRCErrCnt));
1513         cntrs->RxVCRCErrCnt =
1514                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxVCRCErrCnt));
1515         cntrs->RxFlowCtrlErrCnt =
1516                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxFlowCtrlErrCnt));
1517         cntrs->RxBadFormatCnt =
1518                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxBadFormatCnt));
1519         cntrs->RxLinkProblemCnt =
1520                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLinkProblemCnt));
1521         cntrs->RxEBPCnt =
1522                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxEBPCnt));
1523         cntrs->RxLPCRCErrCnt =
1524                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLPCRCErrCnt));
1525         cntrs->RxBufOvflCnt =
1526                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxBufOvflCnt));
1527         cntrs->RxTIDFullErrCnt =
1528                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxTIDFullErrCnt));
1529         cntrs->RxTIDValidErrCnt =
1530                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxTIDValidErrCnt));
1531         cntrs->RxPKeyMismatchCnt =
1532                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxPKeyMismatchCnt));
1533         cntrs->RxP0HdrEgrOvflCnt =
1534                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt));
1535         cntrs->RxP1HdrEgrOvflCnt =
1536                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP1HdrEgrOvflCnt));
1537         cntrs->RxP2HdrEgrOvflCnt =
1538                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP2HdrEgrOvflCnt));
1539         cntrs->RxP3HdrEgrOvflCnt =
1540                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP3HdrEgrOvflCnt));
1541         cntrs->RxP4HdrEgrOvflCnt =
1542                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP4HdrEgrOvflCnt));
1543         cntrs->RxP5HdrEgrOvflCnt = 0;
1544         cntrs->RxP6HdrEgrOvflCnt = 0;
1545         cntrs->RxP7HdrEgrOvflCnt = 0;
1546         cntrs->RxP8HdrEgrOvflCnt = 0;
1547         cntrs->RxP9HdrEgrOvflCnt = 0;
1548         cntrs->RxP10HdrEgrOvflCnt = 0;
1549         cntrs->RxP11HdrEgrOvflCnt = 0;
1550         cntrs->RxP12HdrEgrOvflCnt = 0;
1551         cntrs->RxP13HdrEgrOvflCnt = 0;
1552         cntrs->RxP14HdrEgrOvflCnt = 0;
1553         cntrs->RxP15HdrEgrOvflCnt = 0;
1554         cntrs->RxP16HdrEgrOvflCnt = 0;
1555         cntrs->IBStatusChangeCnt =
1556                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBStatusChangeCnt));
1557         cntrs->IBLinkErrRecoveryCnt =
1558                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt));
1559         cntrs->IBLinkDownedCnt =
1560                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBLinkDownedCnt));
1561         cntrs->IBSymbolErrCnt =
1562                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBSymbolErrCnt));
1563         cntrs->RxVL15DroppedPktCnt = 0;
1564         cntrs->RxOtherLocalPhyErrCnt = 0;
1565         cntrs->PcieRetryBufDiagQwordCnt = 0;
1566         cntrs->ExcessBufferOvflCnt = dd->ipath_overrun_thresh_errs;
1567         cntrs->LocalLinkIntegrityErrCnt = dd->ipath_lli_errs;
1568         cntrs->RxVlErrCnt = 0;
1569         cntrs->RxDlidFltrCnt = 0;
1570 }
1571
1572 /*
1573  * On platforms using this chip, and not having ordered WC stores, we
1574  * can get TXE parity errors due to speculative reads to the PIO buffers,
1575  * and this, due to a chip bug can result in (many) false parity error
1576  * reports.  So it's a debug print on those, and an info print on systems
1577  * where the speculative reads don't occur.
1578  * Because we can get lots of false errors, we have no upper limit
1579  * on recovery attempts on those platforms.
1580  */
1581 static int ipath_pe_txe_recover(struct ipath_devdata *dd)
1582 {
1583         if (ipath_unordered_wc())
1584                 ipath_dbg("Recovering from TXE PIO parity error\n");
1585         else {
1586                 int cnt = ++ipath_stats.sps_txeparity;
1587                 if (cnt >= IPATH_MAX_PARITY_ATTEMPTS)  {
1588                         if (cnt == IPATH_MAX_PARITY_ATTEMPTS)
1589                                 ipath_dev_err(dd,
1590                                         "Too many attempts to recover from "
1591                                         "TXE parity, giving up\n");
1592                         return 0;
1593                 }
1594                 dev_info(&dd->pcidev->dev,
1595                         "Recovering from TXE PIO parity error\n");
1596         }
1597         return 1;
1598 }
1599
1600 /* no interrupt fallback for these chips */
1601 static int ipath_pe_nointr_fallback(struct ipath_devdata *dd)
1602 {
1603         return 0;
1604 }
1605
1606
1607 /*
1608  * reset the XGXS (between serdes and IBC).  Slightly less intrusive
1609  * than resetting the IBC or external link state, and useful in some
1610  * cases to cause some retraining.  To do this right, we reset IBC
1611  * as well.
1612  */
1613 static void ipath_pe_xgxs_reset(struct ipath_devdata *dd)
1614 {
1615         u64 val, prev_val;
1616
1617         prev_val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
1618         val = prev_val | INFINIPATH_XGXS_RESET;
1619         prev_val &= ~INFINIPATH_XGXS_RESET; /* be sure */
1620         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
1621                          dd->ipath_control & ~INFINIPATH_C_LINKENABLE);
1622         ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1623         ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1624         ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, prev_val);
1625         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
1626                          dd->ipath_control);
1627 }
1628
1629
1630 static int ipath_pe_get_ib_cfg(struct ipath_devdata *dd, int which)
1631 {
1632         int ret;
1633
1634         switch (which) {
1635         case IPATH_IB_CFG_LWID:
1636                 ret = dd->ipath_link_width_active;
1637                 break;
1638         case IPATH_IB_CFG_SPD:
1639                 ret = dd->ipath_link_speed_active;
1640                 break;
1641         case IPATH_IB_CFG_LWID_ENB:
1642                 ret = dd->ipath_link_width_enabled;
1643                 break;
1644         case IPATH_IB_CFG_SPD_ENB:
1645                 ret = dd->ipath_link_speed_enabled;
1646                 break;
1647         default:
1648                 ret =  -ENOTSUPP;
1649                 break;
1650         }
1651         return ret;
1652 }
1653
1654
1655 /* we assume range checking is already done, if needed */
1656 static int ipath_pe_set_ib_cfg(struct ipath_devdata *dd, int which, u32 val)
1657 {
1658         int ret = 0;
1659
1660         if (which == IPATH_IB_CFG_LWID_ENB)
1661                 dd->ipath_link_width_enabled = val;
1662         else if (which == IPATH_IB_CFG_SPD_ENB)
1663                 dd->ipath_link_speed_enabled = val;
1664         else
1665                 ret = -ENOTSUPP;
1666         return ret;
1667 }
1668
1669 static void ipath_pe_config_jint(struct ipath_devdata *dd, u16 a, u16 b)
1670 {
1671 }
1672
1673
1674 static int ipath_pe_ib_updown(struct ipath_devdata *dd, int ibup, u64 ibcs)
1675 {
1676         ipath_setup_pe_setextled(dd, ipath_ib_linkstate(dd, ibcs),
1677                 ipath_ib_linktrstate(dd, ibcs));
1678         return 0;
1679 }
1680
1681
1682 /**
1683  * ipath_init_iba6120_funcs - set up the chip-specific function pointers
1684  * @dd: the infinipath device
1685  *
1686  * This is global, and is called directly at init to set up the
1687  * chip-specific function pointers for later use.
1688  */
1689 void ipath_init_iba6120_funcs(struct ipath_devdata *dd)
1690 {
1691         dd->ipath_f_intrsetup = ipath_pe_intconfig;
1692         dd->ipath_f_bus = ipath_setup_pe_config;
1693         dd->ipath_f_reset = ipath_setup_pe_reset;
1694         dd->ipath_f_get_boardname = ipath_pe_boardname;
1695         dd->ipath_f_init_hwerrors = ipath_pe_init_hwerrors;
1696         dd->ipath_f_early_init = ipath_pe_early_init;
1697         dd->ipath_f_handle_hwerrors = ipath_pe_handle_hwerrors;
1698         dd->ipath_f_quiet_serdes = ipath_pe_quiet_serdes;
1699         dd->ipath_f_bringup_serdes = ipath_pe_bringup_serdes;
1700         dd->ipath_f_clear_tids = ipath_pe_clear_tids;
1701         /*
1702          * _f_put_tid may get changed after we read the chip revision,
1703          * but we start with the safe version for all revs
1704          */
1705         dd->ipath_f_put_tid = ipath_pe_put_tid;
1706         dd->ipath_f_cleanup = ipath_setup_pe_cleanup;
1707         dd->ipath_f_setextled = ipath_setup_pe_setextled;
1708         dd->ipath_f_get_base_info = ipath_pe_get_base_info;
1709         dd->ipath_f_free_irq = ipath_pe_free_irq;
1710         dd->ipath_f_tidtemplate = ipath_pe_tidtemplate;
1711         dd->ipath_f_intr_fallback = ipath_pe_nointr_fallback;
1712         dd->ipath_f_xgxs_reset = ipath_pe_xgxs_reset;
1713         dd->ipath_f_get_msgheader = ipath_pe_get_msgheader;
1714         dd->ipath_f_config_ports = ipath_pe_config_ports;
1715         dd->ipath_f_read_counters = ipath_pe_read_counters;
1716         dd->ipath_f_get_ib_cfg = ipath_pe_get_ib_cfg;
1717         dd->ipath_f_set_ib_cfg = ipath_pe_set_ib_cfg;
1718         dd->ipath_f_config_jint = ipath_pe_config_jint;
1719         dd->ipath_f_ib_updown = ipath_pe_ib_updown;
1720
1721
1722         /* initialize chip-specific variables */
1723         ipath_init_pe_variables(dd);
1724 }
1725