9 select PPC_OF_PLATFORM_PCI
10 select PPC_INDIRECT_IO
13 select IBM_NEW_EMAC_EMAC4
14 select IBM_NEW_EMAC_RGMII
15 select IBM_NEW_EMAC_ZMII #test only
16 select IBM_NEW_EMAC_TAH #test only
19 config PPC_IBM_CELL_BLADE
21 depends on PPC_MULTIPLATFORM && PPC64
22 select PPC_CELL_NATIVE
26 select UDBG_RTAS_CONSOLE
29 bool "Toshiba's Cell Reference Set 'Celleb' Architecture"
30 depends on PPC_MULTIPLATFORM && PPC64
32 select PPC_CELL_NATIVE
34 select PPC_INDIRECT_IO
35 select PPC_OF_PLATFORM_PCI
36 select HAS_TXX9_SERIAL
38 select USB_OHCI_BIG_ENDIAN_MMIO
39 select USB_EHCI_BIG_ENDIAN_MMIO
41 menu "Cell Broadband Engine options"
45 tristate "SPU file system"
51 The SPU file system is used to access Synergistic Processing
52 Units on machines implementing the Broadband Processor
56 bool "Use 64K pages to map SPE local store"
57 # we depend on PPC_MM_SLICES for now rather than selecting
58 # it because we depend on hugetlbfs hooks being present. We
59 # will fix that when the generic code has been improved to
60 # not require hijacking hugetlbfs hooks.
61 depends on SPU_FS && PPC_MM_SLICES && !PPC_64K_PAGES
63 select PPC_HAS_HASH_64K
65 This option causes SPE local stores to be mapped in process
66 address spaces using 64K pages while the rest of the kernel
67 uses 4K pages. This can improve performances of applications
68 using multiple SPEs by lowering the TLB pressure on them.
71 tristate "SPU event tracing support"
72 depends on SPU_FS && MARKERS
74 This option allows reading a trace of spu-related events through
75 the sputrace file in procfs.
82 bool "RAS features for bare metal Cell BE"
83 depends on PPC_CELL_NATIVE
86 config PPC_IBM_CELL_RESETBUTTON
87 bool "IBM Cell Blade Pinhole reset button"
88 depends on CBE_RAS && PPC_IBM_CELL_BLADE
91 Support Pinhole Resetbutton on IBM Cell blades.
92 This adds a method to trigger system reset via front panel pinhole button.
94 config PPC_IBM_CELL_POWERBUTTON
95 tristate "IBM Cell Blade power button"
96 depends on PPC_IBM_CELL_BLADE && PPC_PMI && INPUT_EVDEV
99 Support Powerbutton on IBM Cell blades.
100 This will enable the powerbutton as an input device.
103 tristate "CBE thermal support"
108 tristate "CBE frequency scaling"
109 depends on CBE_RAS && CPU_FREQ
112 This adds the cpufreq driver for Cell BE processors.
113 For details, take a look at <file:Documentation/cpu-freq/>.
114 If you don't have such processor, say N
116 config CBE_CPUFREQ_PMI
117 tristate "CBE frequency scaling using PMI interface"
118 depends on CBE_CPUFREQ && PPC_PMI && EXPERIMENTAL
121 Select this, if you want to use the PMI interface
122 to switch frequencies. Using PMI, the
123 processor will not only be able to run at lower speed,
124 but also at lower core voltage.
126 config CBE_CPUFREQ_SPU_GOVERNOR
127 tristate "CBE frequency scaling based on SPU usage"
128 depends on SPU_FS && CPU_FREQ
131 This governor checks for spu usage to adjust the cpu frequency.
132 If no spu is running on a given cpu, that cpu will be throttled to
133 the minimal possible frequency.
139 depends on PPC_CELL_NATIVE && (OPROFILE = m || OPROFILE = y)